trunk/src/mess/machine/trs80.c
| r20881 | r20882 | |
| 230 | 230 | if (m_model4 & 4) /* Model 4P gets RAM while Model 4 gets ROM */ |
| 231 | 231 | { |
| 232 | 232 | if (m_model4 & 8) |
| 233 | | membank("bank1")->set_base(base); |
| 233 | m_bank1->set_base(base); |
| 234 | 234 | else |
| 235 | | membank("bank1")->set_base(base + 0x10000); |
| 235 | m_bank1->set_base(base + 0x10000); |
| 236 | 236 | |
| 237 | | membank("bank2")->set_base(base + 0x11000); |
| 238 | | membank("bank4")->set_base(base + 0x137ea); |
| 237 | m_bank2->set_base(base + 0x11000); |
| 238 | m_bank4->set_base(base + 0x137ea); |
| 239 | 239 | } |
| 240 | 240 | else |
| 241 | 241 | { |
| 242 | | membank("bank1")->set_base(base); |
| 243 | | membank("bank2")->set_base(base + 0x01000); |
| 244 | | membank("bank4")->set_base(base + 0x037ea); |
| 242 | m_bank1->set_base(base); |
| 243 | m_bank2->set_base(base + 0x01000); |
| 244 | m_bank4->set_base(base + 0x037ea); |
| 245 | 245 | } |
| 246 | 246 | |
| 247 | | membank("bank7")->set_base(base + 0x14000); |
| 248 | | membank("bank8")->set_base(base + 0x1f400); |
| 249 | | membank("bank9")->set_base(base + 0x1f800); |
| 250 | | membank("bank11")->set_base(base + 0x05000); |
| 251 | | membank("bank12")->set_base(base + 0x06000); |
| 252 | | membank("bank14")->set_base(base + 0x09000); |
| 253 | | membank("bank15")->set_base(base + 0x0a000); |
| 254 | | membank("bank17")->set_base(base + 0x14000); |
| 255 | | membank("bank18")->set_base(base + 0x1f400); |
| 256 | | membank("bank19")->set_base(base + 0x1f800); |
| 247 | m_bank7->set_base(base + 0x14000); |
| 248 | m_bank8->set_base(base + 0x1f400); |
| 249 | m_bank9->set_base(base + 0x1f800); |
| 250 | m_bank11->set_base(base + 0x05000); |
| 251 | m_bank12->set_base(base + 0x06000); |
| 252 | m_bank14->set_base(base + 0x09000); |
| 253 | m_bank15->set_base(base + 0x0a000); |
| 254 | m_bank17->set_base(base + 0x14000); |
| 255 | m_bank18->set_base(base + 0x1f400); |
| 256 | m_bank19->set_base(base + 0x1f800); |
| 257 | 257 | mem.install_readwrite_handler (0x37e8, 0x37e9, read8_delegate(FUNC(trs80_state::trs80_printer_r), this), write8_delegate(FUNC(trs80_state::trs80_printer_w), this)); /* 3 & 13 */ |
| 258 | 258 | mem.install_read_handler (0x3800, 0x3bff, read8_delegate(FUNC(trs80_state::trs80_keyboard_r), this)); /* 5 */ |
| 259 | 259 | mem.install_readwrite_handler (0x3c00, 0x3fff, read8_delegate(FUNC(trs80_state::trs80_videoram_r), this), write8_delegate(FUNC(trs80_state::trs80_videoram_w), this)); /* 6 & 16 */ |
| r20881 | r20882 | |
| 264 | 264 | if (m_model4 & 4) /* Model 4P gets RAM while Model 4 gets ROM */ |
| 265 | 265 | { |
| 266 | 266 | if (m_model4 & 8) |
| 267 | | membank("bank1")->set_base(base); |
| 267 | m_bank1->set_base(base); |
| 268 | 268 | else |
| 269 | | membank("bank1")->set_base(base + 0x10000); |
| 269 | m_bank1->set_base(base + 0x10000); |
| 270 | 270 | |
| 271 | | membank("bank2")->set_base(base + 0x11000); |
| 272 | | membank("bank3")->set_base(base + 0x137e8); |
| 273 | | membank("bank4")->set_base(base + 0x137ea); |
| 271 | m_bank2->set_base(base + 0x11000); |
| 272 | m_bank3->set_base(base + 0x137e8); |
| 273 | m_bank4->set_base(base + 0x137ea); |
| 274 | 274 | } |
| 275 | 275 | else |
| 276 | 276 | { |
| 277 | | membank("bank1")->set_base(base); |
| 278 | | membank("bank2")->set_base(base + 0x01000); |
| 279 | | membank("bank3")->set_base(base + 0x037e8); |
| 280 | | membank("bank4")->set_base(base + 0x037ea); |
| 277 | m_bank1->set_base(base); |
| 278 | m_bank2->set_base(base + 0x01000); |
| 279 | m_bank3->set_base(base + 0x037e8); |
| 280 | m_bank4->set_base(base + 0x037ea); |
| 281 | 281 | } |
| 282 | 282 | |
| 283 | | membank("bank7")->set_base(base + 0x14000); |
| 284 | | membank("bank8")->set_base(base + 0x1f400); |
| 285 | | membank("bank9")->set_base(base + 0x1f800); |
| 286 | | membank("bank11")->set_base(base + 0x10000); |
| 287 | | membank("bank12")->set_base(base + 0x11000); |
| 288 | | membank("bank13")->set_base(base + 0x137e8); |
| 289 | | membank("bank14")->set_base(base + 0x137ea); |
| 290 | | membank("bank15")->set_base(base + 0x0a000); |
| 291 | | membank("bank17")->set_base(base + 0x14000); |
| 292 | | membank("bank18")->set_base(base + 0x1f400); |
| 293 | | membank("bank19")->set_base(base + 0x1f800); |
| 283 | m_bank7->set_base(base + 0x14000); |
| 284 | m_bank8->set_base(base + 0x1f400); |
| 285 | m_bank9->set_base(base + 0x1f800); |
| 286 | m_bank11->set_base(base + 0x10000); |
| 287 | m_bank12->set_base(base + 0x11000); |
| 288 | m_bank13->set_base(base + 0x137e8); |
| 289 | m_bank14->set_base(base + 0x137ea); |
| 290 | m_bank15->set_base(base + 0x0a000); |
| 291 | m_bank17->set_base(base + 0x14000); |
| 292 | m_bank18->set_base(base + 0x1f400); |
| 293 | m_bank19->set_base(base + 0x1f800); |
| 294 | 294 | mem.install_read_handler (0x3800, 0x3bff, read8_delegate(FUNC(trs80_state::trs80_keyboard_r), this)); /* 5 */ |
| 295 | 295 | mem.install_readwrite_handler (0x3c00, 0x3fff, read8_delegate(FUNC(trs80_state::trs80_videoram_r), this), write8_delegate(FUNC(trs80_state::trs80_videoram_w), this)); /* 6 & 16 */ |
| 296 | 296 | break; |
| 297 | 297 | |
| 298 | 298 | case 2: /* keyboard and video are moved to high memory, and the rest is ram */ |
| 299 | | membank("bank1")->set_base(base + 0x10000); |
| 300 | | membank("bank2")->set_base(base + 0x11000); |
| 301 | | membank("bank3")->set_base(base + 0x137e8); |
| 302 | | membank("bank4")->set_base(base + 0x137ea); |
| 303 | | membank("bank5")->set_base(base + 0x13800); |
| 304 | | membank("bank6")->set_base(base + 0x13c00); |
| 305 | | membank("bank7")->set_base(base + 0x14000); |
| 306 | | membank("bank11")->set_base(base + 0x10000); |
| 307 | | membank("bank12")->set_base(base + 0x11000); |
| 308 | | membank("bank13")->set_base(base + 0x137e8); |
| 309 | | membank("bank14")->set_base(base + 0x137ea); |
| 310 | | membank("bank15")->set_base(base + 0x13800); |
| 311 | | membank("bank16")->set_base(base + 0x13c00); |
| 312 | | membank("bank17")->set_base(base + 0x14000); |
| 313 | | membank("bank18")->set_base(base + 0x0a000); |
| 299 | m_bank1->set_base(base + 0x10000); |
| 300 | m_bank2->set_base(base + 0x11000); |
| 301 | m_bank3->set_base(base + 0x137e8); |
| 302 | m_bank4->set_base(base + 0x137ea); |
| 303 | m_bank5->set_base(base + 0x13800); |
| 304 | m_bank6->set_base(base + 0x13c00); |
| 305 | m_bank7->set_base(base + 0x14000); |
| 306 | m_bank11->set_base(base + 0x10000); |
| 307 | m_bank12->set_base(base + 0x11000); |
| 308 | m_bank13->set_base(base + 0x137e8); |
| 309 | m_bank14->set_base(base + 0x137ea); |
| 310 | m_bank15->set_base(base + 0x13800); |
| 311 | m_bank16->set_base(base + 0x13c00); |
| 312 | m_bank17->set_base(base + 0x14000); |
| 313 | m_bank18->set_base(base + 0x0a000); |
| 314 | 314 | mem.install_read_handler (0xf400, 0xf7ff, read8_delegate(FUNC(trs80_state::trs80_keyboard_r), this)); /* 8 */ |
| 315 | 315 | mem.install_readwrite_handler (0xf800, 0xffff, read8_delegate(FUNC(trs80_state::trs80_videoram_r), this), write8_delegate(FUNC(trs80_state::trs80_videoram_w), this)); /* 9 & 19 */ |
| 316 | 316 | m_model4++; |
| 317 | 317 | break; |
| 318 | 318 | |
| 319 | 319 | case 3: /* 64k of ram */ |
| 320 | | membank("bank1")->set_base(base + 0x10000); |
| 321 | | membank("bank2")->set_base(base + 0x11000); |
| 322 | | membank("bank3")->set_base(base + 0x137e8); |
| 323 | | membank("bank4")->set_base(base + 0x137ea); |
| 324 | | membank("bank5")->set_base(base + 0x13800); |
| 325 | | membank("bank6")->set_base(base + 0x13c00); |
| 326 | | membank("bank7")->set_base(base + 0x14000); |
| 327 | | membank("bank8")->set_base(base + 0x1f400); |
| 328 | | membank("bank9")->set_base(base + 0x1f800); |
| 329 | | membank("bank11")->set_base(base + 0x10000); |
| 330 | | membank("bank12")->set_base(base + 0x11000); |
| 331 | | membank("bank13")->set_base(base + 0x137e8); |
| 332 | | membank("bank14")->set_base(base + 0x137ea); |
| 333 | | membank("bank15")->set_base(base + 0x13800); |
| 334 | | membank("bank16")->set_base(base + 0x13c00); |
| 335 | | membank("bank17")->set_base(base + 0x14000); |
| 336 | | membank("bank18")->set_base(base + 0x1f400); |
| 337 | | membank("bank19")->set_base(base + 0x1f800); |
| 320 | m_bank1->set_base(base + 0x10000); |
| 321 | m_bank2->set_base(base + 0x11000); |
| 322 | m_bank3->set_base(base + 0x137e8); |
| 323 | m_bank4->set_base(base + 0x137ea); |
| 324 | m_bank5->set_base(base + 0x13800); |
| 325 | m_bank6->set_base(base + 0x13c00); |
| 326 | m_bank7->set_base(base + 0x14000); |
| 327 | m_bank8->set_base(base + 0x1f400); |
| 328 | m_bank9->set_base(base + 0x1f800); |
| 329 | m_bank11->set_base(base + 0x10000); |
| 330 | m_bank12->set_base(base + 0x11000); |
| 331 | m_bank13->set_base(base + 0x137e8); |
| 332 | m_bank14->set_base(base + 0x137ea); |
| 333 | m_bank15->set_base(base + 0x13800); |
| 334 | m_bank16->set_base(base + 0x13c00); |
| 335 | m_bank17->set_base(base + 0x14000); |
| 336 | m_bank18->set_base(base + 0x1f400); |
| 337 | m_bank19->set_base(base + 0x1f800); |
| 338 | 338 | break; |
| 339 | 339 | } |
| 340 | 340 | } |
| r20881 | r20882 | |
| 361 | 361 | switch (m_model4 & 8) |
| 362 | 362 | { |
| 363 | 363 | case 0: /* Read-only RAM replaces rom */ |
| 364 | | membank("bank1")->set_base(m_region_maincpu->base() + 0x10000); |
| 364 | m_bank1->set_base(m_region_maincpu->base() + 0x10000); |
| 365 | 365 | break; |
| 366 | 366 | case 8: /* Normal setup - rom enabled */ |
| 367 | | membank("bank1")->set_base(m_region_maincpu->base()); |
| 367 | m_bank1->set_base(m_region_maincpu->base()); |
| 368 | 368 | break; |
| 369 | 369 | } |
| 370 | 370 | } |
| r20881 | r20882 | |
| 863 | 863 | m_cassette_data = 0; |
| 864 | 864 | |
| 865 | 865 | mem.install_read_bank (0x0000, 0x0fff, "bank1"); |
| 866 | m_bank1 = membank("bank1"); |
| 866 | 867 | mem.install_read_bank (0x1000, 0x37e7, "bank2"); |
| 868 | m_bank2 = membank("bank2"); |
| 867 | 869 | mem.install_read_bank (0x37e8, 0x37e9, "bank3"); |
| 870 | m_bank3 = membank("bank3"); |
| 868 | 871 | mem.install_read_bank (0x37ea, 0x37ff, "bank4"); |
| 872 | m_bank4 = membank("bank4"); |
| 869 | 873 | mem.install_read_bank (0x3800, 0x3bff, "bank5"); |
| 874 | m_bank5 = membank("bank5"); |
| 870 | 875 | mem.install_read_bank (0x3c00, 0x3fff, "bank6"); |
| 876 | m_bank6 = membank("bank6"); |
| 871 | 877 | mem.install_read_bank (0x4000, 0xf3ff, "bank7"); |
| 878 | m_bank7 = membank("bank7"); |
| 872 | 879 | mem.install_read_bank (0xf400, 0xf7ff, "bank8"); |
| 880 | m_bank8 = membank("bank8"); |
| 873 | 881 | mem.install_read_bank (0xf800, 0xffff, "bank9"); |
| 882 | m_bank9 = membank("bank9"); |
| 874 | 883 | |
| 875 | 884 | mem.install_write_bank (0x0000, 0x0fff, "bank11"); |
| 885 | m_bank11 = membank("bank11"); |
| 876 | 886 | mem.install_write_bank (0x1000, 0x37e7, "bank12"); |
| 887 | m_bank12 = membank("bank12"); |
| 877 | 888 | mem.install_write_bank (0x37e8, 0x37e9, "bank13"); |
| 889 | m_bank13 = membank("bank13"); |
| 878 | 890 | mem.install_write_bank (0x37ea, 0x37ff, "bank14"); |
| 891 | m_bank14 = membank("bank14"); |
| 879 | 892 | mem.install_write_bank (0x3800, 0x3bff, "bank15"); |
| 893 | m_bank15 = membank("bank15"); |
| 880 | 894 | mem.install_write_bank (0x3c00, 0x3fff, "bank16"); |
| 895 | m_bank16 = membank("bank16"); |
| 881 | 896 | mem.install_write_bank (0x4000, 0xf3ff, "bank17"); |
| 897 | m_bank17 = membank("bank17"); |
| 882 | 898 | mem.install_write_bank (0xf400, 0xf7ff, "bank18"); |
| 899 | m_bank18 = membank("bank18"); |
| 883 | 900 | mem.install_write_bank (0xf800, 0xffff, "bank19"); |
| 901 | m_bank19 = membank("bank19"); |
| 884 | 902 | trs80m4p_9c_w(mem, 0, 1); /* Enable the ROM */ |
| 885 | 903 | trs80m4_84_w(mem, 0, 0); /* switch in devices at power-on */ |
| 886 | 904 | } |