trunk/src/mess/machine/trs80.c
| r20846 | r20847 | |
|---|
| 37 | 37 | { |
| 38 | 38 | m_cassette_data = 0; |
| 39 | 39 | m_irq |= CASS_FALL; |
| 40 | | machine().device("maincpu")->execute().set_input_line(0, HOLD_LINE); |
| 40 | m_maincpu->set_input_line(0, HOLD_LINE); |
| 41 | 41 | } |
| 42 | 42 | } |
| 43 | 43 | else |
| r20846 | r20847 | |
|---|
| 47 | 47 | { |
| 48 | 48 | m_cassette_data = 1; |
| 49 | 49 | m_irq |= CASS_RISE; |
| 50 | | machine().device("maincpu")->execute().set_input_line(0, HOLD_LINE); |
| 50 | m_maincpu->set_input_line(0, HOLD_LINE); |
| 51 | 51 | } |
| 52 | 52 | } |
| 53 | 53 | |
| r20846 | r20847 | |
|---|
| 78 | 78 | d1 Cass 1500 baud Falling |
| 79 | 79 | d0 Cass 1500 baud Rising */ |
| 80 | 80 | |
| 81 | | machine().device("maincpu")->execute().set_input_line(0, CLEAR_LINE); |
| 81 | m_maincpu->set_input_line(0, CLEAR_LINE); |
| 82 | 82 | return ~(m_mask & m_irq); |
| 83 | 83 | } |
| 84 | 84 | |
| r20846 | r20847 | |
|---|
| 94 | 94 | d6 status of Motor Timeout (0=true) |
| 95 | 95 | d5 status of Reset signal (0=true - this will reboot the computer) */ |
| 96 | 96 | |
| 97 | | machine().device("maincpu")->execute().set_input_line(INPUT_LINE_NMI, CLEAR_LINE); |
| 97 | m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE); |
| 98 | 98 | |
| 99 | 99 | return ~(m_nmi_mask & m_nmi_data); |
| 100 | 100 | } |
| r20846 | r20847 | |
|---|
| 216 | 216 | |
| 217 | 217 | /* get address space instead of io space */ |
| 218 | 218 | address_space &mem = m_maincpu->space(AS_PROGRAM); |
| 219 | | UINT8 *base = memregion("maincpu")->base(); |
| 219 | UINT8 *base = m_region_maincpu->base(); |
| 220 | 220 | |
| 221 | 221 | m_mode = (m_mode & 0x73) | (data & 0x8c); |
| 222 | 222 | |
| r20846 | r20847 | |
|---|
| 361 | 361 | switch (m_model4 & 8) |
| 362 | 362 | { |
| 363 | 363 | case 0: /* Read-only RAM replaces rom */ |
| 364 | | membank("bank1")->set_base(machine().root_device().memregion("maincpu")->base() + 0x10000); |
| 364 | membank("bank1")->set_base(m_region_maincpu->base() + 0x10000); |
| 365 | 365 | break; |
| 366 | 366 | case 8: /* Normal setup - rom enabled */ |
| 367 | | membank("bank1")->set_base(machine().root_device().memregion("maincpu")->base()); |
| 367 | membank("bank1")->set_base(m_region_maincpu->base()); |
| 368 | 368 | break; |
| 369 | 369 | } |
| 370 | 370 | } |
| r20846 | r20847 | |
|---|
| 572 | 572 | { |
| 573 | 573 | mem.unmap_readwrite (0x0000, 0x3fff); |
| 574 | 574 | mem.install_read_bank (0x0000, 0x2fff, "bank1"); |
| 575 | | membank("bank1")->set_base(machine().root_device().memregion("maincpu")->base()); |
| 575 | membank("bank1")->set_base(m_region_maincpu->base()); |
| 576 | 576 | mem.install_readwrite_handler (0x37e0, 0x37e3, read8_delegate(FUNC(trs80_state::trs80_irq_status_r), this), write8_delegate(FUNC(trs80_state::trs80_motor_w), this)); |
| 577 | 577 | mem.install_readwrite_handler (0x37e8, 0x37eb, read8_delegate(FUNC(trs80_state::trs80_printer_r), this), write8_delegate(FUNC(trs80_state::trs80_printer_w), this)); |
| 578 | 578 | mem.install_read_handler (0x37ec, 0x37ec, read8_delegate(FUNC(trs80_state::trs80_wd179x_r), this)); |
| r20846 | r20847 | |
|---|
| 643 | 643 | } |
| 644 | 644 | } |
| 645 | 645 | |
| 646 | | static void trs80_fdc_interrupt_internal(running_machine &machine) |
| 646 | void trs80_state::trs80_fdc_interrupt_internal() |
| 647 | 647 | { |
| 648 | | trs80_state *state = machine.driver_data<trs80_state>(); |
| 649 | | if (state->m_model4) |
| 648 | if (m_model4) |
| 650 | 649 | { |
| 651 | | if (state->m_nmi_mask & 0x80) // Model 4 does a NMI |
| 650 | if (m_nmi_mask & 0x80) // Model 4 does a NMI |
| 652 | 651 | { |
| 653 | | state->m_nmi_data = 0x80; |
| 654 | | machine.device("maincpu")->execute().set_input_line(INPUT_LINE_NMI, PULSE_LINE); |
| 652 | m_nmi_data = 0x80; |
| 653 | m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE); |
| 655 | 654 | } |
| 656 | 655 | } |
| 657 | 656 | else // Model 1 does a IRQ |
| 658 | 657 | { |
| 659 | | state->m_irq |= IRQ_M1_FDC; |
| 660 | | machine.device("maincpu")->execute().set_input_line(0, HOLD_LINE); |
| 658 | m_irq |= IRQ_M1_FDC; |
| 659 | m_maincpu->set_input_line(0, HOLD_LINE); |
| 661 | 660 | } |
| 662 | 661 | } |
| 663 | 662 | |
| 664 | 663 | INTERRUPT_GEN_MEMBER(trs80_state::trs80_fdc_interrupt)/* not used - should it be? */ |
| 665 | 664 | { |
| 666 | | trs80_fdc_interrupt_internal(machine()); |
| 665 | trs80_fdc_interrupt_internal(); |
| 667 | 666 | } |
| 668 | 667 | |
| 669 | 668 | WRITE_LINE_MEMBER(trs80_state::trs80_fdc_intrq_w) |
| 670 | 669 | { |
| 671 | 670 | if (state) |
| 672 | 671 | { |
| 673 | | trs80_fdc_interrupt_internal(machine()); |
| 672 | trs80_fdc_interrupt_internal(); |
| 674 | 673 | } |
| 675 | 674 | else |
| 676 | 675 | { |
| r20846 | r20847 | |
|---|
| 748 | 747 | which is dealt with by the DOS. We take the opportunity to reset the cpu INT line. */ |
| 749 | 748 | |
| 750 | 749 | int result = m_irq; |
| 751 | | machine().device("maincpu")->execute().set_input_line(0, CLEAR_LINE); |
| 750 | m_maincpu->set_input_line(0, CLEAR_LINE); |
| 752 | 751 | m_irq = 0; |
| 753 | 752 | return result; |
| 754 | 753 | } |
trunk/src/mess/includes/trs80.h
| r20846 | r20847 | |
|---|
| 33 | 33 | m_fdc(*this, "wd179x"), |
| 34 | 34 | m_speaker(*this, SPEAKER_TAG), |
| 35 | 35 | m_cass(*this, CASSETTE_TAG), |
| 36 | | m_p_videoram(*this, "p_videoram") |
| 36 | m_p_videoram(*this, "p_videoram"), |
| 37 | m_region_maincpu(*this, "maincpu") |
| 37 | 38 | { } |
| 38 | 39 | |
| 39 | 40 | required_device<cpu_device> m_maincpu; |
| r20846 | r20847 | |
|---|
| 126 | 127 | INTERRUPT_GEN_MEMBER(trs80_fdc_interrupt); |
| 127 | 128 | TIMER_CALLBACK_MEMBER(cassette_data_callback); |
| 128 | 129 | DECLARE_WRITE_LINE_MEMBER(trs80_fdc_intrq_w); |
| 130 | |
| 131 | protected: |
| 132 | required_memory_region m_region_maincpu; |
| 133 | |
| 134 | void trs80_fdc_interrupt_internal(); |
| 129 | 135 | }; |
| 130 | 136 | |
| 131 | 137 | |