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r20844 Friday 8th February, 2013 at 20:30:55 UTC by Wilbert Pol
(MESS) special.c: Reduce tagmap lookups (nw)

[src/mess/includes]	special.h
[src/mess/machine]	special.c

trunk/src/mess/machine/special.c

r20843	r20844
16	16	DRIVER_INIT_MEMBER(special_state,special)
17	17	{
18	18	/* set initialy ROM to be visible on first bank */
19		UINT8 *RAM = machine().root_device().memregion("maincpu")->base();
	19	UINT8 *RAM = m_region_maincpu->base();
20	20	memset(RAM,0x0000,0x3000); // make first page empty by default
21		membank("bank1")->configure_entries(1, 2, RAM, 0x0000);
22		membank("bank1")->configure_entries(0, 2, RAM, 0xc000);
	21	m_bank1->configure_entries(1, 2, RAM, 0x0000);
	22	m_bank1->configure_entries(0, 2, RAM, 0xc000);
23	23	}
24	24
25	25	READ8_MEMBER( special_state::specialist_8255_porta_r )
26	26	{
27		if (ioport("LINE0")->read()!=0xff) return 0xfe;
28		if (ioport("LINE1")->read()!=0xff) return 0xfd;
29		if (ioport("LINE2")->read()!=0xff) return 0xfb;
30		if (ioport("LINE3")->read()!=0xff) return 0xf7;
31		if (ioport("LINE4")->read()!=0xff) return 0xef;
32		if (ioport("LINE5")->read()!=0xff) return 0xdf;
33		if (ioport("LINE6")->read()!=0xff) return 0xbf;
34		if (ioport("LINE7")->read()!=0xff) return 0x7f;
	27	if (m_io_line0->read()!=0xff) return 0xfe;
	28	if (m_io_line1->read()!=0xff) return 0xfd;
	29	if (m_io_line2->read()!=0xff) return 0xfb;
	30	if (m_io_line3->read()!=0xff) return 0xf7;
	31	if (m_io_line4->read()!=0xff) return 0xef;
	32	if (m_io_line5->read()!=0xff) return 0xdf;
	33	if (m_io_line6->read()!=0xff) return 0xbf;
	34	if (m_io_line7->read()!=0xff) return 0x7f;
35	35	return 0xff;
36	36	}
37	37
r20843	r20844
40	40	UINT8 dat = 0;
41	41	double level;
42	42
43		if ((m_specialist_8255_porta & 0x01)==0) dat ^= (ioport("LINE0")->read() ^ 0xff);
44		if ((m_specialist_8255_porta & 0x02)==0) dat ^= (ioport("LINE1")->read() ^ 0xff);
45		if ((m_specialist_8255_porta & 0x04)==0) dat ^= (ioport("LINE2")->read() ^ 0xff);
46		if ((m_specialist_8255_porta & 0x08)==0) dat ^= (ioport("LINE3")->read() ^ 0xff);
47		if ((m_specialist_8255_porta & 0x10)==0) dat ^= (ioport("LINE4")->read() ^ 0xff);
48		if ((m_specialist_8255_porta & 0x20)==0) dat ^= (ioport("LINE5")->read() ^ 0xff);
49		if ((m_specialist_8255_porta & 0x40)==0) dat ^= (ioport("LINE6")->read() ^ 0xff);
50		if ((m_specialist_8255_porta & 0x80)==0) dat ^= (ioport("LINE7")->read() ^ 0xff);
51		if ((m_specialist_8255_portc & 0x01)==0) dat ^= (ioport("LINE8")->read() ^ 0xff);
52		if ((m_specialist_8255_portc & 0x02)==0) dat ^= (ioport("LINE9")->read() ^ 0xff);
53		if ((m_specialist_8255_portc & 0x04)==0) dat ^= (ioport("LINE10")->read() ^ 0xff);
54		if ((m_specialist_8255_portc & 0x08)==0) dat ^= (ioport("LINE11")->read() ^ 0xff);
	43	if ((m_specialist_8255_porta & 0x01)==0) dat ^= (m_io_line0->read() ^ 0xff);
	44	if ((m_specialist_8255_porta & 0x02)==0) dat ^= (m_io_line1->read() ^ 0xff);
	45	if ((m_specialist_8255_porta & 0x04)==0) dat ^= (m_io_line2->read() ^ 0xff);
	46	if ((m_specialist_8255_porta & 0x08)==0) dat ^= (m_io_line3->read() ^ 0xff);
	47	if ((m_specialist_8255_porta & 0x10)==0) dat ^= (m_io_line4->read() ^ 0xff);
	48	if ((m_specialist_8255_porta & 0x20)==0) dat ^= (m_io_line5->read() ^ 0xff);
	49	if ((m_specialist_8255_porta & 0x40)==0) dat ^= (m_io_line6->read() ^ 0xff);
	50	if ((m_specialist_8255_porta & 0x80)==0) dat ^= (m_io_line7->read() ^ 0xff);
	51	if ((m_specialist_8255_portc & 0x01)==0) dat ^= (m_io_line8->read() ^ 0xff);
	52	if ((m_specialist_8255_portc & 0x02)==0) dat ^= (m_io_line9->read() ^ 0xff);
	53	if ((m_specialist_8255_portc & 0x04)==0) dat ^= (m_io_line10->read() ^ 0xff);
	54	if ((m_specialist_8255_portc & 0x08)==0) dat ^= (m_io_line11->read() ^ 0xff);
55	55
56	56	dat = (dat  << 2) ^0xff;
57		if (ioport("LINE12")->read()!=0xff) dat ^= 0x02;
	57	if (m_io_line12->read()!=0xff) dat ^= 0x02;
58	58
59	59	level = m_cass->input();
60	60	if (level >=  0)
r20843	r20844
65	65
66	66	READ8_MEMBER( special_state::specialist_8255_portc_r )
67	67	{
68		if (ioport("LINE8")->read()!=0xff) return 0x0e;
69		if (ioport("LINE9")->read()!=0xff) return 0x0d;
70		if (ioport("LINE10")->read()!=0xff) return 0x0b;
71		if (ioport("LINE11")->read()!=0xff) return 0x07;
	68	if (m_io_line8->read()!=0xff) return 0x0e;
	69	if (m_io_line9->read()!=0xff) return 0x0d;
	70	if (m_io_line10->read()!=0xff) return 0x0b;
	71	if (m_io_line11->read()!=0xff) return 0x07;
72	72	return 0x0f;
73	73	}
74	74
r20843	r20844
103	103
104	104	TIMER_CALLBACK_MEMBER(special_state::special_reset)
105	105	{
106		membank("bank1")->set_entry(0);
	106	m_bank1->set_entry(0);
107	107	}
108	108
109	109
110	110	MACHINE_RESET_MEMBER(special_state,special)
111	111	{
112	112	machine().scheduler().timer_set(attotime::from_usec(10), timer_expired_delegate(FUNC(special_state::special_reset),this));
113		membank("bank1")->set_entry(1);
	113	m_bank1->set_entry(1);
114	114	}
115	115
116	116
r20843	r20844
140	140
141	141	space.install_write_bank(0xc000, 0xffbf, "bank3");
142	142	space.install_write_bank(0xffc0, 0xffdf, "bank4");
143		membank("bank4")->set_base(ram + 0xffc0);
	143	m_bank4->set_base(ram + 0xffc0);
144	144	switch(i)
145	145	{
146	146	case 0 :
147	147	space.install_write_bank(0x0000, 0x8fff, "bank1");
148	148	space.install_write_handler(0x9000, 0xbfff, write8_delegate(FUNC(special_state::video_memory_w), this));
149	149
150		membank("bank1")->set_base(ram);
151		membank("bank2")->set_base(ram + 0x9000);
152		membank("bank3")->set_base(ram + 0xc000);
	150	m_bank1->set_base(ram);
	151	m_bank2->set_base(ram + 0x9000);
	152	m_bank3->set_base(ram + 0xc000);
153	153	break;
154	154	case 1 :
155	155	space.install_write_bank(0x0000, 0x8fff, "bank1");
156	156	space.install_write_bank(0x9000, 0xbfff, "bank2");
157	157
158		membank("bank1")->set_base(ram + 0x10000);
159		membank("bank2")->set_base(ram + 0x19000);
160		membank("bank3")->set_base(ram + 0x1c000);
	158	m_bank1->set_base(ram + 0x10000);
	159	m_bank2->set_base(ram + 0x19000);
	160	m_bank3->set_base(ram + 0x1c000);
161	161	break;
162	162	case 2 :
163	163	space.unmap_write(0x0000, 0x8fff);
164	164	space.unmap_write(0x9000, 0xbfff);
165	165
166		membank("bank1")->set_base(machine().root_device().memregion("maincpu")->base() + 0x10000);
167		membank("bank2")->set_base(machine().root_device().memregion("maincpu")->base() + 0x19000);
	166	m_bank1->set_base(m_region_maincpu->base() + 0x10000);
	167	m_bank2->set_base(m_region_maincpu->base() + 0x19000);
168	168
169	169	if (data & 0x80)
170		membank("bank3")->set_base(ram + 0x1c000);
	170	m_bank3->set_base(ram + 0x1c000);
171	171	else
172		membank("bank3")->set_base(ram + 0xc000);
	172	m_bank3->set_base(ram + 0xc000);
173	173
174	174	break;
175	175	}
r20843	r20844
288	288	UINT8 bank2 = (m_RR_register >> 2) & 3;
289	289	UINT8 bank3 = (m_RR_register >> 4) & 3;
290	290	UINT8 bank4 = (m_RR_register >> 6) & 3;
291		UINT8 *mem = memregion("maincpu")->base();
	291	UINT8 *mem = m_region_maincpu->base();
292	292	UINT8 *ram = m_ram->pointer();
293	293	address_space &space = m_maincpu->space(AS_PROGRAM);
294	294
r20843	r20844
304	304	case    1:
305	305	case    2:
306	306	case    3:
307		membank("bank1")->set_base(ram + 0x10000*(bank1-1));
	307	m_bank1->set_base(ram + 0x10000*(bank1-1));
308	308	break;
309	309	case    0:
310	310	space.unmap_write(0x0000, 0x3fff);
311		membank("bank1")->set_base(mem + 0x10000);
	311	m_bank1->set_base(mem + 0x10000);
312	312	break;
313	313	}
314	314	switch(bank2)
r20843	r20844
316	316	case    1:
317	317	case    2:
318	318	case    3:
319		membank("bank2")->set_base(ram + 0x10000*(bank2-1) + 0x4000);
	319	m_bank2->set_base(ram + 0x10000*(bank2-1) + 0x4000);
320	320	break;
321	321	case    0:
322	322	space.unmap_write(0x4000, 0x8fff);
323		membank("bank2")->set_base(mem + 0x14000);
	323	m_bank2->set_base(mem + 0x14000);
324	324	break;
325	325	}
326	326	switch(bank3)
r20843	r20844
328	328	case    1:
329	329	case    2:
330	330	case    3:
331		membank("bank3")->set_base(ram + 0x10000*(bank3-1) + 0x9000);
	331	m_bank3->set_base(ram + 0x10000*(bank3-1) + 0x9000);
332	332	break;
333	333	case    0:
334	334	space.unmap_write(0x9000, 0xbfff);
335		membank("bank3")->set_base(mem + 0x19000);
	335	m_bank3->set_base(mem + 0x19000);
336	336	break;
337	337	}
338	338	switch(bank4)
r20843	r20844
340	340	case    1:
341	341	case    2:
342	342	case    3:
343		membank("bank4")->set_base(ram + 0x10000*(bank4-1) + 0x0c000);
344		membank("bank5")->set_base(ram + 0x10000*(bank4-1) + 0x0f000);
345		membank("bank6")->set_base(ram + 0x10000*(bank4-1) + 0x0f800);
	343	m_bank4->set_base(ram + 0x10000*(bank4-1) + 0x0c000);
	344	m_bank5->set_base(ram + 0x10000*(bank4-1) + 0x0f000);
	345	m_bank6->set_base(ram + 0x10000*(bank4-1) + 0x0f800);
346	346	break;
347	347	case    0:
348	348	space.unmap_write(0xc000, 0xefff);
349		membank("bank4")->set_base(mem + 0x1c000);
	349	m_bank4->set_base(mem + 0x1c000);
350	350	space.unmap_write(0xf000, 0xf7ff);
351	351	space.nop_read(0xf000, 0xf7ff);
352	352	space.install_readwrite_handler(0xf800, 0xf803, 0, 0x7fc, read8_delegate(FUNC(i8255_device::read), (i8255_device*)m_ppi), write8_delegate(FUNC(i8255_device::write), (i8255_device*)m_ppi));

trunk/src/mess/includes/special.h

r20843	r20844
25	25	{
26	26	public:
27	27	special_state(const machine_config &mconfig, device_type type, const char *tag)
28		: driver_device(mconfig, type, tag),
29		m_maincpu(*this, "maincpu"),
30		m_ppi(*this, "ppi8255"),
31		m_fdc(*this, "fd1793"),
32		m_dac(*this, "dac"),
33		m_cass(*this, CASSETTE_TAG),
34		m_ram(*this, RAM_TAG),
35		m_p_videoram(*this, "p_videoram")
	28	: driver_device(mconfig, type, tag)
	29	, m_maincpu(*this, "maincpu")
	30	, m_ppi(*this, "ppi8255")
	31	, m_fdc(*this, "fd1793")
	32	, m_dac(*this, "dac")
	33	, m_cass(*this, CASSETTE_TAG)
	34	, m_ram(*this, RAM_TAG)
	35	, m_p_videoram(*this, "p_videoram")
	36	, m_region_maincpu(*this, "maincpu")
	37	, m_bank1(*this, "bank1")
	38	, m_bank2(*this, "bank2")
	39	, m_bank3(*this, "bank3")
	40	, m_bank4(*this, "bank4")
	41	, m_bank5(*this, "bank5")
	42	, m_bank6(*this, "bank6")
	43	, m_io_line0(*this, "LINE0")
	44	, m_io_line1(*this, "LINE1")
	45	, m_io_line2(*this, "LINE2")
	46	, m_io_line3(*this, "LINE3")
	47	, m_io_line4(*this, "LINE4")
	48	, m_io_line5(*this, "LINE5")
	49	, m_io_line6(*this, "LINE6")
	50	, m_io_line7(*this, "LINE7")
	51	, m_io_line8(*this, "LINE8")
	52	, m_io_line9(*this, "LINE9")
	53	, m_io_line10(*this, "LINE10")
	54	, m_io_line11(*this, "LINE11")
	55	, m_io_line12(*this, "LINE12")
36	56	{ }
37	57
38	58	DECLARE_WRITE8_MEMBER(specimx_select_bank);
r20843	r20844
97	117	TIMER_CALLBACK_MEMBER(setup_pit8253_gates);
98	118	void fdc_drq(bool state);
99	119	DECLARE_FLOPPY_FORMATS( specimx_floppy_formats );
	120
	121	protected:
	122	required_memory_region m_region_maincpu;
	123	required_memory_bank m_bank1;
	124	optional_memory_bank m_bank2;
	125	optional_memory_bank m_bank3;
	126	optional_memory_bank m_bank4;
	127	optional_memory_bank m_bank5;
	128	optional_memory_bank m_bank6;
	129	required_ioport m_io_line0;
	130	required_ioport m_io_line1;
	131	required_ioport m_io_line2;
	132	required_ioport m_io_line3;
	133	required_ioport m_io_line4;
	134	required_ioport m_io_line5;
	135	required_ioport m_io_line6;
	136	required_ioport m_io_line7;
	137	required_ioport m_io_line8;
	138	required_ioport m_io_line9;
	139	required_ioport m_io_line10;
	140	required_ioport m_io_line11;
	141	required_ioport m_io_line12;
100	142	};
101	143
102	144

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