trunk/src/emu/cpu/arm7/arm7drc.c
| r20751 | r20752 | |
| 2287 | 2287 | |
| 2288 | 2288 | if (T_IS_SET(GET_CPSR)) |
| 2289 | 2289 | { |
| 2290 | UINT32 raddr; |
| 2290 | 2291 | |
| 2292 | pc = R15; |
| 2293 | |
| 2294 | // "In Thumb state, bit [0] is undefined and must be ignored. Bits [31:1] contain the PC." |
| 2295 | raddr = pc & (~1); |
| 2296 | |
| 2297 | if ( COPRO_CTRL & COPRO_CTRL_MMU_EN ) |
| 2298 | { |
| 2299 | if (!arm7_tlb_translate(arm, &raddr, ARM7_TLB_ABORT_P | ARM7_TLB_READ)) |
| 2300 | { |
| 2301 | goto skip_exec; |
| 2302 | } |
| 2303 | } |
| 2304 | |
| 2305 | UML_AND(block, I0, DRC_PC, ~1); |
| 2306 | UML_TEST(block, mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN); // test COPRO_CTRL, COPRO_CTRL_MMU_EN |
| 2307 | UML_MOVc(block, COND_Z, I0, 0); // movz i0, 0 |
| 2308 | UML_MOVc(block, COND_NZ, I0, ARM7_TLB_ABORT_P | ARM7_TLB_READ); // movnz i0, ARM7_TLB_ABORT_P | ARM7_TLB_READ |
| 2309 | UML_CALLHc(block, COND_NZ, *arm->impstate->tlb_translate); // callhnz tlb_translate); |
| 2310 | |
| 2311 | insn = arm->direct->read_decrypted_word(raddr); |
| 2312 | thumb_handler[(insn & 0xffc0) >> 6](arm, pc, insn); |
| 2313 | UML_OR(block, I3, I3, ); // or i2, i2, i3 |
| 2314 | UML_CALLHc(block, COND_NZ, *arm->impstate->tlb_translate); // callhnz tlb_translate |
| 2315 | |
| 2291 | 2316 | } |
| 2317 | else |
| 2318 | { |
| 2319 | UML_AND(block, I0, DRC_PC, ~1); |
| 2320 | UML_TEST(block, mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN); // test COPRO_CTRL, COPRO_CTRL_MMU_EN |
| 2321 | UML_MOVc(block, COND_NZ, I3, ARM7_TLB_READ); // movnz i3, ARM7_TLB_READ |
| 2322 | UML_OR(block, I3, I3, I3); // or i2, i2, i3 |
| 2323 | UML_CALLHc(block, COND_NZ, *arm->impstate->tlb_translate); // callhnz tlb_translate |
| 2324 | } |
| 2292 | 2325 | |
| 2293 | 2326 | switch (opswitch) |
| 2294 | 2327 | { |
trunk/src/emu/cpu/arm7/arm7.c
| r20751 | r20752 | |
| 127 | 127 | switch( granularity ) |
| 128 | 128 | { |
| 129 | 129 | case TLB_COARSE: |
| 130 | | desc_lvl2 = ( first_desc & COPRO_TLB_CFLD_ADDR_MASK ) | ( ( vaddr & COPRO_TLB_VADDR_CSLTI_MASK ) >> COPRO_TLB_VADDR_CSLTI_MASK_SHIFT ); |
| 130 | desc_lvl2 = (first_desc & COPRO_TLB_CFLD_ADDR_MASK) | ((vaddr & COPRO_TLB_VADDR_CSLTI_MASK) >> COPRO_TLB_VADDR_CSLTI_MASK_SHIFT); |
| 131 | 131 | break; |
| 132 | 132 | case TLB_FINE: |
| 133 | | LOG( ( "ARM7: Attempting to get second-level TLB descriptor of fine granularity\n" ) ); |
| 133 | desc_lvl2 = (first_desc & COPRO_TLB_FPTB_ADDR_MASK) | ((vaddr & COPRO_TLB_VADDR_FSLTI_MASK) >> COPRO_TLB_VADDR_FSLTI_MASK_SHIFT); |
| 134 | 134 | break; |
| 135 | 135 | default: |
| 136 | 136 | // We shouldn't be here |
| r20751 | r20752 | |
| 322 | 322 | } |
| 323 | 323 | break; |
| 324 | 324 | case COPRO_TLB_FINE_TABLE: |
| 325 | | // Entry is the physical address of a fine second-level table |
| 326 | | fatalerror("ARM7: Not Yet Implemented: fine second-level TLB lookup, PC = %08x, vaddr = %08x\n", R15, vaddr); |
| 325 | // Entry is the physical address of a coarse second-level table |
| 326 | if ((permission == 1) || (permission == 3)) |
| 327 | { |
| 328 | desc_lvl2 = arm7_tlb_get_second_level_descriptor( arm, TLB_FINE, desc_lvl1, vaddr ); |
| 329 | } |
| 330 | else |
| 331 | { |
| 332 | fatalerror("ARM7: Not Yet Implemented: Fine Table, Section Domain fault on virtual address, vaddr = %08x, domain = %08x, PC = %08x\n", vaddr, domain, R15); |
| 333 | } |
| 327 | 334 | break; |
| 328 | 335 | default: |
| 329 | 336 | // Entry is the physical address of a three-legged termite-eaten table |