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r20713 Sunday 3rd February, 2013 at 22:09:53 UTC by R. Belmont
Initial implementation of Ensoniq ES5510 DSP [Christian Brunschen]

nw part: This doesn't actually process samples yet, but it's pretty close to doing so, we just need OG to figure out how that works in the core.
[src/emu/cpu]cpu.mak
[src/emu/cpu/es5510]es5510.c* es5510.h*
[src/emu/imagedev]midiin.c
[src/mess]mess.mak
[src/mess/drivers]esq5505.c

trunk/src/emu/imagedev/midiin.c
r20712r20713
2121
2222midiin_device::midiin_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
2323   : device_t(mconfig, MIDIIN, "MIDI In image device", tag, owner, clock),
24   device_image_interface(mconfig, *this),
25      device_serial_interface(mconfig, *this)
24     device_image_interface(mconfig, *this),
25          device_serial_interface(mconfig, *this)
2626{
2727}
2828
r20712r20713
3535   m_input_func.resolve(m_input_callback, *this);
3636   m_timer = timer_alloc(0);
3737   m_midi = NULL;
38   m_timer->enable(false);
3839}
3940
4041void midiin_device::device_reset()
r20712r20713
7576   UINT8 buf[8192*4];
7677   int bytesRead;
7778
79   if (m_midi == NULL) {
80     return;
81   }
82
7883   while (osd_poll_midi_channel(m_midi))
7984   {
8085      bytesRead = osd_read_midi_channel(m_midi, buf);
r20712r20713
103108   }
104109
105110   m_timer->adjust(attotime::from_hz(1500), 0, attotime::from_hz(1500));
106
111   m_timer->enable(true);
107112   return IMAGE_INIT_PASS;
108113}
109114
r20712r20713
117122   {
118123      osd_close_midi_channel(m_midi);
119124   }
125        m_timer->enable(false);
126        m_midi = NULL;
120127}
121128
122129void midiin_device::tra_complete()
trunk/src/emu/cpu/cpu.mak
r20712r20713
278278                        $(CPUSRC)/cubeqcpu/cubeqcpu.h
279279
280280
281#-------------------------------------------------
282# Ensoniq ES5510 ('ESP') DSP
283#-------------------------------------------------
281284
285ifneq ($(filter ES5510,$(CPUS)),)
286OBJDIRS += $(CPUOBJ)/es5510
287CPUOBJS += $(CPUOBJ)/es5510/es5510.o
288endif
289
290$(CPUOBJ)/es5510.o:   $(CPUSRC)/es5510/es5510.c \
291                        $(CPUSRC)/es5510/es5510.h
292
293
282294#-------------------------------------------------
283295# Entertainment Sciences AM29116-based RIP
284296#-------------------------------------------------
r20712r20713
10551067         $(CPUOBJ)/m6502/m8502.o \
10561068         $(CPUOBJ)/m6502/n2a03.o \
10571069         $(CPUOBJ)/m6502/r65c02.o \
1058         $(CPUOBJ)/m6502/m740.o
1070         $(CPUOBJ)/m6502/m740.o \
1071         $(CPUOBJ)/m6502/m5074x.o
1072
10591073DASMOBJS +=
10601074endif
10611075
r20712r20713
11361150                     $(CPUSRC)/m6502/m740.h \
11371151                     $(CPUSRC)/m6502/m6502.h
11381152
1153$(CPUOBJ)/m6502/m5074x.o:   $(CPUSRC)/m6502/m5074x.c \
1154                     $(CPUSRC)/m6502/m5074x.h
1155
11391156# rule to generate the C files
11401157$(CPUOBJ)/m6502/deco16.inc: $(CPUSRC)/m6502/m6502make.py $(CPUSRC)/m6502/odeco16.lst $(CPUSRC)/m6502/ddeco16.lst
11411158   @echo Generating DECO16 source file...
trunk/src/emu/cpu/es5510/es5510.c
r0r20713
1/***************************************************************************
2 *
3 *   es5510.c - Ensoniq ES5510 (ESP) emulation
4 *   by Christian Brunschen
5 *
6 ***************************************************************************/
7
8#include <cstdio>
9#include "emu.h"
10#include "debugger.h"
11#include "es5510.h"
12#include "cpu/m68000/m68000.h"
13
14const device_type ES5510 = &device_creator<es5510_device>;
15
16#define FLAG_N (1 << 7)
17#define FLAG_C (1 << 6)
18#define FLAG_V (1 << 5)
19#define FLAG_LT (1 << 4)
20#define FLAG_Z (1 << 3)
21#define FLAG_NOT (1 << 2)
22
23#define FLAG_MASK (FLAG_N | FLAG_C | FLAG_V | FLAG_LT | FLAG_Z)
24
25inline static UINT8 setFlag(UINT8 ccr, UINT8 flag) {
26  return ccr | flag;
27}
28
29inline static UINT8 clearFlag(UINT8 ccr, UINT8 flag) {
30  return ccr & ~flag;
31}
32
33inline static UINT8 setFlagTo(UINT8 ccr, UINT8 flag, bool set) {
34  return set ? setFlag(ccr, flag) : clearFlag(ccr, flag);
35}
36
37inline static bool isFlagSet(UINT8 ccr, UINT8 flag) {
38  return (ccr & flag) != 0;
39}
40
41inline static INT32 add(INT32 a, INT32 b, UINT8 &flags) {
42  INT32 aSign = a & 0x00800000;
43  INT32 bSign = (b & 0x00800000) == 0;
44  INT32 result = a + b;
45  INT32 resultSign = result & 0x00800000;
46  bool overflow = (aSign == bSign) && (aSign != resultSign);
47  bool carry = result & 0x01000000;
48  bool negative = resultSign != 0;
49  bool lessThan = (overflow && !negative) || (!overflow && negative);
50  flags = setFlagTo(flags, FLAG_C, carry);
51  flags = setFlagTo(flags, FLAG_N, negative);
52  flags = setFlagTo(flags, FLAG_Z, result == 0);
53  flags = setFlagTo(flags, FLAG_V, overflow);
54  flags = setFlagTo(flags, FLAG_LT, lessThan);
55  return result;
56}
57
58inline static INT32 saturate(INT32 value, UINT8 &flags) {
59  if (isFlagSet(flags, FLAG_V)) {
60    return isFlagSet(flags, FLAG_N) ? 0x00800000 : 0x007fffff;
61  } else {
62    return value;
63  }
64}
65
66inline static INT32 negate(INT32 value) {
67  return (value ^ 0x00ffffff) + 1;
68}
69
70inline static INT32 asl(INT32 value, int shift, UINT8 &flags) {
71  INT32 signBefore = value & 0x00800000;
72  INT32 result = (value << shift) & 0x00ffffff;
73  INT32 signAfter = result & 0x00800000;
74  bool overflow = signBefore != signAfter;
75  flags = setFlagTo(flags, FLAG_V, overflow);
76  return saturate(result, flags);
77}
78
79
80es5510_device::es5510_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
81  : cpu_device(mconfig, ES5510, "ES5510", tag, owner, clock)
82{
83  // Initialize ESP to mostly zeroed, configured for 64k samples of delay line memory, running (not halted)
84  icount = 0;
85  pc = 0;
86  state = STATE_HALTED;
87  bzero(gpr, 0xc0 * sizeof(gpr[0]));
88  ser0r = 0;
89  ser0l = 0;
90  ser1r = 0;
91  ser1l = 0;
92  ser2r = 0;
93  ser2l = 0;
94  ser3r = 0;
95  ser3l = 0;
96  machl = 0;
97  dil   = 0;
98  memsiz       = 0x00ffffff;
99  memmask      = 0x00000000;
100  memincrement = 0x01000000;
101  memshift     = 24;
102  dlength      = 0;
103  abase        = 0;
104  bbase        = 0;
105  dbase        = 0;
106  sigreg       = 1;
107  mulshift     = 1;
108  ccr = 0;
109  cmr = 0;
110  dol[0] = dol[1] = 0;
111  dol_count = 0;
112
113  bzero(instr, 160 * sizeof(instr[0]));
114  bzero(dram, (1<<20) * sizeof(dram[0]));
115
116  dol_latch = 0;
117  dil_latch = 0;
118  dadr_latch = 0;
119  gpr_latch = 0;
120  instr_latch = 0;
121  ram_sel = 0;
122  host_control = 0;
123
124  bzero(&alu, sizeof(alu));
125  bzero(&mulacc, sizeof(mulacc));
126}
127
128typedef es5510_device::alu_op_t alu_op_t;
129typedef es5510_device::op_select_t op_select_t;
130typedef es5510_device::op_src_dst_t op_src_dst_t;
131
132static inline INT32 SX(INT32 x) { return (x & 0x00800000) ? x | 0xff000000 : x & 0x00ffffff; }
133static inline INT32 SC(INT32 x) { return x & 0x00ffffff; }
134static inline INT64 SX64(INT64 x) { return (x & (0x0000800000000000)) ? x | 0xffff000000000000L : x & 0x0000ffffffffffffL; }
135static inline INT64 SC64(INT64 x) { return x & 0x0000ffffffffffff; }
136
137static inline const char * const REGNAME(UINT8 r) {
138  static char rn[8];
139  if (r < 234) { sprintf(rn, "GPR_%02x", r); return rn; }
140  switch(r) {
141  case 234: return "SER0R";
142  case 235: return "SER0L";
143  case 236: return "SER1R";
144  case 237: return "SER1L";
145  case 238: return "SER2R";
146  case 239: return "SER2L";
147  case 240: return "SER3R";
148  case 241: return "SER3L";
149  case 242: return "MACL";
150  case 243: return "MACH";
151  case 244: return "DIL/MEMSIZ";
152  case 245: return "DLENGTH";
153  case 246: return "ABASE";
154  case 247: return "BBASE";
155  case 248: return "DBASE";
156  case 249: return "SIGREG";
157  case 250: return "CCR";
158  case 251: return "CMR";
159  case 252: return "MINUS1";
160  case 253: return "MIN";
161  case 254: return "MAX";
162  case 255: return "ZERO";
163  }
164  return NULL;
165}
166
167static inline char * DESCRIBE_REG(char *s, UINT8 r) {
168  return stpcpy(s, REGNAME(r));
169}
170
171const alu_op_t es5510_device::ALU_OPS[16] = {
172  { 2, "ADD" },
173  { 2, "SUB" },
174  { 2, "ADDU" },
175  { 2, "SUBU" },
176  { 2, "CMP" },
177  { 2, "AND" },
178  { 2, "OR" },
179  { 2, "XOR" },
180  { 1, "ABS" },
181  { 1, "MOV" },
182  { 1, "ASL2" },
183  { 1, "ASL8" },
184  { 1, "LS15" },
185  { 2, "DIFF" },
186  { 1, "ASR" },
187  { 0, "END" },
188};
189
190// The CMP operation is not affected by being skippable
191#define OP_CMP (4)
192
193const op_select_t es5510_device::OPERAND_SELECT[16] = {
194  { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG },
195  { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY },
196  { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_BOTH },
197  { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG },
198  { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_BOTH },
199  { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG },
200  { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG },
201  { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_BOTH, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG },
202  { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_BOTH, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG },
203  { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG },
204  { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY },
205  { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_BOTH },
206  { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG },
207  { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_BOTH },
208  { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_BOTH, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG },
209  { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_BOTH, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG },
210};
211
212static inline char * DESCRIBE_SRC_DST(char *s, UINT8 reg, op_src_dst_t src_dst) {
213  switch (src_dst) {
214  case es5510_device::SRC_DST_REG:
215    return DESCRIBE_REG(s, reg);
216  case es5510_device::SRC_DST_DELAY:
217    return stpcpy(s, "Delay");
218  case es5510_device::SRC_DST_BOTH:
219    s = DESCRIBE_REG(s, reg);
220    return stpcpy(s, ",Delay");
221  }
222  // should never happen!
223  return s;
224}
225
226const es5510_device::ram_control_t es5510_device::RAM_CONTROL[8] = {
227  { es5510_device::RAM_CYCLE_READ,      es5510_device::RAM_CONTROL_DELAY,   "Read Delay+%06x" },
228  { es5510_device::RAM_CYCLE_WRITE,     es5510_device::RAM_CONTROL_DELAY,   "Write Delay+%06x" },
229  { es5510_device::RAM_CYCLE_READ,      es5510_device::RAM_CONTROL_TABLE_A, "Read Table A+%06x" },
230  { es5510_device::RAM_CYCLE_WRITE,     es5510_device::RAM_CONTROL_TABLE_A, "Write Table A+%06x" },
231  { es5510_device::RAM_CYCLE_READ,      es5510_device::RAM_CONTROL_TABLE_B, "Read Table B+%06x" },
232  { es5510_device::RAM_CYCLE_DUMP_FIFO, es5510_device::RAM_CONTROL_DELAY,   "Read Delay+%06x and Dump FIFO" },
233  { es5510_device::RAM_CYCLE_READ,      es5510_device::RAM_CONTROL_IO,      "Read I/O at %06x" },
234  { es5510_device::RAM_CYCLE_WRITE,     es5510_device::RAM_CONTROL_IO,      "Write I/o %06x" },
235};
236
237static inline char * DESCRIBE_RAM(char *s, UINT8 ramControl, UINT32 gprContents) {
238  return s + sprintf(s, es5510_device::RAM_CONTROL[ramControl].description, SC(gprContents));
239}
240
241static inline char * DESCRIBE_ALU(char *s, UINT8 opcode, UINT8 aReg, UINT8 bReg, const op_select_t &opSelect) {
242  const alu_op_t &op = es5510_device::ALU_OPS[opcode];
243
244  switch (op.operands) {
245  case 0:
246    return stpcpy(s, op.opcode);
247
248  case 1:
249    s += sprintf(s, "%s %s >", op.opcode, REGNAME(bReg));
250    return DESCRIBE_SRC_DST(s, aReg, opSelect.alu_dst);
251   
252  case 2:
253    s += sprintf(s, "%s %s,", op.opcode, REGNAME(bReg));
254    s = DESCRIBE_SRC_DST(s, aReg, opSelect.alu_src);
255    s += sprintf(s, " >");
256    return DESCRIBE_SRC_DST(s, aReg, opSelect.alu_dst);
257  }
258  return s;
259}
260
261static inline char * DESCRIBE_MAC(char *s, UINT8 mac, UINT8 cReg, UINT8 dReg, const op_select_t &opSelect)
262{
263  if (mac)
264  {
265    s += sprintf(s, "MAC + ");
266  }
267  s = DESCRIBE_REG(s, dReg);
268  s += sprintf(s, " * ");
269  s = DESCRIBE_SRC_DST(s, cReg, opSelect.mac_src);
270  s += sprintf(s, " >");
271  return DESCRIBE_SRC_DST(s, cReg, opSelect.mac_dst);
272}
273
274static inline char * DESCRIBE_INSTR(char *s, UINT64 instr, UINT32 gpr)
275{
276  UINT8 dReg = (UINT8)((instr >> 40) & 0xff);
277  UINT8 cReg = (UINT8)((instr >> 32) & 0xff);
278  UINT8 bReg = (UINT8)((instr >> 24) & 0xff);
279  UINT8 aReg = (UINT8)((instr >> 16) & 0xff);
280  UINT8 aluOpcode = (UINT8)((instr >> 12) & 0x0f);
281  UINT8 operandSelect = (UINT8)((instr >> 8) & 0x0f);
282  UINT8 skip = (UINT8)((instr >> 7) & 0x01);
283  UINT8 mac = (UINT8)((instr >> 6) & 0x01);
284  UINT8 ramControl = (UINT8)((instr >> 3) & 0x07);
285
286  const op_select_t &opSelect = es5510_device::OPERAND_SELECT[operandSelect];
287
288  s = DESCRIBE_ALU(s, aluOpcode, aReg, bReg, opSelect);
289  s += sprintf(s, "; ");
290  s = DESCRIBE_MAC(s, mac, cReg, dReg, opSelect);
291  s += sprintf(s, "; ");
292  s = DESCRIBE_RAM(s, ramControl, gpr);
293  if (skip) {
294    s += sprintf(s, "; skippable");
295  }
296
297  return s;
298}
299
300
301READ8_MEMBER(es5510_device::host_r)
302{
303  //  printf("%06x: DSP read offset %04x (data is %04x)\n",space.device().safe_pc(),offset,dsp_ram[offset]);
304
305  // VFX hack
306  if (mame_stricmp(space.machine().system().name, "vfx") == 0)
307  {
308    if (space.device().safe_pc() == 0xc091f0)
309    {
310      return space.device().state().state_int(M68K_D2);
311    }
312  }
313 
314  switch(offset)
315  {
316  case 0x00: logerror("ES5510: Read GPR latch[2]: %02x\n", (gpr_latch >> 16) & 0xff); return (gpr_latch >> 16) & 0xff;
317  case 0x01: logerror("ES5510: Read GPR latch[1]: %02x\n", (gpr_latch >>  8) & 0xff); return (gpr_latch >>  8) & 0xff;
318  case 0x02: logerror("ES5510: Read GPR latch[0]: %02x\n", (gpr_latch >>  0) & 0xff); return (gpr_latch >>  0) & 0xff;
319   
320  case 0x03: logerror("ES5510: Read INSTR latch[5]: %02x\n", (UINT8)((instr_latch >> 40) & 0xff)); return (instr_latch >> 40) & 0xff;
321  case 0x04: logerror("ES5510: Read INSTR latch[4]: %02x\n", (UINT8)((instr_latch >> 32) & 0xff)); return (instr_latch >> 32) & 0xff;
322  case 0x05: logerror("ES5510: Read INSTR latch[3]: %02x\n", (UINT8)((instr_latch >> 24) & 0xff)); return (instr_latch >> 24) & 0xff;
323  case 0x06: logerror("ES5510: Read INSTR latch[2]: %02x\n", (UINT8)((instr_latch >> 16) & 0xff)); return (instr_latch >> 16) & 0xff;
324  case 0x07: logerror("ES5510: Read INSTR latch[1]: %02x\n", (UINT8)((instr_latch >>  8) & 0xff)); return (instr_latch >>  8) & 0xff;
325  case 0x08: logerror("ES5510: Read INSTR latch[0]: %02x\n", (UINT8)((instr_latch >>  0) & 0xff)); return (instr_latch >>  0) & 0xff;
326   
327  case 0x09: logerror("ES5510: Read DIL latch[2]: %02x\n", (dil_latch >> 16) & 0xff); return (dil_latch >> 16) & 0xff;
328  case 0x0a: logerror("ES5510: Read DIL latch[1]: %02x\n", (dil_latch >>  8) & 0xff); return (dil_latch >>  8) & 0xff;
329  case 0x0b: logerror("ES5510: Read DIL latch[0]: %02x\n", (dil_latch >>  0) & 0xff); return (dil_latch >>  0) & 0xff; //TODO: docs says that this always returns 0
330   
331  case 0x0c: logerror("ES5510: Read DOL latch[2]: %02x\n", (dol_latch >> 16) & 0xff); return (dol_latch >> 16) & 0xff;
332  case 0x0d: logerror("ES5510: Read DOL latch[1]: %02x\n", (dol_latch >>  8) & 0xff); return (dol_latch >>  8) & 0xff;
333  case 0x0e: logerror("ES5510: Read DOL latch[0]: %02x\n", (dol_latch >>  0) & 0xff); return (dol_latch >>  0) & 0xff; //TODO: docs says that this always returns 0
334   
335  case 0x0f: logerror("ES5510: Read DADR latch[2]: %02x\n", (dadr_latch >> 16) & 0xff); return (dadr_latch >> 16) & 0xff;
336  case 0x10: logerror("ES5510: Read DADR latch[1]: %02x\n", (dadr_latch >>  8) & 0xff); return (dadr_latch >>  8) & 0xff;
337  case 0x11: logerror("ES5510: Read DADR latch[0]: %02x\n", (dadr_latch >>  0) & 0xff); return (dadr_latch >>  0) & 0xff;
338   
339  case 0x12: logerror("ES5510: Reading Host Control\n"); return 0; // Host Control
340   
341  case 0x16: return 0x27; // Program Counter, for test purposes only
342  }
343 
344  // default: 0.
345  return 0x00;
346}
347
348WRITE8_MEMBER(es5510_device::host_w)
349{
350  static char buf[1024];
351  switch (offset) {
352  case 0x00:
353    gpr_latch = (gpr_latch&0x00ffff) | ((data&0xff)<<16);
354    logerror("ES5510: Write GPR latch[2] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch));
355    break;
356  case 0x01:
357    gpr_latch = (gpr_latch&0xff00ff) | ((data&0xff)<< 8);
358    logerror("ES5510: Write GPR latch[1] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch));
359    break;
360  case 0x02:
361    gpr_latch = (gpr_latch&0xffff00) | ((data&0xff)<< 0);
362    logerror("ES5510: Write GPR latch[0] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch));
363    break;
364
365    /* 0x03 to 0x08 INSTR Register */
366  case 0x03: instr_latch = ((instr_latch&0x00ffffffffff) | ((INT64)data&0xff)<<40); logerror("ES5510: Write INSTR latch[5] = %02x -> %012llx\n", data, instr_latch); break;
367  case 0x04: instr_latch = ((instr_latch&0xff00ffffffff) | ((INT64)data&0xff)<<32); logerror("ES5510: Write INSTR latch[4] = %02x -> %012llx\n", data, instr_latch); break;
368  case 0x05: instr_latch = ((instr_latch&0xffff00ffffff) | ((INT64)data&0xff)<<24); logerror("ES5510: Write INSTR latch[3] = %02x -> %012llx\n", data, instr_latch); break;
369  case 0x06: instr_latch = ((instr_latch&0xffffff00ffff) | ((INT64)data&0xff)<<16); logerror("ES5510: Write INSTR latch[2] = %02x -> %012llx\n", data, instr_latch); break;
370  case 0x07: instr_latch = ((instr_latch&0xffffffff00ff) | ((INT64)data&0xff)<< 8); logerror("ES5510: Write INSTR latch[1] = %02x -> %012llx\n", data, instr_latch); break;
371  case 0x08: instr_latch = ((instr_latch&0xffffffffff00) | ((INT64)data&0xff)<< 0); logerror("ES5510: Write INSTR latch[0] = %02x -> %012llx\n", data, instr_latch); break;
372
373    /* 0x09 to 0x0b DIL Register (r/o) */
374
375  case 0x0c: dol_latch = (dol_latch&0x00ffff) | ((data&0xff)<<16); logerror("ES5510: Write DOL latch[2] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch)); break;
376  case 0x0d: dol_latch = (dol_latch&0xff00ff) | ((data&0xff)<< 8); logerror("ES5510: Write DOL latch[1] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch)); break;
377  case 0x0e: dol_latch = (dol_latch&0xffff00) | ((data&0xff)<< 0); logerror("ES5510: Write DOL latch[0] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch)); break; //TODO: docs says that this always returns 0xff
378
379  case 0x0f:
380    dadr_latch = (dadr_latch&0x00ffff) | ((data&0xff)<<16);
381    if (ram_sel)
382    {
383      dil_latch = dram[dadr_latch];
384    }
385    else
386    {
387      dram[dadr_latch] = dol_latch;
388    }
389    break;
390
391  case 0x10: dadr_latch = (dadr_latch&0xff00ff) | ((data&0xff)<< 8); break;
392  case 0x11: dadr_latch = (dadr_latch&0xffff00) | ((data&0xff)<< 0); break;
393
394    /* 0x12 Host Control */
395
396  case 0x14: ram_sel = data & 0x80; /* bit 6 is i/o select, everything else is undefined */break;
397
398    /* 0x16 Program Counter (test purpose, r/o?) */
399    /* 0x17 Internal Refresh counter (test purpose) */
400    /* 0x18 Host Serial Control */
401  case 0x18:
402    logerror("ES5510: Write Host Serial control %02x: %s, %s, ser3 %s, ser2 %s, ser1 %s, ser0 %s\n", data,
403        data&0x80 ? "Master" : "Slave",
404        data&0x40 ? "Sony" : "I2S",
405        data & 0x20 ? "Out" : "In",
406        data & 0x10 ? "Out" : "In",
407        data & 0x08 ? "Out" : "In",
408        data & 0x04 ? "Out" : "In");
409    break;
410
411    /* 0x1f Halt enable (w) / Frame Counter (r) */
412  case 0x1F:
413    logerror("ES5510: Write Halt Enable %02x; HALT line is %d\n", data, input_state(ES5510_HALT));
414    if (input_state(ES5510_HALT)) {
415      logerror("ES5510: Write to Halt Enable while HALT line is asserted: Halting!\n");
416      state = STATE_HALTED;
417    }
418    break;
419
420  case 0x80: /* Read select - GPR + INSTR */
421    logerror("ES5510: Read INSTR+GPR %02x (%s): %012llx %06x (%d)\n", data, REGNAME(data & 0xff), instr[data] & 0xffffffffffffL, gpr[data] & 0xffffff, gpr[data]);
422
423    /* Check if an INSTR address is selected */
424    if (data < 0xa0) {
425      instr_latch = instr[data];
426    }
427    if (data < 0xc0) {
428      gpr_latch = gpr[data] & 0xffffff;
429    } else if (data >= 0xea) {
430      gpr_latch = read_reg(data);
431    }
432    break;
433
434  case 0xa0: /* Write select - GPR */
435    logerror("ES5510: Write GPR %02x (%s): %06x (%d)\n",data, REGNAME(data&0xff), gpr_latch, SX(gpr_latch));
436    write_reg(data, gpr_latch);
437    break;
438
439  case 0xc0: /* Write select - INSTR */
440    DESCRIBE_INSTR(buf, instr_latch, gpr[data]);
441    logerror("ES5510: Write INSTR %02x %012llx: %s\n",data, instr_latch&0xffffffffffffL, buf);
442    if (data < 0xa0) {
443      instr[data] = instr_latch&0xffffffffffffL;
444    }
445    break;
446
447  case 0xe0: /* Write select - GPR + INSTR */
448    DESCRIBE_INSTR(buf, instr_latch, gpr_latch);
449    logerror("ES5510:  Write INSTR+GPR %02x (%s): %012llx %06x (%d): %s\n",data, REGNAME(data&0xff), instr_latch, gpr_latch, SX(gpr_latch), buf);
450    if (data < 0xa0) {
451      instr[data] = instr_latch;
452    }
453    write_reg(data, gpr_latch);
454    break;
455  }
456}
457
458void es5510_device::device_start() {
459  m_icountptr = &icount;
460  state_add(STATE_GENPC,"GENPC", pc).noshow();
461}
462
463void es5510_device::device_reset() {
464  pc = 0x00;
465  memset(gpr, 0, sizeof(*gpr) * 0xc0);
466  memset(instr, 0, sizeof(*instr) * 0xa0);
467  memset(dram, 0, sizeof(*dram) * (1<<20));
468  state = STATE_RUNNING;
469  dil_latch = dol_latch = dadr_latch = gpr_latch = 0;
470  instr_latch = UINT64(0);
471  ram_sel = 0;
472  host_control = 0;
473}
474
475const address_space_config *es5510_device::memory_space_config(address_spacenum spacenum) const {
476  return 0;
477}
478
479UINT64 es5510_device::execute_clocks_to_cycles(UINT64 clocks) const {
480  return clocks / 3;
481}
482
483UINT64 es5510_device::execute_cycles_to_clocks(UINT64 cycles) const {
484  return cycles * 3;
485}
486
487UINT32 es5510_device::execute_min_cycles() const {
488  return 1;
489}
490
491UINT32 es5510_device::execute_max_cycles() const {
492  return 1;
493}
494
495UINT32 es5510_device::execute_input_lines() const {
496  return 1;
497}
498
499void es5510_device::execute_run() {
500  while (icount > 0) {
501    if (state == STATE_HALTED) {
502      // Currently halted, sample the HALT line
503      if (input_state(ES5510_HALT)) {
504   // remain halted
505   host_control |= 0x04; // Signal Host Access OK
506      } else {
507   logerror("ES5501: Starting!\n");
508   state = STATE_RUNNING;
509   
510   UINT8 addr;
511   char buf[1024];
512   for (addr = 0; addr < 0xa0; addr++) {
513     DESCRIBE_INSTR(buf, instr[addr], gpr[addr]);
514     logerror("%02x: %012llx %06x  %s\n", addr, instr[addr], gpr[addr]&0xffffff, buf);
515   }
516   for (; addr < 0xc0; addr++) {
517     logerror("%02x: %06x (%d)\n", addr, gpr[addr]&0xffffff, gpr[addr]);
518   }
519      }
520    } else {
521      // currently running, execute one instruction.
522
523      ram_pp = ram_p;
524      ram_p = ram;
525     
526      // *** T0, clock high
527      // --- nothing to do!
528
529      // *** T0, clock low
530      // --- Read instruction N
531      UINT64 instr = this->instr[pc];
532
533      // --- RAM cycle N-2 (if a Read cycle): data read from bus is stored in DIL
534      if (ram_pp.cycle != RAM_CYCLE_WRITE) {
535   if (ram_pp.io) { // read from I/O and store into DIL
536     dil = 0; // read_io(ram_pp.address);;
537   } else { // read from DRAM and store into DIL
538     dil = dram[ram_pp.address];
539   }
540      }
541
542      // --- start of RAM cycle N
543      ram_control_t ramControl = RAM_CONTROL[((instr >> 3) & 0x07)];
544      ram.cycle = ramControl.cycle;
545      ram.io = ramControl.access == RAM_CONTROL_IO;
546
547      // --- RAM cycle N: read offset N
548      INT32 offset = gpr[pc];
549      switch(ramControl.access) {
550      case RAM_CONTROL_DELAY:
551   ram.address = (((dbase + offset) % (dlength + 1)) & memmask) >> memshift;
552   break;
553      case RAM_CONTROL_TABLE_A:
554   ram.address = ((abase + offset) & memmask) >> memshift;
555   break;
556      case RAM_CONTROL_TABLE_B:
557   ram.address = ((bbase + offset) & memmask) >> memshift;
558   break;
559      case RAM_CONTROL_IO:
560   ram.address = offset & 0x00fffff0; // mask off the low 4 bits
561   break;
562      }
563     
564      // *** T1, clock high
565      // --- Decode instruction N;
566      //     we will do this both here and in stages as the different parts of the instruction complete & recommence.
567
568      UINT8 operandSelect = (UINT8)((instr >> 8) & 0x0f);
569      const op_select_t &opSelect = OPERAND_SELECT[operandSelect];
570      bool skip = false;
571      bool skippable = ((instr >> 7) & 0x01) != 0; // aka the 'SKIP' bit in the instruction word
572      if (skippable) {
573   bool skipConditionSatisfied = (ccr & cmr & FLAG_MASK) != 0;
574   if (isFlagSet(cmr, FLAG_NOT)) {
575     skipConditionSatisfied = !skipConditionSatisfied;
576   }
577   skip = skipConditionSatisfied;
578      }
579
580      // --- Write Multiplier result N-1
581      if (mulacc.write_result) {
582   mulacc.product = (mulacc.cValue * mulacc.dValue) << mulshift;
583   mulacc.result = (mulacc.accumulate ? machl : 0) + mulacc.product;
584   INT32 tmp = (mulacc.result & 0x0000ffffff000000) >> 24;
585   if (mulacc.dst & SRC_DST_REG) {
586     machl = mulacc.result;
587     write_reg(mulacc.cReg, tmp);
588   }
589   if (mulacc.dst & SRC_DST_DELAY) {
590     write_to_dol(tmp);
591   }
592      }
593
594      // *** T1, clock low
595      // --- Start of multiplier cycle N
596      mulacc.cReg = (UINT8)((instr >> 32) & 0xff);
597      mulacc.dReg = (UINT8)((instr >> 40) & 0xff);
598      mulacc.src = opSelect.mac_src;
599      mulacc.dst = opSelect.mac_dst;
600      mulacc.accumulate = ((instr >> 6) & 0x01) != 0;
601      mulacc.write_result = skip;
602
603      // --- Read Multiplier Operands N
604      if (mulacc.src == SRC_DST_REG) {
605   mulacc.cValue = read_reg(mulacc.cReg);
606      } else { // must be SRC_DST_DELAY
607   mulacc.cValue = dil;
608      }
609      mulacc.dValue = read_reg(mulacc.dReg);
610     
611      // *** T2, clock high
612      // --- Write ALU Result N-1
613      if (alu.write_result) {
614   UINT8 flags = ccr;
615   alu.result = alu_operation(alu.op, alu.aValue, alu.bValue, flags);
616   if (alu.dst & SRC_DST_REG) {
617     write_reg(alu.aReg, alu.result);
618   }
619   if (alu.dst & SRC_DST_DELAY) {
620     write_to_dol(alu.result);
621   }
622   if (alu.update_ccr) {
623     ccr = flags;
624   }
625      }
626
627      // *** T2, clock low
628      // --- Start of ALU cycle N
629      alu.aReg = (instr >> 16) & 0xff;
630      alu.bReg = (instr >> 24) & 0xff;
631      alu.op = (instr >> 12) & 0x0f;
632      alu.src = opSelect.alu_src;
633      alu.dst = opSelect.alu_dst;
634      alu.write_result = skip;
635      alu.update_ccr = !skippable || (alu.op == OP_CMP);
636
637      // --- Read ALU Operands N
638      alu_op_t aluOp = ALU_OPS[alu.op];
639      if (aluOp.operands == 2) {
640   if (alu.src == SRC_DST_REG) {
641     alu.aValue = read_reg(alu.aReg);
642   } else { // must be SRC_DST_DELAY
643     alu.aValue = dil;
644   }
645      }
646      if (aluOp.operands >= 1) {
647   alu.bValue = read_reg(alu.bReg);
648      }
649
650      // --- RAM cycle N-1
651      if (ram_p.cycle != RAM_CYCLE_READ) {
652   if (ram_p.cycle == RAM_CYCLE_WRITE) {
653     // If this is a write cycle, write the frontmost DOL value to RAM or I/O
654     if (ram_p.io) {
655       // write_io(ram_p.io, dol[0]);
656     } else {
657       dram[ram_p.address] = dol[0];
658     }
659   }
660   // If this is a Write or Dump cycle, eject the frontmost DL value.
661   dol[0] = dol[1];
662   if (dol_count > 0) {
663     --dol_count;
664   }
665      }
666
667      ++pc;
668    }
669    --icount;
670  }
671}
672
673UINT32 es5510_device::disasm_min_opcode_bytes() const
674{
675  return 6;
676}
677
678UINT32 es5510_device::disasm_max_opcode_bytes() const
679{
680  return 6;
681}
682
683offs_t es5510_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
684{
685  return pc;
686}
687
688INT32 es5510_device::read_reg(UINT8 reg)
689{
690  if (reg < 0xc0) {
691    return gpr[reg];
692  } else {
693    switch(reg)
694    {
695    case 234: return ser0r;
696    case 235: return ser0l;
697    case 236: return ser1r;
698    case 237: return ser1l;
699    case 238: return ser2r;
700    case 239: return ser2l;
701    case 240: return ser3r;
702    case 241: return ser3l;
703    case 242: return (machl >>  0) & 0x00ffffff;
704    case 243: return (machl >> 24) & 0x00ffffff;
705    case 244: return dil; // DIL when reading
706    case 245: return dlength;
707    case 246: return abase;
708    case 247: return bbase;
709    case 248: return dbase;
710    case 249: return sigreg;
711    case 250: return ccr;
712    case 251: return cmr;
713    case 252: return 0x00ffffff;
714    case 253: return 0x00800000;
715    case 254: return 0x007fffff;
716    case 255: return 0x00000000;
717    default:
718      // unknown SPR
719      return 0;
720    }
721  }
722}
723
724INT8 countLowOnes(INT32 x) {
725  INT8 n = 0;
726  while ((x & 1) == 1) {
727    ++n;
728    x >>= 1;
729  }
730  return n;
731}
732
733void es5510_device::write_reg(UINT8 reg, INT32 value)
734{
735  value &= 0x00ffffff;
736  if (reg < 0xc0) {
737    gpr[reg] = value;
738  } else {
739    switch(reg)
740    {
741    case 234: ser0r = value;
742    case 235: ser0l = value;
743    case 236: ser1r = value;
744    case 237: ser1l = value;
745    case 238: ser2r = value;
746    case 239: ser2l = value;
747    case 240: ser3r = value;
748    case 241: ser3l = value;
749    case 242: machl = (machl & ~((INT64)0x00ffffff <<  0)) | (value <<  0);
750    case 243: machl = (machl & ~((INT64)0x00ffffff << 24)) | (value << 24);
751    case 244:
752      memshift = countLowOnes(value);
753      memsiz = 0x00ffffff >> (24 - memshift);
754      memmask = 0x00ffffff & ~memsiz;
755      memincrement = 1 << memshift;
756    case 245: dlength = value;
757    case 246: abase = value;
758    case 247: bbase = value;
759    case 248: dbase = value;
760    case 249: sigreg = (value != 0);
761    case 250: ccr = (value >> 16) & FLAG_MASK;
762    case 251: cmr = (value >> 16) & (FLAG_MASK | FLAG_NOT);
763    case 252: // no-op
764    case 253: // no-op
765    case 254: // no-op
766    case 255: // no-op
767    default:
768      // unknown register
769      ;
770    }
771  }
772}
773
774void es5510_device::write_to_dol(INT32 value) {
775  if (dol_count >= 2) {
776    dol[0] = dol[1];
777    dol[1] = value;
778  } else {
779    dol[dol_count++] = value;
780  }
781}
782
783INT32 es5510_device::alu_operation(UINT8 op, INT32 a, INT32 b, UINT8 &flags) {
784  switch(op) {
785  case 0x0: // ADD
786    return saturate(add(a, b, flags), flags);
787   
788  case 0x1: // SUB
789    return saturate(add(a, negate(b), flags), flags);
790
791  case 0x2: // ADDU
792    return add(a, b, flags);
793
794  case 0x3: // SUBU
795    return add(a, negate(b), flags);
796
797  case 0x4: // CMP
798    add(a, negate(b), flags);
799    return a;
800
801  case 0x5: // AND
802    a &= b;
803    setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0);
804    setFlagTo(flags, FLAG_Z, a == 0);
805    return a;
806
807  case 0x6: // OR
808    a |= b;
809    setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0);
810    setFlagTo(flags, FLAG_Z, a == 0);
811    return a;
812
813  case 0x7: // XOR
814    a ^= b;
815    setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0);
816    setFlagTo(flags, FLAG_Z, a == 0);
817    return a;
818
819  case 0x8: // ABS
820  {
821    clearFlag(flags, FLAG_N);
822    bool isNegative = (a & 0x00800000) != 0;
823    setFlagTo(flags, FLAG_C, isNegative);
824    if (isNegative) {
825      a = (a ^ 0x00ffffff) + 1;
826    }
827    return a;
828  }
829
830  case 0x9: // MOV
831    return b;
832
833  case 0xA: // ASL2
834    return asl(b, 2, flags);
835
836  case 0xB: // ASL8
837    return asl(b, 8, flags);
838
839  case 0xC: // LS15
840    return (b << 15) & 0x007fffff;
841
842  case 0xD: // DIFF
843    return add(0x007fffff, negate(b), flags);
844
845  case 0xE: // ASR
846    return (b >> 1) | (b & 0x00800000);
847
848  case 0xF: // END
849    // sample the HALT line
850    if (input_state(ES5510_HALT)) {
851      // halt
852      state = STATE_HALTED;     
853      host_control |= 0x04; // Signal Host Access OK
854    }
855    // update the delay line base pointer
856    dbase -= memincrement;
857    if (dbase < 0) {
858      dbase = dlength;
859    }
860
861  default:
862    return 0;
863  }
864}
Property changes on: trunk/src/emu/cpu/es5510/es5510.c
Added: svn:eol-style
   + native
Added: svn:mime-type
   + text/plain
trunk/src/emu/cpu/es5510/es5510.h
r0r20713
1/**********************************************************************************************
2 *
3 *   es5510.h - Ensoniq ES5510 (ESP) driver
4 *   by Christian Brunschen
5 *
6 **********************************************************************************************/
7
8#pragma once
9
10#ifndef __ES5510_H__
11#define __ES5510_H__
12
13#include "emu.h"
14
15class es5510_device : public cpu_device {
16 public:
17  es5510_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
18
19  DECLARE_READ8_MEMBER(host_r);
20  DECLARE_WRITE8_MEMBER(host_w);
21
22  DECLARE_READ16_MEMBER(ser_r);
23  DECLARE_WRITE16_MEMBER(ser_w);
24
25  enum line_t {
26    ES5510_HALT = 0
27  };
28
29  enum state_t {
30    STATE_RUNNING = 0,
31    STATE_HALTED = 1
32  };
33
34  struct alu_op_t {
35    int operands;
36    const char * const opcode;
37  };
38
39  enum op_src_dst_t {
40    SRC_DST_REG =   1 << 0,
41    SRC_DST_DELAY = 1 << 1,
42    SRC_DST_BOTH =  (1 << 0) | (1 << 1)
43  };
44 
45  struct op_select_t {
46    const op_src_dst_t alu_src;
47    const op_src_dst_t alu_dst;
48    const op_src_dst_t mac_src;
49    const op_src_dst_t mac_dst;
50  };
51
52  enum ram_control_access_t {
53    RAM_CONTROL_DELAY = 0,
54    RAM_CONTROL_TABLE_A,
55    RAM_CONTROL_TABLE_B,
56    RAM_CONTROL_IO
57  };
58
59  enum ram_cycle_t {
60    RAM_CYCLE_READ = 0,
61    RAM_CYCLE_WRITE = 1,
62    RAM_CYCLE_DUMP_FIFO = 2
63  };
64
65  struct ram_control_t {
66    ram_cycle_t cycle;
67    ram_control_access_t access;
68    const char * const description;
69  };
70
71  static const alu_op_t ALU_OPS[16];
72  static const op_select_t OPERAND_SELECT[16];
73  static const ram_control_t RAM_CONTROL[8];
74
75  struct alu_t {
76    UINT8 aReg;
77    UINT8 bReg;
78    op_src_dst_t src;
79    op_src_dst_t dst;
80    UINT8 op;
81    INT32 aValue;
82    INT32 bValue;
83    INT32 result;
84    bool update_ccr;
85    bool write_result;
86  };
87
88  struct mulacc_t {
89    UINT8 cReg;
90    UINT8 dReg;
91    op_src_dst_t src;
92    op_src_dst_t dst;
93    bool accumulate;
94    INT64 cValue;
95    INT64 dValue;
96    INT64 product;
97    INT64 result;
98    bool write_result;
99  };
100
101  struct ram_t {
102    INT32 address;     // up to 20 bits, left-justified within the right 24 bits of the 32-bit word
103    bool io;           // I/O space, rather than delay line memory
104    ram_cycle_t cycle; // cycle type
105  };
106
107 protected:
108  virtual void device_start();
109  virtual void device_reset();
110  virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
111  virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const;
112  virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const;
113  virtual UINT32 execute_min_cycles() const;
114  virtual UINT32 execute_max_cycles() const;
115  virtual UINT32 execute_input_lines() const;
116  virtual void execute_run();
117  virtual UINT32 disasm_min_opcode_bytes() const;
118  virtual UINT32 disasm_max_opcode_bytes() const;
119  virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
120
121  INT32 read_reg(UINT8 reg);
122  void write_reg(UINT8 reg, INT32 value);
123  void write_to_dol(INT32 value);
124
125  INT32 alu_operation(UINT8 op, INT32 aValue, INT32 bValue, UINT8 &flags);
126
127 private:
128  int icount;
129  UINT8 pc;
130  state_t state;
131  INT32 gpr[0xc0];     // 24 bits, right justified and sign extended
132  INT32 ser0r;
133  INT32 ser0l;
134  INT32 ser1r;
135  INT32 ser1l;
136  INT32 ser2r;
137  INT32 ser2l;
138  INT32 ser3r;
139  INT32 ser3l;
140  INT64 machl;      // 48 bits, right justified and sign extended
141  INT32 dil;
142  INT32 memsiz;
143  INT32 memmask;
144  INT32 memincrement;
145  INT8 memshift;
146  INT32 dlength;
147  INT32 abase;
148  INT32 bbase;
149  INT32 dbase;
150  INT32 sigreg;
151  int mulshift;
152  INT8 ccr;         // really, 5 bits, left justified
153  INT8 cmr;         // really, 6 bits, left justified
154  INT32 dol[2];
155  int dol_count;
156
157  UINT64 instr[160];    // 48 bits, right justified
158  UINT16 dram[1<<20];   // there are up to 20 address bits (at least 16 expected), left justified within the 24 bits of a gpr or dadr; we preallocate all of it.
159
160  // latch registers for host interaction
161  INT32  dol_latch;     // 24 bits
162  INT32  dil_latch;     // 24 bits
163  UINT32 dadr_latch;    // 24 bits
164  INT32  gpr_latch;     // 24 bits, holding up to 20 address bits, left justified
165  UINT64 instr_latch;   // 48 bits, right justified
166  UINT8  ram_sel;       // effectively a boolean
167  UINT8  host_control;  //
168
169  // currently executing instruction(s)
170  alu_t alu;
171  mulacc_t mulacc;
172  ram_t ram, ram_p, ram_pp; // ram operations for cycles N, N-1 and N-2
173};
174
175extern const device_type ES5510;
176
177#endif // __ES5510_H__
Property changes on: trunk/src/emu/cpu/es5510/es5510.h
Added: svn:eol-style
   + native
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trunk/src/mess/drivers/esq5505.c
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3939    4 = WAVE
4040    5 = SELECT VOICE
4141    6 = MIXER/SHAPER
42    7 = EFFECT
42    7 = EFFECT
4343    8 = COMPARE
4444    9 = COPY EFFECTS PARAMETERS
4545    10 = LFO
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9999
100100***************************************************************************/
101101
102#include <cstdio>
103
102104#include "emu.h"
103105#include "cpu/m68000/m68000.h"
104106#include "sound/es5506.h"
105107#include "machine/n68681.h"
108#include "cpu/es5510/es5510.h"
106109#include "machine/wd_fdc.h"
107110#include "machine/hd63450.h"    // compatible with MC68450, which is what these really have
108111#include "formats/esq16_dsk.h"
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117120#define SQ1     (2)
118121
119122#define KEYBOARD_HACK (1)   // turn on to play the SQ-1, SD-1, and SD-1 32-voice: Z and X are program up/down, A/S/D/F/G/H/J/K/L and Q/W/E/R/T/Y/U play notes
120#define HACK_VIA_MIDI   (0) // won't work right now
121123
122124#if KEYBOARD_HACK
123#if HACK_VIA_MIDI
124static int program = 0;
125#else
126125static int shift = 32;
127126#endif
128#endif
129127
130128class esq5505_state : public driver_device
131129{
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134132   : driver_device(mconfig, type, tag),
135133      m_maincpu(*this, "maincpu"),
136134      m_duart(*this, "duart"),
135      m_esp(*this, "esp"),
137136      m_fdc(*this, "wd1772"),
138137      m_panel(*this, "panel"),
139138      m_dmac(*this, "mc68450"),
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142141
143142   required_device<m68000_device> m_maincpu;
144143   required_device<duartn68681_device> m_duart;
144   required_device<es5510_device> m_esp;
145145   optional_device<wd1772_t> m_fdc;
146146   required_device<esqpanel_device> m_panel;
147147   optional_device<hd63450_device> m_dmac;
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162162
163163   int m_system_type;
164164   UINT8 m_duart_io;
165   UINT8 otis_irq_state;
166   UINT8 dmac_irq_state;
167   int dmac_irq_vector;
168   UINT8 duart_irq_state;
169   int duart_irq_vector;
165170
171   void update_irq_to_maincpu();
172
166173   DECLARE_FLOPPY_FORMATS( floppy_formats );
167174
168175private:
169   UINT16  es5510_dsp_ram[0x200];
170   UINT32  es5510_gpr[0xc0];
171   UINT32  es5510_dram[1<<24];
172   UINT32  es5510_dol_latch;
173   UINT32  es5510_dil_latch;
174   UINT32  es5510_dadr_latch;
175   UINT32  es5510_gpr_latch;
176   UINT8   es5510_ram_sel;
177
178176   UINT16  *m_rom, *m_ram;
179177
180178public:
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193191   SLOT_INTERFACE( "35dd", FLOPPY_35_DD )
194192SLOT_INTERFACE_END
195193
196void esq5505_state::machine_reset()
197{
198   m_rom = (UINT16 *)machine().root_device().memregion("osrom")->base();
199   m_ram = (UINT16 *)machine().root_device().memshare("osram")->ptr();
194static int maincpu_irq_acknowledge_callback(device_t *device, int irqnum) {
195  // We immediately update the interrupt presented to the CPU, so that it doesn't
196  // end up retrying the same interrupt over and over. We then return the appropriate vector.
197  esq5505_state *esq5505 = device->machine().driver_data<esq5505_state>();
198  int vector = 0;
199  switch(irqnum) {
200  case 1:
201    esq5505->otis_irq_state = 0;
202    vector = M68K_INT_ACK_AUTOVECTOR;
203    break;
204  case 2:
205    esq5505->dmac_irq_state = 0;
206    vector = esq5505->dmac_irq_vector;
207    break;
208  case 3:
209    esq5505->duart_irq_state = 0;
210    vector = esq5505->duart_irq_vector;
211    break;
212  default:
213    printf("\nUnexpected IRQ ACK Callback: IRQ %d\n", irqnum);
214    return 0;
215  }
216  esq5505->update_irq_to_maincpu();
217  return vector;
200218}
201219
202READ16_MEMBER(esq5505_state::es5510_dsp_r)
220void esq5505_state::machine_reset()
203221{
204//  printf("%06x: DSP read offset %04x (data is %04x)\n",space.device().safe_pc(),offset,es5510_dsp_ram[offset]);
205
206   // VFX hack
207   if (mame_stricmp(space.machine().system().name, "vfx") == 0)
208   {
209      if (space.device().safe_pc() == 0xc091f0)
210      {
211         return space.device().state().state_int(M68K_D2);
212      }
213   }
214
215   switch(offset)
216   {
217      case 0x09: return (es5510_dil_latch >> 16) & 0xff;
218      case 0x0a: return (es5510_dil_latch >> 8) & 0xff;
219      case 0x0b: return (es5510_dil_latch >> 0) & 0xff; //TODO: docs says that this always returns 0
220   }
221
222   if (offset==0x12) return 0;
223
224   if (offset==0x16) return 0x27;
225
226   return es5510_dsp_ram[offset];
222   m_rom = (UINT16 *)(void *)machine().root_device().memregion("osrom")->base();
223   m_ram = (UINT16 *)(void *)machine().root_device().memshare("osram")->ptr();
224   m_maincpu->set_irq_acknowledge_callback(maincpu_irq_acknowledge_callback);
227225}
228226
229WRITE16_MEMBER(esq5505_state::es5510_dsp_w)
230{
231   UINT8 *snd_mem = (UINT8 *)space.machine().root_device().memregion("waverom")->base();
232
233   COMBINE_DATA(&es5510_dsp_ram[offset]);
234
235   switch (offset) {
236      case 0x00: es5510_gpr_latch=(es5510_gpr_latch&0x00ffff)|((data&0xff)<<16); break;
237      case 0x01: es5510_gpr_latch=(es5510_gpr_latch&0xff00ff)|((data&0xff)<< 8); break;
238      case 0x02: es5510_gpr_latch=(es5510_gpr_latch&0xffff00)|((data&0xff)<< 0); break;
239
240      /* 0x03 to 0x08 INSTR Register */
241      /* 0x09 to 0x0b DIL Register (r/o) */
242
243      case 0x0c: es5510_dol_latch=(es5510_dol_latch&0x00ffff)|((data&0xff)<<16); break;
244      case 0x0d: es5510_dol_latch=(es5510_dol_latch&0xff00ff)|((data&0xff)<< 8); break;
245      case 0x0e: es5510_dol_latch=(es5510_dol_latch&0xffff00)|((data&0xff)<< 0); break; //TODO: docs says that this always returns 0xff
246
247      case 0x0f:
248         es5510_dadr_latch=(es5510_dadr_latch&0x00ffff)|((data&0xff)<<16);
249         if(es5510_ram_sel)
250            es5510_dil_latch = es5510_dram[es5510_dadr_latch];
251         else
252            es5510_dram[es5510_dadr_latch] = es5510_dol_latch;
253         break;
254
255      case 0x10: es5510_dadr_latch=(es5510_dadr_latch&0xff00ff)|((data&0xff)<< 8); break;
256      case 0x11: es5510_dadr_latch=(es5510_dadr_latch&0xffff00)|((data&0xff)<< 0); break;
257
258      /* 0x12 Host Control */
259
260      case 0x14: es5510_ram_sel = data & 0x80; /* bit 6 is i/o select, everything else is undefined */break;
261
262      /* 0x16 Program Counter (test purpose, r/o?) */
263      /* 0x17 Internal Refresh counter (test purpose) */
264      /* 0x18 Host Serial Control */
265      /* 0x1f Halt enable (w) / Frame Counter (r) */
266
267      case 0x80: /* Read select - GPR + INSTR */
268   //      logerror("ES5510:  Read GPR/INSTR %06x (%06x)\n",data,es5510_gpr[data]);
269
270         /* Check if a GPR is selected */
271         if (data<0xc0) {
272            //es_tmp=0;
273            es5510_gpr_latch=es5510_gpr[data];
274         }// else es_tmp=1;
275         break;
276
277      case 0xa0: /* Write select - GPR */
278   //      logerror("ES5510:  Write GPR %06x %06x (0x%04x:=0x%06x\n",data,es5510_gpr_latch,data,snd_mem[es5510_gpr_latch>>8]);
279         if (data<0xc0)
280            es5510_gpr[data]=snd_mem[es5510_gpr_latch>>8];
281         break;
282
283      case 0xc0: /* Write select - INSTR */
284   //      logerror("ES5510:  Write INSTR %06x %06x\n",data,es5510_gpr_latch);
285         break;
286
287      case 0xe0: /* Write select - GPR + INSTR */
288   //      logerror("ES5510:  Write GPR/INSTR %06x %06x\n",data,es5510_gpr_latch);
289         break;
290   }
227void esq5505_state::update_irq_to_maincpu() {
228  //printf("\nupdating IRQ state: have OTIS=%d, DMAC=%d, DUART=%d\n", otis_irq_state, dmac_irq_state, duart_irq_state);
229  if (duart_irq_state) {
230    m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
231    m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
232    m_maincpu->set_input_line_and_vector(M68K_IRQ_3, ASSERT_LINE, duart_irq_vector);
233  } else if (dmac_irq_state) {
234    m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
235    m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
236    m_maincpu->set_input_line_and_vector(M68K_IRQ_2, ASSERT_LINE, dmac_irq_vector);
237  } else if (otis_irq_state) {
238    m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
239    m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
240    m_maincpu->set_input_line(M68K_IRQ_1, ASSERT_LINE);
241  } else {
242    m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
243    m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
244    m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
245  }
291246}
292247
293248READ16_MEMBER(esq5505_state::lower_r)
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297252   // get pointers when 68k resets
298253   if (!m_rom)
299254   {
300      m_rom = (UINT16 *)machine().root_device().memregion("osrom")->base();
301      m_ram = (UINT16 *)machine().root_device().memshare("osram")->ptr();
255     m_rom = (UINT16 *)(void *)machine().root_device().memregion("osrom")->base();
256     m_ram = (UINT16 *)(void *)machine().root_device().memshare("osram")->ptr();
302257   }
303258
304   if (offset < 0x4000)
259   if (m68k_get_fc(m_maincpu) == 0x6)   // supervisor mode = ROM
305260   {
306      if (m68k_get_fc(m_maincpu) == 0x6)  // supervisor mode = ROM
307      {
308         return m_rom[offset];
309      }
310      else
311      {
312         return m_ram[offset];
313      }
261     return m_rom[offset];
314262   }
315263   else
316264   {
317      return m_ram[offset];
265     return m_ram[offset];
318266   }
319267}
320268
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342290static ADDRESS_MAP_START( vfx_map, AS_PROGRAM, 16, esq5505_state )
343291   AM_RANGE(0x000000, 0x007fff) AM_READWRITE(lower_r, lower_w)
344292   AM_RANGE(0x200000, 0x20001f) AM_DEVREADWRITE_LEGACY("ensoniq", es5505_r, es5505_w)
345   AM_RANGE(0x260000, 0x2601ff) AM_READWRITE(es5510_dsp_r, es5510_dsp_w)
346293   AM_RANGE(0x280000, 0x28001f) AM_DEVREADWRITE8("duart", duartn68681_device, read, write, 0x00ff)
294   AM_RANGE(0x260000, 0x2601ff) AM_DEVREADWRITE8("esp", es5510_device, host_r, host_w, 0x00ff)
347295   AM_RANGE(0xc00000, 0xc1ffff) AM_ROM AM_REGION("osrom", 0)
348296   AM_RANGE(0xff0000, 0xffffff) AM_RAM AM_SHARE("osram")
349297ADDRESS_MAP_END
350298
351299static ADDRESS_MAP_START( vfxsd_map, AS_PROGRAM, 16, esq5505_state )
352   AM_RANGE(0x000000, 0x007fff) AM_READWRITE(lower_r, lower_w)
300   AM_RANGE(0x000000, 0x00ffff) AM_READWRITE(lower_r, lower_w)
353301   AM_RANGE(0x200000, 0x20001f) AM_DEVREADWRITE_LEGACY("ensoniq", es5505_r, es5505_w)
354   AM_RANGE(0x260000, 0x2601ff) AM_READWRITE(es5510_dsp_r, es5510_dsp_w)
355302   AM_RANGE(0x280000, 0x28001f) AM_DEVREADWRITE8("duart", duartn68681_device, read, write, 0x00ff)
303   AM_RANGE(0x260000, 0x2601ff) AM_DEVREADWRITE8("esp", es5510_device, host_r, host_w, 0x00ff)
356304   AM_RANGE(0x2c0000, 0x2c0007) AM_DEVREADWRITE8("wd1772", wd1772_t, read, write, 0x00ff)
357305   AM_RANGE(0x330000, 0x3bffff) AM_RAM // sequencer memory?
358306   AM_RANGE(0xc00000, 0xc3ffff) AM_ROM AM_REGION("osrom", 0)
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373321static ADDRESS_MAP_START( sq1_map, AS_PROGRAM, 16, esq5505_state )
374322   AM_RANGE(0x000000, 0x03ffff) AM_READWRITE(lower_r, lower_w)
375323   AM_RANGE(0x200000, 0x20001f) AM_DEVREADWRITE_LEGACY("ensoniq", es5505_r, es5505_w)
376   AM_RANGE(0x260000, 0x2601ff) AM_READWRITE(es5510_dsp_r, es5510_dsp_w)
324   AM_RANGE(0x260000, 0x2601ff) AM_DEVREADWRITE8("esp", es5510_device, host_r, host_w, 0x0ff)
377325   AM_RANGE(0x280000, 0x28001f) AM_DEVREADWRITE8("duart", duartn68681_device, read, write, 0x00ff)
378326   AM_RANGE(0x2c0000, 0x2c0007) AM_DEVREADWRITE8("wd1772", wd1772_t, read, write, 0x00ff)
379327   AM_RANGE(0x330000, 0x3bffff) AM_RAM // sequencer memory?
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383331
384332static void esq5505_otis_irq(device_t *device, int state)
385333{
386   #if 0   // 5505/06 IRQ generation needs (more) work
387334   esq5505_state *esq5505 = device->machine().driver_data<esq5505_state>();
388   esq5505->m_maincpu->set_input_line(1, state);
389   #endif
335   esq5505->otis_irq_state = (state != 0);
336   esq5505->update_irq_to_maincpu();
390337}
391338
392339static UINT16 esq5505_read_adc(device_t *device)
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398345   // VFX & SD-1 32 voice schematics agree:
399346   // bit 0: reference
400347   // bit 1: battery
401   // bit 2: vol
348   // bit 2: vol (volume)
402349   // bit 3: pedal
403   // bit 4: val
350   // bit 4: val (data entry slider)
404351   // bit 5: mod wheel
405352   // bit 6: psel
406353   // bit 7: pitch wheel
407354   switch ((state->m_duart_io & 7) ^ 7)
408355   {
409      case 0:     // vRef to check battery
410         return 0x5b00;
356      case 0: // vRef to check battery
357         return 0x5555;
411358
412      case 1:     // battery voltage
413         return 0x7f00;
359      case 1: // battery voltage
360         return 0x7fff;
414361
415         return 0x7f00;
362      case 2: // volume control
363              return 0xffff;
416364
417365      case 3: // pedal
366              return 0xffff;
367
418368      case 5: // mod wheel
419         return 0;
369         return 0xffff;
420370
421371      case 7: // pitch wheel
422         return 0x3f00;
372         return 0x7fff;
423373
424      case 2: // volume control
425      case 4: // val (?)
426      case 6: // psel
427         return 0x7f00;
428   }
374      case 4: // val, aka data entry slider
375         return 0xffff;
429376
430   if (state->m_duart_io & 1)
431   {
432      return 0x5b00;              // vRef
377      case 6: // psel, patch select buttons
378         return 0x0000;
433379   }
434   else
435   {
436      return 0x7f00;              // vBattery
437   }
380   return 0x0000;
438381}
439382
440383WRITE_LINE_MEMBER(esq5505_state::duart_irq_handler)
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442385//    printf("\nDUART IRQ: state %d vector %d\n", state, vector);
443386   if (state == ASSERT_LINE)
444387   {
445      m_maincpu->set_input_line_vector(M68K_IRQ_3, m_duart->get_irq_vector());
446      m_maincpu->set_input_line(M68K_IRQ_3, ASSERT_LINE);
388      duart_irq_vector = m_duart->get_irq_vector();
389      duart_irq_state = 1;
447390   }
448391   else
449392   {
450      m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
393                duart_irq_state = 0;
451394   }
395   update_irq_to_maincpu();
452396};
453397
454398READ8_MEMBER(esq5505_state::duart_input)
r20712r20713
502446       bit 7 = SACK (?)
503447   */
504448
505   if (floppy)
506   {
449    if (data & 0x40) {
450      if (!m_esp->input_state(es5510_device::ES5510_HALT)) {
451   logerror("ESQ5505: Asserting ESPHALT\n");
452   m_esp->set_input_line(es5510_device::ES5510_HALT, ASSERT_LINE);
453      }
454    } else {
455      if (m_esp->input_state(es5510_device::ES5510_HALT)) {
456   logerror("ESQ5505: Clearing ESPHALT\n");
457   m_esp->set_input_line(es5510_device::ES5510_HALT, CLEAR_LINE);
458      }
459    }
460
461    if (floppy)
462    {
507463      if (m_system_type == EPS)
508464      {
509465         floppy->ss_w((data & 2)>>1);
r20712r20713
543499static void esq_dma_end(running_machine &machine, int channel, int irq)
544500{
545501   device_t *device = machine.device("mc68450");
502   esq5505_state *state = machine.driver_data<esq5505_state>();
546503
547504   if (irq != 0)
548505   {
549506      printf("DMAC IRQ, vector = %x\n", hd63450_get_vector(device, channel));
507      state->dmac_irq_state = 1;
508      state->dmac_irq_vector = hd63450_get_vector(device, channel);
550509   }
510   else
511   {
512      state->dmac_irq_state = 0;
513   }
514
515   state->update_irq_to_maincpu();
551516}
552517
553518static void esq_dma_error(running_machine &machine, int channel, int irq)
554519{
555520   device_t *device = machine.device("mc68450");
521   esq5505_state *state = machine.driver_data<esq5505_state>();
522
556523   if(irq != 0)
557524   {
558525      printf("DMAC error, vector = %x\n", hd63450_get_error_vector(device, channel));
526      state->dmac_irq_state = 1;
527      state->dmac_irq_vector = hd63450_get_vector(device, channel);
559528   }
529   else
530   {
531      state->dmac_irq_state = 0;
532   }
533
534   state->update_irq_to_maincpu();
560535}
561536
562537static int esq_fdc_read_byte(running_machine &machine, int addr)
r20712r20713
575550#if KEYBOARD_HACK
576551INPUT_CHANGED_MEMBER(esq5505_state::key_stroke)
577552{
578   #if HACK_VIA_MIDI
579   // send a MIDI Note On
580   if (oldval == 0 && newval == 1)
581   {
582      if ((UINT8)(FPTR)param < 0x40)
583      {
584         int code = (int)(FPTR)param;
585
586         if (code == 0)
587         {
588            program--;
589            if (program < 0)
590            {
591               program = 0;
592            }
593            printf("program to %d\n", program);
594         }
595         if (code == 1)
596         {
597            program++;
598            if (program > 127)
599            {
600               program = 127;
601            }
602            printf("program to %d\n", program);
603         }
604
605         m_duart->duart68681_rx_data(0, (UINT8)(FPTR)0xc0); // program change
606         m_duart->duart68681_rx_data(0, program); // program
607      }
608      else
609      {
610         m_duart->duart68681_rx_data(0, (UINT8)(FPTR)0x90); // note on
611         m_duart->duart68681_rx_data(0, (UINT8)(FPTR)param);
612         m_duart->duart68681_rx_data(0, (UINT8)(FPTR)0x7f);
613      }
614   }
615   else if (oldval == 1 && newval == 0)
616   {
617      if ((UINT8)(FPTR)param != 0x40)
618      {
619         m_duart->duart68681_rx_data(0, (UINT8)(FPTR)0x80); // note off
620         m_duart->duart68681_rx_data(0, (UINT8)(FPTR)param);
621         m_duart->duart68681_rx_data(0, (UINT8)(FPTR)0x7f);
622      }
623   }
624   #else
625553   int val = (UINT8)(FPTR)param;
626554
627555   if (val < 0x60)
r20712r20713
638566            shift += 32;
639567            printf("New shift %d\n", shift);
640568         }
569         else if (val == 0x02)
570         {
571           printf("Analog tests!\n");
572           m_panel->xmit_char(54 | 0x80); m_panel->xmit_char(0); // Preset down
573           m_panel->xmit_char(8 | 0x80);  m_panel->xmit_char(0); // Compare down
574           m_panel->xmit_char(8);         m_panel->xmit_char(0); // Compare up
575           m_panel->xmit_char(54);        m_panel->xmit_char(0); // Preset up       
576         }
641577      }
642578   }
643579   else
r20712r20713
656592         m_panel->xmit_char(0x00);
657593      }
658594   }
659   #endif
660595}
661596#endif
662597
r20712r20713
676611   "waverom",  /* Bank 0 */
677612   "waverom2", /* Bank 1 */
678613   esq5505_otis_irq, /* irq */
679   esq5505_read_adc
614        esq5505_read_adc
680615};
681616
682617static const esqpanel_interface esqpanel_config =
r20712r20713
706641   MCFG_CPU_ADD("maincpu", M68000, XTAL_10MHz)
707642   MCFG_CPU_PROGRAM_MAP(vfx_map)
708643
644   MCFG_CPU_ADD("esp", ES5510, XTAL_10MHz)
645
709646   MCFG_ESQPANEL2x40_ADD("panel", esqpanel_config)
710647
711648   MCFG_DUARTN68681_ADD("duart", 4000000, duart_config)
r20712r20713
746683   MCFG_CPU_ADD("maincpu", M68000, XTAL_30_4761MHz / 2)
747684   MCFG_CPU_PROGRAM_MAP(vfxsd_map)
748685
686   MCFG_CPU_ADD("esp", ES5510, XTAL_10MHz)
687
749688   MCFG_ESQPANEL2x40_ADD("panel", esqpanel_config)
750689
751690   MCFG_DUARTN68681_ADD("duart", 4000000, duart_config)
r20712r20713
773712
774713static INPUT_PORTS_START( vfx )
775714#if KEYBOARD_HACK
776#if HACK_VIA_MIDI
777715   PORT_START("KEY0")
778   PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x40)
779   PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x41)
780   PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x42)
781   PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x43)
782   PORT_BIT(0x0010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x44)
783   PORT_BIT(0x0020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x45)
784   PORT_BIT(0x0040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x46)
785   PORT_BIT(0x0080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x47)
786   PORT_BIT(0x0100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x48)
787   PORT_BIT(0x0200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x49)
788   PORT_BIT(0x0400, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x4a)
789   PORT_BIT(0x0800, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x4b)
790   PORT_BIT(0x1000, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x4c)
791   PORT_BIT(0x2000, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x4d)
792   PORT_BIT(0x4000, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x4e)
793   PORT_BIT(0x8000, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x4f)
794
795   PORT_START("KEY1")
796   PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x0)
797   PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x1)
798#else
799   PORT_START("KEY0")
800716   PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x80)
801717   PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x81)
802718   PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0x82)
r20712r20713
835751   PORT_START("KEY2")
836752   PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 0)
837753   PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 1)
754
755   PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHANGED_MEMBER(DEVICE_SELF, esq5505_state, key_stroke, 2)
838756#endif
839#endif
840757INPUT_PORTS_END
841758
842759ROM_START( vfx )
r20712r20713
886803
887804ROM_START( sd132 )
888805   ROM_REGION(0x40000, "osrom", 0)
889   ROM_LOAD16_BYTE( "sd1_32_402_lo.bin", 0x000000, 0x020000, CRC(5da2572b) SHA1(cb6ddd637ed13bfeb40a99df56000479e63fc8ec) )
890   ROM_LOAD16_BYTE( "sd1_32_402_hi.bin", 0x000001, 0x010000, CRC(fc45c210) SHA1(23b81ebd9176112e6eae0c7c75b39fcb1656c953) )
806   ROM_LOAD16_BYTE( "sd1_410_lo.bin", 0x000000, 0x020000, CRC(faa613a6) SHA1(60066765cddfa9d3b5d09057d8f83fb120f4e65e) )
807   ROM_LOAD16_BYTE( "sd1_410_hi.bin", 0x000001, 0x010000, CRC(618c0aa8) SHA1(74acf458aa1d04a0a7a0cd5855c49e6855dbd301) )
891808
892809   ROM_REGION(0x200000, "waverom", ROMREGION_ERASE00)  // BS=0 region (12-bit)
893810   ROM_LOAD16_BYTE( "u34.bin", 0x000001, 0x080000, CRC(85592299) SHA1(1aa7cf612f91972baeba15991d9686ccde01599c) )
trunk/src/mess/mess.mak
r20712r20713
122122CPUS += UPD7725
123123CPUS += HD61700
124124CPUS += LC8670
125CPUS += ES5510
125126
126127#-------------------------------------------------
127128# specify available sound cores; some of these are

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