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r20618 Wednesday 30th January, 2013 at 19:54:41 UTC by Wilbert Pol
sm8500: Converted to C++ (nw)

[src/emu/cpu/sm8500]	sm8500.c sm8500.h sm85ops.h
[src/mess/drivers]	gamecom.c
[src/mess/includes]	gamecom.h
[src/mess/machine]	gamecom.c

trunk/src/emu/cpu/sm8500/sm8500.c

r20617	r20618
21	21	#include "debugger.h"
22	22	#include "sm8500.h"
23	23
24		#define FLAG_C  0x80
25		#define FLAG_Z  0x40
26		#define FLAG_S  0x20
27		#define FLAG_V  0x10
28		#define FLAG_D  0x08
29		#define FLAG_H  0x04
30		#define FLAG_B  0x02
31		#define FLAG_I  0x01
32	24
33		struct sm8500_state
34		{
35		SM8500_CONFIG config;
36		UINT16 PC;
37		UINT8 IE0;
38		UINT8 IE1;
39		UINT8 IR0;
40		UINT8 IR1;
41		UINT8 SYS;
42		UINT8 CKC;
43		UINT8 clock_changed;
44		UINT16 SP;
45		UINT8 PS0;
46		UINT8 PS1;
47		UINT16 IFLAGS;
48		UINT8 CheckInterrupts;
49		int halted;
50		int icount;
51		device_irq_acknowledge_callback irq_callback;
52		legacy_cpu_device *device;
53		address_space *program;
54		UINT16 oldpc;
55		UINT8 register_ram[0x108];
56		};
	25	const device_type SM8500 = &device_creator<sm8500_cpu_device>;
57	26
58		INLINE sm8500_state *get_safe_token(device_t *device)
59		{
60		assert(device != NULL);
61		assert(device->type() == SM8500);
62		return (sm8500_state *)downcast<legacy_cpu_device *>(device)->token();
63		}
64	27
65	28	static const UINT8 sm8500_b2w[8] = {
66	29	0, 8, 2, 10, 4, 12, 6, 14
67	30	};
68	31
69		INLINE void sm8500_get_sp( sm8500_state *cpustate )
	32
	33	sm8500_cpu_device::sm8500_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	34	: cpu_device(mconfig, SM8500, "SM8500", tag, owner, clock)
	35	, m_program_config("program", ENDIANNESS_BIG, 8, 16, 0)
	36	, m_dma_func(*this)
	37	, m_timer_func(*this)
70	38	{
71		UINT16 data = cpustate->program->read_byte(0x1c) << 8;
72		cpustate->SP = cpustate->program->read_byte(0x1d);
73		if (cpustate->SYS&0x40) cpustate->SP |= data;
74	39	}
75	40
76		static UINT8 sm85cpu_mem_readbyte( sm8500_state *cpustate, UINT32 offset )
	41
	42	void sm8500_cpu_device::get_sp()
77	43	{
	44	m_SP = m_program->read_byte(0x1d);
	45	if (m_SYS & 0x40) m_SP |= ( m_program->read_byte(0x1c) << 8 );
	46	}
	47
	48
	49	UINT8 sm8500_cpu_device::mem_readbyte( UINT32 offset )
	50	{
78	51	offset &= 0xffff;
79		return (offset < 0x10) ? cpustate->register_ram[offset + (cpustate->PS0 & 0xF8)]
80		: cpustate->program->read_byte( offset );
	52	if ( offset < 0x10)
	53	{
	54	return m_register_ram[offset + (m_PS0 & 0xF8)];
	55	}
	56
	57	return m_program->read_byte( offset );
81	58	}
82	59
83		static void sm85cpu_mem_writebyte( sm8500_state *cpustate, UINT32 offset, UINT8 data )
	60
	61	void sm8500_cpu_device::mem_writebyte( UINT32 offset, UINT8 data )
84	62	{
85	63	UINT8 i;
86	64	offset &= 0xffff;
87	65	if (offset < 0x10)
88		cpustate->register_ram[offset + (cpustate->PS0 & 0xF8)] = data;
	66	{
	67	m_register_ram[offset + (m_PS0 & 0xF8)] = data;
	68	}
89	69
90		cpustate->program->write_byte ( offset, data );
	70	m_program->write_byte( offset, data );
91	71
92	72	switch (offset)
93	73	{
94		case 0x10: cpustate->IE0 = data; break;
95		case 0x11: cpustate->IE1 = data; break;
96		case 0x12: cpustate->IR0 = data; break;
97		case 0x13: cpustate->IR1 = data; break;
98		case 0x19: cpustate->SYS = data; break;
99		case 0x1a: cpustate->CKC = data; break;
	74	case 0x10: m_IE0 = data; break;
	75	case 0x11: m_IE1 = data; break;
	76	case 0x12: m_IR0 = data; break;
	77	case 0x13: m_IR1 = data; break;
	78	case 0x19: m_SYS = data; break;
	79	case 0x1a: m_CKC = data; break;
100	80	case 0x1c:
101		case 0x1d: sm8500_get_sp(cpustate); break;
102		case 0x1e: cpustate->PS0 = data;
	81	case 0x1d: get_sp(); break;
	82	case 0x1e: m_PS0 = data;
103	83	for (i = 0; i < 16; i++)    // refresh register contents in debugger
104		cpustate->program->write_byte(i, sm85cpu_mem_readbyte(cpustate, i)); break;
105		case 0x1f: cpustate->PS1 = data; break;
	84	{
	85	m_program->write_byte(i, mem_readbyte(i));
	86	}
	87	break;
	88	case 0x1f: m_PS1 = data; break;
106	89	}
107	90	}
108	91
109	92
110		INLINE UINT16 sm85cpu_mem_readword( sm8500_state *cpustate, UINT32 address )
	93	void sm8500_cpu_device::device_start()
111	94	{
112		return (sm85cpu_mem_readbyte( cpustate, address ) << 8) | (sm85cpu_mem_readbyte( cpustate, address+1 ));
113		}
	95	m_program = &space(AS_PROGRAM);
114	96
115		INLINE void sm85cpu_mem_writeword( sm8500_state *cpustate, UINT32 address, UINT16 value )
116		{
117		sm85cpu_mem_writebyte( cpustate, address, value >> 8 );
118		sm85cpu_mem_writebyte( cpustate, address+1, value );
	97	m_dma_func.resolve_safe();
	98	m_timer_func.resolve_safe();
	99
	100	save_item(NAME(m_PC));
	101	save_item(NAME(m_IE0));
	102	save_item(NAME(m_IE1));
	103	save_item(NAME(m_IR0));
	104	save_item(NAME(m_IR1));
	105	save_item(NAME(m_SYS));
	106	save_item(NAME(m_CKC));
	107	save_item(NAME(m_clock_changed));
	108	save_item(NAME(m_SP));
	109	save_item(NAME(m_PS0));
	110	save_item(NAME(m_PS1));
	111	save_item(NAME(m_IFLAGS));
	112	save_item(NAME(m_CheckInterrupts));
	113	save_item(NAME(m_halted));
	114	save_item(NAME(m_oldpc));
	115	save_pointer(NAME(m_register_ram),0x108);
	116
	117	// Register state for debugger
	118	state_add(SM8500_PC, "PC", m_PC ).callimport().callexport().formatstr("%04X");
	119	state_add(SM8500_SP, "SP", m_SP ).callimport().callexport().formatstr("%04X");
	120	state_add(SM8500_PS, "PS", m_PS0 ).callimport().callexport().formatstr("%04s");
	121	state_add(SM8500_SYS, "SYS", m_SYS ).callimport().callexport().formatstr("%04X");
	122	state_add(SM8500_RR0, "RR0", m_PC ).callimport().callexport().formatstr("%04s");
	123	state_add(SM8500_RR2, "RR2", m_PC ).callimport().callexport().formatstr("%04s");
	124	state_add(SM8500_RR4, "RR4", m_PC ).callimport().callexport().formatstr("%04s");
	125	state_add(SM8500_RR6, "RR6", m_PC ).callimport().callexport().formatstr("%04s");
	126	state_add(SM8500_RR8, "RR8", m_PC ).callimport().callexport().formatstr("%04s");
	127	state_add(SM8500_RR10, "RR10", m_PC ).callimport().callexport().formatstr("%04s");
	128	state_add(SM8500_RR12, "RR12", m_PC ).callimport().callexport().formatstr("%04s");
	129	state_add(SM8500_RR14, "RR14", m_PC ).callimport().callexport().formatstr("%04s");
	130	state_add(STATE_GENPC, "curpc", m_PC).callimport().callexport().formatstr("%8s").noshow();
	131	state_add(STATE_GENFLAGS, "GENFLAGS", m_PS1).formatstr("%8s").noshow();
	132
	133	m_icountptr = &m_icount;
119	134	}
120	135
121		static CPU_INIT( sm8500 )
	136
	137	void sm8500_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
122	138	{
123		sm8500_state *cpustate = get_safe_token(device);
	139	switch (entry.index())
	140	{
	141	case SM8500_PS:
	142	string.printf( "%04X", ( m_PS0 << 8 ) | m_PS1 );
	143	break;
124	144
125		cpustate->irq_callback = irqcallback;
126		cpustate->device = device;
127		cpustate->program = &device->space(AS_PROGRAM);
128		if ( device->static_config() != NULL ) {
129		cpustate->config.handle_dma = ((SM8500_CONFIG *)device->static_config())->handle_dma;
130		cpustate->config.handle_timers = ((SM8500_CONFIG *)device->static_config())->handle_timers;
131		} else {
132		cpustate->config.handle_dma = NULL;
133		cpustate->config.handle_timers = NULL;
	145	case SM8500_RR0:
	146	string.printf( "%04X", mem_readword( 0x00 ) );
	147	break;
	148
	149	case SM8500_RR2:
	150	string.printf( "%04X", mem_readword( 0x02 ) );
	151	break;
	152
	153	case SM8500_RR4:
	154	string.printf( "%04X", mem_readword( 0x04 ) );
	155	break;
	156
	157	case SM8500_RR6:
	158	string.printf( "%04X", mem_readword( 0x06 ) );
	159	break;
	160
	161	case SM8500_RR8:
	162	string.printf( "%04X", mem_readword( 0x08 ) );
	163	break;
	164
	165	case SM8500_RR10:
	166	string.printf( "%04X", mem_readword( 0x0a ) );
	167	break;
	168
	169	case SM8500_RR12:
	170	string.printf( "%04X", mem_readword( 0x0c ) );
	171	break;
	172
	173	case SM8500_RR14:
	174	string.printf( "%04X", mem_readword( 0x0e ) );
	175	break;
	176
	177	case STATE_GENFLAGS:
	178	string.printf( "%c%c%c%c%c%c%c%c",
	179	m_PS1 & FLAG_C ? 'C' : '.',
	180	m_PS1 & FLAG_Z ? 'Z' : '.',
	181	m_PS1 & FLAG_S ? 'S' : '.',
	182	m_PS1 & FLAG_V ? 'V' : '.',
	183	m_PS1 & FLAG_D ? 'D' : '.',
	184	m_PS1 & FLAG_H ? 'H' : '.',
	185	m_PS1 & FLAG_B ? 'B' : '.',
	186	m_PS1 & FLAG_I ? 'I' : '.' );
	187	break;
134	188	}
135	189	}
136	190
137		static CPU_RESET( sm8500 )
	191
	192	void sm8500_cpu_device::device_reset()
138	193	{
139		sm8500_state *cpustate = get_safe_token(device);
	194	for ( int i = 0; i < 0x108; i++ )
	195	{
	196	m_register_ram[i] = 0;
	197	}
140	198
141		cpustate->PC = 0x1020;
142		cpustate->clock_changed = 0;
143		cpustate->halted = 0;
144		sm85cpu_mem_writeword(cpustate, 0x10, 0);                 // IE0, IE1
145		sm85cpu_mem_writeword(cpustate, 0x12, 0);                 // IR0, IR1
146		sm85cpu_mem_writeword(cpustate, 0x14, 0xffff);            // P0, P1
147		sm85cpu_mem_writeword(cpustate, 0x16, 0xff00);            // P2, P3
148		sm85cpu_mem_writebyte(cpustate, 0x19, 0);                 // SYS
149		sm85cpu_mem_writebyte(cpustate, 0x1a, 0);                 // CKC
150		sm85cpu_mem_writebyte(cpustate, 0x1f, 0);                 // PS1
151		sm85cpu_mem_writebyte(cpustate, 0x2b, 0xff);              // URTT
152		sm85cpu_mem_writebyte(cpustate, 0x2d, 0x42);              // URTS
153		sm85cpu_mem_writebyte(cpustate, 0x5f, 0x38);              // WDTC
	199	m_PC = 0x1020;
	200	m_clock_changed = 0;
	201	m_CheckInterrupts = 0;
	202	m_halted = 0;
	203	m_IFLAGS = 0;
	204	mem_writeword(0x10, 0);                 // IE0, IE1
	205	mem_writeword(0x12, 0);                 // IR0, IR1
	206	mem_writeword(0x14, 0xffff);            // P0, P1
	207	mem_writeword(0x16, 0xff00);            // P2, P3
	208	mem_writebyte(0x19, 0);                 // SYS
	209	mem_writebyte(0x1a, 0);                 // CKC
	210	mem_writebyte(0x1f, 0);                 // PS1
	211	mem_writebyte(0x2b, 0xff);              // URTT
	212	mem_writebyte(0x2d, 0x42);              // URTS
	213	mem_writebyte(0x5f, 0x38);              // WDTC
154	214	}
155	215
156		static CPU_EXIT( sm8500 )
157		{
158		}
159	216
160		#define PUSH_BYTE(X)    cpustate->SP--; \
161		if ( ( cpustate->SYS & 0x40 ) == 0 ) cpustate->SP &= 0xFF; \
162		sm85cpu_mem_writebyte( cpustate, cpustate->SP, X );
	217	#define PUSH_BYTE(X)    m_SP--; \
	218	if ( ( m_SYS & 0x40 ) == 0 ) m_SP &= 0xFF; \
	219	mem_writebyte( m_SP, X );
163	220
164		INLINE void sm8500_do_interrupt(sm8500_state *cpustate, UINT16 vector) {
	221
	222	void sm8500_cpu_device::take_interrupt(UINT16 vector)
	223	{
165	224	/* Get regs from ram */
166		sm8500_get_sp(cpustate);
167		cpustate->SYS = cpustate->program->read_byte(0x19);
168		cpustate->PS1 = cpustate->program->read_byte(0x1f);
	225	get_sp();
	226	m_SYS = m_program->read_byte(0x19);
	227	m_PS1 = m_program->read_byte(0x1f);
169	228	/* Push PC */
170		PUSH_BYTE( cpustate->PC & 0xFF );
171		PUSH_BYTE( cpustate->PC >> 8 );
	229	PUSH_BYTE( m_PC & 0xFF );
	230	PUSH_BYTE( m_PC >> 8 );
172	231	/* Push PS1 */
173		PUSH_BYTE( cpustate->PS1 );
	232	PUSH_BYTE( m_PS1 );
174	233	/* Clear I flag */
175		cpustate->PS1 &= ~ 0x01;
	234	m_PS1 &= ~ 0x01;
176	235	/* save regs to ram */
177		cpustate->program->write_byte (0x1f, cpustate->PS1);
178		cpustate->program->write_byte (0x1d, cpustate->SP&0xFF);
179		if (cpustate->SYS&0x40) cpustate->program->write_byte(0x1c, cpustate->SP>>8);
	236	m_program->write_byte(0x1f, m_PS1);
	237	m_program->write_byte(0x1d, m_SP&0xFF);
	238	if (m_SYS&0x40) m_program->write_byte(0x1c, m_SP>>8);
180	239	/* Change PC to address stored at "vector" */
181		cpustate->PC = sm85cpu_mem_readword( cpustate, vector );
	240	m_PC = mem_readword( vector );
182	241	}
183	242
184		INLINE void sm8500_process_interrupts(sm8500_state *cpustate) {
185		if ( cpustate->CheckInterrupts ) {
	243
	244	void sm8500_cpu_device::process_interrupts()
	245	{
	246	if ( m_CheckInterrupts )
	247	{
186	248	int irqline = 0;
187		while( irqline < 11 ) {
188		if ( cpustate->IFLAGS & ( 1 << irqline ) ) {
189		cpustate->halted = 0;
190		cpustate->IE0 = cpustate->program->read_byte(0x10);
191		cpustate->IE1 = cpustate->program->read_byte(0x11);
192		cpustate->IR0 = cpustate->program->read_byte(0x12);
193		cpustate->IR1 = cpustate->program->read_byte(0x13);
194		cpustate->PS0 = cpustate->program->read_byte(0x1e);
195		cpustate->PS1 = cpustate->program->read_byte(0x1f);
196		switch( irqline ) {
	249	while( irqline < 11 )
	250	{
	251	if ( m_IFLAGS & ( 1 << irqline ) )
	252	{
	253	m_halted = 0;
	254	m_IE0 = m_program->read_byte(0x10);
	255	m_IE1 = m_program->read_byte(0x11);
	256	m_IR0 = m_program->read_byte(0x12);
	257	m_IR1 = m_program->read_byte(0x13);
	258	m_PS0 = m_program->read_byte(0x1e);
	259	m_PS1 = m_program->read_byte(0x1f);
	260	switch( irqline )
	261	{
197	262	case WDT_INT:
198		sm8500_do_interrupt( cpustate, 0x101C );
	263	take_interrupt( 0x101C );
199	264	break;
200	265	case ILL_INT:
201	266	case NMI_INT:
202		sm8500_do_interrupt( cpustate, 0x101E );
	267	take_interrupt( 0x101E );
203	268	break;
204	269	case DMA_INT:
205		cpustate->IR0 |= 0x80;
206		if ( ( cpustate->IE0 & 0x80 ) && ( ( cpustate->PS0 & 0x07 ) < 8 ) && ( cpustate->PS1 & 0x01 ) ) {
207		sm8500_do_interrupt( cpustate, 0x1000 );
	270	m_IR0 |= 0x80;
	271	if ( ( m_IE0 & 0x80 ) && ( ( m_PS0 & 0x07 ) < 8 ) && ( m_PS1 & 0x01 ) )
	272	{
	273	take_interrupt( 0x1000 );
208	274	}
209	275	break;
210	276	case TIM0_INT:
211		cpustate->IR0 |= 0x40;
212		if ( ( cpustate->IE0 & 0x40 ) && ( ( cpustate->PS0 & 0x07 ) < 8 ) && ( cpustate->PS1 & 0x01 ) ) {
213		sm8500_do_interrupt( cpustate, 0x1002 );
	277	m_IR0 |= 0x40;
	278	if ( ( m_IE0 & 0x40 ) && ( ( m_PS0 & 0x07 ) < 8 ) && ( m_PS1 & 0x01 ) )
	279	{
	280	take_interrupt( 0x1002 );
214	281	}
215	282	break;
216	283	case EXT_INT:
217		cpustate->IR0 |= 0x10;
218		if ( ( cpustate->IE0 & 0x10 ) && ( ( cpustate->PS0 & 0x07 ) < 7 ) && ( cpustate->PS1 & 0x01 ) ) {
219		sm8500_do_interrupt( cpustate, 0x1006 );
	284	m_IR0 |= 0x10;
	285	if ( ( m_IE0 & 0x10 ) && ( ( m_PS0 & 0x07 ) < 7 ) && ( m_PS1 & 0x01 ) )
	286	{
	287	take_interrupt( 0x1006 );
220	288	}
221	289	break;
222	290	case UART_INT:
223		cpustate->IR0 |= 0x08;
224		if ( ( cpustate->IE0 & 0x08 ) && ( ( cpustate->PS0 & 0x07 ) < 6 ) && ( cpustate->PS1 & 0x01 ) ) {
225		sm8500_do_interrupt( cpustate, 0x1008 );
	291	m_IR0 |= 0x08;
	292	if ( ( m_IE0 & 0x08 ) && ( ( m_PS0 & 0x07 ) < 6 ) && ( m_PS1 & 0x01 ) )
	293	{
	294	take_interrupt( 0x1008 );
226	295	}
227	296	break;
228	297	case LCDC_INT:
229		cpustate->IR0 |= 0x01;
230		if ( ( cpustate->IE0 & 0x01 ) && ( ( cpustate->PS0 & 0x07 ) < 5 ) && ( cpustate->PS1 & 0x01 ) ) {
231		sm8500_do_interrupt( cpustate, 0x100E );
	298	m_IR0 |= 0x01;
	299	if ( ( m_IE0 & 0x01 ) && ( ( m_PS0 & 0x07 ) < 5 ) && ( m_PS1 & 0x01 ) )
	300	{
	301	take_interrupt( 0x100E );
232	302	}
233	303	break;
234	304	case TIM1_INT:
235		cpustate->IR1 |= 0x40;
236		if ( ( cpustate->IE1 & 0x40 ) && ( ( cpustate->PS0 & 0x07 ) < 4 ) && ( cpustate->PS1 & 0x01 ) ) {
237		sm8500_do_interrupt( cpustate, 0x1012 );
	305	m_IR1 |= 0x40;
	306	if ( ( m_IE1 & 0x40 ) && ( ( m_PS0 & 0x07 ) < 4 ) && ( m_PS1 & 0x01 ) )
	307	{
	308	take_interrupt( 0x1012 );
238	309	}
239	310	break;
240	311	case CK_INT:
241		cpustate->IR1 |= 0x10;
242		if ( ( cpustate->IE1 & 0x10 ) && ( ( cpustate->PS0 & 0x07 ) < 3 ) && ( cpustate->PS1 & 0x01 ) ) {
243		sm8500_do_interrupt( cpustate, 0x1016 );
	312	m_IR1 |= 0x10;
	313	if ( ( m_IE1 & 0x10 ) && ( ( m_PS0 & 0x07 ) < 3 ) && ( m_PS1 & 0x01 ) )
	314	{
	315	take_interrupt( 0x1016 );
244	316	}
245	317	break;
246	318	case PIO_INT:
247		cpustate->IR1 |= 0x04;
248		if ( ( cpustate->IE1 & 0x04 ) && ( ( cpustate->PS0 & 0x07 ) < 2 ) && ( cpustate->PS1 & 0x01 ) ) {
249		sm8500_do_interrupt( cpustate, 0x101A );
	319	m_IR1 |= 0x04;
	320	if ( ( m_IE1 & 0x04 ) && ( ( m_PS0 & 0x07 ) < 2 ) && ( m_PS1 & 0x01 ) )
	321	{
	322	take_interrupt( 0x101A );
250	323	}
251	324	break;
252	325	}
253		cpustate->IFLAGS &= ~ ( 1 << irqline );
254		cpustate->program->write_byte(0x12, cpustate->IR0);
255		cpustate->program->write_byte(0x13, cpustate->IR1);
	326	m_IFLAGS &= ~ ( 1 << irqline );
	327	m_program->write_byte(0x12, m_IR0);
	328	m_program->write_byte(0x13, m_IR1);
256	329	}
257	330	irqline++;
258	331	}
259	332	}
260	333	}
261	334
262		static CPU_EXECUTE( sm8500 )
	335
	336	offs_t sm8500_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
263	337	{
264		sm8500_state *cpustate = get_safe_token(device);
265		UINT8   op;
266		int mycycles;
	338	extern CPU_DISASSEMBLE( sm8500 );
	339	return CPU_DISASSEMBLE_NAME( sm8500 )(NULL, buffer, pc, oprom, opram, 0);
	340	}
267	341
	342
	343	void sm8500_cpu_device::execute_run()
	344	{
268	345	do
269	346	{
	347	int     mycycles = 0;
270	348	UINT8   r1,r2;
271	349	UINT16  s1,s2;
272	350	UINT32  d1,d2;
273	351	UINT32  res;
274	352
275		debugger_instruction_hook(device, cpustate->PC);
276		cpustate->oldpc = cpustate->PC;
277		mycycles = 0;
278		sm8500_process_interrupts(cpustate);
279		if ( !cpustate->halted ) {
280		op = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
281		cpustate->SYS = cpustate->program->read_byte(0x19);
282		cpustate->PS0 = cpustate->program->read_byte(0x1e);
283		cpustate->PS1 = cpustate->program->read_byte(0x1f);
284		sm8500_get_sp(cpustate);
	353	debugger_instruction_hook(this, m_PC);
	354	m_oldpc = m_PC;
	355	process_interrupts();
	356	if ( !m_halted ) {
	357	UINT8 op = mem_readbyte( m_PC++ );
	358	m_SYS = m_program->read_byte(0x19);
	359	m_PS0 = m_program->read_byte(0x1e);
	360	m_PS1 = m_program->read_byte(0x1f);
	361	get_sp();
285	362	switch( op )
286	363	{
287	364	#include "sm85ops.h"
288	365	}
289		if (cpustate->SYS&0x40) cpustate->program->write_byte(0x1c,cpustate->SP>>8);
290		cpustate->program->write_byte(0x1d,cpustate->SP&0xFF);
291		sm85cpu_mem_writebyte(cpustate,0x1e,cpustate->PS0); // need to update debugger
292		cpustate->program->write_byte(0x1f,cpustate->PS1);
	366	if (m_SYS&0x40) m_program->write_byte(0x1c,m_SP>>8);
	367	m_program->write_byte(0x1d,m_SP&0xFF);
	368	mem_writebyte(0x1e,m_PS0); // need to update debugger
	369	m_program->write_byte(0x1f,m_PS1);
293	370	} else {
294	371	mycycles = 4;
295		if ( cpustate->config.handle_dma ) {
296		cpustate->config.handle_dma( device, mycycles );
297		}
	372	m_dma_func( mycycles );
298	373	}
299		if ( cpustate->config.handle_timers ) {
300		cpustate->config.handle_timers( device, mycycles );
301		}
302		cpustate->icount -= mycycles;
303		} while ( cpustate->icount > 0 );
	374	m_timer_func( mycycles );
	375	m_icount -= mycycles;
	376	} while ( m_icount > 0 );
304	377	}
305	378
306		static CPU_BURN( sm8500 )
307		{
308		sm8500_state *cpustate = get_safe_token(device);
309	379
310		if ( cycles > 0 ) {
311		/* burn a number of 4 cycles */
312		int n = ( cycles + 3 ) / 4;
313		cpustate->icount -= 4 * n;
314		}
315		}
316
317		static unsigned sm8500_get_reg( sm8500_state *cpustate, int regnum )
	380	void sm8500_cpu_device::execute_set_input( int inptnum, int state )
318	381	{
319		switch( regnum )
	382	m_IR0 = m_program->read_byte(0x12);
	383	m_IR1 = m_program->read_byte(0x13);
	384	if ( state == ASSERT_LINE )
320	385	{
321		case STATE_GENPC:
322		case SM8500_PC:     return cpustate->PC;
323		case STATE_GENSP:
324		case SM8500_SP:     return cpustate->SP;
325		case SM8500_PS:     return sm85cpu_mem_readword( cpustate, 0x1e );
326		case SM8500_SYS16:  return cpustate->SYS;
327		case SM8500_RR0:    return sm85cpu_mem_readword( cpustate, 0x00 );
328		case SM8500_RR2:    return sm85cpu_mem_readword( cpustate, 0x02 );
329		case SM8500_RR4:    return sm85cpu_mem_readword( cpustate, 0x04 );
330		case SM8500_RR6:    return sm85cpu_mem_readword( cpustate, 0x06 );
331		case SM8500_RR8:    return sm85cpu_mem_readword( cpustate, 0x08 );
332		case SM8500_RR10:   return sm85cpu_mem_readword( cpustate, 0x0A );
333		case SM8500_RR12:   return sm85cpu_mem_readword( cpustate, 0x0C );
334		case SM8500_RR14:   return sm85cpu_mem_readword( cpustate, 0x0E );
335		case SM8500_IE0:    return sm85cpu_mem_readbyte( cpustate, 0x10 );
336		case SM8500_IE1:    return sm85cpu_mem_readbyte( cpustate, 0x11 );
337		case SM8500_IR0:    return sm85cpu_mem_readbyte( cpustate, 0x12 );
338		case SM8500_IR1:    return sm85cpu_mem_readbyte( cpustate, 0x13 );
339		case SM8500_P0:     return sm85cpu_mem_readbyte( cpustate, 0x14 );
340		case SM8500_P1:     return sm85cpu_mem_readbyte( cpustate, 0x15 );
341		case SM8500_P2:     return sm85cpu_mem_readbyte( cpustate, 0x16 );
342		case SM8500_P3:     return sm85cpu_mem_readbyte( cpustate, 0x17 );
343		case SM8500_SYS:    return sm85cpu_mem_readbyte( cpustate, 0x19 );
344		case SM8500_CKC:    return sm85cpu_mem_readbyte( cpustate, 0x1a );
345		case SM8500_SPH:    return sm85cpu_mem_readbyte( cpustate, 0x1c );
346		case SM8500_SPL:    return sm85cpu_mem_readbyte( cpustate, 0x1d );
347		case SM8500_PS0:    return sm85cpu_mem_readbyte( cpustate, 0x1e );
348		case SM8500_PS1:    return sm85cpu_mem_readbyte( cpustate, 0x1f );
349		case SM8500_P0C:    return sm85cpu_mem_readbyte( cpustate, 0x20 );
350		case SM8500_P1C:    return sm85cpu_mem_readbyte( cpustate, 0x21 );
351		case SM8500_P2C:    return sm85cpu_mem_readbyte( cpustate, 0x22 );
352		case SM8500_P3C:    return sm85cpu_mem_readbyte( cpustate, 0x23 );
	386	m_IFLAGS |= ( 0x01 << inptnum );
	387	m_CheckInterrupts = 1;
	388	switch( inptnum )
	389	{
	390	case DMA_INT:   m_IR0 |= 0x80; break;
	391	case TIM0_INT:  m_IR0 |= 0x40; break;
	392	case EXT_INT:   m_IR0 |= 0x10; break;
	393	case UART_INT:  m_IR0 |= 0x08; break;
	394	case LCDC_INT:  m_IR0 |= 0x01; break;
	395	case TIM1_INT:  m_IR1 |= 0x40; break;
	396	case CK_INT:    m_IR1 |= 0x10; break;
	397	case PIO_INT:   m_IR1 |= 0x04; break;
	398	}
353	399	}
354		return 0;
355		}
356
357		static void sm8500_set_reg( sm8500_state *cpustate, int regnum, unsigned val )
358		{
359		switch( regnum )
	400	else
360	401	{
361		case STATE_GENPC:
362		case SM8500_PC:     cpustate->PC = val; break;
363		case STATE_GENSP:
364		case SM8500_SP:     cpustate->SP = val; cpustate->program->write_byte(0x1d, val&0xff); if (cpustate->SYS&0x40) cpustate->program->write_byte(0x1c, val>>8); break;
365		case SM8500_PS:     sm85cpu_mem_writeword( cpustate, 0x1e, val); break;
366		case SM8500_SYS16:  val&=0xff; sm85cpu_mem_writebyte( cpustate, 0x19, val); break;
367		case SM8500_RR0:    sm85cpu_mem_writeword( cpustate, 0x00, val); break;
368		case SM8500_RR2:    sm85cpu_mem_writeword( cpustate, 0x02, val); break;
369		case SM8500_RR4:    sm85cpu_mem_writeword( cpustate, 0x04, val); break;
370		case SM8500_RR6:    sm85cpu_mem_writeword( cpustate, 0x06, val); break;
371		case SM8500_RR8:    sm85cpu_mem_writeword( cpustate, 0x08, val); break;
372		case SM8500_RR10:   sm85cpu_mem_writeword( cpustate, 0x0A, val); break;
373		case SM8500_RR12:   sm85cpu_mem_writeword( cpustate, 0x0C, val); break;
374		case SM8500_RR14:   sm85cpu_mem_writeword( cpustate, 0x0E, val); break;
375		case SM8500_IE0:    sm85cpu_mem_writebyte( cpustate, 0x10, val); break;
376		case SM8500_IE1:    sm85cpu_mem_writebyte( cpustate, 0x11, val); break;
377		case SM8500_IR0:    sm85cpu_mem_writebyte( cpustate, 0x12, val); break;
378		case SM8500_IR1:    sm85cpu_mem_writebyte( cpustate, 0x13, val); break;
379		case SM8500_P0:     sm85cpu_mem_writebyte( cpustate, 0x14, val); break;
380		case SM8500_P1:     sm85cpu_mem_writebyte( cpustate, 0x15, val); break;
381		case SM8500_P2:     sm85cpu_mem_writebyte( cpustate, 0x16, val); break;
382		case SM8500_P3:     sm85cpu_mem_writebyte( cpustate, 0x17, val); break;
383		case SM8500_SYS:    sm85cpu_mem_writebyte( cpustate, 0x19, val); break;
384		case SM8500_CKC:    sm85cpu_mem_writebyte( cpustate, 0x1a, val); if ( val & 0x80 ) { cpustate->clock_changed = 1; }; break;
385		case SM8500_SPH:    sm85cpu_mem_writebyte( cpustate, 0x1c, val); break;
386		case SM8500_SPL:    sm85cpu_mem_writebyte( cpustate, 0x1d, val); break;
387		case SM8500_PS0:    sm85cpu_mem_writebyte( cpustate, 0x1e, val); break;
388		case SM8500_PS1:    sm85cpu_mem_writebyte( cpustate, 0x1f, val); break;
389		case SM8500_P0C:    sm85cpu_mem_writebyte( cpustate, 0x20, val); break;
390		case SM8500_P1C:    sm85cpu_mem_writebyte( cpustate, 0x21, val); break;
391		case SM8500_P2C:    sm85cpu_mem_writebyte( cpustate, 0x22, val); break;
392		case SM8500_P3C:    sm85cpu_mem_writebyte( cpustate, 0x23, val); break;
393		}
394		}
395
396		static void sm8500_set_irq_line( sm8500_state *cpustate, int irqline, int state )
397		{
398		cpustate->IR0 = cpustate->program->read_byte(0x12);
399		cpustate->IR1 = cpustate->program->read_byte(0x13);
400		if ( state == ASSERT_LINE ) {
401		cpustate->IFLAGS |= ( 0x01 << irqline );
402		cpustate->CheckInterrupts = 1;
403		switch( irqline ) {
404		case DMA_INT:   cpustate->IR0 |= 0x80; break;
405		case TIM0_INT:  cpustate->IR0 |= 0x40; break;
406		case EXT_INT:   cpustate->IR0 |= 0x10; break;
407		case UART_INT:  cpustate->IR0 |= 0x08; break;
408		case LCDC_INT:  cpustate->IR0 |= 0x01; break;
409		case TIM1_INT:  cpustate->IR1 |= 0x40; break;
410		case CK_INT:    cpustate->IR1 |= 0x10; break;
411		case PIO_INT:   cpustate->IR1 |= 0x04; break;
	402	m_IFLAGS &= ~( 0x01 << inptnum );
	403	switch( inptnum )
	404	{
	405	case DMA_INT:   m_IR0 &= ~0x80; break;
	406	case TIM0_INT:  m_IR0 &= ~0x40; break;
	407	case EXT_INT:   m_IR0 &= ~0x10; break;
	408	case UART_INT:  m_IR0 &= ~0x08; break;
	409	case LCDC_INT:  m_IR0 &= ~0x01; break;
	410	case TIM1_INT:  m_IR1 &= ~0x40; break;
	411	case CK_INT:    m_IR1 &= ~0x10; break;
	412	case PIO_INT:   m_IR1 &= ~0x04; break;
412	413	}
413		} else {
414		cpustate->IFLAGS &= ~( 0x01 << irqline );
415		switch( irqline ) {
416		case DMA_INT:   cpustate->IR0 &= ~0x80; break;
417		case TIM0_INT:  cpustate->IR0 &= ~0x40; break;
418		case EXT_INT:   cpustate->IR0 &= ~0x10; break;
419		case UART_INT:  cpustate->IR0 &= ~0x08; break;
420		case LCDC_INT:  cpustate->IR0 &= ~0x01; break;
421		case TIM1_INT:  cpustate->IR1 &= ~0x40; break;
422		case CK_INT:    cpustate->IR1 &= ~0x10; break;
423		case PIO_INT:   cpustate->IR1 &= ~0x04; break;
	414	if ( 0 == m_IFLAGS )
	415	{
	416	m_CheckInterrupts = 0;
424	417	}
425		if ( 0 == cpustate->IFLAGS ) {
426		cpustate->CheckInterrupts = 0;
427		}
428	418	}
429		cpustate->program->write_byte(0x12, cpustate->IR0);
430		cpustate->program->write_byte(0x13, cpustate->IR1);
	419	m_program->write_byte(0x12, m_IR0);
	420	m_program->write_byte(0x13, m_IR1);
431	421	}
432	422
433		static CPU_SET_INFO( sm8500 )
434		{
435		sm8500_state *cpustate = get_safe_token(device);
436
437		switch(state)
438		{
439		case CPUINFO_INT_INPUT_STATE + 0:
440		case CPUINFO_INT_INPUT_STATE + 1:
441		case CPUINFO_INT_INPUT_STATE + 2:
442		case CPUINFO_INT_INPUT_STATE + 3:
443		case CPUINFO_INT_INPUT_STATE + 4:
444		case CPUINFO_INT_INPUT_STATE + 5:
445		case CPUINFO_INT_INPUT_STATE + 6:
446		case CPUINFO_INT_INPUT_STATE + 7:
447		case CPUINFO_INT_INPUT_STATE + 8:
448		case CPUINFO_INT_INPUT_STATE + 9:
449		case CPUINFO_INT_INPUT_STATE + 10:
450		sm8500_set_irq_line( cpustate, state - CPUINFO_INT_INPUT_STATE, info->i ); break;
451
452		case CPUINFO_INT_REGISTER + SM8500_RR0:
453		case CPUINFO_INT_REGISTER + SM8500_RR2:
454		case CPUINFO_INT_REGISTER + SM8500_RR4:
455		case CPUINFO_INT_REGISTER + SM8500_RR6:
456		case CPUINFO_INT_REGISTER + SM8500_RR8:
457		case CPUINFO_INT_REGISTER + SM8500_RR10:
458		case CPUINFO_INT_REGISTER + SM8500_RR12:
459		case CPUINFO_INT_REGISTER + SM8500_RR14:
460		case CPUINFO_INT_REGISTER + SM8500_PC:
461		case CPUINFO_INT_REGISTER + SM8500_SP:
462		case CPUINFO_INT_REGISTER + SM8500_PS:
463		case CPUINFO_INT_REGISTER + SM8500_SYS16:
464		case CPUINFO_INT_REGISTER + SM8500_SYS:
465		case CPUINFO_INT_REGISTER + SM8500_IE0:
466		case CPUINFO_INT_REGISTER + SM8500_IE1:
467		case CPUINFO_INT_REGISTER + SM8500_IR0:
468		case CPUINFO_INT_REGISTER + SM8500_IR1:
469		case CPUINFO_INT_REGISTER + SM8500_P0:
470		case CPUINFO_INT_REGISTER + SM8500_P1:
471		case CPUINFO_INT_REGISTER + SM8500_P2:
472		case CPUINFO_INT_REGISTER + SM8500_P3:
473		case CPUINFO_INT_REGISTER + SM8500_CKC:
474		case CPUINFO_INT_REGISTER + SM8500_SPH:
475		case CPUINFO_INT_REGISTER + SM8500_SPL:
476		case CPUINFO_INT_REGISTER + SM8500_PS0:
477		case CPUINFO_INT_REGISTER + SM8500_PS1:
478		case CPUINFO_INT_REGISTER + SM8500_P0C:
479		case CPUINFO_INT_REGISTER + SM8500_P1C:
480		case CPUINFO_INT_REGISTER + SM8500_P2C:
481		case CPUINFO_INT_REGISTER + SM8500_P3C:
482		sm8500_set_reg( cpustate, state - CPUINFO_INT_REGISTER, info->i ); break;
483
484		}
485		}
486
487		CPU_GET_INFO( sm8500 )
488		{
489		sm8500_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
490
491		switch(state)
492		{
493		case CPUINFO_INT_CONTEXT_SIZE:              info->i = sizeof(sm8500_state); break;
494		case CPUINFO_INT_INPUT_LINES:               info->i = 8; break;
495		case CPUINFO_INT_DEFAULT_IRQ_VECTOR:            info->i = 0xff; break;
496		case CPUINFO_INT_ENDIANNESS:                info->i = ENDIANNESS_BIG; break;
497		case CPUINFO_INT_CLOCK_MULTIPLIER:              info->i = 1; break;
498		case CPUINFO_INT_CLOCK_DIVIDER:             info->i = 1; break;
499		case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 1; break;
500		case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 5; break;
501		case CPUINFO_INT_MIN_CYCLES:                info->i = 1; break;
502		case CPUINFO_INT_MAX_CYCLES:                info->i = 16; break;
503		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 8; break;
504		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM:    info->i = 16; break;
505		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM:    info->i = 0; break;
506		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 0; break;
507		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 0; break;
508		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = 0; break;
509		case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
510		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
511		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
512		case CPUINFO_INT_INPUT_STATE + 0:
513		case CPUINFO_INT_INPUT_STATE + 1:
514		case CPUINFO_INT_INPUT_STATE + 2:
515		case CPUINFO_INT_INPUT_STATE + 3:
516		case CPUINFO_INT_INPUT_STATE + 4:
517		case CPUINFO_INT_INPUT_STATE + 5:
518		case CPUINFO_INT_INPUT_STATE + 6:
519		case CPUINFO_INT_INPUT_STATE + 7:
520		case CPUINFO_INT_INPUT_STATE + 8:
521		case CPUINFO_INT_INPUT_STATE + 9:
522		case CPUINFO_INT_INPUT_STATE + 10:          info->i = cpustate->IFLAGS & ( 1 << (state - CPUINFO_INT_INPUT_STATE)); break;
523		case CPUINFO_INT_REGISTER + SM8500_RR0:
524		case CPUINFO_INT_REGISTER + SM8500_RR2:
525		case CPUINFO_INT_REGISTER + SM8500_RR4:
526		case CPUINFO_INT_REGISTER + SM8500_RR6:
527		case CPUINFO_INT_REGISTER + SM8500_RR8:
528		case CPUINFO_INT_REGISTER + SM8500_RR10:
529		case CPUINFO_INT_REGISTER + SM8500_RR12:
530		case CPUINFO_INT_REGISTER + SM8500_RR14:
531		case CPUINFO_INT_REGISTER + SM8500_PC:
532		case CPUINFO_INT_REGISTER + SM8500_SP:
533		case CPUINFO_INT_REGISTER + SM8500_PS:
534		case CPUINFO_INT_REGISTER + SM8500_SYS16:
535		case CPUINFO_INT_REGISTER + SM8500_SYS:
536		case CPUINFO_INT_REGISTER + SM8500_IE0:
537		case CPUINFO_INT_REGISTER + SM8500_IE1:
538		case CPUINFO_INT_REGISTER + SM8500_IR0:
539		case CPUINFO_INT_REGISTER + SM8500_IR1:
540		case CPUINFO_INT_REGISTER + SM8500_P0:
541		case CPUINFO_INT_REGISTER + SM8500_P1:
542		case CPUINFO_INT_REGISTER + SM8500_P2:
543		case CPUINFO_INT_REGISTER + SM8500_P3:
544		case CPUINFO_INT_REGISTER + SM8500_CKC:
545		case CPUINFO_INT_REGISTER + SM8500_SPH:
546		case CPUINFO_INT_REGISTER + SM8500_SPL:
547		case CPUINFO_INT_REGISTER + SM8500_PS0:
548		case CPUINFO_INT_REGISTER + SM8500_PS1:
549		case CPUINFO_INT_REGISTER + SM8500_P0C:
550		case CPUINFO_INT_REGISTER + SM8500_P1C:
551		case CPUINFO_INT_REGISTER + SM8500_P2C:
552		case CPUINFO_INT_REGISTER + SM8500_P3C:
553		info->i = sm8500_get_reg( cpustate, state - CPUINFO_INT_REGISTER ); break;
554		case CPUINFO_INT_REGISTER + STATE_GENPC:            info->i = sm8500_get_reg( cpustate, SM8500_PC ); break;
555		case CPUINFO_INT_REGISTER + STATE_GENSP:            info->i = sm8500_get_reg( cpustate, SM8500_SP ); break;
556		case CPUINFO_INT_PREVIOUSPC:                info->i = cpustate->oldpc; break;
557
558
559		case CPUINFO_FCT_SET_INFO:              info->setinfo = CPU_SET_INFO_NAME(sm8500); break;
560		case CPUINFO_FCT_INIT:                  info->init = CPU_INIT_NAME(sm8500); break;
561		case CPUINFO_FCT_RESET:                 info->reset = CPU_RESET_NAME(sm8500); break;
562		case CPUINFO_FCT_EXIT:                  info->exit = CPU_EXIT_NAME(sm8500); break;
563		case CPUINFO_FCT_EXECUTE:               info->execute = CPU_EXECUTE_NAME(sm8500); break;
564		case CPUINFO_FCT_BURN:                  info->burn = CPU_BURN_NAME(sm8500); break;
565		case CPUINFO_FCT_DISASSEMBLE:           info->disassemble = CPU_DISASSEMBLE_NAME(sm8500); break;
566		case CPUINFO_PTR_INSTRUCTION_COUNTER:           info->icount = &cpustate->icount; break;
567
568		case CPUINFO_STR_NAME:                  strcpy( info->s, "sm8500" ); break;
569		case CPUINFO_STR_FAMILY:                strcpy( info->s, "Sharp SM8500" ); break;
570		case CPUINFO_STR_VERSION:               strcpy( info->s, "0.1" ); break;
571		case CPUINFO_STR_SOURCE_FILE:               strcpy( info->s, __FILE__ ); break;
572		case CPUINFO_STR_CREDITS:               strcpy( info->s, "Copyright The MESS Team." ); break;
573		case CPUINFO_STR_FLAGS:
574		sprintf( info->s, "%c%c%c%c%c%c%c%c",
575		cpustate->PS1 & FLAG_C ? 'C' : '.',
576		cpustate->PS1 & FLAG_Z ? 'Z' : '.',
577		cpustate->PS1 & FLAG_S ? 'S' : '.',
578		cpustate->PS1 & FLAG_V ? 'V' : '.',
579		cpustate->PS1 & FLAG_D ? 'D' : '.',
580		cpustate->PS1 & FLAG_H ? 'H' : '.',
581		cpustate->PS1 & FLAG_B ? 'B' : '.',
582		cpustate->PS1 & FLAG_I ? 'I' : '.' );
583		break;
584		case CPUINFO_STR_REGISTER + SM8500_RR0:         sprintf(info->s, "RR0:%04X", sm85cpu_mem_readword( cpustate, 0x00 ) ); break;
585		case CPUINFO_STR_REGISTER + SM8500_RR2:         sprintf(info->s, "RR2:%04X", sm85cpu_mem_readword( cpustate, 0x02 ) ); break;
586		case CPUINFO_STR_REGISTER + SM8500_RR4:         sprintf(info->s, "RR4:%04X", sm85cpu_mem_readword( cpustate, 0x04 ) ); break;
587		case CPUINFO_STR_REGISTER + SM8500_RR6:         sprintf(info->s, "RR6:%04X", sm85cpu_mem_readword( cpustate, 0x06 ) ); break;
588		case CPUINFO_STR_REGISTER + SM8500_RR8:         sprintf(info->s, "RR8:%04X", sm85cpu_mem_readword( cpustate, 0x08 ) ); break;
589		case CPUINFO_STR_REGISTER + SM8500_RR10:        sprintf(info->s, "RR10:%04X", sm85cpu_mem_readword( cpustate, 0x0A ) ); break;
590		case CPUINFO_STR_REGISTER + SM8500_RR12:        sprintf(info->s, "RR12:%04X", sm85cpu_mem_readword( cpustate, 0x0C ) ); break;
591		case CPUINFO_STR_REGISTER + SM8500_RR14:        sprintf(info->s, "RR14:%04X", sm85cpu_mem_readword( cpustate, 0x0E ) ); break;
592		case CPUINFO_STR_REGISTER + SM8500_PC:          sprintf(info->s, "PC:%04X", cpustate->PC); break;
593		case CPUINFO_STR_REGISTER + SM8500_SP:          sprintf(info->s, "SP:%04X", cpustate->SP); break;
594		case CPUINFO_STR_REGISTER + SM8500_PS:          sprintf(info->s, "PS:%04X", ( cpustate->PS0 << 8 ) | cpustate->PS1 ); break;
595		case CPUINFO_STR_REGISTER + SM8500_SYS16:       sprintf(info->s, "SYS:%02X", cpustate->SYS ); break;
596		}
597		}
598
599
600		DEFINE_LEGACY_CPU_DEVICE(SM8500, sm8500);

trunk/src/emu/cpu/sm8500/sm8500.h

r20617	r20618
3	3	#ifndef __SM8500_H__
4	4	#define __SM8500_H__
5	5
	6	#define MCFG_SM8500_DMA_CB(_devcb) \
	7	sm8500_cpu_device::set_dma_cb(*device, DEVCB2_##_devcb); \
6	8
7		struct SM8500_CONFIG {
8		void (*handle_dma)(device_t *device, int cycles);
9		void (*handle_timers)(device_t *device, int cycles);
10		};
11	9
12		/* interrupts */
13		#define ILL_INT         0
14		#define DMA_INT         1
15		#define TIM0_INT        2
16		#define EXT_INT         3
17		#define UART_INT        4
18		#define LCDC_INT        5
19		#define TIM1_INT        6
20		#define CK_INT          7
21		#define PIO_INT         8
22		#define WDT_INT         9
23		#define NMI_INT         10
	10	#define MCFG_SM8500_TIMER_CB(_devcb) \
	11	sm8500_cpu_device::set_timer_cb(*device, DEVCB2_##_devcb); \
24	12
	13
25	14	enum
26	15	{
27	16	/* "main" 16 bit register */
r20617	r20618
32	21	SM8500_SPH, SM8500_SPL, SM8500_PS0, SM8500_PS1, SM8500_P0C, SM8500_P1C, SM8500_P2C, SM8500_P3C,
33	22	};
34	23
35		DECLARE_LEGACY_CPU_DEVICE(SM8500, sm8500);
36	24
37		extern CPU_DISASSEMBLE( sm8500 );
	25	class sm8500_cpu_device : public cpu_device
	26	{
	27	public:
	28	// construction/destruction
	29	sm8500_cpu_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
38	30
	31	// static configuration helpers
	32	template<class _Object> static devcb2_base &set_dma_cb(device_t &device, _Object object) { return downcast<sm8500_cpu_device &>(device).m_dma_func.set_callback(object); }
	33	template<class _Object> static devcb2_base &set_timer_cb(device_t &device, _Object object) { return downcast<sm8500_cpu_device &>(device).m_timer_func.set_callback(object); }
	34
	35	/* interrupts */
	36	static const int ILL_INT  = 0;
	37	static const int DMA_INT  = 1;
	38	static const int TIM0_INT = 2;
	39	static const int EXT_INT  = 3;
	40	static const int UART_INT = 4;
	41	static const int LCDC_INT = 5;
	42	static const int TIM1_INT = 6;
	43	static const int CK_INT   = 7;
	44	static const int PIO_INT  = 8;
	45	static const int WDT_INT  = 9;
	46	static const int NMI_INT  = 10;
	47
	48	protected:
	49	// Flags
	50	static const UINT8 FLAG_C = 0x80;
	51	static const UINT8 FLAG_Z = 0x40;
	52	static const UINT8 FLAG_S = 0x20;
	53	static const UINT8 FLAG_V = 0x10;
	54	static const UINT8 FLAG_D = 0x08;
	55	static const UINT8 FLAG_H = 0x04;
	56	static const UINT8 FLAG_B = 0x02;
	57	static const UINT8 FLAG_I = 0x01;
	58
	59	// device-level overrides
	60	virtual void device_start();
	61	virtual void device_reset();
	62
	63	// device_execute_interface overrides
	64	virtual UINT32 execute_min_cycles() const { return 1; }
	65	virtual UINT32 execute_max_cycles() const { return 16; }
	66	virtual UINT32 execute_input_lines() const { return 11; }
	67	virtual void execute_run();
	68	virtual void execute_set_input(int inputnum, int state);
	69
	70	// device_memory_interface overrides
	71	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
	72
	73	// device_state_interface overrides
	74	void state_string_export(const device_state_entry &entry, astring &string);
	75
	76	// device_disasm_interface overrides
	77	virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
	78	virtual UINT32 disasm_max_opcode_bytes() const { return 5; }
	79	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	80
	81	inline void get_sp();
	82	inline UINT8 mem_readbyte(UINT32 offset);
	83	inline void mem_writebyte(UINT32 offset, UINT8 data);
	84	inline UINT16 mem_readword(UINT32 address) { return (mem_readbyte(address ) << 8) | (mem_readbyte(address+1)); }
	85	inline void mem_writeword(UINT32 address, UINT16 value) { mem_writebyte(address, value >> 8); mem_writebyte(address+1, value); }
	86	inline void take_interrupt(UINT16 vector);
	87	void process_interrupts();
	88
	89	address_space_config m_program_config;
	90
	91	devcb2_write8 m_dma_func;
	92	devcb2_write8 m_timer_func;
	93
	94	UINT16 m_PC;
	95	UINT8 m_IE0;
	96	UINT8 m_IE1;
	97	UINT8 m_IR0;
	98	UINT8 m_IR1;
	99	UINT8 m_SYS;
	100	UINT8 m_CKC;
	101	UINT8 m_clock_changed;
	102	UINT16 m_SP;
	103	UINT8 m_PS0;
	104	UINT8 m_PS1;
	105	UINT16 m_IFLAGS;
	106	UINT8 m_CheckInterrupts;
	107	int m_halted;
	108	int m_icount;
	109	address_space *m_program;
	110	UINT16 m_oldpc;
	111	UINT8 m_register_ram[0x108];
	112	};
	113
	114
	115	extern const device_type SM8500;
	116
	117
39	118	#endif /* __SM8500_H__ */

trunk/src/emu/cpu/sm8500/sm85ops.h

r20617	r20618
1	1
2		#define ARG_R   r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
	2	#define ARG_R   r1 = mem_readbyte( m_PC++ );
3	3
4		#define ARG_RR  r2 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
5		r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
	4	#define ARG_RR  r2 = mem_readbyte( m_PC++ ); \
	5	r1 = mem_readbyte( m_PC++ );
6	6
7	7	#define ARG_rR  r1 = op & 0x07; \
8		r2 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
	8	r2 = mem_readbyte( m_PC++ );
9	9
10		#define ARG_iR  r2 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
11		r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
	10	#define ARG_iR  r2 = mem_readbyte( m_PC++ ); \
	11	r1 = mem_readbyte( m_PC++ );
12	12
13		#define ARG_Sw  r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
14		s2 = sm85cpu_mem_readword( cpustate, cpustate->PC ); cpustate->PC += 2;
	13	#define ARG_Sw  r1 = mem_readbyte( m_PC++ ); \
	14	s2 = mem_readword( m_PC ); m_PC += 2;
15	15
16	16	#define ARG_rrw r1 = sm8500_b2w[op & 0x07]; \
17		s2 = sm85cpu_mem_readword( cpustate, cpustate->PC ); cpustate->PC += 2;
	17	s2 = mem_readword( m_PC ); m_PC += 2;
18	18
19	19	#define ARG_ri  r1 = op & 0x07; \
20		r2 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
	20	r2 = mem_readbyte( m_PC++ );
21	21
22	22	#define ARG_pi  r1 = 0x10 + ( op & 0x07 ); \
23		r2 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
	23	r2 = mem_readbyte( m_PC++ );
24	24
25		#define ARG_rmb r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
	25	#define ARG_rmb r1 = mem_readbyte( m_PC++ ); \
26	26	s2 = 0; \
27	27	switch( r1 & 0xC0 ) { \
28	28	case 0x00: \
29		s2 = sm85cpu_mem_readbyte( cpustate, r1 & 0x07 ); \
	29	s2 = mem_readbyte( r1 & 0x07 ); \
30	30	break; \
31	31	case 0x40: \
32		s2 = sm85cpu_mem_readbyte( cpustate, r1 & 0x07 ); \
33		sm85cpu_mem_writebyte( cpustate, r1 & 0x07, s2 + 1 ); \
	32	s2 = mem_readbyte( r1 & 0x07 ); \
	33	mem_writebyte( r1 & 0x07, s2 + 1 ); \
34	34	break; \
35	35	case 0x80: \
36		s2 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
	36	s2 = mem_readbyte( m_PC++ ); \
37	37	if ( r1 & 0x07 ) { \
38		s2 = s2 + sm85cpu_mem_readbyte( cpustate, r1 & 0x07 ); \
	38	s2 = s2 + mem_readbyte( r1 & 0x07 ); \
39	39	} \
40	40	break; \
41	41	case 0xC0: \
42		s2 = sm85cpu_mem_readbyte( cpustate, r1 & 0x07 ); \
43		sm85cpu_mem_writebyte( cpustate, r1 & 0x07, s2 - 1 ); \
	42	s2 = mem_readbyte( r1 & 0x07 ); \
	43	mem_writebyte( r1 & 0x07, s2 - 1 ); \
44	44	break; \
45	45	} \
46	46	r2 = r1; \
47	47	r1 = ( r1 >> 3 ) & 0x07;
48	48
49		#define ARG_rmw r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
	49	#define ARG_rmw r1 = mem_readbyte( m_PC++ ); \
50	50	s2 = 0; \
51	51	switch( r1 & 0xC0 ) { \
52	52	case 0x00: \
53		s2 = sm85cpu_mem_readword( cpustate, sm8500_b2w[r1 & 0x07] ); \
	53	s2 = mem_readword( sm8500_b2w[r1 & 0x07] ); \
54	54	break; \
55	55	case 0x40: \
56		s2 = sm85cpu_mem_readword( cpustate, sm8500_b2w[r1 & 0x07] ); \
57		sm85cpu_mem_writeword( cpustate, sm8500_b2w[r1 & 0x07], s2 + 1 ); \
	56	s2 = mem_readword( sm8500_b2w[r1 & 0x07] ); \
	57	mem_writeword( sm8500_b2w[r1 & 0x07], s2 + 1 ); \
58	58	break; \
59	59	case 0x80: \
60		s2 = sm85cpu_mem_readword( cpustate, cpustate->PC ); cpustate->PC += 2; \
	60	s2 = mem_readword( m_PC ); m_PC += 2; \
61	61	if ( r1 & 0x07 ) { \
62		s2 = s2 + sm85cpu_mem_readword( cpustate, sm8500_b2w[r1 & 0x07] ); \
	62	s2 = s2 + mem_readword( sm8500_b2w[r1 & 0x07] ); \
63	63	} \
64	64	break; \
65	65	case 0xC0: \
66		s2 = sm85cpu_mem_readword( cpustate, sm8500_b2w[r1 & 0x07] ); \
67		sm85cpu_mem_writeword( cpustate, sm8500_b2w[r1 & 0x07], s2 - 1 ); \
	66	s2 = mem_readword( sm8500_b2w[r1 & 0x07] ); \
	67	mem_writeword( sm8500_b2w[r1 & 0x07], s2 - 1 ); \
68	68	break; \
69	69	} \
70	70	r2 = r1; \
71	71	r1 = ( r1 >> 3 ) & 0x07;
72	72
73		#define ARG_smw r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
	73	#define ARG_smw r1 = mem_readbyte( m_PC++ ); \
74	74	s2 = 0; \
75	75	switch( r1 & 0xC0 ) { \
76	76	case 0x00: \
77		s2 = sm85cpu_mem_readword( cpustate, sm8500_b2w[r1 & 0x07] ); \
	77	s2 = mem_readword( sm8500_b2w[r1 & 0x07] ); \
78	78	break; \
79	79	case 0x40: \
80		s2 = sm85cpu_mem_readword( cpustate, sm8500_b2w[r1 & 0x07] ); \
81		sm85cpu_mem_writeword( cpustate, sm8500_b2w[r1 & 0x07], s2 + 1 ); \
	80	s2 = mem_readword( sm8500_b2w[r1 & 0x07] ); \
	81	mem_writeword( sm8500_b2w[r1 & 0x07], s2 + 1 ); \
82	82	break; \
83	83	case 0x80: \
84		s2 = sm85cpu_mem_readword( cpustate, cpustate->PC ); cpustate->PC += 2; \
	84	s2 = mem_readword( m_PC ); m_PC += 2; \
85	85	if ( r1 & 0x07 ) { \
86		s2 = s2 + sm85cpu_mem_readword( cpustate, sm8500_b2w[r1 & 0x07] ); \
	86	s2 = s2 + mem_readword( sm8500_b2w[r1 & 0x07] ); \
87	87	} \
88	88	break; \
89	89	case 0xC0: \
90		s2 = sm85cpu_mem_readword( cpustate, sm8500_b2w[ r1 & 0x07] ); \
91		sm85cpu_mem_writeword( cpustate, sm8500_b2w[r1 & 0x07], s2 - 1 ); \
	90	s2 = mem_readword( sm8500_b2w[ r1 & 0x07] ); \
	91	mem_writeword( sm8500_b2w[r1 & 0x07], s2 - 1 ); \
92	92	break; \
93	93	} \
94	94	r2 = r1; \
95	95	r1 = sm8500_b2w[ ( r1 >> 3 ) & 0x07 ];
96	96
97		#define ARG_d8  r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
98		s2 = cpustate->PC + ((INT8)r1);
	97	#define ARG_d8  r1 = mem_readbyte( m_PC++ ); \
	98	s2 = m_PC + ((INT8)r1);
99	99
100		#define ARG_Rbr r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
101		r2 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
102		s2 = cpustate->PC + ((INT8)r2);
	100	#define ARG_Rbr r1 = mem_readbyte( m_PC++ ); \
	101	r2 = mem_readbyte( m_PC++ ); \
	102	s2 = m_PC + ((INT8)r2);
103	103
104		#define ARG_ad16    s2 = sm85cpu_mem_readword( cpustate, cpustate->PC ); \
105		cpustate->PC += 2;
	104	#define ARG_ad16    s2 = mem_readword( m_PC ); \
	105	m_PC += 2;
106	106
107		#define ARG_rr  r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
	107	#define ARG_rr  r1 = mem_readbyte( m_PC++ ); \
108	108	r2 = 0x00; \
109	109	switch( r1 & 0xC0 ) { \
110	110	case 0x00: \
r20617	r20618
117	117	break; \
118	118	}
119	119
120		#define ARG_ss  r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
	120	#define ARG_ss  r1 = mem_readbyte( m_PC++ ); \
121	121	r2 = 0x00; \
122	122	switch( r1 & 0xC0 ) { \
123	123	case 0x00: \
r20617	r20618
130	130	break; \
131	131	}
132	132
133		#define ARG_2   r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
	133	#define ARG_2   r1 = mem_readbyte( m_PC++ ); \
134	134	s2 = 0; \
135	135	switch( r1 & 0xC0 ) { \
136	136	case 0x00: \
137		s2 = sm85cpu_mem_readword( cpustate, sm8500_b2w[ r1 & 0x07 ] ); \
	137	s2 = mem_readword( sm8500_b2w[ r1 & 0x07 ] ); \
138	138	break; \
139	139	case 0x40: \
140		s2 = sm85cpu_mem_readword( cpustate, cpustate->PC ); cpustate->PC += 2; \
	140	s2 = mem_readword( m_PC ); m_PC += 2; \
141	141	if ( r1 & 0x38 ) { \
142		s2 = s2 + sm85cpu_mem_readbyte( cpustate, ( r1 >> 3 ) & 0x07 ); \
	142	s2 = s2 + mem_readbyte( ( r1 >> 3 ) & 0x07 ); \
143	143	}  \
144		s2 = sm85cpu_mem_readword( cpustate, s2 ); \
	144	s2 = mem_readword( s2 ); \
145	145	case 0x80: \
146	146	case 0xC0: \
147	147	break; \
148	148	}
149	149
150		#define ARG_RiR r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
151		d1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
152		r2 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
	150	#define ARG_RiR r1 = mem_readbyte( m_PC++ ); \
	151	d1 = mem_readbyte( m_PC++ ); \
	152	r2 = mem_readbyte( m_PC++ );
153	153
154		#define ARG_Rii r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
155		d1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
156		r2 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
	154	#define ARG_Rii r1 = mem_readbyte( m_PC++ ); \
	155	d1 = mem_readbyte( m_PC++ ); \
	156	r2 = mem_readbyte( m_PC++ );
157	157
158		#define ARG_riB r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
	158	#define ARG_riB r1 = mem_readbyte( m_PC++ ); \
159	159	s2 = 1 << ( r1 & 0x07 ); \
160		d1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
	160	d1 = mem_readbyte( m_PC++ ); \
161	161	if ( r1 & 0x38 ) { \
162		s1 = d1 + sm85cpu_mem_readbyte( cpustate, ( r1 >> 3 ) & 0x07 ); \
	162	s1 = d1 + mem_readbyte( ( r1 >> 3 ) & 0x07 ); \
163	163	} else { \
164	164	s1 = 0xFF00 + d1; \
165	165	}
166	166
167		#define ARG_riBd    r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
	167	#define ARG_riBd    r1 = mem_readbyte( m_PC++ ); \
168	168	s2 = 1 << ( r1 & 0x07 ); \
169		d1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ ); \
	169	d1 = mem_readbyte( m_PC++ ); \
170	170	if ( r1 & 0x38 ) { \
171		s1 = d1 + sm85cpu_mem_readbyte( cpustate, ( r1 >> 3 ) & 0x07 ); \
	171	s1 = d1 + mem_readbyte( ( r1 >> 3 ) & 0x07 ); \
172	172	} else { \
173	173	s1 = 0xFF00 + d1; \
174	174	} \
175		d1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
	175	d1 = mem_readbyte( m_PC++ );
176	176
177	177	#define OP_INTSUB8(X,Y,MASK)    d1 = X; \
178	178	d2 = Y; \
179	179	res = d1 - d2; \
180		cpustate->PS1 = cpustate->PS1 & ( MASK ); \
181		cpustate->PS1 = cpustate->PS1 | ( ( res > 0xFF ) ? FLAG_C : 0 ); \
182		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
183		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
184		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d2 ^ d1 ) & ( res ^ d1 ) ) & 0x80 ) ? FLAG_V : 0 );
	180	m_PS1 = m_PS1 & ( MASK ); \
	181	m_PS1 = m_PS1 | ( ( res > 0xFF ) ? FLAG_C : 0 ); \
	182	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	183	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
	184	m_PS1 = m_PS1 | ( ( ( ( d2 ^ d1 ) & ( res ^ d1 ) ) & 0x80 ) ? FLAG_V : 0 );
185	185
186	186	#define OP_CMP8(X,Y)    OP_INTSUB8( X, Y, (FLAG_B | FLAG_I | FLAG_H | FLAG_D ) );
187	187
188	188	#define OP_SUB8(X,Y)    OP_INTSUB8( X, Y, (FLAG_B | FLAG_I ) ); \
189		cpustate->PS1 = cpustate->PS1 | FLAG_D; \
190		cpustate->PS1 = cpustate->PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x10 ) ? FLAG_H : 0 );
	189	m_PS1 = m_PS1 | FLAG_D; \
	190	m_PS1 = m_PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x10 ) ? FLAG_H : 0 );
191	191
192	192	#define OP_INTSUB16(X,Y,MASK)   d1 = X; \
193	193	d2 = Y; \
194	194	res = d1 - d2; \
195		cpustate->PS1 = cpustate->PS1 & ( MASK ); \
196		cpustate->PS1 = cpustate->PS1 | ( ( res > 0xFFFF ) ? FLAG_C : 0 ); \
197		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 ); \
198		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x8000 ) ? FLAG_S : 0 ); \
199		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d2 ^ d1 ) & (res ^ d1) ) & 0x8000 ) ? FLAG_V : 0 );
	195	m_PS1 = m_PS1 & ( MASK ); \
	196	m_PS1 = m_PS1 | ( ( res > 0xFFFF ) ? FLAG_C : 0 ); \
	197	m_PS1 = m_PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 ); \
	198	m_PS1 = m_PS1 | ( ( res & 0x8000 ) ? FLAG_S : 0 ); \
	199	m_PS1 = m_PS1 | ( ( ( ( d2 ^ d1 ) & (res ^ d1) ) & 0x8000 ) ? FLAG_V : 0 );
200	200
201	201	#define OP_CMP16(X,Y)   OP_INTSUB16( X, Y, ( FLAG_B | FLAG_I | FLAG_H | FLAG_D ) );
202	202
203	203	#define OP_SUB16(X,Y)   OP_INTSUB16( X, Y, ( FLAG_B | FLAG_I ) ); \
204		cpustate->PS1 = cpustate->PS1 | FLAG_D; \
205		cpustate->PS1 = cpustate->PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x0010 ) ? FLAG_H : 0 );
	204	m_PS1 = m_PS1 | FLAG_D; \
	205	m_PS1 = m_PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x0010 ) ? FLAG_H : 0 );
206	206
207	207	#define OP_SBC8(X,Y)    d1 = X; \
208	208	d2 = Y; \
209		res = d1 - d2 - ((cpustate->PS1 & FLAG_C) ? 1 : 0); \
210		cpustate->PS1 = cpustate->PS1 & ( FLAG_B | FLAG_I ); \
211		cpustate->PS1 = cpustate->PS1 | ( ( res > 0xFF ) ? FLAG_C : 0 ); \
212		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
213		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0); \
214		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d2 ^ d1 ) & (res ^ d1) ) & 0x80 ) ? FLAG_V : 0 ); \
215		cpustate->PS1 = cpustate->PS1 | FLAG_D; \
216		cpustate->PS1 = cpustate->PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x10 ) ? FLAG_H : 0 );
	209	res = d1 - d2 - ((m_PS1 & FLAG_C) ? 1 : 0); \
	210	m_PS1 = m_PS1 & ( FLAG_B | FLAG_I ); \
	211	m_PS1 = m_PS1 | ( ( res > 0xFF ) ? FLAG_C : 0 ); \
	212	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	213	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0); \
	214	m_PS1 = m_PS1 | ( ( ( ( d2 ^ d1 ) & (res ^ d1) ) & 0x80 ) ? FLAG_V : 0 ); \
	215	m_PS1 = m_PS1 | FLAG_D; \
	216	m_PS1 = m_PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x10 ) ? FLAG_H : 0 );
217	217
218	218	#define OP_SBC16(X,Y)   d1 = X; \
219	219	d2 = Y; \
220		res = d1 - d2 - ((cpustate->PS1 & FLAG_C) ? 1 : 0); \
221		cpustate->PS1 = cpustate->PS1 & ( FLAG_B | FLAG_I ); \
222		cpustate->PS1 = cpustate->PS1 | ( ( res > 0xFFFF ) ? FLAG_C : 0 ); \
223		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 ); \
224		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x8000 ) ? FLAG_S : 0 ); \
225		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d2 ^ d1 ) & ( res ^ d1 ) ) & 0x8000 ) ? FLAG_V : 0 ); \
226		cpustate->PS1 = cpustate->PS1 | FLAG_D; \
227		cpustate->PS1 = cpustate->PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x10 ) ? FLAG_H : 0 );
	220	res = d1 - d2 - ((m_PS1 & FLAG_C) ? 1 : 0); \
	221	m_PS1 = m_PS1 & ( FLAG_B | FLAG_I ); \
	222	m_PS1 = m_PS1 | ( ( res > 0xFFFF ) ? FLAG_C : 0 ); \
	223	m_PS1 = m_PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 ); \
	224	m_PS1 = m_PS1 | ( ( res & 0x8000 ) ? FLAG_S : 0 ); \
	225	m_PS1 = m_PS1 | ( ( ( ( d2 ^ d1 ) & ( res ^ d1 ) ) & 0x8000 ) ? FLAG_V : 0 ); \
	226	m_PS1 = m_PS1 | FLAG_D; \
	227	m_PS1 = m_PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x10 ) ? FLAG_H : 0 );
228	228
229	229	#define OP_ADD8(X,Y)    d1 = X; \
230	230	d2 = Y; \
231	231	res = d1 + d2; \
232		cpustate->PS1 = cpustate->PS1 & ( FLAG_B | FLAG_I ); \
233		cpustate->PS1 = cpustate->PS1 | ( ( res > 0xFF ) ? FLAG_C : 0 ); \
234		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
235		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0); \
236		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d2 ^ d1 ^ 0x80 ) & (res ^ d1) ) & 0x80 ) ? FLAG_V : 0 ); \
237		cpustate->PS1 = cpustate->PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x10 ) ? FLAG_H : 0 );
	232	m_PS1 = m_PS1 & ( FLAG_B | FLAG_I ); \
	233	m_PS1 = m_PS1 | ( ( res > 0xFF ) ? FLAG_C : 0 ); \
	234	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	235	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0); \
	236	m_PS1 = m_PS1 | ( ( ( ( d2 ^ d1 ^ 0x80 ) & (res ^ d1) ) & 0x80 ) ? FLAG_V : 0 ); \
	237	m_PS1 = m_PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x10 ) ? FLAG_H : 0 );
238	238
239	239	#define OP_ADD16(X,Y)   d1 = X; \
240	240	d2 = Y; \
241	241	res = d1 + d2; \
242		cpustate->PS1 = cpustate->PS1 & ( FLAG_B | FLAG_I ); \
243		cpustate->PS1 = cpustate->PS1 | ( ( res > 0xFFFF ) ? FLAG_C : 0 ); \
244		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 ); \
245		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x8000 ) ? FLAG_S : 0 ); \
246		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d2 ^ d1 ) & ( res ^ d1 ) ) & 0x8000 ) ? FLAG_V : 0 ); \
247		cpustate->PS1 = cpustate->PS1 | ( ( ( d2 ^ d1 ^ res ) & 0x0010 ) ? FLAG_H : 0 );
	242	m_PS1 = m_PS1 & ( FLAG_B | FLAG_I ); \
	243	m_PS1 = m_PS1 | ( ( res > 0xFFFF ) ? FLAG_C : 0 ); \
	244	m_PS1 = m_PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 ); \
	245	m_PS1 = m_PS1 | ( ( res & 0x8000 ) ? FLAG_S : 0 ); \
	246	m_PS1 = m_PS1 | ( ( ( ( d2 ^ d1 ) & ( res ^ d1 ) ) & 0x8000 ) ? FLAG_V : 0 ); \
	247	m_PS1 = m_PS1 | ( ( ( d2 ^ d1 ^ res ) & 0x0010 ) ? FLAG_H : 0 );
248	248
249	249	#define OP_ADC8(X,Y)    d1 = X; \
250	250	d2 = Y; \
251		res = d1 + d2 + ((cpustate->PS1 & FLAG_C) ? 1 : 0); \
252		cpustate->PS1 = cpustate->PS1 & ( FLAG_B | FLAG_I ); \
253		cpustate->PS1 = cpustate->PS1 | ( ( res > 0xFF ) ? FLAG_C : 0 ); \
254		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
255		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0); \
256		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d2 ^ d1 ) & (res ^ d1) ) & 0x80 ) ? FLAG_V : 0 ); \
257		cpustate->PS1 = cpustate->PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x10 ) ? FLAG_H : 0 );
	251	res = d1 + d2 + ((m_PS1 & FLAG_C) ? 1 : 0); \
	252	m_PS1 = m_PS1 & ( FLAG_B | FLAG_I ); \
	253	m_PS1 = m_PS1 | ( ( res > 0xFF ) ? FLAG_C : 0 ); \
	254	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	255	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0); \
	256	m_PS1 = m_PS1 | ( ( ( ( d2 ^ d1 ) & (res ^ d1) ) & 0x80 ) ? FLAG_V : 0 ); \
	257	m_PS1 = m_PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x10 ) ? FLAG_H : 0 );
258	258
259	259	#define OP_ADC16(X,Y)   d1 = X; \
260	260	d2 = Y; \
261		res = d1 + d2 + ((cpustate->PS1 & FLAG_C) ? 1 : 0); \
262		cpustate->PS1 = cpustate->PS1 & ( FLAG_B | FLAG_I ); \
263		cpustate->PS1 = cpustate->PS1 | ( ( res > 0xFFFF ) ? FLAG_C : 0 ); \
264		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 ); \
265		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x8000 ) ? FLAG_S : 0 ); \
266		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d2 ^ d1 ) & ( res ^ d1) ) & 0x8000 ) ? FLAG_V : 0 ); \
267		cpustate->PS1 = cpustate->PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x10 ) ? FLAG_H : 0 );
	261	res = d1 + d2 + ((m_PS1 & FLAG_C) ? 1 : 0); \
	262	m_PS1 = m_PS1 & ( FLAG_B | FLAG_I ); \
	263	m_PS1 = m_PS1 | ( ( res > 0xFFFF ) ? FLAG_C : 0 ); \
	264	m_PS1 = m_PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 ); \
	265	m_PS1 = m_PS1 | ( ( res & 0x8000 ) ? FLAG_S : 0 ); \
	266	m_PS1 = m_PS1 | ( ( ( ( d2 ^ d1 ) & ( res ^ d1) ) & 0x8000 ) ? FLAG_V : 0 ); \
	267	m_PS1 = m_PS1 | ( ( ( d1 ^ d2 ^ res ) & 0x10 ) ? FLAG_H : 0 );
268	268
269	269	#define OP_NEG8(X)  res = -X; \
270		cpustate->PS1 = cpustate->PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
271		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_C | FLAG_Z : 0 ); \
272		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
273		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0x80 ) ? FLAG_V : 0 );
	270	m_PS1 = m_PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
	271	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_C | FLAG_Z : 0 ); \
	272	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
	273	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0x80 ) ? FLAG_V : 0 );
274	274
275	275	#define OP_COM8(X)  res = ~X; \
276		cpustate->PS1 = cpustate->PS1 & ( FLAG_C | FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
277		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
278		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
	276	m_PS1 = m_PS1 & ( FLAG_C | FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
	277	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	278	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
279	279
280	280	#define OP_RR8(X)   d1 = X; \
281	281	res = d1 >> 1; \
282	282	if ( d1 & 0x01 ) { \
283	283	res |= 0x80; \
284	284	} \
285		cpustate->PS1 = cpustate->PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
286		cpustate->PS1 = cpustate->PS1 | ( ( d1 & 0x01 ) ? FLAG_C : 0 ); \
287		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
288		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
289		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d1 ^ res ) & 0x80 ) && ! ( res & 0x80 ) ) ? FLAG_V : 0 );
	285	m_PS1 = m_PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
	286	m_PS1 = m_PS1 | ( ( d1 & 0x01 ) ? FLAG_C : 0 ); \
	287	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	288	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
	289	m_PS1 = m_PS1 | ( ( ( ( d1 ^ res ) & 0x80 ) && ! ( res & 0x80 ) ) ? FLAG_V : 0 );
290	290
291	291	#define OP_RL8(X)   d1 = X; \
292	292	res = d1 << 1; \
293	293	if ( d1 & 0x80 ) { \
294	294	res |= 0x01; \
295	295	} \
296		cpustate->PS1 = cpustate->PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
297		cpustate->PS1 = cpustate->PS1 | ( ( d1 & 0x80 ) ? FLAG_C : 0 ); \
298		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
299		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
300		cpustate->PS1 = cpustate->PS1 | ( ( ( d1 ^ res ) & 0x80 ) ? FLAG_V : 0 );
	296	m_PS1 = m_PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
	297	m_PS1 = m_PS1 | ( ( d1 & 0x80 ) ? FLAG_C : 0 ); \
	298	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	299	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
	300	m_PS1 = m_PS1 | ( ( ( d1 ^ res ) & 0x80 ) ? FLAG_V : 0 );
301	301
302	302	#define OP_RRC8(X)  d1 = X; \
303	303	res = d1 >> 1; \
304		if ( cpustate->PS1 & FLAG_C ) { \
	304	if ( m_PS1 & FLAG_C ) { \
305	305	res |= 0x80; \
306	306	} \
307		cpustate->PS1 = cpustate->PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
308		cpustate->PS1 = cpustate->PS1 | ( ( d1 & 0x01 ) ? FLAG_C : 0 ); \
309		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
310		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
311		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d1 ^ res ) & 0x80 ) && ! ( res & 0x80 ) ) ? FLAG_V : 0 );
	307	m_PS1 = m_PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
	308	m_PS1 = m_PS1 | ( ( d1 & 0x01 ) ? FLAG_C : 0 ); \
	309	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	310	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
	311	m_PS1 = m_PS1 | ( ( ( ( d1 ^ res ) & 0x80 ) && ! ( res & 0x80 ) ) ? FLAG_V : 0 );
312	312
313	313	#define OP_RLC8(X)  d1 = X; \
314	314	res = d1 << 1; \
315		if ( cpustate->PS1 & FLAG_C ) { \
	315	if ( m_PS1 & FLAG_C ) { \
316	316	res |= 0x01; \
317	317	} \
318		cpustate->PS1 = cpustate->PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
319		cpustate->PS1 = cpustate->PS1 | ( ( d1 & 0x80 ) ? FLAG_C : 0 ); \
320		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
321		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
322		cpustate->PS1 = cpustate->PS1 | ( ( ( d1 ^ res ) & 0x80 ) ? FLAG_V : 0 );
	318	m_PS1 = m_PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
	319	m_PS1 = m_PS1 | ( ( d1 & 0x80 ) ? FLAG_C : 0 ); \
	320	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	321	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
	322	m_PS1 = m_PS1 | ( ( ( d1 ^ res ) & 0x80 ) ? FLAG_V : 0 );
323	323
324	324	#define OP_SRL8(X)  d1 = X; \
325	325	res = d1 >> 1; \
326		cpustate->PS1 = cpustate->PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
327		cpustate->PS1 = cpustate->PS1 | ( ( d1 & 0x01 ) ? FLAG_C : 0 ); \
328		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 );
	326	m_PS1 = m_PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
	327	m_PS1 = m_PS1 | ( ( d1 & 0x01 ) ? FLAG_C : 0 ); \
	328	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 );
329	329
330	330	#define OP_SRA8(X)  d1 = X; \
331	331	res = d1 >> 1; \
332	332	if ( d1 & 0x80 ) { \
333	333	res |= 0x80; \
334	334	} \
335		cpustate->PS1 = cpustate->PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
336		cpustate->PS1 = cpustate->PS1 | ( ( d1 & 0x01 ) ? FLAG_C : 0 ); \
337		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
338		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
	335	m_PS1 = m_PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
	336	m_PS1 = m_PS1 | ( ( d1 & 0x01 ) ? FLAG_C : 0 ); \
	337	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	338	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
339	339
340	340	#define OP_SLL8(X)  d1 = X; \
341	341	res = d1 << 1; \
342		cpustate->PS1 = cpustate->PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
343		cpustate->PS1 = cpustate->PS1 | ( ( d1 & 0x80 ) ? FLAG_C : 0 ); \
344		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
345		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
	342	m_PS1 = m_PS1 & ( FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
	343	m_PS1 = m_PS1 | ( ( d1 & 0x80 ) ? FLAG_C : 0 ); \
	344	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	345	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
346	346
347	347	#define OP_INC8(X)  d1 = X; \
348	348	res = d1 + 1; \
349		cpustate->PS1 = cpustate->PS1 & ( FLAG_C | FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
350		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
351		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
352		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d1 ^ res ) & 0x80 ) && ! ( res & 0x80 ) ) ? FLAG_V : 0 );
	349	m_PS1 = m_PS1 & ( FLAG_C | FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
	350	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	351	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
	352	m_PS1 = m_PS1 | ( ( ( ( d1 ^ res ) & 0x80 ) && ! ( res & 0x80 ) ) ? FLAG_V : 0 );
353	353
354	354	#define OP_INC16(X) d1 = X; \
355	355	res = d1 + 1; \
356		cpustate->PS1 = cpustate->PS1 & ( FLAG_C | FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
357		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
358		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x8000 ) ? FLAG_S : 0 ); \
359		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d1 ^ res ) & 0x8000 ) && ! ( res & 0x8000 ) ) ? FLAG_V : 0 );
	356	m_PS1 = m_PS1 & ( FLAG_C | FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
	357	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	358	m_PS1 = m_PS1 | ( ( res & 0x8000 ) ? FLAG_S : 0 ); \
	359	m_PS1 = m_PS1 | ( ( ( ( d1 ^ res ) & 0x8000 ) && ! ( res & 0x8000 ) ) ? FLAG_V : 0 );
360	360
361	361	#define OP_DEC8(X)  d1 = X; \
362	362	res = d1 - 1; \
363		cpustate->PS1 = cpustate->PS1 & ( FLAG_C | FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
364		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
365		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
366		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d1 ^ res ) & 0x80 ) && ( res & 0x80 ) ) ? FLAG_V : 0 );
	363	m_PS1 = m_PS1 & ( FLAG_C | FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
	364	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	365	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 ); \
	366	m_PS1 = m_PS1 | ( ( ( ( d1 ^ res ) & 0x80 ) && ( res & 0x80 ) ) ? FLAG_V : 0 );
367	367
368	368	#define OP_DEC16(X) d1 = X; \
369	369	res = d1 - 1; \
370		cpustate->PS1 = cpustate->PS1 & ( FLAG_C | FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
371		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 ); \
372		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x8000 ) ? FLAG_S : 0 ); \
373		cpustate->PS1 = cpustate->PS1 | ( ( ( ( d1 ^ res ) & 0x8000 ) && ( res & 0x8000 ) ) ? FLAG_V : 0 );
	370	m_PS1 = m_PS1 & ( FLAG_C | FLAG_D | FLAG_H | FLAG_B | FLAG_I ); \
	371	m_PS1 = m_PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 ); \
	372	m_PS1 = m_PS1 | ( ( res & 0x8000 ) ? FLAG_S : 0 ); \
	373	m_PS1 = m_PS1 | ( ( ( ( d1 ^ res ) & 0x8000 ) && ( res & 0x8000 ) ) ? FLAG_V : 0 );
374	374
375	375	#define OP_AND8(X,Y)    d1 = X; \
376	376	d2 = Y; \
377	377	res = d1 & d2; \
378		cpustate->PS1 = cpustate->PS1 & ( FLAG_B | FLAG_I | FLAG_H | FLAG_D ); \
379		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
380		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
	378	m_PS1 = m_PS1 & ( FLAG_B | FLAG_I | FLAG_H | FLAG_D ); \
	379	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	380	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
381	381
382	382	#define OP_AND16(X,Y)   d1 = X; \
383	383	d2 = Y; \
384	384	res = d1 & d2; \
385		cpustate->PS1 = cpustate->PS1 & ( FLAG_C | FLAG_S | FLAG_B | FLAG_I | FLAG_H | FLAG_D ); \
386		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 );
	385	m_PS1 = m_PS1 & ( FLAG_C | FLAG_S | FLAG_B | FLAG_I | FLAG_H | FLAG_D ); \
	386	m_PS1 = m_PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 );
387	387
388	388	#define OP_OR8(X,Y) d1 = X; \
389	389	d2 = Y; \
390	390	res = d1 | d2; \
391		cpustate->PS1 = cpustate->PS1 & ( FLAG_B | FLAG_I | FLAG_H | FLAG_D ); \
392		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
393		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
	391	m_PS1 = m_PS1 & ( FLAG_B | FLAG_I | FLAG_H | FLAG_D ); \
	392	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	393	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
394	394
395	395	#define OP_OR16(X,Y)    d1 = X; \
396	396	d2 = Y; \
397	397	res = d1 | d2; \
398		cpustate->PS1 = cpustate->PS1 & ( FLAG_B | FLAG_I | FLAG_H | FLAG_D | FLAG_C | FLAG_S ); \
399		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 );
	398	m_PS1 = m_PS1 & ( FLAG_B | FLAG_I | FLAG_H | FLAG_D | FLAG_C | FLAG_S ); \
	399	m_PS1 = m_PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 );
400	400
401	401	#define OP_XOR8(X,Y)    d1 = X; \
402	402	d2 = Y; \
403	403	res = d1 ^ d2; \
404		cpustate->PS1 = cpustate->PS1 & ( FLAG_B | FLAG_I | FLAG_H | FLAG_D ); \
405		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
406		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
	404	m_PS1 = m_PS1 & ( FLAG_B | FLAG_I | FLAG_H | FLAG_D ); \
	405	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0 ) ? FLAG_Z : 0 ); \
	406	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
407	407
408	408	#define OP_XOR16(X,Y)   d1 = X; \
409	409	d2 = Y; \
410	410	res = d1 ^ d2; \
411		cpustate->PS1 = cpustate->PS1 & ( FLAG_B | FLAG_I | FLAG_H | FLAG_D | FLAG_C | FLAG_S ); \
412		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 );
	411	m_PS1 = m_PS1 & ( FLAG_B | FLAG_I | FLAG_H | FLAG_D | FLAG_C | FLAG_S ); \
	412	m_PS1 = m_PS1 | ( ( ( res & 0xFFFF ) == 0 ) ? FLAG_Z : 0 );
413	413
414	414	#define OP_DA8(X)   d1 = X; \
415	415	res = d1; \
416		if ( cpustate->PS1 & FLAG_D ) { \
417		if ( cpustate->PS1 & FLAG_C ) { \
418		if ( cpustate->PS1 & FLAG_H ) { \
	416	if ( m_PS1 & FLAG_D ) { \
	417	if ( m_PS1 & FLAG_C ) { \
	418	if ( m_PS1 & FLAG_H ) { \
419	419	res += 0x9A; \
420	420	} else { \
421	421	res += 0xA0; \
422	422	} \
423	423	} else { \
424		if ( cpustate->PS1 & FLAG_H ) { \
	424	if ( m_PS1 & FLAG_H ) { \
425	425	res += 0xFA; \
426	426	} \
427	427	} \
428	428	} else { \
429		if ( cpustate->PS1 & FLAG_C ) { \
430		if ( cpustate->PS1 & FLAG_H ) { \
	429	if ( m_PS1 & FLAG_C ) { \
	430	if ( m_PS1 & FLAG_H ) { \
431	431	res += 0x66; \
432	432	} else { \
433	433	if ( ( res & 0x0F ) < 10 ) { \
r20617	r20618
437	437	} \
438	438	} \
439	439	} else { \
440		if ( cpustate->PS1 & FLAG_H ) { \
	440	if ( m_PS1 & FLAG_H ) { \
441	441	if ( ( res & 0xF0 ) < 0xA0 ) { \
442	442	res += 0x06; \
443	443	} else { \
444	444	res += 0x66; \
445		cpustate->PS1 = cpustate->PS1 | FLAG_C; \
	445	m_PS1 = m_PS1 | FLAG_C; \
446	446	} \
447	447	} else { \
448	448	if ( ( res & 0x0F ) < 10 ) { \
449	449	if ( ( res & 0xF0 ) >= 0xA0 ) { \
450	450	res += 0x60; \
451		cpustate->PS1 = cpustate->PS1 | FLAG_C; \
	451	m_PS1 = m_PS1 | FLAG_C; \
452	452	} \
453	453	} else { \
454	454	if ( ( res & 0xF0 ) < 0x90 ) { \
455	455	res += 0x06; \
456	456	} else { \
457	457	res += 0x66; \
458		cpustate->PS1 = cpustate->PS1 | FLAG_C; \
	458	m_PS1 = m_PS1 | FLAG_C; \
459	459	} \
460	460	} \
461	461	} \
462	462	} \
463	463	} \
464		cpustate->PS1 = cpustate->PS1 & ~ ( FLAG_Z | FLAG_S ); \
465		cpustate->PS1 = cpustate->PS1 | ( ( ( res & 0xFF ) == 0x00 ) ? FLAG_Z : 0 ); \
466		cpustate->PS1 = cpustate->PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
	464	m_PS1 = m_PS1 & ~ ( FLAG_Z | FLAG_S ); \
	465	m_PS1 = m_PS1 | ( ( ( res & 0xFF ) == 0x00 ) ? FLAG_Z : 0 ); \
	466	m_PS1 = m_PS1 | ( ( res & 0x80 ) ? FLAG_S : 0 );
467	467
468	468	#define OP_SWAP8(X) d1 = X; \
469	469	res = ( d1 << 4 ) | ( d1 >> 4 );
r20617	r20618
471	471	#define CHECK_CC    res = 0; \
472	472	switch( op & 0x0F ) { \
473	473	case 0x00: /* F   */ res = 0; break; \
474		case 0x01: /* LT  */ if ( ( cpustate->PS1 & FLAG_S ) ^ ( ( cpustate->PS1 & FLAG_V ) << 1 ) ) res = 1; break; \
475		case 0x02: /* LE  */ if ( ( ( cpustate->PS1 & FLAG_S ) && ! ( cpustate->PS1 & FLAG_V ) ) || ( ( cpustate->PS1 & FLAG_S ) && ( cpustate->PS1 & FLAG_V ) && ( cpustate->PS1 & FLAG_Z ) ) || ( ! ( cpustate->PS1 & FLAG_S ) && ( ( cpustate->PS1 & FLAG_Z ) || (cpustate->PS1 & FLAG_V ) ) ) ) res = 1; break; \
476		case 0x03: /* ULE */ if ( cpustate->PS1 & FLAG_Z || cpustate->PS1 & FLAG_C ) res = 1; break; \
477		case 0x04: /* OV  */ if ( cpustate->PS1 & FLAG_V ) res = 1; break; \
478		case 0x05: /* MI  */ if ( cpustate->PS1 & FLAG_S ) res = 1; break; \
479		case 0x06: /* Z   */ if ( cpustate->PS1 & FLAG_Z ) res = 1; break; \
480		case 0x07: /* C   */ if ( cpustate->PS1 & FLAG_C ) res = 1; break; \
	474	case 0x01: /* LT  */ if ( ( m_PS1 & FLAG_S ) ^ ( ( m_PS1 & FLAG_V ) << 1 ) ) res = 1; break; \
	475	case 0x02: /* LE  */ if ( ( ( m_PS1 & FLAG_S ) && ! ( m_PS1 & FLAG_V ) ) || ( ( m_PS1 & FLAG_S ) && ( m_PS1 & FLAG_V ) && ( m_PS1 & FLAG_Z ) ) || ( ! ( m_PS1 & FLAG_S ) && ( ( m_PS1 & FLAG_Z ) || (m_PS1 & FLAG_V ) ) ) ) res = 1; break; \
	476	case 0x03: /* ULE */ if ( m_PS1 & FLAG_Z || m_PS1 & FLAG_C ) res = 1; break; \
	477	case 0x04: /* OV  */ if ( m_PS1 & FLAG_V ) res = 1; break; \
	478	case 0x05: /* MI  */ if ( m_PS1 & FLAG_S ) res = 1; break; \
	479	case 0x06: /* Z   */ if ( m_PS1 & FLAG_Z ) res = 1; break; \
	480	case 0x07: /* C   */ if ( m_PS1 & FLAG_C ) res = 1; break; \
481	481	case 0x08: /* T   */ res = 1; break; \
482		case 0x09: /* GE  */ if ( ! ( ( cpustate->PS1 & FLAG_S ) ^ ( ( cpustate->PS1 & FLAG_V ) << 1 ) ) ) res = 1; break; \
483		case 0x0A: /* GT  */ if ( ( ! ( cpustate->PS1 & FLAG_Z ) && ( cpustate->PS1 & FLAG_S ) && ( cpustate->PS1 & FLAG_V ) ) || ( ! ( cpustate->PS1 & FLAG_Z ) && ! ( cpustate->PS1 & FLAG_V ) && ! ( cpustate->PS1 & FLAG_S ) ) ) res = 1; break; \
484		case 0x0B: /* UGT */ if ( ! ( cpustate->PS1 & FLAG_Z || cpustate->PS1 & FLAG_C ) ) res = 1; break; \
485		case 0x0C: /* NOV */ if ( ! (cpustate->PS1 & FLAG_V) ) res = 1; break; \
486		case 0x0D: /* PL  */ if ( ! (cpustate->PS1 & FLAG_S) ) res = 1; break; \
487		case 0x0E: /* NZ  */ if ( ! (cpustate->PS1 & FLAG_Z) ) res = 1; break; \
488		case 0x0F: /* NC  */ if ( ! (cpustate->PS1 & FLAG_C) ) res = 1; break; \
	482	case 0x09: /* GE  */ if ( ! ( ( m_PS1 & FLAG_S ) ^ ( ( m_PS1 & FLAG_V ) << 1 ) ) ) res = 1; break; \
	483	case 0x0A: /* GT  */ if ( ( ! ( m_PS1 & FLAG_Z ) && ( m_PS1 & FLAG_S ) && ( m_PS1 & FLAG_V ) ) || ( ! ( m_PS1 & FLAG_Z ) && ! ( m_PS1 & FLAG_V ) && ! ( m_PS1 & FLAG_S ) ) ) res = 1; break; \
	484	case 0x0B: /* UGT */ if ( ! ( m_PS1 & FLAG_Z || m_PS1 & FLAG_C ) ) res = 1; break; \
	485	case 0x0C: /* NOV */ if ( ! (m_PS1 & FLAG_V) ) res = 1; break; \
	486	case 0x0D: /* PL  */ if ( ! (m_PS1 & FLAG_S) ) res = 1; break; \
	487	case 0x0E: /* NZ  */ if ( ! (m_PS1 & FLAG_Z) ) res = 1; break; \
	488	case 0x0F: /* NC  */ if ( ! (m_PS1 & FLAG_C) ) res = 1; break; \
489	489	}
490	490
491		#define PUSH8(X)    cpustate->SP--; \
492		if ( ( cpustate->SYS & 0x40 ) == 0 ) cpustate->SP &= 0xFF; \
493		sm85cpu_mem_writebyte( cpustate, cpustate->SP, X );
	491	#define PUSH8(X)    m_SP--; \
	492	if ( ( m_SYS & 0x40 ) == 0 ) m_SP &= 0xFF; \
	493	mem_writebyte( m_SP, X );
494	494
495		#define POP8(X)     X = sm85cpu_mem_readbyte( cpustate, cpustate->SP ); \
496		cpustate->SP++; \
497		if ( ( cpustate->SYS & 0x40 ) == 0 ) cpustate->SP &= 0xFF;
	495	#define POP8(X)     X = mem_readbyte( m_SP ); \
	496	m_SP++; \
	497	if ( ( m_SYS & 0x40 ) == 0 ) m_SP &= 0xFF;
498	498
499	499	case 0x00:  /* CLR R - 4 cycles - Flags affected: -------- */
500	500	ARG_R;
501		sm85cpu_mem_writebyte( cpustate, r1, 0 );
	501	mem_writebyte( r1, 0 );
502	502	mycycles += 4;
503	503	break;
504	504	case 0x01:  /* NEG R - 5 cycles - Flags affected: CZSV---- */
505	505	ARG_R;
506		OP_NEG8( sm85cpu_mem_readbyte( cpustate, r1 ) );
507		sm85cpu_mem_writebyte( cpustate, r1 , res & 0xFF );
	506	OP_NEG8( mem_readbyte( r1 ) );
	507	mem_writebyte( r1 , res & 0xFF );
508	508	mycycles += 5;
509	509	break;
510	510	case 0x02:  /* COM R - 4 cycles - Flags affected: -ZS0---- */
511	511	ARG_R;
512		OP_COM8( sm85cpu_mem_readbyte( cpustate, r1 ) );
513		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	512	OP_COM8( mem_readbyte( r1 ) );
	513	mem_writebyte( r1, res & 0xFF );
514	514	mycycles += 4;
515	515	break;
516	516	case 0x03:  /* RR R - 4 cycles - Flags affected: CZSV---- */
517	517	ARG_R;
518		OP_RR8( sm85cpu_mem_readbyte( cpustate, r1 ) );
519		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	518	OP_RR8( mem_readbyte( r1 ) );
	519	mem_writebyte( r1, res & 0xFF );
520	520	mycycles += 4;
521	521	break;
522	522	case 0x04:  /* RL R - 4 cycles - Flags affected: CZSV---- */
523	523	ARG_R;
524		OP_RL8( sm85cpu_mem_readbyte( cpustate, r1 ) );
525		sm85cpu_mem_writebyte( cpustate, r1 , res & 0xFF );
	524	OP_RL8( mem_readbyte( r1 ) );
	525	mem_writebyte( r1 , res & 0xFF );
526	526	mycycles += 4;
527	527	break;
528	528	case 0x05:  /* RRC R - 4 cycles - Flags affected: CZSV---- */
529	529	ARG_R;
530		OP_RRC8( sm85cpu_mem_readbyte( cpustate, r1 ) );
531		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	530	OP_RRC8( mem_readbyte( r1 ) );
	531	mem_writebyte( r1, res & 0xFF );
532	532	mycycles += 4;
533	533	break;
534	534	case 0x06:  /* RLC R - 4 cycles - Flags affected: CZSV---- */
535	535	ARG_R;
536		OP_RLC8( sm85cpu_mem_readbyte( cpustate, r1 ) );
537		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	536	OP_RLC8( mem_readbyte( r1 ) );
	537	mem_writebyte( r1, res & 0xFF );
538	538	mycycles += 4;
539	539	break;
540	540	case 0x07:  /* SRL R - 4 cycles - Flags affected: CZ00---- */
541	541	ARG_R;
542		OP_SRL8( sm85cpu_mem_readbyte( cpustate, r1 ) );
543		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	542	OP_SRL8( mem_readbyte( r1 ) );
	543	mem_writebyte( r1, res & 0xFF );
544	544	mycycles += 4;
545	545	break;
546	546	case 0x08:  /* INC R - 4 cycles - Flags affected: -ZSV---- */
547	547	ARG_R;
548		OP_INC8( sm85cpu_mem_readbyte( cpustate, r1 ) );
549		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	548	OP_INC8( mem_readbyte( r1 ) );
	549	mem_writebyte( r1, res & 0xFF );
550	550	mycycles += 4;
551	551	break;
552	552	case 0x09:  /* DEC R - 4 cycles - Flags affected: -ZSV---- */
553	553	ARG_R;
554		OP_DEC8( sm85cpu_mem_readbyte( cpustate, r1 ) );
555		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	554	OP_DEC8( mem_readbyte( r1 ) );
	555	mem_writebyte( r1, res & 0xFF );
556	556	mycycles += 4;
557	557	break;
558	558	case 0x0A:  /* SRA R - 4 cycles - Flags affected: CZS0---- */
559	559	ARG_R;
560		OP_SRA8( sm85cpu_mem_readbyte( cpustate, r1 ) );
561		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	560	OP_SRA8( mem_readbyte( r1 ) );
	561	mem_writebyte( r1, res & 0xFF );
562	562	mycycles += 4;
563	563	break;
564	564	case 0x0B:  /* SLL R - 4 cycles - Flags affected: CZS0---- */
565	565	ARG_R;
566		OP_SLL8( sm85cpu_mem_readbyte( cpustate, r1 ) );
567		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	566	OP_SLL8( mem_readbyte( r1 ) );
	567	mem_writebyte( r1, res & 0xFF );
568	568	mycycles += 4;
569	569	break;
570	570	case 0x0C:  /* DA R - 4 cycles - Flags affected: CZS----- */
571	571	ARG_R;
572		OP_DA8( sm85cpu_mem_readbyte( cpustate, r1 ) );
573		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	572	OP_DA8( mem_readbyte( r1 ) );
	573	mem_writebyte( r1, res & 0xFF );
574	574	mycycles += 4;
575	575	break;
576	576	case 0x0D:  /* SWAP R - 7 cycles - Flags affected: -------- */
577	577	ARG_R;
578		OP_SWAP8( sm85cpu_mem_readbyte( cpustate, r1 ) );
579		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	578	OP_SWAP8( mem_readbyte( r1 ) );
	579	mem_writebyte( r1, res & 0xFF );
580	580	mycycles += 7;
581	581	break;
582	582	case 0x0E:  /* PUSH R - 5?/12? (8bit SP),10 (16bit SP) cycles */
583	583	ARG_R;
584		PUSH8( sm85cpu_mem_readbyte( cpustate, r1 ) );
585		mycycles += ( ( cpustate->SYS & 0x40 ) ? 12 : 10 );
	584	PUSH8( mem_readbyte( r1 ) );
	585	mycycles += ( ( m_SYS & 0x40 ) ? 12 : 10 );
586	586	break;
587	587	case 0x0F:  /* POP R - 9,8 cycles */
588	588	ARG_R;
589	589	POP8( r2 );
590		sm85cpu_mem_writebyte( cpustate, r1, r2 );
591		mycycles += ( ( cpustate->SYS & 0x40 ) ? 9 : 8 );
	590	mem_writebyte( r1, r2 );
	591	mycycles += ( ( m_SYS & 0x40 ) ? 9 : 8 );
592	592	break;
593	593	case 0x10:  /* CMP Rr,Rs - 5 cycles - Flags affected: CZSV---- */
594	594	ARG_rr;
595		OP_CMP8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
	595	OP_CMP8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
596	596	mycycles += 5;
597	597	break;
598	598	case 0x11:  /* ADD Rr,Rs - 5 cycles - Flags affected: CZSV0H-- */
599	599	ARG_rr;
600		OP_ADD8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
601		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	600	OP_ADD8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	601	mem_writebyte( r1, res & 0xFF );
602	602	mycycles += 5;
603	603	break;
604	604	case 0x12:  /* SUB Rr,Rs - 5 cycles - Flags affected: CZSV1H-- */
605	605	ARG_rr;
606		OP_SUB8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
607		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	606	OP_SUB8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	607	mem_writebyte( r1, res & 0xFF );
608	608	mycycles += 5;
609	609	break;
610	610	case 0x13:  /* ADC Rr,Rs - 5 cycles - Flags affected: CZSV0H-- */
611	611	ARG_rr;
612		OP_ADC8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
613		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	612	OP_ADC8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	613	mem_writebyte( r1, res & 0xFF );
614	614	mycycles += 5;
615	615	break;
616	616	case 0x14:  /* SBC Rr,Rs - 5 cycles - Flags affected: CZSV1H-- */
617	617	ARG_rr;
618		OP_SBC8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
619		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	618	OP_SBC8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	619	mem_writebyte( r1, res & 0xFF );
620	620	mycycles += 5;
621	621	break;
622	622	case 0x15:  /* AND Rr,Rs - 5 cycles - Flags affected: -ZS0---- */
623	623	ARG_rr;
624		OP_AND8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
625		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	624	OP_AND8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	625	mem_writebyte( r1, res & 0xFF );
626	626	mycycles += 5;
627	627	break;
628	628	case 0x16:  /* OR Rr,Rs - 5 cycles - Flags affected: -ZS0---- */
629	629	ARG_rr;
630		OP_OR8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
631		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	630	OP_OR8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	631	mem_writebyte( r1, res & 0xFF );
632	632	mycycles += 5;
633	633	break;
634	634	case 0x17:  /* XOR Rr,Rs - 5 cycles - Flags affected: -ZS0---- */
635	635	ARG_rr;
636		OP_XOR8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
637		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	636	OP_XOR8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	637	mem_writebyte( r1, res & 0xFF );
638	638	mycycles += 5;
639	639	break;
640	640	case 0x18:  /* INCW S - 8 cycles - Flags affected: -ZSV---- */
641	641	ARG_R;
642		OP_INC16( sm85cpu_mem_readword( cpustate, r1 ) );
643		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	642	OP_INC16( mem_readword( r1 ) );
	643	mem_writeword( r1, res & 0xFFFF );
644	644	mycycles += 8;
645	645	break;
646	646	case 0x19:  /* DECW S - 8 cycles - Flags affected: -ZSV---- */
647	647	ARG_R;
648		OP_DEC16( sm85cpu_mem_readword( cpustate, r1 ) );
649		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	648	OP_DEC16( mem_readword( r1 ) );
	649	mem_writeword( r1, res & 0xFFFF );
650	650	mycycles += 8;
651	651	break;
652	652	case 0x1A:  /* CLR/NEG/COM/RR/RL/RRC/RLC/SRL @Rr - 7/8/7/7/7/7/7/6 cycles */
653	653	ARG_rr;
654	654	res = 0;
655		s1 = sm85cpu_mem_readbyte( cpustate, r1 );
	655	s1 = mem_readbyte( r1 );
656	656	switch( r2 ) {
657	657	case 0x00:  /* Flags affected: -------- */
658	658	res = 0;
659	659	mycycles += 7;
660	660	break;
661	661	case 0x01:  /* Flags affected: CZSV---- */
662		OP_NEG8( sm85cpu_mem_readbyte( cpustate, s1 ) );
	662	OP_NEG8( mem_readbyte( s1 ) );
663	663	mycycles += 8;
664	664	break;
665	665	case 0x02:  /* Flags affected: -ZS0---- */
666		OP_COM8( sm85cpu_mem_readbyte( cpustate, s1 ) );
	666	OP_COM8( mem_readbyte( s1 ) );
667	667	mycycles += 7;
668	668	break;
669	669	case 0x03:  /* Flags affected: CZSV---- */
670		OP_RR8( sm85cpu_mem_readbyte( cpustate, s1 ) );
	670	OP_RR8( mem_readbyte( s1 ) );
671	671	mycycles += 7;
672	672	break;
673	673	case 0x04:  /* Flags affected: CZSV---- */
674		OP_RL8( sm85cpu_mem_readbyte( cpustate, s1 ) );
	674	OP_RL8( mem_readbyte( s1 ) );
675	675	mycycles += 7;
676	676	break;
677	677	case 0x05:  /* Flags affected: CZSV---- */
678		OP_RRC8( sm85cpu_mem_readbyte( cpustate, s1 ) );
	678	OP_RRC8( mem_readbyte( s1 ) );
679	679	mycycles += 7;
680	680	break;
681	681	case 0x06:  /* Flags affected: CZSV---- */
682		OP_RLC8( sm85cpu_mem_readbyte( cpustate, s1 ) );
	682	OP_RLC8( mem_readbyte( s1 ) );
683	683	mycycles += 7;
684	684	break;
685	685	case 0x07:  /* Flags affected: CZ00---- */
686		OP_SRL8( sm85cpu_mem_readbyte( cpustate, s1 ) );
	686	OP_SRL8( mem_readbyte( s1 ) );
687	687	mycycles += 6;
688	688	break;
689	689	}
690		sm85cpu_mem_writebyte( cpustate, s1, res & 0xFF );
	690	mem_writebyte( s1, res & 0xFF );
691	691	break;
692	692	case 0x1B:  /* INC/DEC/SRA/SLL/DA/SWAP/PUSH/POP @Rr - 7,7,6,7,9,13,8,12,11 cycles */
693	693	ARG_rr;
694		s1 = sm85cpu_mem_readbyte( cpustate, r1 );
	694	s1 = mem_readbyte( r1 );
695	695	switch( r2 ) {
696	696	case 0x00:  /* Flags affected: -ZSV---- */
697		OP_INC8( sm85cpu_mem_readbyte( cpustate, s1 ) );
698		sm85cpu_mem_writebyte( cpustate, s1, res & 0xFF );
	697	OP_INC8( mem_readbyte( s1 ) );
	698	mem_writebyte( s1, res & 0xFF );
699	699	mycycles += 7;
700	700	break;
701	701	case 0x01:  /* Flags affected: -ZSV---- */
702		OP_DEC8( sm85cpu_mem_readbyte( cpustate, s1 ) );
703		sm85cpu_mem_writebyte( cpustate, s1, res & 0xFF );
	702	OP_DEC8( mem_readbyte( s1 ) );
	703	mem_writebyte( s1, res & 0xFF );
704	704	mycycles += 7;
705	705	break;
706	706	case 0x02:  /* Flags affected: CZS0---- */
707		OP_SRA8( sm85cpu_mem_readbyte( cpustate, s1 ) );
708		sm85cpu_mem_writebyte( cpustate, s1, res & 0xFF );
	707	OP_SRA8( mem_readbyte( s1 ) );
	708	mem_writebyte( s1, res & 0xFF );
709	709	mycycles += 6;
710	710	break;
711	711	case 0x03:  /* Flags affected: CZS0---- */
712		OP_SLL8( sm85cpu_mem_readbyte( cpustate, s1 ) );
713		sm85cpu_mem_writebyte( cpustate, s1, res & 0xFF );
	712	OP_SLL8( mem_readbyte( s1 ) );
	713	mem_writebyte( s1, res & 0xFF );
714	714	mycycles += 6;
715	715	break;
716	716	case 0x04:  /* Flags affected: CZS----- */
717		OP_DA8( sm85cpu_mem_readbyte( cpustate, s1 ) );
718		sm85cpu_mem_writebyte( cpustate, s1, res & 0xFF );
	717	OP_DA8( mem_readbyte( s1 ) );
	718	mem_writebyte( s1, res & 0xFF );
719	719	mycycles += 7;
720	720	break;
721	721	case 0x05:  /* Flags affected: -------- */
722		OP_SWAP8( sm85cpu_mem_readbyte( cpustate, s1 ) );
723		sm85cpu_mem_writebyte( cpustate, s1, res & 0xFF );
	722	OP_SWAP8( mem_readbyte( s1 ) );
	723	mem_writebyte( s1, res & 0xFF );
724	724	mycycles += 9;
725	725	break;
726	726	case 0x06:  /* Flags affected: -------- */
727		PUSH8( sm85cpu_mem_readbyte( cpustate, s1 ) );
728		mycycles += ( ( cpustate->SYS & 0x40 ) ? 13 : 8 );
	727	PUSH8( mem_readbyte( s1 ) );
	728	mycycles += ( ( m_SYS & 0x40 ) ? 13 : 8 );
729	729	break;
730	730	case 0x07:  /* Flags affected: -------- */
731	731	POP8( res );
732		sm85cpu_mem_writebyte( cpustate, s1, res );
733		mycycles += ( ( cpustate->SYS & 0x40 ) ? 12 : 11 );
	732	mem_writebyte( s1, res );
	733	mycycles += ( ( m_SYS & 0x40 ) ? 12 : 11 );
734	734	break;
735	735	}
736	736	break;
737	737	case 0x1C:  /* BCLR 0xFFdd/d8(r),#b - 12,8 cycles - Flags affected: -------- */
738	738	ARG_riB;
739		sm85cpu_mem_writebyte( cpustate, s1, sm85cpu_mem_readbyte( cpustate, s1 ) & ~s2 );
	739	mem_writebyte( s1, mem_readbyte( s1 ) & ~s2 );
740	740	mycycles += ( ( r1 & 0x38 ) ? 8 : 12 );
741	741	break;
742	742	case 0x1D:  /* BSET 0xFFdd/d8(r),#b - 12,8 cycles - Flags affected: -------- */
743	743	ARG_riB;
744		sm85cpu_mem_writebyte( cpustate, s1, sm85cpu_mem_readbyte( cpustate, s1 ) | s2 );
	744	mem_writebyte( s1, mem_readbyte( s1 ) | s2 );
745	745	mycycles += ( ( r1 & 0x38 ) ? 8 : 12 );
746	746	break;
747	747	case 0x1E:  /* PUSHW S - 12,9 cycles - Flags affected: -------- */
748	748	ARG_R;
749		PUSH8( sm85cpu_mem_readbyte( cpustate, r1 + 1 ) );
750		PUSH8( sm85cpu_mem_readbyte( cpustate, r1 ) );
751		mycycles += ( ( cpustate->SYS & 0x40 ) ? 12 : 9 );
	749	PUSH8( mem_readbyte( r1 + 1 ) );
	750	PUSH8( mem_readbyte( r1 ) );
	751	mycycles += ( ( m_SYS & 0x40 ) ? 12 : 9 );
752	752	break;
753	753	case 0x1F:  /* POPW S - 12,13 cycles - Flags affected: -------- */
754	754	ARG_R;
755	755	POP8( r2 );
756		sm85cpu_mem_writebyte( cpustate, r1, r2 );
	756	mem_writebyte( r1, r2 );
757	757	POP8( r2 );
758		sm85cpu_mem_writebyte( cpustate, r1 + 1, r2 );
759		mycycles += ( ( cpustate->SYS & 0x40 ) ? 12 : 13 );
	758	mem_writebyte( r1 + 1, r2 );
	759	mycycles += ( ( m_SYS & 0x40 ) ? 12 : 13 );
760	760	break;
761	761	case 0x20:  /* CMP r,@r / CMP r,(r)+ / CMP r,@w / CMP r,w(r) / CMP r,-(r) - 7,8,10,8,9 cycles - Flags affected: CZSV---- */
762	762	ARG_rmb;
763		OP_CMP8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
	763	OP_CMP8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
764	764	switch( r2 & 0xC0 ) {
765	765	case 0x00:  mycycles += 7; break;
766	766	case 0x40:  mycycles += 8; break;
r20617	r20618
770	770	break;
771	771	case 0x21:  /* ADD r,@r / ADD r,(r)+ / ADD r,@w / ADD r,w(r) / ADD r,-(r) - 7,8,10,8,9 cycles - Flags affected: CZSV0H-- */
772	772	ARG_rmb;
773		OP_ADD8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
774		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	773	OP_ADD8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
	774	mem_writebyte( r1, res & 0xFF );
775	775	switch( r2 & 0xC0 ) {
776	776	case 0x00:  mycycles += 7; break;
777	777	case 0x40:  mycycles += 8; break;
r20617	r20618
781	781	break;
782	782	case 0x22:  /* SUB r,@r / SUB r,(r)+ / SUB r,@w / SUB r,w(r) / SUB r,-(r) - 7,8,10,8,9 cycles - Flags affected: CZSV1H-- */
783	783	ARG_rmb;
784		OP_SUB8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
785		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	784	OP_SUB8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
	785	mem_writebyte( r1, res & 0xFF );
786	786	switch( r2 & 0xC0 ) {
787	787	case 0x00:  mycycles += 7; break;
788	788	case 0x40:  mycycles += 8; break;
r20617	r20618
792	792	break;
793	793	case 0x23:  /* ADC r,@r / ADC r,(r)+ / ADC r,@w / ADC r,w(r) / ADC r,-(r) - 7,8,10,8,9 cycles - Flags affected: CZSV0H-- */
794	794	ARG_rmb;
795		OP_ADC8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
796		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	795	OP_ADC8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
	796	mem_writebyte( r1, res & 0xFF );
797	797	switch( r2 & 0xC0 ) {
798	798	case 0x00:  mycycles += 7; break;
799	799	case 0x40:  mycycles += 8; break;
r20617	r20618
803	803	break;
804	804	case 0x24:  /* SBC r,@r / SBC r,(r)+ / SBC r,@w / SBC r,w(r) / SBC r,-(r) - 7,8,10,8,9 cycles - Flags affected: CZSV1H-- */
805	805	ARG_rmb;
806		OP_SBC8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
807		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	806	OP_SBC8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
	807	mem_writebyte( r1, res & 0xFF );
808	808	switch( r2 & 0xC0 ) {
809	809	case 0x00:  mycycles += 7; break;
810	810	case 0x40:  mycycles += 8; break;
r20617	r20618
814	814	break;
815	815	case 0x25:  /* AND r,@r / AND r,(r)+ / AND r,@w / AND r,w(r) / AND r,-(r) - 7,8,10,8,9 cycles - Flags affected: -ZS0---- */
816	816	ARG_rmb;
817		OP_AND8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
818		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	817	OP_AND8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
	818	mem_writebyte( r1, res & 0xFF );
819	819	switch( r2 & 0xC0 ) {
820	820	case 0x00:  mycycles += 7; break;
821	821	case 0x40:  mycycles += 8; break;
r20617	r20618
825	825	break;
826	826	case 0x26:  /* OR r,@r / OR r,(r)+ / OR r,@w / OR r,w(r) / OR r,-(r) - 7,8,10,8,9 cycles - Flags affected: -ZS0---- */
827	827	ARG_rmb;
828		OP_OR8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
829		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	828	OP_OR8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
	829	mem_writebyte( r1, res & 0xFF );
830	830	switch( r2 & 0xC0 ) {
831	831	case 0x00:  mycycles += 7; break;
832	832	case 0x40:  mycycles += 8; break;
r20617	r20618
836	836	break;
837	837	case 0x27:  /* XOR r,@r / XOR r,(r)+ / XOR r,@w / XOR r,w(r) / XOR r,-(r) - 7,8,10,8,9 cycles - Flags affected: -ZS0---- */
838	838	ARG_rmb;
839		OP_XOR8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
840		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	839	OP_XOR8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
	840	mem_writebyte( r1, res & 0xFF );
841	841	switch( r2 & 0xC0 ) {
842	842	case 0x00:  mycycles += 7; break;
843	843	case 0x40:  mycycles += 8; break;
r20617	r20618
847	847	break;
848	848	case 0x28:  /* MOV r,@r / MOV r,(r)+ / MOV r,@w / MOV r,w(r) / MOV r,-(r) - 6,7,10,7,8 cycles - Flags affected: -------- */
849	849	ARG_rmb;
850		sm85cpu_mem_writebyte( cpustate, r1, sm85cpu_mem_readbyte( cpustate, s2 ) );
	850	mem_writebyte( r1, mem_readbyte( s2 ) );
851	851	switch( r2 & 0xC0 ) {
852	852	case 0x00:  mycycles += 6; break;
853	853	case 0x40:  mycycles += 7; break;
r20617	r20618
857	857	break;
858	858	case 0x29:  /* MOV @r,r / MOV (r)+,r / MOV @w,r / MOV w(r),r / MOV -(r),r - 8,8,10,9,9 cycles - Flags affected: -------- */
859	859	ARG_rmb;
860		sm85cpu_mem_writebyte( cpustate, s2, sm85cpu_mem_readbyte( cpustate, r1 ) );
	860	mem_writebyte( s2, mem_readbyte( r1 ) );
861	861	switch( r2 & 0xC0 ) {
862	862	case 0x00:  mycycles += 8; break;
863	863	case 0x40:  mycycles += 8; break;
r20617	r20618
867	867	break;
868	868	case 0x2A:  /* BBC FFii/i(Rr),#b,d8 - 16,12/14,10 cycles - Flags affected: -------- */
869	869	ARG_riBd;
870		if ( sm85cpu_mem_readbyte( cpustate, s1 ) & s2 ) {
	870	if ( mem_readbyte( s1 ) & s2 ) {
871	871	mycycles += 10;
872	872	} else {
873		cpustate->PC = cpustate->PC + ((INT8)d1);
	873	m_PC = m_PC + ((INT8)d1);
874	874	mycycles += 14;
875	875	}
876	876	if ( ( r1 & 0x38 ) == 0 ) {
r20617	r20618
879	879	break;
880	880	case 0x2B:  /* BBS FFii/i(Rr),#b,d8 - 16,12/14,10 cycles - Flags affected: -------- */
881	881	ARG_riBd;
882		if ( sm85cpu_mem_readbyte( cpustate, s1 ) & s2 ) {
883		cpustate->PC = cpustate->PC + ((INT8)d1);
	882	if ( mem_readbyte( s1 ) & s2 ) {
	883	m_PC = m_PC + ((INT8)d1);
884	884	mycycles += 14;
885	885	} else {
886	886	mycycles += 10;
r20617	r20618
891	891	break;
892	892	case 0x2C:  /* EXTS Rr - 6 cycles - Flags affected: -------- */
893	893	ARG_R;
894		res = sm85cpu_mem_readword( cpustate, r1 );
	894	res = mem_readword( r1 );
895	895	if ( res & 0x80 ) {
896	896	res = res | 0xFF00;
897	897	} else {
898	898	res = res & 0x00FF;
899	899	}
900		sm85cpu_mem_writeword( cpustate, r1, res );
	900	mem_writeword( r1, res );
901	901	mycycles += 6;
902	902	break;
903	903	case 0x2D:  /* unk2D - 4 cycles */
904		logerror( "%04X: unk%02x\n", cpustate->PC-1,op );
	904	logerror( "%04X: unk%02x\n", m_PC-1,op );
905	905	mycycles += 4;
906	906	break;
907	907	case 0x2E:  /* MOV PS0,#00 - 4 cycles - Flags affected: -------- */
908	908	ARG_R;
909		cpustate->PS0 = r1;
	909	m_PS0 = r1;
910	910	mycycles += 4;
911	911	break;
912	912	case 0x2F:  /* BTST R,i - 6 cycles - Flags affected: -Z-0---- */
913	913	ARG_RR;
914		cpustate->PS1 = cpustate->PS1 & ~ FLAG_V;
915		if ( ( sm85cpu_mem_readbyte( cpustate, r2 ) & r1 ) == 0x00 ) {
916		cpustate->PS1 = cpustate->PS1 | FLAG_Z;
	914	m_PS1 = m_PS1 & ~ FLAG_V;
	915	if ( ( mem_readbyte( r2 ) & r1 ) == 0x00 ) {
	916	m_PS1 = m_PS1 | FLAG_Z;
917	917	} else {
918		cpustate->PS1 = cpustate->PS1 & ( ~ FLAG_Z );
	918	m_PS1 = m_PS1 & ( ~ FLAG_Z );
919	919	}
920	920	mycycles += 6;
921	921	break;
922	922	case 0x30:  /* CMP r,@rr / CMP r,(rr)+ / CMP r,@ww / CMP r,ww(rr) / CMP r,-(rr) - 8,13,11,15,13 cycles - Flags affected: CZSV---- */
923	923	ARG_rmw;
924		OP_CMP8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
	924	OP_CMP8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
925	925	switch( r2 & 0xC0 ) {
926	926	case 0x00:  mycycles += 8; break;
927	927	case 0x40:  mycycles += 13; break;
r20617	r20618
931	931	break;
932	932	case 0x31:  /* ADD r,@rr / ADD r,(rr)+ / ADD r,@ww / ADD r,ww(rr) / ADD r,-(rr) - 8,13,11,15,13 cycles - Flags affected: CZSV0H-- */
933	933	ARG_rmw;
934		OP_ADD8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
935		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	934	OP_ADD8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
	935	mem_writebyte( r1, res & 0xFF );
936	936	switch( r2 & 0xC0 ) {
937	937	case 0x00:  mycycles += 8; break;
938	938	case 0x40:  mycycles += 13; break;
r20617	r20618
942	942	break;
943	943	case 0x32:  /* SUB r,@rr / SUB r,(rr)+ / SUB r,@ww / SUB r,ww(rr) / SUB r,-(rr) - 8,13,11,15,13 cycles - Flags affected: CZSV1H-- */
944	944	ARG_rmw;
945		OP_SUB8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
	945	OP_SUB8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
946	946	switch( r2 & 0xC0 ) {
947	947	case 0x00:  mycycles += 8; break;
948	948	case 0x40:  mycycles += 13; break;
r20617	r20618
952	952	break;
953	953	case 0x33:  /* ADC r,@rr / ADC r,(rr)+ / ADC r,@ww / ADC r,ww(rr) / ADC r,-(rr) - 8,13,11,15,13 cycles - Flags affected: CZSV0H-- */
954	954	ARG_rmw;
955		OP_ADC8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
956		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	955	OP_ADC8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
	956	mem_writebyte( r1, res & 0xFF );
957	957	switch( r2 & 0xC0 ) {
958	958	case 0x00:  mycycles += 8; break;
959	959	case 0x40:  mycycles += 13; break;
r20617	r20618
963	963	break;
964	964	case 0x34:  /* SBC r,@rr / SBC r,(rr)+ / SBC r,@ww / SBC r,ww(rr) / SBC r,-(rr) - 8,13,11,15,13 cycles - Flags affected: CZSV1H-- */
965	965	ARG_rmw;
966		OP_SBC8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
967		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	966	OP_SBC8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
	967	mem_writebyte( r1, res & 0xFF );
968	968	switch( r2 & 0xC0 ) {
969	969	case 0x00:  mycycles += 8; break;
970	970	case 0x40:  mycycles += 13; break;
r20617	r20618
974	974	break;
975	975	case 0x35:  /* AND r,@rr / AND r,(rr)+ / AND r,@ww / AND r,ww(rr) / AND r,-(rr) - 8,13,11,15,13 cycles - Flags affected: -ZS0---- */
976	976	ARG_rmw;
977		OP_AND8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
978		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	977	OP_AND8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
	978	mem_writebyte( r1, res & 0xFF );
979	979	switch( r2 & 0xC0 ) {
980	980	case 0x00:  mycycles += 8; break;
981	981	case 0x40:  mycycles += 13; break;
r20617	r20618
985	985	break;
986	986	case 0x36:  /* OR r,@rr / OR r,(rr)+ / OR r,@ww / OR r,ww(rr) / OR r,-(rr) - 8,13,11,15,13 cycles - Flags affected: -ZS0---- */
987	987	ARG_rmw;
988		OP_OR8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
989		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	988	OP_OR8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
	989	mem_writebyte( r1, res & 0xFF );
990	990	switch( r2 & 0xC0 ) {
991	991	case 0x00:  mycycles += 8; break;
992	992	case 0x40:  mycycles += 13; break;
r20617	r20618
996	996	break;
997	997	case 0x37:  /* XOR? r,@rr / XOR r,(rr)+ / XOR r,@ww / XOR r,ww(rr) / XOR r,-(rr) - 8,13,11,15,13 cycles - Flagsaffected: -ZS0---- */
998	998	ARG_rmw;
999		OP_XOR8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, s2 ) );
1000		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	999	OP_XOR8( mem_readbyte( r1 ), mem_readbyte( s2 ) );
	1000	mem_writebyte( r1, res & 0xFF );
1001	1001	switch( r2 & 0xC0 ) {
1002	1002	case 0x00:  mycycles += 8; break;
1003	1003	case 0x40:  mycycles += 13; break;
r20617	r20618
1007	1007	break;
1008	1008	case 0x38:  /* MOV r,@rr / MOV r,(rr)+ / MOV r,@ww / MOV r,ww(rr) / MOV r,-(rr) - 8,13,11,15,13 cycles - Flags affected: -------- */
1009	1009	ARG_rmw;
1010		sm85cpu_mem_writebyte( cpustate, r1, sm85cpu_mem_readbyte( cpustate, s2 ) );
	1010	mem_writebyte( r1, mem_readbyte( s2 ) );
1011	1011	switch( r2 & 0xC0 ) {
1012	1012	case 0x00:  mycycles += 8; break;
1013	1013	case 0x40:  mycycles += 13; break;
r20617	r20618
1017	1017	break;
1018	1018	case 0x39:  /* MOV @rr,r / MOV (rr)+,r / MOV @ww,r / MOV ww(rr),r /  MOV -(rr),r - 8,13,11,15,13 cycles - Flags affected: -------- */
1019	1019	ARG_rmw;
1020		sm85cpu_mem_writebyte( cpustate, s2, sm85cpu_mem_readbyte( cpustate, r1 ) );
	1020	mem_writebyte( s2, mem_readbyte( r1 ) );
1021	1021	switch( r2 & 0xC0 ) {
1022	1022	case 0x00:  mycycles += 8; break;
1023	1023	case 0x40:  mycycles += 13; break;
r20617	r20618
1027	1027	break;
1028	1028	case 0x3A:  /* MOVW rr,@rr / MOV rr,(rr)+ / MOV rr,@ww / MOV rr,ww(rr) / MOV rr,-(rr) - 11,16,14,18,16 cycles - Flags affected: -------- */
1029	1029	ARG_smw;
1030		sm85cpu_mem_writeword( cpustate, r1, sm85cpu_mem_readword( cpustate, s2 ) );
	1030	mem_writeword( r1, mem_readword( s2 ) );
1031	1031	switch( r2 & 0xC0 ) {
1032	1032	case 0x00:  mycycles += 11; break;
1033	1033	case 0x40:  mycycles += 16; break;
r20617	r20618
1037	1037	break;
1038	1038	case 0x3B:  /* MOVW @rr,rr / MOV (rr)+,rr / MOV @ww,rr / MOV ww(rr),rr / MOV -(rr),rr - 11,16,14,18,16 cycles - Flags affected: -------- */
1039	1039	ARG_smw;
1040		sm85cpu_mem_writeword( cpustate, s2, sm85cpu_mem_readword( cpustate, r1 ) );
	1040	mem_writeword( s2, mem_readword( r1 ) );
1041	1041	switch( r2 & 0xC0 ) {
1042	1042	case 0x00:  mycycles += 11; break;
1043	1043	case 0x40:  mycycles += 16; break;
r20617	r20618
1047	1047	break;
1048	1048	case 0x3C:  /* MOVW RRr,RRs - 7 cycles - Flags affected: -------- */
1049	1049	ARG_ss;
1050		sm85cpu_mem_writeword( cpustate, r1, sm85cpu_mem_readword( cpustate, r2 ) );
	1050	mem_writeword( r1, mem_readword( r2 ) );
1051	1051	mycycles += 7;
1052	1052	break;
1053	1053	case 0x3D:  /* unk3D DM??? 3D 0E -> DM R0Eh ?? - 4,4 cycles */
1054		logerror( "%04X: unk%02x\n", cpustate->PC-1,op );
	1054	logerror( "%04X: unk%02x\n", m_PC-1,op );
1055	1055	mycycles += 4;
1056	1056	break;
1057	1057	case 0x3E:  /* JMP RRr/@ww/ww(RRr) - 7/15/19 cycles - Flags affected: -------- */
1058	1058	ARG_2;
1059		cpustate->PC = s2;
	1059	m_PC = s2;
1060	1060	switch( r1 & 0xc0 ) {
1061	1061	case 0x00:  mycycles += 7; break;
1062	1062	case 0x40:  mycycles += ( ( r1 & 0x38 ) ? 19 : 15 ); break;
r20617	r20618
1065	1065	break;
1066	1066	case 0x3F:  /* CALL RRr/@ww/ww(RRr) - 11,14/22,19/26,23 cycles - Flags affected: -------- */
1067	1067	ARG_2;
1068		PUSH8( cpustate->PC & 0xFF );
1069		PUSH8( cpustate->PC >> 8 );
1070		cpustate->PC = s2;
	1068	PUSH8( m_PC & 0xFF );
	1069	PUSH8( m_PC >> 8 );
	1070	m_PC = s2;
1071	1071	switch( r1 & 0xc0 ) {
1072		case 0x00:  mycycles += ( ( cpustate->SYS & 0x40 ) ? 14 : 11 ); break;
1073		case 0x40:  mycycles += ( ( r1 & 0x38 ) ? ( ( cpustate->SYS & 0x40 ) ? 26 : 23 ) : ( ( cpustate->SYS & 0x40 ) ? 22 : 19 ) );break;
	1072	case 0x00:  mycycles += ( ( m_SYS & 0x40 ) ? 14 : 11 ); break;
	1073	case 0x40:  mycycles += ( ( r1 & 0x38 ) ? ( ( m_SYS & 0x40 ) ? 26 : 23 ) : ( ( m_SYS & 0x40 ) ? 22 : 19 ) );break;
1074	1074	default:    mycycles += 4;
1075	1075	}
1076	1076	break;
1077	1077	case 0x40:  /* CMP Rr,Rs - 6 cycles - Flags affected: CZSV---- */
1078	1078	ARG_RR;
1079		OP_CMP8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
	1079	OP_CMP8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
1080	1080	mycycles += 6;
1081	1081	break;
1082	1082	case 0x41:  /* ADD Rr,Rs - 6 cycles - Flags affected: CZSV0H-- */
1083	1083	ARG_RR;
1084		OP_ADD8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
1085		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1084	OP_ADD8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	1085	mem_writebyte( r1, res & 0xFF );
1086	1086	mycycles += 6;
1087	1087	break;
1088	1088	case 0x42:  /* SUB Rr,Rs - 6 cycles - Flags affected: CZSV1H-- */
1089	1089	ARG_RR;
1090		OP_SUB8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
1091		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1090	OP_SUB8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	1091	mem_writebyte( r1, res & 0xFF );
1092	1092	mycycles += 6;
1093	1093	break;
1094	1094	case 0x43:  /* ADC Rr,Rs - 6 cycles - Flags affected: CZSV0H-- */
1095	1095	ARG_RR;
1096		OP_ADC8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
1097		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1096	OP_ADC8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	1097	mem_writebyte( r1, res & 0xFF );
1098	1098	mycycles += 6;
1099	1099	break;
1100	1100	case 0x44:  /* SBC Rr,Rs - 6 cycles - Flags affected: CZSV1H-- */
1101	1101	ARG_RR;
1102		OP_SBC8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
1103		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1102	OP_SBC8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	1103	mem_writebyte( r1, res & 0xFF );
1104	1104	mycycles += 6;
1105	1105	break;
1106	1106	case 0x45:  /* AND Rr,Rs - 6 cycles - Flags affected: -ZS0---- */
1107	1107	ARG_RR;
1108		OP_AND8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
1109		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1108	OP_AND8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	1109	mem_writebyte( r1, res & 0xFF );
1110	1110	mycycles += 6;
1111	1111	break;
1112	1112	case 0x46:  /* OR Rr,Rs - 6 cycles - Flags affected: -ZS0---- */
1113	1113	ARG_RR;
1114		OP_OR8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
1115		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1114	OP_OR8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	1115	mem_writebyte( r1, res & 0xFF );
1116	1116	mycycles += 6;
1117	1117	break;
1118	1118	case 0x47:  /* XOR Rr,Rs - 6 cycles - Flags affected: -ZS0---- */
1119	1119	ARG_RR;
1120		OP_XOR8( sm85cpu_mem_readbyte( cpustate, r1 ), sm85cpu_mem_readbyte( cpustate, r2 ) );
1121		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1120	OP_XOR8( mem_readbyte( r1 ), mem_readbyte( r2 ) );
	1121	mem_writebyte( r1, res & 0xFF );
1122	1122	mycycles += 6;
1123	1123	break;
1124	1124	case 0x48:  /* MOV Rr,Rs - 6 cycles - Flags affected: -------- */
1125	1125	ARG_RR;
1126		sm85cpu_mem_writebyte( cpustate, r1, sm85cpu_mem_readbyte( cpustate, r2 ) );
	1126	mem_writebyte( r1, mem_readbyte( r2 ) );
1127	1127	mycycles += 6;
1128	1128	break;
1129	1129	case 0x49:  /* CALL ad16 - 12,10 - Flags affected: -------- */
1130	1130	ARG_ad16;
1131		PUSH8( cpustate->PC & 0xFF );
1132		PUSH8( cpustate->PC >> 8 );
1133		cpustate->PC = s2;
1134		mycycles += ( ( cpustate->SYS & 0x40 ) ? 12 : 10 );
	1131	PUSH8( m_PC & 0xFF );
	1132	PUSH8( m_PC >> 8 );
	1133	m_PC = s2;
	1134	mycycles += ( ( m_SYS & 0x40 ) ? 12 : 10 );
1135	1135	break;
1136	1136	case 0x4A:  /* MOVW RRr,RRs - 8 cycles - Flags affected: -------- */
1137	1137	ARG_RR;
1138		sm85cpu_mem_writeword( cpustate, r1, sm85cpu_mem_readword( cpustate, r2 ) );
	1138	mem_writeword( r1, mem_readword( r2 ) );
1139	1139	mycycles += 8;
1140	1140	break;
1141	1141	case 0x4B:  /* MOVW RRr,ww - 9 cycles - Flags affected: -------- */
1142	1142	ARG_Sw;
1143		sm85cpu_mem_writeword( cpustate, r1, s2 );
	1143	mem_writeword( r1, s2 );
1144	1144	mycycles += 9;
1145	1145	break;
1146	1146	case 0x4C:  /* MULT Rrr,Rs - 24 cycles - Flags affected: -Z-0---- */
1147	1147	ARG_RR;
1148		res = sm85cpu_mem_readword( cpustate, r1 ) * sm85cpu_mem_readbyte( cpustate, r2 );
1149		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
1150		cpustate->PS1 = cpustate->PS1 & ~ ( FLAG_Z | FLAG_V );
1151		cpustate->PS1 |= ( ( res & 0xFFFF ) == 0x00 ? FLAG_Z : 0 );
	1148	res = mem_readword( r1 ) * mem_readbyte( r2 );
	1149	mem_writeword( r1, res & 0xFFFF );
	1150	m_PS1 = m_PS1 & ~ ( FLAG_Z | FLAG_V );
	1151	m_PS1 |= ( ( res & 0xFFFF ) == 0x00 ? FLAG_Z : 0 );
1152	1152	mycycles += 24;
1153	1153	break;
1154	1154	case 0x4D:  /* MULT RRr,i - 24 cycles - Flags affected: -Z-0---- */
1155	1155	ARG_iR;
1156		res = sm85cpu_mem_readbyte( cpustate, r1 + 1 ) * r2;
1157		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
1158		cpustate->PS1 = cpustate->PS1 & ~ ( FLAG_Z | FLAG_V );
1159		cpustate->PS1 |= ( ( res & 0xFFFF ) == 0x00 ? FLAG_Z : 0 );
	1156	res = mem_readbyte( r1 + 1 ) * r2;
	1157	mem_writeword( r1, res & 0xFFFF );
	1158	m_PS1 = m_PS1 & ~ ( FLAG_Z | FLAG_V );
	1159	m_PS1 |= ( ( res & 0xFFFF ) == 0x00 ? FLAG_Z : 0 );
1160	1160	mycycles += 24;
1161	1161	break;
1162	1162	case 0x4E:  /* BMOV Rr,#b,BF/BF,Rr,#b - 6 cycles - Flags affected: --------/-Z-0--B- */
1163		r2 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
1164		r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
	1163	r2 = mem_readbyte( m_PC++ );
	1164	r1 = mem_readbyte( m_PC++ );
1165	1165	switch( r2 & 0xC0 ) {
1166	1166	case 0x00:
1167		res = sm85cpu_mem_readbyte( cpustate, r1 );
1168		if ( cpustate->PS1 & FLAG_B ) {
	1167	res = mem_readbyte( r1 );
	1168	if ( m_PS1 & FLAG_B ) {
1169	1169	res = res | ( 1 << ( r2 & 0x07 ) );
1170	1170	} else {
1171	1171	res = res & ~( 1 << ( r2 & 0x07 ) );
1172	1172	}
1173		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1173	mem_writebyte( r1, res & 0xFF );
1174	1174	break;
1175	1175	case 0x40:
1176		cpustate->PS1 = cpustate->PS1 & ( FLAG_C | FLAG_S | FLAG_D | FLAG_H | FLAG_I );
1177		if ( sm85cpu_mem_readbyte( cpustate, r1 ) & ( 1 << ( r2 & 0x07 ) ) ) {
1178		cpustate->PS1 = cpustate->PS1 | FLAG_B;
	1176	m_PS1 = m_PS1 & ( FLAG_C | FLAG_S | FLAG_D | FLAG_H | FLAG_I );
	1177	if ( mem_readbyte( r1 ) & ( 1 << ( r2 & 0x07 ) ) ) {
	1178	m_PS1 = m_PS1 | FLAG_B;
1179	1179	} else {
1180		cpustate->PS1 = cpustate->PS1 | FLAG_Z;
	1180	m_PS1 = m_PS1 | FLAG_Z;
1181	1181	}
1182	1182	break;
1183	1183	case 0x80:
r20617	r20618
1187	1187	mycycles += 6;
1188	1188	break;
1189	1189	case 0x4F:  /* BCMP/BAND/BOR/BXOR BF,Rr,#b - 6 cycles - Flags affected: -Z-0---- / -Z-0--B- */
1190		r2 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
1191		r1 = sm85cpu_mem_readbyte( cpustate, cpustate->PC++ );
1192		s1 = sm85cpu_mem_readbyte( cpustate, r1 ) & ( 1 << ( r2 & 0x07 ) );
1193		s2 = ( ( cpustate->PS1 & FLAG_B ) >> 1 ) << ( r2 & 0x07 );
	1190	r2 = mem_readbyte( m_PC++ );
	1191	r1 = mem_readbyte( m_PC++ );
	1192	s1 = mem_readbyte( r1 ) & ( 1 << ( r2 & 0x07 ) );
	1193	s2 = ( ( m_PS1 & FLAG_B ) >> 1 ) << ( r2 & 0x07 );
1194	1194	switch( r2 & 0xC0 ) {
1195	1195	case 0x00:
1196		cpustate->PS1 = cpustate->PS1 & ~ ( FLAG_Z | FLAG_V );
	1196	m_PS1 = m_PS1 & ~ ( FLAG_Z | FLAG_V );
1197	1197	if ( s1 == s2 ) {
1198		cpustate->PS1 = cpustate->PS1 | FLAG_Z;
	1198	m_PS1 = m_PS1 | FLAG_Z;
1199	1199	}
1200	1200	break;
1201	1201	case 0x40:
1202		cpustate->PS1 = cpustate->PS1 & ~ ( FLAG_Z | FLAG_V | FLAG_B );
1203		cpustate->PS1 = cpustate->PS1 | ( ( s1 & s2 ) ? FLAG_B : FLAG_Z );
	1202	m_PS1 = m_PS1 & ~ ( FLAG_Z | FLAG_V | FLAG_B );
	1203	m_PS1 = m_PS1 | ( ( s1 & s2 ) ? FLAG_B : FLAG_Z );
1204	1204	break;
1205	1205	case 0x80:
1206		cpustate->PS1 = cpustate->PS1 & ~ ( FLAG_Z | FLAG_V | FLAG_B );
1207		cpustate->PS1 = cpustate->PS1 | ( ( s1 | s2 ) ? FLAG_B : FLAG_Z );
	1206	m_PS1 = m_PS1 & ~ ( FLAG_Z | FLAG_V | FLAG_B );
	1207	m_PS1 = m_PS1 | ( ( s1 | s2 ) ? FLAG_B : FLAG_Z );
1208	1208	break;
1209	1209	case 0xC0:
1210		cpustate->PS1 = cpustate->PS1 & ~ ( FLAG_Z | FLAG_V | FLAG_B );
1211		cpustate->PS1 = cpustate->PS1 | ( ( s1 ^ s2 ) ? FLAG_B : FLAG_Z );
	1210	m_PS1 = m_PS1 & ~ ( FLAG_Z | FLAG_V | FLAG_B );
	1211	m_PS1 = m_PS1 | ( ( s1 ^ s2 ) ? FLAG_B : FLAG_Z );
1212	1212	break;
1213	1213	}
1214	1214	mycycles += 6;
1215	1215	break;
1216	1216	case 0x50:  /* CMP Rr,i - 6 cycles - Flags affected: CZSV---- */
1217	1217	ARG_iR;
1218		OP_CMP8( sm85cpu_mem_readbyte( cpustate, r1 ), r2 );
	1218	OP_CMP8( mem_readbyte( r1 ), r2 );
1219	1219	mycycles += 6;
1220	1220	break;
1221	1221	case 0x51:  /* ADD Rr,i - 6 cycles - Flags affected: CZSV0H-- */
1222	1222	ARG_iR;
1223		OP_ADD8( sm85cpu_mem_readbyte( cpustate, r1 ), r2 );
1224		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1223	OP_ADD8( mem_readbyte( r1 ), r2 );
	1224	mem_writebyte( r1, res & 0xFF );
1225	1225	mycycles += 6;
1226	1226	break;
1227	1227	case 0x52:  /* SUB Rr,i - 6 cycles - Flags affected: CZSV1H-- */
1228	1228	ARG_iR;
1229		OP_SUB8( sm85cpu_mem_readbyte( cpustate, r1 ), r2 );
1230		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1229	OP_SUB8( mem_readbyte( r1 ), r2 );
	1230	mem_writebyte( r1, res & 0xFF );
1231	1231	mycycles += 6;
1232	1232	break;
1233	1233	case 0x53:  /* ADC Rr,i - 6 cycles - Flags affected: CZSV0H-- */
1234	1234	ARG_iR;
1235		OP_ADC8( sm85cpu_mem_readbyte( cpustate, r1 ), r2 );
1236		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1235	OP_ADC8( mem_readbyte( r1 ), r2 );
	1236	mem_writebyte( r1, res & 0xFF );
1237	1237	mycycles += 6;
1238	1238	break;
1239	1239	case 0x54:  /* SBC Rr,i - 6 cycles - Flags affected: CZSV1H-- */
1240	1240	ARG_iR;
1241		OP_SBC8( sm85cpu_mem_readbyte( cpustate, r1 ), r2 );
1242		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1241	OP_SBC8( mem_readbyte( r1 ), r2 );
	1242	mem_writebyte( r1, res & 0xFF );
1243	1243	mycycles += 6;
1244	1244	break;
1245	1245	case 0x55:  /* AND Rr,i - 6 cycles - Flags affected: -ZS0---- */
1246	1246	ARG_iR;
1247		OP_AND8( sm85cpu_mem_readbyte( cpustate, r1 ), r2 );
1248		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1247	OP_AND8( mem_readbyte( r1 ), r2 );
	1248	mem_writebyte( r1, res & 0xFF );
1249	1249	mycycles += 6;
1250	1250	break;
1251	1251	case 0x56:  /* OR Rr,i - 6 cycles - Flags affected: -ZS0---- */
1252	1252	ARG_iR;
1253		OP_OR8( sm85cpu_mem_readbyte( cpustate, r1 ), r2 );
1254		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1253	OP_OR8( mem_readbyte( r1 ), r2 );
	1254	mem_writebyte( r1, res & 0xFF );
1255	1255	mycycles += 6;
1256	1256	break;
1257	1257	case 0x57:  /* XOR Rr,i - 6 cycles - Flags affected: -ZS0---- */
1258	1258	ARG_iR;
1259		OP_XOR8( sm85cpu_mem_readbyte( cpustate, r1 ), r2 );
1260		sm85cpu_mem_writebyte( cpustate, r1, res & 0xFF );
	1259	OP_XOR8( mem_readbyte( r1 ), r2 );
	1260	mem_writebyte( r1, res & 0xFF );
1261	1261	mycycles += 6;
1262	1262	break;
1263	1263	case 0x58:  /* MOV Rr,i - 6 cycles - Flags affected: -------- */
1264	1264	ARG_iR;
1265		sm85cpu_mem_writebyte( cpustate, r1, r2 );
	1265	mem_writebyte( r1, r2 );
1266	1266	mycycles += 6;
1267	1267	break;
1268	1268	case 0x59:  /* Invalid - 2? cycles - Flags affected: --------? */
1269		logerror( "%04X: 59h: Invalid instruction\n", cpustate->PC-1 );
	1269	logerror( "%04X: 59h: Invalid instruction\n", m_PC-1 );
1270	1270	mycycles += 2;
1271	1271	break;
1272	1272	case 0x5A:  /* unk5A - 7,8,12,9,8 cycles */
1273		logerror( "%04X: unk%02x\n", cpustate->PC-1,op );
	1273	logerror( "%04X: unk%02x\n", m_PC-1,op );
1274	1274	ARG_ad16;
1275	1275	mycycles += 7;
1276	1276	break;
1277	1277	case 0x5B:  /* unk5B - 6,7,11,8,7 cycles */
1278		logerror( "%04X: unk%02x\n", cpustate->PC-1,op );
	1278	logerror( "%04X: unk%02x\n", m_PC-1,op );
1279	1279	/* NOTE: This unknown command is used in several carts, the code below allows those carts to boot */
1280	1280	ARG_iR;
1281	1281	r1 = r2 & 7;
1282		res = sm85cpu_mem_readbyte( cpustate, r1 ) + 1;
1283		sm85cpu_mem_writebyte( cpustate, r1, res );
	1282	res = mem_readbyte( r1 ) + 1;
	1283	mem_writebyte( r1, res );
1284	1284	mycycles += 6;
1285	1285	break;
1286	1286	case 0x5C:  /* DIV RRr,RRs - 47 cycles - Flags affected: -Z-V---- */
1287	1287	/* lower 8 bits of RRs is used to divide */
1288	1288	/* remainder in stored upper 8 bits of RRs */
1289		logerror( "%04X: DIV RRr,Rs!\n", cpustate->PC-1 );
	1289	logerror( "%04X: DIV RRr,Rs!\n", m_PC-1 );
1290	1290	ARG_RR;
1291		cpustate->PS1 = cpustate->PS1 & ~ ( FLAG_Z | FLAG_V );
1292		s1 = sm85cpu_mem_readbyte( cpustate, r2 + 1 );
	1291	m_PS1 = m_PS1 & ~ ( FLAG_Z | FLAG_V );
	1292	s1 = mem_readbyte( r2 + 1 );
1293	1293	if ( s1 ) {
1294		UINT16 div = sm85cpu_mem_readword( cpustate, r1 );
	1294	UINT16 div = mem_readword( r1 );
1295	1295	res = div / s1;
1296		sm85cpu_mem_writebyte( cpustate, r2, div % s1 );
1297		sm85cpu_mem_writeword( cpustate, r1, res );
1298		cpustate->PS1 = cpustate->PS1 | ( ( res == 0 ) ? FLAG_Z : 0 );
	1296	mem_writebyte( r2, div % s1 );
	1297	mem_writeword( r1, res );
	1298	m_PS1 = m_PS1 | ( ( res == 0 ) ? FLAG_Z : 0 );
1299	1299	} else {
1300		cpustate->PS1 = cpustate->PS1 | FLAG_V;
	1300	m_PS1 = m_PS1 | FLAG_V;
1301	1301	}
1302	1302	mycycles += 47;
1303	1303	break;
1304	1304	case 0x5D:  /* DIV RRr,i - 44 cycles - Flags affected: -Z-V---- */
1305		logerror( "%04X: DIV RRr,i!\n", cpustate->PC-1 );
	1305	logerror( "%04X: DIV RRr,i!\n", m_PC-1 );
1306	1306	ARG_iR;
1307		cpustate->PS1 = cpustate->PS1 & ~ ( FLAG_Z | FLAG_V );
	1307	m_PS1 = m_PS1 & ~ ( FLAG_Z | FLAG_V );
1308	1308	if ( r2 ) {
1309		res = sm85cpu_mem_readword( cpustate, r1 ) / r2;
1310		sm85cpu_mem_writeword( cpustate, r1, res );
1311		cpustate->PS1 = cpustate->PS1 | ( ( res == 0 ) ? FLAG_Z : 0 );
	1309	res = mem_readword( r1 ) / r2;
	1310	mem_writeword( r1, res );
	1311	m_PS1 = m_PS1 | ( ( res == 0 ) ? FLAG_Z : 0 );
1312	1312	} else {
1313		cpustate->PS1 = cpustate->PS1 | FLAG_V;
	1313	m_PS1 = m_PS1 | FLAG_V;
1314	1314	}
1315	1315	mycycles += 44;
1316	1316	break;
1317	1317	case 0x5E:  /* MOVM Rr,i,Rs - 9 cycles - Flags affected: -------- */
1318	1318	ARG_RiR;
1319		sm85cpu_mem_writebyte( cpustate, r1, ( sm85cpu_mem_readbyte( cpustate, r1 ) & d1 ) | sm85cpu_mem_readbyte( cpustate, r2 ) );
	1319	mem_writebyte( r1, ( mem_readbyte( r1 ) & d1 ) | mem_readbyte( r2 ) );
1320	1320	mycycles += 9;
1321	1321	break;
1322	1322	case 0x5F:  /* MOVM Rr,i,j - 8 cycles - Flags affected: -------- */
1323	1323	ARG_Rii;
1324		sm85cpu_mem_writebyte( cpustate, r1, ( sm85cpu_mem_readbyte( cpustate, r1 ) & d1 ) | r2 );
	1324	mem_writebyte( r1, ( mem_readbyte( r1 ) & d1 ) | r2 );
1325	1325	mycycles += 8;
1326	1326	break;
1327	1327	case 0x60:  /* CMPW RRr,RRs - 9 cycles - Flags affected: CZSV---- */
1328	1328	ARG_RR;
1329		OP_CMP16( sm85cpu_mem_readword( cpustate, r1 ), sm85cpu_mem_readword( cpustate, r2 ) );
	1329	OP_CMP16( mem_readword( r1 ), mem_readword( r2 ) );
1330	1330	mycycles += 9;
1331	1331	break;
1332	1332	case 0x61:  /* ADDW RRr,RRs - 10 cycles - Flags affected: CZSV0H-- */
1333	1333	ARG_RR;
1334		OP_ADD16( sm85cpu_mem_readword( cpustate, r1 ), sm85cpu_mem_readword( cpustate, r2 ) );
1335		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	1334	OP_ADD16( mem_readword( r1 ), mem_readword( r2 ) );
	1335	mem_writeword( r1, res & 0xFFFF );
1336	1336	mycycles += 10;
1337	1337	break;
1338	1338	case 0x62:  /* SUBW RRr,RRs - 10 cycles - Flags affected: CZSV1H-- */
1339	1339	ARG_RR;
1340		OP_SUB16( sm85cpu_mem_readword( cpustate, r1 ), sm85cpu_mem_readword( cpustate, r2 ) );
1341		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	1340	OP_SUB16( mem_readword( r1 ), mem_readword( r2 ) );
	1341	mem_writeword( r1, res & 0xFFFF );
1342	1342	mycycles += 10;
1343	1343	break;
1344	1344	case 0x63:  /* ADCW RRr,RRs - 10 cycles - Flags affected: CZSV0H-- */
1345	1345	ARG_RR;
1346		OP_ADC16( sm85cpu_mem_readword( cpustate, r1 ), sm85cpu_mem_readword( cpustate, r2 ) );
1347		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	1346	OP_ADC16( mem_readword( r1 ), mem_readword( r2 ) );
	1347	mem_writeword( r1, res & 0xFFFF );
1348	1348	mycycles += 10;
1349	1349	break;
1350	1350	case 0x64:  /* SBCW RRr,RRs - 10 cycles - Flags affected: CZSV1H-- */
1351	1351	ARG_RR;
1352		OP_SBC16( sm85cpu_mem_readword( cpustate, r1 ), sm85cpu_mem_readword( cpustate, r2 ) );
1353		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	1352	OP_SBC16( mem_readword( r1 ), mem_readword( r2 ) );
	1353	mem_writeword( r1, res & 0xFFFF );
1354	1354	mycycles += 10;
1355	1355	break;
1356	1356	case 0x65:  /* ANDW RRr,RRs - 14 cycles - Flags affected: -Z-0---- */
1357	1357	ARG_RR;
1358		OP_AND16( sm85cpu_mem_readword( cpustate, r1 ), sm85cpu_mem_readword( cpustate, r2 ) );
1359		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	1358	OP_AND16( mem_readword( r1 ), mem_readword( r2 ) );
	1359	mem_writeword( r1, res & 0xFFFF );
1360	1360	mycycles += 14;
1361	1361	break;
1362	1362	case 0x66:  /* ORW RRr,RRs - 14 cycles - Flags affected: -Z-0---- */
1363	1363	ARG_RR;
1364		OP_OR16( sm85cpu_mem_readword( cpustate, r1 ), sm85cpu_mem_readword( cpustate, r2 ) );
1365		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	1364	OP_OR16( mem_readword( r1 ), mem_readword( r2 ) );
	1365	mem_writeword( r1, res & 0xFFFF );
1366	1366	mycycles += 14;
1367	1367	break;
1368	1368	case 0x67:  /* XORW RRr,RRs - 14 cycles - Flags affected: -Z-0---- */
1369	1369	ARG_RR;
1370		OP_XOR16( sm85cpu_mem_readword( cpustate, r1 ), sm85cpu_mem_readword( cpustate, r2 ) );
1371		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	1370	OP_XOR16( mem_readword( r1 ), mem_readword( r2 ) );
	1371	mem_writeword( r1, res & 0xFFFF );
1372	1372	mycycles += 14;
1373	1373	break;
1374	1374	case 0x68:  /* CMPW RRr,w - 9 cycles - Flags affected: CZSV---- */
1375	1375	ARG_Sw;
1376		OP_CMP16( sm85cpu_mem_readword( cpustate, r1 ), s2 );
	1376	OP_CMP16( mem_readword( r1 ), s2 );
1377	1377	mycycles += 9;
1378	1378	break;
1379	1379	case 0x69:  /* ADDW RRr,w - 10 cycles - Flags affected: CZSV0H-- */
1380	1380	ARG_Sw;
1381		OP_ADD16( sm85cpu_mem_readword( cpustate, r1 ), s2 );
1382		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	1381	OP_ADD16( mem_readword( r1 ), s2 );
	1382	mem_writeword( r1, res & 0xFFFF );
1383	1383	mycycles += 10;
1384	1384	break;
1385	1385	case 0x6A:  /* SUBW RRr,w - 10 cycles - Flags affected: CZSV1H-- */
1386	1386	ARG_Sw;
1387		OP_SUB16( sm85cpu_mem_readword( cpustate, r1 ), s2 );
1388		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	1387	OP_SUB16( mem_readword( r1 ), s2 );
	1388	mem_writeword( r1, res & 0xFFFF );
1389	1389	mycycles += 10;
1390	1390	break;
1391	1391	case 0x6B:  /* ADCW RRr,w - 10 cycles - Flags affected: CZSV0H-- */
1392	1392	ARG_Sw;
1393		OP_ADC16( sm85cpu_mem_readword( cpustate, r1 ), s2 );
1394		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	1393	OP_ADC16( mem_readword( r1 ), s2 );
	1394	mem_writeword( r1, res & 0xFFFF );
1395	1395	mycycles += 10;
1396	1396	break;
1397	1397	case 0x6C:  /* SBCW RRr,w - 10 cycles - Flags affected: CZSV1H-- */
1398	1398	ARG_Sw;
1399		OP_SBC16( sm85cpu_mem_readword( cpustate, r1 ), s2 );
1400		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	1399	OP_SBC16( mem_readword( r1 ), s2 );
	1400	mem_writeword( r1, res & 0xFFFF );
1401	1401	mycycles += 10;
1402	1402	break;
1403	1403	case 0x6D:  /* ANDW RRr,w - 13 cycles - Flags affected: -Z-0---- */
1404	1404	ARG_Sw;
1405		OP_AND16( sm85cpu_mem_readword( cpustate, r1 ), s2 );
1406		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	1405	OP_AND16( mem_readword( r1 ), s2 );
	1406	mem_writeword( r1, res & 0xFFFF );
1407	1407	mycycles += 13;
1408	1408	break;
1409	1409	case 0x6E:  /* ORW RRr,w - 13 cycles - Flags affected: -Z-0---- */
1410	1410	ARG_Sw;
1411		OP_OR16( sm85cpu_mem_readword( cpustate, r1 ), s2 );
1412		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF );
	1411	OP_OR16( mem_readword( r1 ), s2 );
	1412	mem_writeword( r1, res & 0xFFFF );
1413	1413	mycycles += 13;
1414	1414	break;
1415	1415	case 0x6F:  /* XORW RRr,w - 13 cycles - Flags affected: -Z-0---- */
1416	1416	ARG_Sw;
1417		OP_XOR16( sm85cpu_mem_readword( cpustate, r1 ), s2 );
1418		sm85cpu_mem_writeword( cpustate, r1, res & 0xFFFF);
	1417	OP_XOR16( mem_readword( r1 ), s2 );
	1418	mem_writeword( r1, res & 0xFFFF);
1419	1419	mycycles += 13;
1420	1420	break;
1421	1421	case 0x70:  /* DBNZ r,rel8 - 10,6 cycles - Flags affected: -------- */
r20617	r20618
1427	1427	case 0x76:
1428	1428	case 0x77:
1429	1429	ARG_d8;
1430		r1 = sm85cpu_mem_readbyte( cpustate, op & 0x07 );
	1430	r1 = mem_readbyte( op & 0x07 );
1431	1431	r1--;
1432		sm85cpu_mem_writebyte( cpustate, op & 0x07, r1 );
	1432	mem_writebyte( op & 0x07, r1 );
1433	1433	if ( r1 != 0 ) {
1434		cpustate->PC = s2;
	1434	m_PC = s2;
1435	1435	mycycles += 10;
1436	1436	} else {
1437	1437	mycycles += 6;
r20617	r20618
1446	1446	case 0x7E:
1447	1447	case 0x7F:
1448	1448	ARG_rrw;
1449		sm85cpu_mem_writeword( cpustate, r1, s2 );
	1449	mem_writeword( r1, s2 );
1450	1450	mycycles += 6;
1451	1451	break;
1452	1452	case 0x80:  /* BBC R,#b,d8 - 10,6 cycles - Flags affected: -------- */
r20617	r20618
1458	1458	case 0x86:
1459	1459	case 0x87:
1460	1460	ARG_Rbr;
1461		if ( ( sm85cpu_mem_readbyte( cpustate, r1 ) & ( 1 << (op & 0x07) ) ) == 0 ) {
1462		cpustate->PC = s2;
	1461	if ( ( mem_readbyte( r1 ) & ( 1 << (op & 0x07) ) ) == 0 ) {
	1462	m_PC = s2;
1463	1463	mycycles += 10;
1464	1464	} else {
1465	1465	mycycles += 6;
r20617	r20618
1474	1474	case 0x8E:
1475	1475	case 0x8F:
1476	1476	ARG_Rbr;
1477		if ( ( sm85cpu_mem_readbyte( cpustate, r1 ) & ( 1 << (op & 0x07) ) ) ) {
1478		cpustate->PC = s2;
	1477	if ( ( mem_readbyte( r1 ) & ( 1 << (op & 0x07) ) ) ) {
	1478	m_PC = s2;
1479	1479	mycycles += 10;
1480	1480	} else {
1481	1481	mycycles += 6;
r20617	r20618
1500	1500	ARG_ad16;
1501	1501	CHECK_CC;
1502	1502	if ( res ) {
1503		cpustate->PC = s2;
	1503	m_PC = s2;
1504	1504	}
1505	1505	mycycles += 6;
1506	1506	break;
r20617	r20618
1513	1513	case 0xA6:
1514	1514	case 0xA7:
1515	1515	ARG_R;
1516		sm85cpu_mem_writebyte( cpustate, r1, sm85cpu_mem_readbyte( cpustate, r1 ) & ~ ( 1 << (op & 0x07) ) );
	1516	mem_writebyte( r1, mem_readbyte( r1 ) & ~ ( 1 << (op & 0x07) ) );
1517	1517	mycycles += 4;
1518	1518	break;
1519	1519	case 0xA8:  /* BSET R,#b - 4 cycles - Flags affected: -------- */
r20617	r20618
1525	1525	case 0xAE:
1526	1526	case 0xAF:
1527	1527	ARG_R;
1528		sm85cpu_mem_writebyte( cpustate, r1, sm85cpu_mem_readbyte( cpustate, r1 ) | ( 1 << (op & 0x07) ) );
	1528	mem_writebyte( r1, mem_readbyte( r1 ) | ( 1 << (op & 0x07) ) );
1529	1529	mycycles += 4;
1530	1530	break;
1531	1531	case 0xB0:  /* MOV Rx,Rr - 4 cycles - Flags affected: -------- */
r20617	r20618
1537	1537	case 0xB6:
1538	1538	case 0xB7:
1539	1539	ARG_rR;
1540		sm85cpu_mem_writebyte( cpustate, r1, sm85cpu_mem_readbyte( cpustate, r2 ) );
	1540	mem_writebyte( r1, mem_readbyte( r2 ) );
1541	1541	mycycles += 4;
1542	1542	break;
1543	1543	case 0xB8:  /* MOV Rr,Rx - 4 cycles - Flags affected: -------- */
r20617	r20618
1549	1549	case 0xBE:
1550	1550	case 0xBF:
1551	1551	ARG_rR;
1552		sm85cpu_mem_writebyte( cpustate, r2, sm85cpu_mem_readbyte( cpustate, r1 ) );
	1552	mem_writebyte( r2, mem_readbyte( r1 ) );
1553	1553	mycycles += 4;
1554	1554	break;
1555	1555	case 0xC0:  /* MOV Rx,i - 4 cycles - Flags affected: -------- */
r20617	r20618
1561	1561	case 0xC6:
1562	1562	case 0xC7:
1563	1563	ARG_ri;
1564		sm85cpu_mem_writebyte( cpustate, r1, r2 );
	1564	mem_writebyte( r1, r2 );
1565	1565	mycycles += 4;
1566	1566	break;
1567	1567	case 0xC8:  /* MOV IE0/IE1/IR0/IR1/P0/P1/P2/P3,i - 4 cycles - Flags affected: -------- */
r20617	r20618
1573	1573	case 0xCE:
1574	1574	case 0xCF:
1575	1575	ARG_pi;
1576		sm85cpu_mem_writebyte( cpustate, r1, r2 );
	1576	mem_writebyte( r1, r2 );
1577	1577	mycycles += 4;
1578	1578	break;
1579	1579	case 0xD0:  /* BR cc,rel8 - 8,4 cycles - Flags affected: -------- */
r20617	r20618
1595	1595	ARG_d8;
1596	1596	CHECK_CC;
1597	1597	if ( res ) {
1598		cpustate->PC = s2;
	1598	m_PC = s2;
1599	1599	mycycles += 8;
1600	1600	} else {
1601	1601	mycycles += 4;
r20617	r20618
1619	1619	case 0xEF:  /* CALS 1xWW - 12,9 cycles - Flags affected: -------- */
1620	1620	ARG_R;
1621	1621	s2 = 0x1000 + ( ( op & 0x0F ) << 8 ) + r1;
1622		PUSH8( cpustate->PC & 0xFF );
1623		PUSH8( cpustate->PC >> 8 );
1624		cpustate->PC = s2;
1625		mycycles += ( ( cpustate->SYS & 0x40 ) ? 12 : 9 );
	1622	PUSH8( m_PC & 0xFF );
	1623	PUSH8( m_PC >> 8 );
	1624	m_PC = s2;
	1625	mycycles += ( ( m_SYS & 0x40 ) ? 12 : 9 );
1626	1626	break;
1627	1627	case 0xF0:  /* STOP - 2 cycles - Flags affected: -------- */
1628	1628	mycycles += 2;
1629		if ( cpustate->clock_changed ) {
	1629	if ( m_clock_changed ) {
1630	1630	/* TODO: Set system clock divider */
1631	1631	/* TODO: Add a bunch of additional cycles */
1632		cpustate->clock_changed = 0;
	1632	m_clock_changed = 0;
1633	1633	}
1634	1634	break;
1635	1635	case 0xF1:  /* HALT - 2 cycles - Flags affected: -------- */
1636		cpustate->halted = 1;
	1636	m_halted = 1;
1637	1637	mycycles += 2;
1638	1638	break;
1639	1639	case 0xF2:  /* Invalid - 2? cycles - Flags affected: --------? */
r20617	r20618
1647	1647	case 0xF8:  /* RET - 10,8 cycles - Flags affected: -------- */
1648	1648	POP8( r1 );
1649	1649	POP8( r2 );
1650		cpustate->PC = ( r1 << 8 ) | r2;
1651		mycycles += ( ( cpustate->SYS & 0x40 ) ? 10 : 8 );
	1650	m_PC = ( r1 << 8 ) | r2;
	1651	mycycles += ( ( m_SYS & 0x40 ) ? 10 : 8 );
1652	1652	break;
1653	1653	case 0xF9:  /* IRET - 12,10 cycles - Flags affected: CZSVDHBI */
1654		POP8( cpustate->PS1 );
	1654	POP8( m_PS1 );
1655	1655	POP8( r1 );
1656	1656	POP8( r2 );
1657		cpustate->PC = ( r1 << 8 ) | r2;
1658		mycycles += ( ( cpustate->SYS & 0x40 ) ? 12 : 10 );
	1657	m_PC = ( r1 << 8 ) | r2;
	1658	mycycles += ( ( m_SYS & 0x40 ) ? 12 : 10 );
1659	1659	break;
1660	1660	case 0xFA:  /* CLRC - 2 cycles - Flags affected: C------- */
1661		cpustate->PS1 = cpustate->PS1 & ~ ( FLAG_C );
	1661	m_PS1 = m_PS1 & ~ ( FLAG_C );
1662	1662	mycycles += 2;
1663	1663	break;
1664	1664	case 0xFB:  /* COMC - 2 cycles - Flags affected: C------- */
1665		cpustate->PS1 = cpustate->PS1 ^ FLAG_C;
	1665	m_PS1 = m_PS1 ^ FLAG_C;
1666	1666	mycycles += 2;
1667	1667	break;
1668	1668	case 0xFC:  /* SETC - 2 cycles - Flags affected: C------- */
1669		cpustate->PS1 = cpustate->PS1 | FLAG_C;
	1669	m_PS1 = m_PS1 | FLAG_C;
1670	1670	mycycles += 2;
1671	1671	break;
1672	1672	case 0xFD:  /* EI - 2 cycles - Flags affected: -------I */
1673		cpustate->PS1 = cpustate->PS1 | FLAG_I;
	1673	m_PS1 = m_PS1 | FLAG_I;
1674	1674	mycycles += 2;
1675	1675	break;
1676	1676	case 0xFE:  /* DI - 2 cycles - Flags affected: -------I */
1677		cpustate->PS1 = cpustate->PS1 & ~ ( FLAG_I );
	1677	m_PS1 = m_PS1 & ~ ( FLAG_I );
1678	1678	mycycles += 2;
1679	1679	break;
1680	1680	case 0xFF:  /* NOP - 2 cycles - Flags affected: -------- */

trunk/src/mess/machine/gamecom.c

r20617	r20618
10	10	UINT8 * RAM = m_region_maincpu->base();
11	11	UINT8 val = ( ( RAM[SM8521_CLKT] & 0x3F ) + 1 ) & 0x3F;
12	12	RAM[SM8521_CLKT] = ( RAM[SM8521_CLKT] & 0xC0 ) | val;
13		m_maincpu->set_input_line(CK_INT, ASSERT_LINE );
	13	m_maincpu->set_input_line(sm8500_cpu_device::CK_INT, ASSERT_LINE );
14	14	}
15	15
16	16	void gamecom_state::machine_reset()
r20617	r20618
353	353	Their usage is also not explained properly in the manuals. Guess we'll have to wait
354	354	for them to show up in some rom images...
355	355	*/
356		void gamecom_handle_dma( device_t *device, int cycles )
	356	WRITE8_MEMBER( gamecom_state::gamecom_handle_dma )
357	357	{
358		gamecom_state *state = device->machine().driver_data<gamecom_state>();
359		UINT8 * RAM = state->memregion("maincpu")->base();
360		UINT8 data = RAM[SM8521_DMC];
361		state->m_dma.overwrite_mode = data & 0x01;
362		state->m_dma.transfer_mode = data & 0x06;
363		state->m_dma.decrement_x = data & 0x08;
364		state->m_dma.decrement_y = data & 0x10;
365		state->m_dma.enabled = data & 0x80;
366		if ( !state->m_dma.enabled ) return;
	358	UINT8 * RAM = m_region_maincpu->base();
	359	UINT8 dmc = RAM[SM8521_DMC];
	360	m_dma.overwrite_mode = dmc & 0x01;
	361	m_dma.transfer_mode = dmc & 0x06;
	362	m_dma.decrement_x = dmc & 0x08;
	363	m_dma.decrement_y = dmc & 0x10;
	364	m_dma.enabled = dmc & 0x80;
	365	if ( !m_dma.enabled )
	366	{
	367	return;
	368	}
367	369
	370	if ( m_dma.decrement_x || m_dma.decrement_y )
	371	{
	372	popmessage( "TODO: Decrement-x and decrement-y are not supported yet\n" );
	373	}
368	374
369		if ( state->m_dma.decrement_x || state->m_dma.decrement_y )
370		logerror( "TODO: Decrement-x and decrement-y are not supported yet\n" );
371
372		state->m_dma.width_x = RAM[SM8521_DMDX];
373		state->m_dma.width_x_count = 0;
374		state->m_dma.width_y = RAM[SM8521_DMDY];
375		state->m_dma.width_y_count = 0;
376		state->m_dma.source_x = RAM[SM8521_DMX1];
377		state->m_dma.source_x_current = state->m_dma.source_x;
378		state->m_dma.source_y = RAM[SM8521_DMY1];
379		state->m_dma.source_width = ( RAM[SM8521_LCH] & 0x20 ) ? 50 : 40;
380		state->m_dma.dest_x = RAM[SM8521_DMX2];
381		state->m_dma.dest_x_current = state->m_dma.dest_x;
382		state->m_dma.dest_y = RAM[SM8521_DMY2];
383		state->m_dma.dest_width = ( RAM[SM8521_LCH] & 0x20 ) ? 50 : 40;
384		state->m_dma.palette[0] = RAM[SM8521_DMPL] & 0x03;
385		state->m_dma.palette[1] = ( RAM[SM8521_DMPL] >> 2 ) & 3;
386		state->m_dma.palette[2] = ( RAM[SM8521_DMPL] >> 4 ) & 3;
387		state->m_dma.palette[3] = RAM[SM8521_DMPL] >> 6;
388		state->m_dma.source_mask = 0x1FFF;
389		state->m_dma.dest_mask = 0x1FFF;
390		//  logerror("DMA: width %Xx%X, source (%X,%X), dest (%X,%X), transfer_mode %X, banks %X \n", state->m_dma.width_x, state->m_dma.width_y, state->m_dma.source_x, state->m_dma.source_y, state->m_dma.dest_x, state->m_dma.dest_y, state->m_dma.transfer_mode, RAM[SM8521_DMVP] );
391		//  logerror( "   Palette: %d, %d, %d, %d\n", state->m_dma.palette[0], state->m_dma.palette[1], state->m_dma.palette[2], state->m_dma.palette[3] );
392		switch( state->m_dma.transfer_mode )
	375	m_dma.width_x = RAM[SM8521_DMDX];
	376	m_dma.width_x_count = 0;
	377	m_dma.width_y = RAM[SM8521_DMDY];
	378	m_dma.width_y_count = 0;
	379	m_dma.source_x = RAM[SM8521_DMX1];
	380	m_dma.source_x_current = m_dma.source_x;
	381	m_dma.source_y = RAM[SM8521_DMY1];
	382	m_dma.source_width = ( RAM[SM8521_LCH] & 0x20 ) ? 50 : 40;
	383	m_dma.dest_x = RAM[SM8521_DMX2];
	384	m_dma.dest_x_current = m_dma.dest_x;
	385	m_dma.dest_y = RAM[SM8521_DMY2];
	386	m_dma.dest_width = ( RAM[SM8521_LCH] & 0x20 ) ? 50 : 40;
	387	m_dma.palette[0] = RAM[SM8521_DMPL] & 0x03;
	388	m_dma.palette[1] = ( RAM[SM8521_DMPL] >> 2 ) & 3;
	389	m_dma.palette[2] = ( RAM[SM8521_DMPL] >> 4 ) & 3;
	390	m_dma.palette[3] = RAM[SM8521_DMPL] >> 6;
	391	m_dma.source_mask = 0x1FFF;
	392	m_dma.dest_mask = 0x1FFF;
	393	//  logerror("DMA: width %Xx%X, source (%X,%X), dest (%X,%X), transfer_mode %X, banks %X \n", m_dma.width_x, m_dma.width_y, m_dma.source_x, m_dma.source_y, m_dma.dest_x, m_dma.dest_y, m_dma.transfer_mode, RAM[SM8521_DMVP] );
	394	//  logerror( "   Palette: %d, %d, %d, %d\n", m_dma.palette[0], m_dma.palette[1], m_dma.palette[2], m_dma.palette[3] );
	395	switch( m_dma.transfer_mode )
393	396	{
394	397	case 0x00:
395	398	/* VRAM->VRAM */
396		state->m_dma.source_bank = &state->m_p_videoram[(RAM[SM8521_DMVP] & 0x01) ? 0x2000 : 0x0000];
397		state->m_dma.dest_bank = &state->m_p_videoram[(RAM[SM8521_DMVP] & 0x02) ? 0x2000 : 0x0000];
	399	m_dma.source_bank = &m_p_videoram[(RAM[SM8521_DMVP] & 0x01) ? 0x2000 : 0x0000];
	400	m_dma.dest_bank = &m_p_videoram[(RAM[SM8521_DMVP] & 0x02) ? 0x2000 : 0x0000];
398	401	break;
399	402	case 0x02:
400	403	/* ROM->VRAM */
401	404	//      logerror( "DMA DMBR = %X\n", RAM[SM8521_DMBR] );
402		state->m_dma.source_width = 64;
403		state->m_dma.source_mask = 0x3FFF;
	405	m_dma.source_width = 64;
	406	m_dma.source_mask = 0x3FFF;
404	407	if ( RAM[SM8521_DMBR] < 16 )
405		state->m_dma.source_bank = state->memregion("kernel")->base() + (RAM[SM8521_DMBR] << 14);
	408	{
	409	m_dma.source_bank = m_region_kernel->base() + (RAM[SM8521_DMBR] << 14);
	410	}
406	411	else
407		if (state->m_cartridge)
408		state->m_dma.source_bank = state->m_cartridge + (RAM[SM8521_DMBR] << 14);
	412	{
	413	if (m_cartridge)
	414	{
	415	m_dma.source_bank = m_cartridge + (RAM[SM8521_DMBR] << 14);
	416	}
	417	}
409	418
410		state->m_dma.dest_bank = &state->m_p_videoram[(RAM[SM8521_DMVP] & 0x02) ? 0x2000 : 0x0000];
	419	m_dma.dest_bank = &m_p_videoram[(RAM[SM8521_DMVP] & 0x02) ? 0x2000 : 0x0000];
411	420	break;
412	421	case 0x04:
413	422	/* Extend RAM->VRAM */
414		state->m_dma.source_width = 64;
415		state->m_dma.source_bank = &state->m_p_nvram[0x0000];
416		state->m_dma.dest_bank = &state->m_p_videoram[(RAM[SM8521_DMVP] & 0x02) ? 0x2000 : 0x0000];
	423	m_dma.source_width = 64;
	424	m_dma.source_bank = &m_p_nvram[0x0000];
	425	m_dma.dest_bank = &m_p_videoram[(RAM[SM8521_DMVP] & 0x02) ? 0x2000 : 0x0000];
417	426	break;
418	427	case 0x06:
419	428	/* VRAM->Extend RAM */
420		state->m_dma.source_bank = &state->m_p_videoram[(RAM[SM8521_DMVP] & 0x01) ? 0x2000 : 0x0000];
421		state->m_dma.dest_width = 64;
422		state->m_dma.dest_bank = &state->m_p_nvram[0x0000];
	429	m_dma.source_bank = &m_p_videoram[(RAM[SM8521_DMVP] & 0x01) ? 0x2000 : 0x0000];
	430	m_dma.dest_width = 64;
	431	m_dma.dest_bank = &m_p_nvram[0x0000];
423	432	break;
424	433	}
425		state->m_dma.source_current = state->m_dma.source_width * state->m_dma.source_y;
426		state->m_dma.source_current += state->m_dma.source_x >> 2;
427		state->m_dma.dest_current = state->m_dma.dest_width * state->m_dma.dest_y;
428		state->m_dma.dest_current += state->m_dma.dest_x >> 2;
429		state->m_dma.source_line = state->m_dma.source_current;
430		state->m_dma.dest_line = state->m_dma.dest_current;
431		state->m_dma.state_count = 0;
	434	m_dma.source_current = m_dma.source_width * m_dma.source_y;
	435	m_dma.source_current += m_dma.source_x >> 2;
	436	m_dma.dest_current = m_dma.dest_width * m_dma.dest_y;
	437	m_dma.dest_current += m_dma.dest_x >> 2;
	438	m_dma.source_line = m_dma.source_current;
	439	m_dma.dest_line = m_dma.dest_current;
	440	m_dma.state_count = 0;
432	441
433	442	unsigned y_count, x_count;
434	443
435		for( y_count = 0; y_count <= state->m_dma.width_y; y_count++ )
	444	for( y_count = 0; y_count <= m_dma.width_y; y_count++ )
436	445	{
437		for( x_count = 0; x_count <= state->m_dma.width_x; x_count++ )
	446	for( x_count = 0; x_count <= m_dma.width_x; x_count++ )
438	447	{
439	448	int source_pixel = 0;
440	449	int dest_pixel = 0;
441		int src_addr = state->m_dma.source_current & state->m_dma.source_mask;
442		int dest_addr = state->m_dma.dest_current & state->m_dma.dest_mask;
	450	int src_addr = m_dma.source_current & m_dma.source_mask;
	451	int dest_addr = m_dma.dest_current & m_dma.dest_mask;
443	452	/* handle DMA for 1 pixel */
444	453	/* Read pixel data */
445		switch ( state->m_dma.source_x_current & 0x03 )
	454	switch ( m_dma.source_x_current & 0x03 )
446	455	{
447		case 0x00: source_pixel = state->m_dma.source_bank[src_addr] >> 6; break;
448		case 0x01: source_pixel = ( state->m_dma.source_bank[src_addr] >> 4 ) & 3; break;
449		case 0x02: source_pixel = ( state->m_dma.source_bank[src_addr] >> 2 ) & 3; break;
450		case 0x03: source_pixel = state->m_dma.source_bank[src_addr] & 3;      break;
	456	case 0x00: source_pixel = m_dma.source_bank[src_addr] >> 6; break;
	457	case 0x01: source_pixel = ( m_dma.source_bank[src_addr] >> 4 ) & 3; break;
	458	case 0x02: source_pixel = ( m_dma.source_bank[src_addr] >> 2 ) & 3; break;
	459	case 0x03: source_pixel = m_dma.source_bank[src_addr] & 3;      break;
451	460	}
452	461
453		if ( !state->m_dma.overwrite_mode && source_pixel == 0 )
	462	if ( !m_dma.overwrite_mode && source_pixel == 0 )
454	463	{
455		switch ( state->m_dma.dest_x_current & 0x03 )
	464	switch ( m_dma.dest_x_current & 0x03 )
456	465	{
457		case 0x00: dest_pixel = state->m_dma.dest_bank[dest_addr] >> 6; break;
458		case 0x01: dest_pixel = ( state->m_dma.dest_bank[dest_addr] >> 4 ) & 3; break;
459		case 0x02: dest_pixel = ( state->m_dma.dest_bank[dest_addr] >> 2 ) & 3; break;
460		case 0x03: dest_pixel = state->m_dma.dest_bank[dest_addr] & 3;      break;
	466	case 0x00: dest_pixel = m_dma.dest_bank[dest_addr] >> 6; break;
	467	case 0x01: dest_pixel = ( m_dma.dest_bank[dest_addr] >> 4 ) & 3; break;
	468	case 0x02: dest_pixel = ( m_dma.dest_bank[dest_addr] >> 2 ) & 3; break;
	469	case 0x03: dest_pixel = m_dma.dest_bank[dest_addr] & 3;      break;
461	470	}
462	471	source_pixel = dest_pixel;
463	472	}
464	473
465	474	/* Translate pixel data using DMA palette. */
466	475	/* Not sure if this should be done before the compound stuff - WP */
467		source_pixel = state->m_dma.palette[ source_pixel ];
	476	source_pixel = m_dma.palette[ source_pixel ];
468	477	/* Write pixel data */
469		switch( state->m_dma.dest_x_current & 0x03 )
	478	switch( m_dma.dest_x_current & 0x03 )
470	479	{
471	480	case 0x00:
472		state->m_dma.dest_bank[dest_addr] = ( state->m_dma.dest_bank[dest_addr] & 0x3F ) | ( source_pixel << 6 );
	481	m_dma.dest_bank[dest_addr] = ( m_dma.dest_bank[dest_addr] & 0x3F ) | ( source_pixel << 6 );
473	482	break;
474	483	case 0x01:
475		state->m_dma.dest_bank[dest_addr] = ( state->m_dma.dest_bank[dest_addr] & 0xCF ) | ( source_pixel << 4 );
	484	m_dma.dest_bank[dest_addr] = ( m_dma.dest_bank[dest_addr] & 0xCF ) | ( source_pixel << 4 );
476	485	break;
477	486	case 0x02:
478		state->m_dma.dest_bank[dest_addr] = ( state->m_dma.dest_bank[dest_addr] & 0xF3 ) | ( source_pixel << 2 );
	487	m_dma.dest_bank[dest_addr] = ( m_dma.dest_bank[dest_addr] & 0xF3 ) | ( source_pixel << 2 );
479	488	break;
480	489	case 0x03:
481		state->m_dma.dest_bank[dest_addr] = ( state->m_dma.dest_bank[dest_addr] & 0xFC ) | source_pixel;
	490	m_dma.dest_bank[dest_addr] = ( m_dma.dest_bank[dest_addr] & 0xFC ) | source_pixel;
482	491	break;
483	492	}
484	493
485	494	/* Advance a pixel */
486		if ( state->m_dma.decrement_x )
	495	if ( m_dma.decrement_x )
487	496	{
488		state->m_dma.source_x_current--;
489		if ( ( state->m_dma.source_x_current & 0x03 ) == 0x03 )
490		state->m_dma.source_current--;
	497	m_dma.source_x_current--;
	498	if ( ( m_dma.source_x_current & 0x03 ) == 0x03 )
	499	m_dma.source_current--;
491	500	}
492	501	else
493	502	{
494		state->m_dma.source_x_current++;
495		if ( ( state->m_dma.source_x_current & 0x03 ) == 0x00 )
496		state->m_dma.source_current++;
	503	m_dma.source_x_current++;
	504	if ( ( m_dma.source_x_current & 0x03 ) == 0x00 )
	505	m_dma.source_current++;
497	506	}
498		state->m_dma.dest_x_current++;
499		if ( ( state->m_dma.dest_x_current & 0x03 ) == 0x00 )
500		state->m_dma.dest_current++;
	507	m_dma.dest_x_current++;
	508	if ( ( m_dma.dest_x_current & 0x03 ) == 0x00 )
	509	m_dma.dest_current++;
501	510	}
502	511
503	512	/* Advance a line */
504		state->m_dma.source_x_current = state->m_dma.source_x;
505		state->m_dma.dest_x_current = state->m_dma.dest_x;
506		state->m_dma.source_line += state->m_dma.source_width;
507		state->m_dma.source_current = state->m_dma.source_line;
508		state->m_dma.dest_line += state->m_dma.dest_width;
509		state->m_dma.dest_current = state->m_dma.dest_line;
	513	m_dma.source_x_current = m_dma.source_x;
	514	m_dma.dest_x_current = m_dma.dest_x;
	515	m_dma.source_line += m_dma.source_width;
	516	m_dma.source_current = m_dma.source_line;
	517	m_dma.dest_line += m_dma.dest_width;
	518	m_dma.dest_current = m_dma.dest_line;
510	519	}
511		state->m_dma.enabled = 0;
512		device->machine().device("maincpu")->execute().set_input_line(DMA_INT, ASSERT_LINE );
	520	m_dma.enabled = 0;
	521	m_maincpu->set_input_line(sm8500_cpu_device::DMA_INT, ASSERT_LINE );
513	522	}
514	523
515		void gamecom_update_timers( device_t *device, int cycles )
	524	WRITE8_MEMBER( gamecom_state::gamecom_update_timers )
516	525	{
517		gamecom_state *state = device->machine().driver_data<gamecom_state>();
518		UINT8 * RAM = state->memregion("maincpu")->base();
519		if ( state->m_timer[0].enabled )
	526	UINT8 * RAM = m_region_maincpu->base();
	527	if ( m_timer[0].enabled )
520	528	{
521		state->m_timer[0].state_count += cycles;
522		while ( state->m_timer[0].state_count >= state->m_timer[0].state_limit )
	529	m_timer[0].state_count += data;
	530	while ( m_timer[0].state_count >= m_timer[0].state_limit )
523	531	{
524		state->m_timer[0].state_count -= state->m_timer[0].state_limit;
	532	m_timer[0].state_count -= m_timer[0].state_limit;
525	533	RAM[SM8521_TM0D]++;
526		if ( RAM[SM8521_TM0D] >= state->m_timer[0].check_value )
	534	if ( RAM[SM8521_TM0D] >= m_timer[0].check_value )
527	535	{
528	536	RAM[SM8521_TM0D] = 0;
529		device->machine().device("maincpu")->execute().set_input_line(TIM0_INT, ASSERT_LINE );
	537	m_maincpu->set_input_line(sm8500_cpu_device::TIM0_INT, ASSERT_LINE );
530	538	}
531	539	}
532	540	}
533		if ( state->m_timer[1].enabled )
	541	if ( m_timer[1].enabled )
534	542	{
535		state->m_timer[1].state_count += cycles;
536		while ( state->m_timer[1].state_count >= state->m_timer[1].state_limit )
	543	m_timer[1].state_count += data;
	544	while ( m_timer[1].state_count >= m_timer[1].state_limit )
537	545	{
538		state->m_timer[1].state_count -= state->m_timer[1].state_limit;
	546	m_timer[1].state_count -= m_timer[1].state_limit;
539	547	RAM[SM8521_TM1D]++;
540		if ( RAM[SM8521_TM1D] >= state->m_timer[1].check_value )
	548	if ( RAM[SM8521_TM1D] >= m_timer[1].check_value )
541	549	{
542	550	RAM[SM8521_TM1D] = 0;
543		device->machine().device("maincpu")->execute().set_input_line(TIM1_INT, ASSERT_LINE );
	551	m_maincpu->set_input_line(sm8500_cpu_device::TIM1_INT, ASSERT_LINE );
544	552	}
545	553	}
546	554	}

trunk/src/mess/includes/gamecom.h

r20617	r20618
258	258	INTERRUPT_GEN_MEMBER(gamecom_interrupt);
259	259	TIMER_CALLBACK_MEMBER(gamecom_clock_timer_callback);
260	260	TIMER_CALLBACK_MEMBER(gamecom_scanline);
	261	DECLARE_WRITE8_MEMBER( gamecom_handle_dma );
	262	DECLARE_WRITE8_MEMBER( gamecom_update_timers );
261	263
262	264	protected:
263	265	required_memory_bank m_bank1;
r20617	r20618
279	281	extern DEVICE_IMAGE_LOAD( gamecom_cart1 );
280	282	extern DEVICE_IMAGE_LOAD( gamecom_cart2 );
281	283
282		extern void gamecom_handle_dma( device_t *device, int cycles );
283		extern void gamecom_update_timers( device_t *device, int cycles );
284
285	284	#endif /* GAMECOM_H_ */

trunk/src/mess/drivers/gamecom.c

r20617	r20618
33	33	AM_RANGE( 0xE000, 0xFFFF )  AM_RAM AM_SHARE("p_nvram")// AM_SHARE("nvram")           /* Extended I/O, Extended RAM */
34	34	ADDRESS_MAP_END
35	35
36		static const SM8500_CONFIG gamecom_cpu_config = {
37		gamecom_handle_dma,
38		gamecom_update_timers
39		};
40
41	36	static INPUT_PORTS_START( gamecom )
42	37	PORT_START("IN0")
43	38	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_NAME( "Up" )
r20617	r20618
91	86
92	87	INTERRUPT_GEN_MEMBER(gamecom_state::gamecom_interrupt)
93	88	{
94		m_maincpu->set_input_line(LCDC_INT, ASSERT_LINE );
	89	m_maincpu->set_input_line(sm8500_cpu_device::LCDC_INT, ASSERT_LINE );
95	90	}
96	91
97	92	static MACHINE_CONFIG_START( gamecom, gamecom_state )
98	93	/* basic machine hardware */
99	94	MCFG_CPU_ADD( "maincpu", SM8500, XTAL_11_0592MHz/2 )   /* actually it's an sm8521 microcontroller containing an sm8500 cpu */
100	95	MCFG_CPU_PROGRAM_MAP( gamecom_mem_map)
101		MCFG_CPU_CONFIG( gamecom_cpu_config )
	96	MCFG_SM8500_DMA_CB( WRITE8( gamecom_state, gamecom_handle_dma ) )
	97	MCFG_SM8500_TIMER_CB( WRITE8( gamecom_state, gamecom_update_timers ) )
102	98	MCFG_CPU_VBLANK_INT_DRIVER("screen", gamecom_state,  gamecom_interrupt)
103	99
104	100	MCFG_QUANTUM_TIME(attotime::from_hz(60))

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