trunk/src/mame/drivers/saturn.c
| r20593 | r20594 | |
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| 448 | 448 | |
| 449 | 449 | void saturn_state::scu_dma_direct(address_space &space, UINT8 dma_ch) |
| 450 | 450 | { |
| 451 | | UINT32 tmp_src,tmp_dst,tmp_size; |
| 451 | UINT32 tmp_src,tmp_dst,total_size; |
| 452 | 452 | UINT8 cd_transfer_flag; |
| 453 | 453 | |
| 454 | 454 | if(m_scu.src_add[dma_ch] == 0 || (m_scu.dst_add[dma_ch] != 2 && m_scu.dst_add[dma_ch] != 4)) |
| r20593 | r20594 | |
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| 469 | 469 | |
| 470 | 470 | tmp_src = tmp_dst = 0; |
| 471 | 471 | |
| 472 | | tmp_size = m_scu.size[dma_ch]; |
| 472 | total_size = m_scu.size[dma_ch]; |
| 473 | 473 | if(!(DRUP(dma_ch))) tmp_src = m_scu.src[dma_ch]; |
| 474 | 474 | if(!(DWUP(dma_ch))) tmp_dst = m_scu.dst[dma_ch]; |
| 475 | 475 | |
| r20593 | r20594 | |
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| 518 | 518 | if(!(DWUP(dma_ch))) m_scu.dst[dma_ch] = tmp_dst; |
| 519 | 519 | |
| 520 | 520 | { |
| 521 | | /*TODO: change DMA into DRQ model. */ |
| 521 | /*TODO: change DMA into DRQ model. Timing is a guess. */ |
| 522 | 522 | switch(dma_ch) |
| 523 | 523 | { |
| 524 | | case 0: machine().scheduler().timer_set(m_maincpu->cycles_to_attotime(tmp_size/4), timer_expired_delegate(FUNC(saturn_state::dma_lv0_ended),this)); break; |
| 525 | | case 1: machine().scheduler().timer_set(m_maincpu->cycles_to_attotime(tmp_size/4), timer_expired_delegate(FUNC(saturn_state::dma_lv1_ended),this)); break; |
| 526 | | case 2: machine().scheduler().timer_set(m_maincpu->cycles_to_attotime(tmp_size/4), timer_expired_delegate(FUNC(saturn_state::dma_lv2_ended),this)); break; |
| 524 | case 0: machine().scheduler().timer_set(m_maincpu->cycles_to_attotime(total_size/4), timer_expired_delegate(FUNC(saturn_state::dma_lv0_ended),this)); break; |
| 525 | case 1: machine().scheduler().timer_set(m_maincpu->cycles_to_attotime(total_size/4), timer_expired_delegate(FUNC(saturn_state::dma_lv1_ended),this)); break; |
| 526 | case 2: machine().scheduler().timer_set(m_maincpu->cycles_to_attotime(total_size/4), timer_expired_delegate(FUNC(saturn_state::dma_lv2_ended),this)); break; |
| 527 | 527 | } |
| 528 | 528 | } |
| 529 | 529 | } |
| r20593 | r20594 | |
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| 536 | 536 | UINT32 tmp_src; |
| 537 | 537 | UINT32 indirect_src,indirect_dst; |
| 538 | 538 | INT32 indirect_size; |
| 539 | UINT32 total_size = 0; |
| 539 | 540 | |
| 540 | 541 | DnMV_1(dma_ch); |
| 541 | 542 | |
| r20593 | r20594 | |
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| 582 | 583 | } |
| 583 | 584 | } |
| 584 | 585 | |
| 585 | | //if(DRUP(0)) space.write_dword(tmp_src+8,m_scu.src[0]|job_done ? 0x80000000 : 0); |
| 586 | /* Guess: Size + data acquire (1 cycle for src/dst/size) */ |
| 587 | total_size += indirect_size + 3*4; |
| 588 | |
| 589 | //if(DRUP(0)) space.write_dword(tmp_src+8,m_scu.src[0]|job_done ? 0x80000000 : 0); |
| 586 | 590 | //if(DWUP(0)) space.write_dword(tmp_src+4,m_scu.dst[0]); |
| 587 | 591 | |
| 588 | 592 | m_scu.index[dma_ch] = tmp_src+0xc; |
| r20593 | r20594 | |
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| 590 | 594 | }while(job_done == 0); |
| 591 | 595 | |
| 592 | 596 | { |
| 593 | | /*TODO: this is completely wrong HW-wise ... */ |
| 597 | /*TODO: change DMA into DRQ model. Timing is a guess. */ |
| 594 | 598 | switch(dma_ch) |
| 595 | 599 | { |
| 596 | | case 0: machine().scheduler().timer_set(attotime::from_usec(300), timer_expired_delegate(FUNC(saturn_state::dma_lv0_ended),this)); break; |
| 597 | | case 1: machine().scheduler().timer_set(attotime::from_usec(300), timer_expired_delegate(FUNC(saturn_state::dma_lv1_ended),this)); break; |
| 598 | | case 2: machine().scheduler().timer_set(attotime::from_usec(300), timer_expired_delegate(FUNC(saturn_state::dma_lv2_ended),this)); break; |
| 600 | case 0: machine().scheduler().timer_set(m_maincpu->cycles_to_attotime(total_size/4), timer_expired_delegate(FUNC(saturn_state::dma_lv0_ended),this)); break; |
| 601 | case 1: machine().scheduler().timer_set(m_maincpu->cycles_to_attotime(total_size/4), timer_expired_delegate(FUNC(saturn_state::dma_lv1_ended),this)); break; |
| 602 | case 2: machine().scheduler().timer_set(m_maincpu->cycles_to_attotime(total_size/4), timer_expired_delegate(FUNC(saturn_state::dma_lv2_ended),this)); break; |
| 599 | 603 | } |
| 600 | 604 | } |
| 601 | 605 | } |