trunk/src/mess/drivers/pentagon.c
| r20563 | r20564 | |
| 15 | 15 | pentagon_state(const machine_config &mconfig, device_type type, const char *tag) |
| 16 | 16 | : spectrum_state(mconfig, type, tag) |
| 17 | 17 | , m_maincpu(*this, "maincpu") |
| 18 | , m_bank1(*this, "bank1") |
| 19 | , m_bank2(*this, "bank2") |
| 20 | , m_bank3(*this, "bank3") |
| 21 | , m_bank4(*this, "bank4") |
| 22 | , m_beta(*this, BETA_DISK_TAG) |
| 23 | , m_ram(*this, RAM_TAG) |
| 18 | 24 | { } |
| 19 | 25 | |
| 20 | 26 | DECLARE_DIRECT_UPDATE_MEMBER(pentagon_direct); |
| r20563 | r20564 | |
| 23 | 29 | |
| 24 | 30 | protected: |
| 25 | 31 | required_device<cpu_device> m_maincpu; |
| 26 | | UINT8 *m_maincpu_rom; |
| 27 | | |
| 32 | required_memory_bank m_bank1; |
| 33 | required_memory_bank m_bank2; |
| 34 | required_memory_bank m_bank3; |
| 35 | required_memory_bank m_bank4; |
| 36 | required_device<device_t> m_beta; |
| 37 | required_device<ram_device> m_ram; |
| 38 | private: |
| 39 | UINT8 *m_p_ram; |
| 28 | 40 | void pentagon_update_memory(); |
| 29 | 41 | }; |
| 30 | 42 | |
| 31 | 43 | DIRECT_UPDATE_MEMBER(pentagon_state::pentagon_direct) |
| 32 | 44 | { |
| 33 | | device_t *beta = machine().device(BETA_DISK_TAG); |
| 34 | 45 | UINT16 pc = m_maincpu->pcbase(); |
| 35 | 46 | |
| 36 | | if (beta->started() && betadisk_is_active(beta)) |
| 47 | if (m_beta->started() && betadisk_is_active(m_beta) && (pc >= 0x4000)) |
| 37 | 48 | { |
| 38 | | if (pc >= 0x4000) |
| 39 | | { |
| 40 | | m_ROMSelection = ((m_port_7ffd_data>>4) & 0x01) ? 1 : 0; |
| 41 | | betadisk_disable(beta); |
| 42 | | membank("bank1")->set_base(m_maincpu_rom + 0x010000 + (m_ROMSelection<<14)); |
| 43 | | } |
| 44 | | } else if (((pc & 0xff00) == 0x3d00) && (m_ROMSelection==1)) |
| 49 | m_ROMSelection = BIT(m_port_7ffd_data, 4); |
| 50 | betadisk_disable(m_beta); |
| 51 | m_bank1->set_base(&m_p_ram[0x10000 + (m_ROMSelection<<14)]); |
| 52 | } |
| 53 | else |
| 54 | if (((pc & 0xff00) == 0x3d00) && (m_ROMSelection==1)) |
| 45 | 55 | { |
| 46 | 56 | m_ROMSelection = 3; |
| 47 | | if (beta->started()) |
| 48 | | betadisk_enable(beta); |
| 57 | if (m_beta->started()) |
| 58 | betadisk_enable(m_beta); |
| 59 | } |
| 49 | 60 | |
| 50 | | } |
| 51 | | if(address<=0x3fff) |
| 61 | if (address<=0x3fff) |
| 52 | 62 | { |
| 53 | | if (m_ROMSelection == 3) { |
| 54 | | if (beta->started()) { |
| 63 | if (m_ROMSelection == 3) |
| 64 | { |
| 65 | if (m_beta->started()) |
| 66 | { |
| 55 | 67 | direct.explicit_configure(0x0000, 0x3fff, 0x3fff, machine().root_device().memregion("beta:beta")->base()); |
| 56 | | membank("bank1")->set_base(machine().root_device().memregion("beta:beta")->base()); |
| 68 | m_bank1->set_base(machine().root_device().memregion("beta:beta")->base()); |
| 57 | 69 | } |
| 58 | | } else { |
| 59 | | direct.explicit_configure(0x0000, 0x3fff, 0x3fff, m_maincpu_rom + 0x010000 + (m_ROMSelection<<14)); |
| 60 | | membank("bank1")->set_base(m_maincpu_rom + 0x010000 + (m_ROMSelection<<14)); |
| 61 | 70 | } |
| 71 | else |
| 72 | { |
| 73 | direct.explicit_configure(0x0000, 0x3fff, 0x3fff, &m_p_ram[0x10000 + (m_ROMSelection<<14)]); |
| 74 | m_bank1->set_base(&m_p_ram[0x10000 + (m_ROMSelection<<14)]); |
| 75 | } |
| 62 | 76 | return ~0; |
| 63 | 77 | } |
| 78 | |
| 64 | 79 | return address; |
| 65 | 80 | } |
| 66 | 81 | |
| 67 | 82 | void pentagon_state::pentagon_update_memory() |
| 68 | 83 | { |
| 69 | | device_t *beta = machine().device(BETA_DISK_TAG); |
| 70 | | UINT8 *messram = machine().device<ram_device>(RAM_TAG)->pointer(); |
| 84 | UINT8 *messram = m_ram->pointer(); |
| 85 | |
| 71 | 86 | m_screen_location = messram + ((m_port_7ffd_data & 8) ? (7<<14) : (5<<14)); |
| 72 | 87 | |
| 73 | | membank("bank4")->set_base(messram + ((m_port_7ffd_data & 0x07) * 0x4000)); |
| 88 | m_bank4->set_base(messram + ((m_port_7ffd_data & 0x07) * 0x4000)); |
| 74 | 89 | |
| 75 | | if (beta->started() && betadisk_is_active(beta) && !( m_port_7ffd_data & 0x10 ) ) |
| 90 | if (m_beta->started() && betadisk_is_active(m_beta) && !( m_port_7ffd_data & 0x10 ) ) |
| 76 | 91 | { |
| 77 | 92 | /* GLUK */ |
| 78 | | if (strcmp(machine().system().name, "pent1024")==0) { |
| 93 | if (strcmp(machine().system().name, "pent1024")==0) |
| 79 | 94 | m_ROMSelection = 2; |
| 80 | | } else { |
| 81 | | m_ROMSelection = ((m_port_7ffd_data>>4) & 0x01) ; |
| 82 | | } |
| 95 | else |
| 96 | m_ROMSelection = BIT(m_port_7ffd_data, 4); |
| 83 | 97 | } |
| 84 | | else { |
| 98 | else |
| 85 | 99 | /* ROM switching */ |
| 86 | | m_ROMSelection = ((m_port_7ffd_data>>4) & 0x01) ; |
| 87 | | } |
| 100 | m_ROMSelection = BIT(m_port_7ffd_data, 4); |
| 101 | |
| 88 | 102 | /* rom 0 is 128K rom, rom 1 is 48 BASIC */ |
| 89 | | membank("bank1")->set_base(m_maincpu_rom + 0x010000 + (m_ROMSelection<<14)); |
| 103 | m_bank1->set_base(&m_p_ram[0x10000 + (m_ROMSelection<<14)]); |
| 90 | 104 | } |
| 91 | 105 | |
| 92 | 106 | WRITE8_MEMBER(pentagon_state::pentagon_port_7ffd_w) |
| r20563 | r20564 | |
| 117 | 131 | |
| 118 | 132 | MACHINE_RESET_MEMBER(pentagon_state,pentagon) |
| 119 | 133 | { |
| 120 | | UINT8 *messram = machine().device<ram_device>(RAM_TAG)->pointer(); |
| 121 | | device_t *beta = machine().device(BETA_DISK_TAG); |
| 134 | UINT8 *messram = m_ram->pointer(); |
| 122 | 135 | address_space &space = m_maincpu->space(AS_PROGRAM); |
| 136 | m_p_ram = memregion("maincpu")->base(); |
| 123 | 137 | |
| 124 | | m_maincpu_rom = memregion("maincpu")->base(); |
| 125 | | |
| 126 | 138 | space.install_read_bank(0x0000, 0x3fff, "bank1"); |
| 127 | 139 | space.unmap_write(0x0000, 0x3fff); |
| 128 | 140 | |
| 129 | | if (beta->started()) { |
| 130 | | betadisk_enable(beta); |
| 131 | | betadisk_clear_status(beta); |
| 141 | if (m_beta->started()) |
| 142 | { |
| 143 | betadisk_enable(m_beta); |
| 144 | betadisk_clear_status(m_beta); |
| 132 | 145 | } |
| 133 | 146 | space.set_direct_update_handler(direct_update_delegate(FUNC(pentagon_state::pentagon_direct), this)); |
| 134 | 147 | |
| 135 | 148 | memset(messram,0,128*1024); |
| 136 | 149 | |
| 137 | 150 | /* Bank 5 is always in 0x4000 - 0x7fff */ |
| 138 | | membank("bank2")->set_base(messram + (5<<14)); |
| 151 | m_bank2->set_base(messram + (5<<14)); |
| 139 | 152 | |
| 140 | 153 | /* Bank 2 is always in 0x8000 - 0xbfff */ |
| 141 | | membank("bank3")->set_base(messram + (2<<14)); |
| 154 | m_bank3->set_base(messram + (2<<14)); |
| 142 | 155 | |
| 143 | 156 | m_port_7ffd_data = 0; |
| 144 | 157 | m_port_1ffd_data = -1; |