trunk/src/mess/includes/mpz80.h
| r20531 | r20532 | |
| 27 | 27 | m_ram(*this, RAM_TAG), |
| 28 | 28 | m_terminal(*this, TERMINAL_TAG), |
| 29 | 29 | m_s100(*this, S100_TAG), |
| 30 | m_rom(*this, Z80_TAG), |
| 30 | 31 | m_map_ram(*this, "map_ram"), |
| 31 | 32 | m_16c(*this, "16C"), |
| 32 | 33 | m_nmi(1), |
| r20531 | r20532 | |
| 46 | 47 | required_device<ram_device> m_ram; |
| 47 | 48 | required_device<generic_terminal_device> m_terminal; |
| 48 | 49 | required_device<s100_device> m_s100; |
| 50 | required_memory_region m_rom; |
| 49 | 51 | optional_shared_ptr<UINT8> m_map_ram; |
| 50 | 52 | required_ioport m_16c; |
| 51 | 53 | |
trunk/src/mess/includes/abc1600.h
| r20531 | r20532 | |
| 74 | 74 | m_bus0x(*this, BUS0X_TAG), |
| 75 | 75 | m_bus1(*this, BUS1_TAG), |
| 76 | 76 | m_bus2(*this, BUS2_TAG), |
| 77 | m_rom(*this, MC68008P8_TAG), |
| 78 | m_wrmsk_rom(*this, "wrmsk"), |
| 79 | m_shinf_rom(*this, "shinf"), |
| 80 | m_drmsk_rom(*this, "drmsk"), |
| 77 | 81 | m_segment_ram(*this, "segment_ram"), |
| 78 | 82 | m_page_ram(*this, "page_ram"), |
| 79 | 83 | m_video_ram(*this, "video_ram") |
| r20531 | r20532 | |
| 98 | 102 | required_device<abc1600bus_slot_device> m_bus0x; |
| 99 | 103 | required_device<abc1600bus_slot_device> m_bus1; |
| 100 | 104 | required_device<abc1600bus_slot_device> m_bus2; |
| 105 | required_memory_region m_rom; |
| 106 | required_memory_region m_wrmsk_rom; |
| 107 | required_memory_region m_shinf_rom; |
| 108 | required_memory_region m_drmsk_rom; |
| 101 | 109 | optional_shared_ptr<UINT8> m_segment_ram; |
| 102 | 110 | optional_shared_ptr<UINT16> m_page_ram; |
| 103 | 111 | optional_shared_ptr<UINT16> m_video_ram; |
| r20531 | r20532 | |
| 223 | 231 | int m_btce; // V.24 channel B external clock enable |
| 224 | 232 | |
| 225 | 233 | // video |
| 226 | | const UINT8 *m_wrmsk_rom; // write mask ROM |
| 227 | | const UINT8 *m_shinf_rom; // shifter info ROM |
| 228 | | const UINT8 *m_drmsk_rom; // data read mask ROM |
| 229 | 234 | int m_endisp; // enable display |
| 230 | 235 | int m_clocks_disabled; // clocks disabled |
| 231 | 236 | UINT16 m_gmdi; // video RAM data latch |
trunk/src/mess/video/abc1600.c
| r20531 | r20532 | |
| 779 | 779 | */ |
| 780 | 780 | |
| 781 | 781 | UINT16 shinf_addr = (m_udx << 8) | ((m_xto & 0x0f) << 4) | (m_xfrom & 0x0f); |
| 782 | | UINT8 shinf = m_shinf_rom[shinf_addr]; |
| 782 | UINT8 shinf = m_shinf_rom->base()[shinf_addr]; |
| 783 | 783 | |
| 784 | 784 | m_sh = shinf & 0x0f; |
| 785 | 785 | m_hold_1w_cyk = BIT(shinf, 5); |
| r20531 | r20532 | |
| 805 | 805 | */ |
| 806 | 806 | |
| 807 | 807 | UINT16 drmsk_addr = (m_udx << 4) | (m_sh & 0x0f); |
| 808 | | UINT8 drmskl = m_drmsk_rom[drmsk_addr]; |
| 809 | | UINT8 drmskh = m_drmsk_rom[drmsk_addr + 0x20]; |
| 808 | UINT8 drmskl = m_drmsk_rom->base()[drmsk_addr]; |
| 809 | UINT8 drmskh = m_drmsk_rom->base()[drmsk_addr + 0x20]; |
| 810 | 810 | UINT16 drmsk = (drmskh << 8) | drmskl; |
| 811 | 811 | |
| 812 | 812 | return drmsk; |
| r20531 | r20532 | |
| 839 | 839 | */ |
| 840 | 840 | |
| 841 | 841 | UINT16 wrmsk_addr = (m_wrms1 << 11) | (m_wrms0 << 10) | ((!m_wrms1 && !m_wrms0) << 9) | (m_udx << 8) | ((m_xsize & 0x0f) << 4) | (m_xto & 0x0f); |
| 842 | | UINT8 wrmskl = m_wrmsk_rom[wrmsk_addr]; |
| 843 | | UINT8 wrmskh = m_wrmsk_rom[wrmsk_addr + 0x1000]; |
| 842 | UINT8 wrmskl = m_wrmsk_rom->base()[wrmsk_addr]; |
| 843 | UINT8 wrmskh = m_wrmsk_rom->base()[wrmsk_addr + 0x1000]; |
| 844 | 844 | UINT16 wrmsk = (wrmskh << 8) | wrmskl; |
| 845 | 845 | |
| 846 | 846 | return wrmsk ^ 0xffff; |
| r20531 | r20532 | |
| 1054 | 1054 | // allocate video RAM |
| 1055 | 1055 | m_video_ram.allocate(VIDEORAM_SIZE); |
| 1056 | 1056 | |
| 1057 | | // find memory regions |
| 1058 | | m_wrmsk_rom = memregion("wrmsk")->base(); |
| 1059 | | m_shinf_rom = memregion("shinf")->base(); |
| 1060 | | m_drmsk_rom = memregion("drmsk")->base(); |
| 1061 | | |
| 1062 | 1057 | // state saving |
| 1063 | 1058 | save_item(NAME(m_endisp)); |
| 1064 | 1059 | save_item(NAME(m_clocks_disabled)); |
trunk/src/mess/drivers/mpz80.c
| r20531 | r20532 | |
| 163 | 163 | READ8_MEMBER( mpz80_state::mmu_r ) |
| 164 | 164 | { |
| 165 | 165 | m_addr = get_address(offset); |
| 166 | | UINT8 *rom = memregion(Z80_TAG)->base(); |
| 167 | 166 | UINT8 data = 0; |
| 168 | 167 | |
| 169 | 168 | if (m_pretrap) |
| r20531 | r20532 | |
| 180 | 179 | { |
| 181 | 180 | if (offset < 0x400) |
| 182 | 181 | { |
| 183 | | UINT8 *ram = m_ram->pointer(); |
| 184 | | data = ram[offset & 0x3ff]; |
| 182 | data = m_ram->pointer()[offset & 0x3ff]; |
| 185 | 183 | } |
| 186 | 184 | else if (offset == 0x400) |
| 187 | 185 | { |
| r20531 | r20532 | |
| 206 | 204 | else if (offset < 0xc00) |
| 207 | 205 | { |
| 208 | 206 | UINT16 rom_addr = (m_trap_reset << 10) | (offset & 0x3ff); |
| 209 | | data = rom[rom_addr]; |
| 207 | data = m_rom->base()[rom_addr]; |
| 210 | 208 | } |
| 211 | 209 | else |
| 212 | 210 | { |
| r20531 | r20532 | |
| 234 | 232 | { |
| 235 | 233 | if (offset < 0x400) |
| 236 | 234 | { |
| 237 | | UINT8 *ram = m_ram->pointer(); |
| 238 | | ram[offset & 0x3ff] = data; |
| 235 | m_ram->pointer()[offset & 0x3ff] = data; |
| 239 | 236 | } |
| 240 | 237 | else if (offset == 0x400) |
| 241 | 238 | { |
| r20531 | r20532 | |
| 813 | 810 | { |
| 814 | 811 | if (m_trap && address >= m_trap_start && address <= m_trap_start + 0xf) |
| 815 | 812 | { |
| 816 | | direct.explicit_configure(m_trap_start, m_trap_start + 0xf, 0xf, memregion(Z80_TAG)->base() + ((m_trap_reset << 10) | 0x3f0)); |
| 813 | direct.explicit_configure(m_trap_start, m_trap_start + 0xf, 0xf, m_rom->base() + ((m_trap_reset << 10) | 0x3f0)); |
| 817 | 814 | return ~0; |
| 818 | 815 | } |
| 819 | 816 | |