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r20525 Sunday 27th January, 2013 at 11:48:56 UTC by Wilbert Pol
(MESS) z80ne.c: Tagmap cleanups (nw)

[src/mess/drivers]	z80ne.c
[src/mess/includes]	z80ne.h
[src/mess/machine]	z80ne.c

trunk/src/mess/machine/z80ne.c

r20524	r20525
18	18	#include "machine/wd17xx.h"
19	19
20	20	/* Devices */
21		#include "imagedev/cassette.h"
22	21	#include "imagedev/flopdrv.h"
23	22
24	23	#define VERBOSE 0
r20524	r20525
30	29
31	30	/* timer to read cassette waveforms */
32	31
33		static cassette_image_device *cassette_device_image(running_machine &machine)
	32	cassette_image_device* z80ne_state::cassette_device_image()
34	33	{
35		z80ne_state *state = machine.driver_data<z80ne_state>();
36		if (state->m_lx385_ctrl & 0x08)
37		return machine.device<cassette_image_device>(CASSETTE2_TAG);
	34	if (m_lx385_ctrl & 0x08)
	35	return m_cassette2;
38	36	else
39		return machine.device<cassette_image_device>(CASSETTE_TAG);
	37	return m_cassette1;
40	38	}
41	39
42	40	TIMER_CALLBACK_MEMBER(z80ne_state::z80ne_cassette_tc)
r20524	r20525
44	42	UINT8 cass_ws = 0;
45	43	m_cass_data.input.length++;
46	44
47		cass_ws = ((cassette_device_image(machine()))->input() > +0.02) ? 1 : 0;
	45	cass_ws = ((cassette_device_image())->input() > +0.02) ? 1 : 0;
48	46
49	47	if ((cass_ws ^ m_cass_data.input.level) & cass_ws)
50	48	{
r20524	r20525
69	67	cass_ws = ay31015_get_output_pin( m_ay31015, AY31015_SO );
70	68	m_cass_data.wave_length = cass_ws ? m_cass_data.wave_short : m_cass_data.wave_long;
71	69	}
72		cassette_device_image(machine())->output(m_cass_data.output.level ? -1.0 : +1.0);
	70	cassette_device_image()->output(m_cass_data.output.level ? -1.0 : +1.0);
73	71	m_cass_data.output.length = m_cass_data.wave_length;
74	72	}
75	73	}
r20524	r20525
78	76	DRIVER_INIT_MEMBER(z80ne_state,z80ne)
79	77	{
80	78	/* first two entries point to rom on reset */
81		UINT8 *RAM = memregion("z80ne")->base();
82		membank("bank1")->configure_entry(0, &RAM[0x00000]); /* RAM   at 0x0000 */
83		membank("bank1")->configure_entry(1, &RAM[0x14000]); /* ep382 at 0x0000 */
84		membank("bank2")->configure_entry(0, &RAM[0x14000]); /* ep382 at 0x8000 */
	79	UINT8 *RAM = m_region_z80ne->base();
	80	m_bank1->configure_entry(0, &RAM[0x00000]); /* RAM   at 0x0000 */
	81	m_bank1->configure_entry(1, &RAM[0x14000]); /* ep382 at 0x0000 */
	82	m_bank2->configure_entry(0, &RAM[0x14000]); /* ep382 at 0x8000 */
85	83	}
86	84
87	85	DRIVER_INIT_MEMBER(z80ne_state,z80net)
r20524	r20525
96	94	DRIVER_INIT_MEMBER(z80ne_state,z80netf)
97	95	{
98	96	/* first two entries point to rom on reset */
99		UINT8 *RAM = memregion("z80ne")->base();
100		membank("bank1")->configure_entry(0, &RAM[0x00000]); /* RAM   at 0x0000-0x03FF */
101		membank("bank1")->configure_entries(1, 3, &RAM[0x14400], 0x0400); /* ep390, ep1390, ep2390 at 0x0000-0x03FF */
102		membank("bank1")->configure_entry(4, &RAM[0x14000]); /* ep382 at 0x0000-0x03FF */
103		membank("bank1")->configure_entry(5, &RAM[0x10000]); /* ep548 at 0x0000-0x03FF */
	97	UINT8 *RAM = m_region_z80ne->base();
	98	m_bank1->configure_entry(0, &RAM[0x00000]); /* RAM   at 0x0000-0x03FF */
	99	m_bank1->configure_entries(1, 3, &RAM[0x14400], 0x0400); /* ep390, ep1390, ep2390 at 0x0000-0x03FF */
	100	m_bank1->configure_entry(4, &RAM[0x14000]); /* ep382 at 0x0000-0x03FF */
	101	m_bank1->configure_entry(5, &RAM[0x10000]); /* ep548 at 0x0000-0x03FF */
104	102
105		membank("bank2")->configure_entry(0, &RAM[0x00400]); /* RAM   at 0x0400 */
106		membank("bank2")->configure_entry(1, &RAM[0x10400]); /* ep548 at 0x0400-0x3FFF */
	103	m_bank2->configure_entry(0, &RAM[0x00400]); /* RAM   at 0x0400 */
	104	m_bank2->configure_entry(1, &RAM[0x10400]); /* ep548 at 0x0400-0x3FFF */
107	105
108		membank("bank3")->configure_entry(0, &RAM[0x08000]); /* RAM   at 0x8000 */
109		membank("bank3")->configure_entry(1, &RAM[0x14000]); /* ep382 at 0x8000 */
	106	m_bank3->configure_entry(0, &RAM[0x08000]); /* RAM   at 0x8000 */
	107	m_bank3->configure_entry(1, &RAM[0x14000]); /* ep382 at 0x8000 */
110	108
111		membank("bank4")->configure_entry(0, &RAM[0x0F000]); /* RAM   at 0xF000 */
112		membank("bank4")->configure_entries(1, 3, &RAM[0x14400], 0x0400); /* ep390, ep1390, ep2390 at 0xF000 */
	109	m_bank4->configure_entry(0, &RAM[0x0F000]); /* RAM   at 0xF000 */
	110	m_bank4->configure_entries(1, 3, &RAM[0x14400], 0x0400); /* ep390, ep1390, ep2390 at 0xF000 */
113	111
114	112	}
115	113
r20524	r20525
145	143	if ( --m_lx383_downsampler == 0 )
146	144	{
147	145	m_lx383_downsampler = LX383_DOWNSAMPLING;
148		key_bits = (machine().root_device().ioport("ROW1")->read() << 8) | machine().root_device().ioport("ROW0")->read();
149		//      rst = machine().root_device().ioport("RST")->read();
150		ctrl = machine().root_device().ioport("CTRL")->read();
	146	key_bits = (m_io_row1->read() << 8) | m_io_row0->read();
	147	//      rst = m_io_rst->read();
	148	ctrl = m_io_ctrl->read();
151	149
152	150	for ( i = 0; i<LX383_KEYS; i++)
153	151	{
r20524	r20525
195	193	/* remove this callback */
196	194	machine().device("z80ne")->memory().space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_default), this));
197	195	/* and switch to RAM bank at address 0x0000 */
198		membank( "bank1" )->set_entry( 0 ); /* RAM at 0x0000 (bank 1) */
	196	m_bank1->set_entry( 0 ); /* RAM at 0x0000 (bank 1) */
199	197	}
200	198	return address;
201	199	}
202	200
203		static void reset_lx388(running_machine &machine)
	201	void z80ne_state::reset_lx388()
204	202	{
205		z80ne_state *state = machine.driver_data<z80ne_state>();
206		state->m_lx388_kr2376 = machine.device("lx388_kr2376");
207		kr2376_set_input_pin( state->m_lx388_kr2376, KR2376_DSII, 0);
208		kr2376_set_input_pin( state->m_lx388_kr2376, KR2376_PII, 0);
	203	kr2376_set_input_pin( m_lx388_kr2376, KR2376_DSII, 0);
	204	kr2376_set_input_pin( m_lx388_kr2376, KR2376_PII, 0);
209	205	}
210	206
211		static void reset_lx382_banking(running_machine &machine)
	207	void z80ne_state::reset_lx382_banking()
212	208	{
213		z80ne_state *state = machine.driver_data<z80ne_state>();
214		address_space &space = machine.device("z80ne")->memory().space(AS_PROGRAM);
215
216	209	/* switch to ROM bank at address 0x0000 */
217		state->membank("bank1")->set_entry(1);
218		state->membank("bank2")->set_entry(0);  /* ep382 at 0x8000 */
	210	m_bank1->set_entry(1);
	211	m_bank2->set_entry(0);  /* ep382 at 0x8000 */
219	212
220	213	/* after the first 3 bytes have been read from ROM, switch the RAM back in */
221		state->m_reset_delay_counter = 2;
222		space.set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_reset_delay_count), state));
	214	m_reset_delay_counter = 2;
	215	m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_reset_delay_count), this));
223	216	}
224	217
225		static void reset_lx390_banking(running_machine &machine)
	218	void z80ne_state::reset_lx390_banking()
226	219	{
227		z80ne_state *state = machine.driver_data<z80ne_state>();
228		address_space &space = machine.device("z80ne")->memory().space(AS_PROGRAM);
229		state->m_reset_delay_counter = 0;
	220	m_reset_delay_counter = 0;
230	221
231		switch (machine.root_device().ioport("CONFIG")->read() & 0x07) {
	222	switch (m_io_config->read() & 0x07) {
232	223	case 0x01: /* EP382 Hex Monitor */
233	224	if (VERBOSE)
234	225	logerror("reset_lx390_banking: banking ep382\n");
235		state->membank("bank1")->set_entry(4);  /* ep382 at 0x0000 for 3 cycles, then RAM */
236		state->membank("bank2")->set_entry(0);  /* RAM   at 0x0400 */
237		state->membank("bank3")->set_entry(1);  /* ep382 at 0x8000 */
238		state->membank("bank4")->set_entry(0);  /* RAM   at 0xF000 */
	226	m_bank1->set_entry(4);  /* ep382 at 0x0000 for 3 cycles, then RAM */
	227	m_bank2->set_entry(0);  /* RAM   at 0x0400 */
	228	m_bank3->set_entry(1);  /* ep382 at 0x8000 */
	229	m_bank4->set_entry(0);  /* RAM   at 0xF000 */
239	230	/* after the first 3 bytes have been read from ROM, switch the RAM back in */
240		state->m_reset_delay_counter = 2;
241		space.set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_reset_delay_count), state));
	231	m_reset_delay_counter = 2;
	232	m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_reset_delay_count), this));
242	233	break;
243	234	case 0x02: /* EP548  16k BASIC */
244	235	if (VERBOSE)
245	236	logerror("reset_lx390_banking: banking ep548\n");
246		state->membank("bank1")->set_entry(5);  /* ep548 at 0x0000-0x03FF */
247		state->membank("bank2")->set_entry(1);  /* ep548 at 0x0400-0x3FFF */
248		state->membank("bank3")->set_entry(0);  /* RAM   at 0x8000 */
249		state->membank("bank4")->set_entry(0);  /* RAM   at 0xF000 */
250		machine.device("z80ne")->memory().space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_default), state));
	237	m_bank1->set_entry(5);  /* ep548 at 0x0000-0x03FF */
	238	m_bank2->set_entry(1);  /* ep548 at 0x0400-0x3FFF */
	239	m_bank3->set_entry(0);  /* RAM   at 0x8000 */
	240	m_bank4->set_entry(0);  /* RAM   at 0xF000 */
	241	m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_default), this));
251	242	break;
252	243	case 0x03: /* EP390  Boot Loader for 5.5k floppy BASIC */
253	244	if (VERBOSE)
254	245	logerror("reset_lx390_banking: banking ep390\n");
255		state->membank("bank1")->set_entry(1);  /* ep390 at 0x0000-0 x03FF for 3 cycles, then RAM */
256		state->membank("bank2")->set_entry(0);  /* RAM   at 0x0400-0x3FFF */
257		state->membank("bank3")->set_entry(0);  /* RAM   at 0x8000 */
258		state->membank("bank4")->set_entry(1);  /* ep390 at 0xF000 */
259		machine.device("z80ne")->memory().space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_default), state));
	246	m_bank1->set_entry(1);  /* ep390 at 0x0000-0 x03FF for 3 cycles, then RAM */
	247	m_bank2->set_entry(0);  /* RAM   at 0x0400-0x3FFF */
	248	m_bank3->set_entry(0);  /* RAM   at 0x8000 */
	249	m_bank4->set_entry(1);  /* ep390 at 0xF000 */
	250	m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_default), this));
260	251	break;
261	252	case 0x04: /* EP1390 Boot Loader for NE DOS 1.0/1.5 */
262	253	if (VERBOSE)
263	254	logerror("reset_lx390_banking: banking ep1390\n");
264		state->membank("bank1")->set_entry(2);  /* ep1390 at 0x0000-0x03FF for 3 cycles, then RAM */
265		state->membank("bank2")->set_entry(0);  /* RAM   at 0x0400-0x3FFF */
266		state->membank("bank3")->set_entry(0);  /* RAM   at 0x8000 */
267		state->membank("bank4")->set_entry(2);  /* ep1390 at 0xF000 */
268		machine.device("z80ne")->memory().space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_default), state));
	255	m_bank1->set_entry(2);  /* ep1390 at 0x0000-0x03FF for 3 cycles, then RAM */
	256	m_bank2->set_entry(0);  /* RAM   at 0x0400-0x3FFF */
	257	m_bank3->set_entry(0);  /* RAM   at 0x8000 */
	258	m_bank4->set_entry(2);  /* ep1390 at 0xF000 */
	259	m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_default), this));
269	260	break;
270	261	case 0x05: /* EP2390 Boot Loader for NE DOS G.1 */
271	262	if (VERBOSE)
272	263	logerror("reset_lx390_banking: banking ep2390\n");
273		state->membank("bank1")->set_entry(3);  /* ep2390 at 0x0000-0x03FF for 3 cycles, then RAM */
274		state->membank("bank2")->set_entry(0);  /* RAM   at 0x0400-0x3FFF */
275		state->membank("bank3")->set_entry(0);  /* RAM   at 0x8000 */
276		state->membank("bank4")->set_entry(3);  /* ep2390 at 0xF000 */
277		machine.device("z80ne")->memory().space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_default), state));
	264	m_bank1->set_entry(3);  /* ep2390 at 0x0000-0x03FF for 3 cycles, then RAM */
	265	m_bank2->set_entry(0);  /* RAM   at 0x0400-0x3FFF */
	266	m_bank3->set_entry(0);  /* RAM   at 0x8000 */
	267	m_bank4->set_entry(3);  /* ep2390 at 0xF000 */
	268	m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_default), this));
278	269	break;
279	270	}
280	271
r20524	r20525
286	277	MACHINE_RESET_MEMBER(z80ne_state,z80ne_base)
287	278	{
288	279	int i;
289		address_space &space = machine().device("z80ne")->memory().space(AS_PROGRAM);
290	280
291	281	LOG(("In MACHINE_RESET z80ne_base\n"));
292	282
r20524	r20525
296	286	m_lx383_downsampler = LX383_DOWNSAMPLING;
297	287
298	288	/* Initialize cassette interface */
299		switch(machine().root_device().ioport("LX.385")->read() & 0x07)
	289	switch(m_io_lx_385->read() & 0x07)
300	290	{
301	291	case 0x01:
302	292	m_cass_data.speed = TAPE_300BPS;
r20524	r20525
322	312	m_cass_data.input.length = 0;
323	313	m_cass_data.input.bit = 1;
324	314
325		m_ay31015 = machine().device("ay_3_1015");
326	315	ay31015_set_input_pin( m_ay31015, AY31015_CS, 0 );
327	316	ay31015_set_input_pin( m_ay31015, AY31015_NB1, 1 );
328	317	ay31015_set_input_pin( m_ay31015, AY31015_NB2, 1 );
329	318	ay31015_set_input_pin( m_ay31015, AY31015_TSB, 1 );
330	319	ay31015_set_input_pin( m_ay31015, AY31015_EPS, 1 );
331		ay31015_set_input_pin( m_ay31015, AY31015_NP, machine().root_device().ioport("LX.385")->read() & 0x80 ? 1 : 0 );
	320	ay31015_set_input_pin( m_ay31015, AY31015_NP, m_io_lx_385->read() & 0x80 ? 1 : 0 );
332	321	ay31015_set_input_pin( m_ay31015, AY31015_CS, 1 );
333	322	ay31015_set_receiver_clock( m_ay31015, m_cass_data.speed * 16.0);
334	323	ay31015_set_transmitter_clock( m_ay31015, m_cass_data.speed * 16.0);
335	324
336	325	m_nmi_delay_counter = 0;
337		lx385_ctrl_w(space, 0, 0);
	326	lx385_ctrl_w(m_maincpu->space(AS_PROGRAM), 0, 0);
338	327
339	328	}
340	329
341	330	MACHINE_RESET_MEMBER(z80ne_state,z80ne)
342	331	{
343	332	LOG(("In MACHINE_RESET z80ne\n"));
344		reset_lx382_banking(machine());
	333	reset_lx382_banking();
345	334	MACHINE_RESET_CALL_MEMBER( z80ne_base );
346	335	}
347	336
r20524	r20525
349	338	{
350	339	LOG(("In MACHINE_RESET z80net\n"));
351	340	MACHINE_RESET_CALL_MEMBER( z80ne );
352		reset_lx388(machine());
	341	reset_lx388();
353	342	}
354	343
355	344	MACHINE_RESET_MEMBER(z80ne_state,z80netb)
356	345	{
357	346	LOG(("In MACHINE_RESET z80netb\n"));
358	347	MACHINE_RESET_CALL_MEMBER( z80ne_base );
359		reset_lx388(machine());
	348	reset_lx388();
360	349	}
361	350
362	351	MACHINE_RESET_MEMBER(z80ne_state,z80netf)
363	352	{
364	353	LOG(("In MACHINE_RESET z80netf\n"));
365		reset_lx390_banking(machine());
	354	reset_lx390_banking();
366	355	MACHINE_RESET_CALL_MEMBER( z80ne_base );
367		reset_lx388(machine());
	356	reset_lx388();
368	357	}
369	358
370	359	INPUT_CHANGED_MEMBER(z80ne_state::z80ne_reset)
371	360	{
372	361	UINT8 rst;
373		rst = machine().root_device().ioport("RST")->read();
	362	rst = m_io_rst->read();
374	363
375	364	if ( ! BIT(rst, 0))
376	365	{
r20524	r20525
381	370	INPUT_CHANGED_MEMBER(z80ne_state::z80ne_nmi)
382	371	{
383	372	UINT8 nmi;
384		nmi = machine().root_device().ioport("LX388_BRK")->read();
	373	nmi = m_io_lx388_brk->read();
385	374
386	375	if ( ! BIT(nmi, 0))
387	376	{
388		machine().device("z80ne")->execute().set_input_line(INPUT_LINE_NMI, PULSE_LINE);
	377	m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
389	378	}
390	379	}
391	380
r20524	r20525
393	382	{
394	383	LOG(("In MACHINE_START z80ne\n"));
395	384	m_lx385_ctrl = 0x1f;
396		state_save_register_item( machine(), "z80ne", NULL, 0, m_lx383_scan_counter );
397		state_save_register_item( machine(), "z80ne", NULL, 0, m_lx383_downsampler );
398		state_save_register_item_array( machine(), "z80ne", NULL, 0, m_lx383_key );
399		state_save_register_item( machine(), "z80ne", NULL, 0, m_nmi_delay_counter );
	385	save_item(NAME(m_lx383_scan_counter));
	386	save_item(NAME(m_lx383_downsampler));
	387	save_item(NAME(m_lx383_key));
	388	save_item(NAME(m_nmi_delay_counter));
400	389	m_cassette_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(z80ne_state::z80ne_cassette_tc),this));
401	390	machine().scheduler().timer_pulse( attotime::from_hz(1000), timer_expired_delegate(FUNC(z80ne_state::z80ne_kbd_scan),this));
402	391	}
r20524	r20525
476	465	if ( offset < 8 )
477	466	output_set_digit_value( offset, data ^ 0xff );
478	467	else
	468	{
479	469	/* after writing to port 0xF8 and the first ~M1 cycles strike a NMI for single step execution */
480	470	m_nmi_delay_counter = 1;
481		machine().device("z80ne")->memory().space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_nmi_delay_count), this));
	471	m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(z80ne_state::z80ne_nmi_delay_count), this));
	472	}
482	473	}
483	474
484	475
r20524	r20525
596	587	/* motors */
597	588	if(changed_bits & 0x18)
598	589	{
599		machine().device<cassette_image_device>(CASSETTE_TAG)->change_state(
	590	m_cassette1->change_state(
600	591	(motor_a) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
601	592
602		machine().device<cassette_image_device>(CASSETTE2_TAG)->change_state(
	593	m_cassette2->change_state(
603	594	(motor_b) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
604	595
605	596	if (motor_a || motor_b)
r20524	r20525
688	679	if (drive < 4)
689	680	{
690	681	LOG(("lx390_motor_w, set drive %1d\n", drive));
691		wd17xx_set_drive(machine().device("wd1771"),drive);
	682	wd17xx_set_drive(m_wd1771,drive);
692	683	LOG(("lx390_motor_w, set side %1d\n", m_wd17xx_state.head));
693		wd17xx_set_side(machine().device("wd1771"), m_wd17xx_state.head);
	684	wd17xx_set_side(m_wd1771, m_wd17xx_state.head);
694	685	}
695	686	}
696	687
r20524	r20525
699	690	offs_t pc;
700	691
701	692	/* if PC is not in range, we are under integrated debugger control, DON'T SWAP */
702		pc = machine().device("z80ne")->safe_pc();
	693	pc = m_maincpu->pc();
703	694	if((pc >= 0xf000) && (pc <=0xffff))
704	695	{
705	696	LOG(("lx390_reset_bank, reset memory bank 1\n"));
706		membank("bank1")->set_entry(0); /* RAM at 0x0000 (bank 1) */
	697	m_bank1->set_entry(0); /* RAM at 0x0000 (bank 1) */
707	698	}
708	699	else
709	700	{
r20524	r20525
719	710	switch(offset)
720	711	{
721	712	case 0:
722		d = wd17xx_status_r(machine().device("wd1771"), space, 0) ^ 0xff;
	713	d = wd17xx_status_r(m_wd1771, space, 0) ^ 0xff;
723	714	LOG(("lx390_fdc_r, WD17xx status: %02x\n", d));
724	715	break;
725	716	case 1:
726		d = wd17xx_track_r(machine().device("wd1771"), space, 0) ^ 0xff;
	717	d = wd17xx_track_r(m_wd1771, space, 0) ^ 0xff;
727	718	LOG(("lx390_fdc_r, WD17xx track:  %02x\n", d));
728	719	break;
729	720	case 2:
730		d = wd17xx_sector_r(machine().device("wd1771"), space, 0) ^ 0xff;
	721	d = wd17xx_sector_r(m_wd1771, space, 0) ^ 0xff;
731	722	LOG(("lx390_fdc_r, WD17xx sector: %02x\n", d));
732	723	break;
733	724	case 3:
734		d = wd17xx_data_r(machine().device("wd1771"), space, 0) ^ 0xff;
	725	d = wd17xx_data_r(m_wd1771, space, 0) ^ 0xff;
735	726	LOG(("lx390_fdc_r, WD17xx data3:  %02x\n", d));
736	727	break;
737	728	case 6:
r20524	r20525
739	730	lx390_reset_bank(space, 0);
740	731	break;
741	732	case 7:
742		d = wd17xx_data_r(machine().device("wd1771"), space, 3) ^ 0xff;
	733	d = wd17xx_data_r(m_wd1771, space, 3) ^ 0xff;
743	734	LOG(("lx390_fdc_r, WD17xx data7, force:  %02x\n", d));
744	735	break;
745	736	default:
r20524	r20525
757	748	{
758	749	case 0:
759	750	LOG(("lx390_fdc_w, WD17xx command: %02x\n", d));
760		wd17xx_command_w(machine().device("wd1771"), space, offset, d ^ 0xff);
	751	wd17xx_command_w(m_wd1771, space, offset, d ^ 0xff);
761	752	if (m_wd17xx_state.drive & 1)
762	753	output_set_value("drv0", 2);
763	754	else if (m_wd17xx_state.drive & 2)
r20524	r20525
765	756	break;
766	757	case 1:
767	758	LOG(("lx390_fdc_w, WD17xx track:   %02x\n", d));
768		wd17xx_track_w(machine().device("wd1771"), space, offset, d ^ 0xff);
	759	wd17xx_track_w(m_wd1771, space, offset, d ^ 0xff);
769	760	break;
770	761	case 2:
771	762	LOG(("lx390_fdc_w, WD17xx sector:  %02x\n", d));
772		wd17xx_sector_w(machine().device("wd1771"), space, offset, d ^ 0xff);
	763	wd17xx_sector_w(m_wd1771, space, offset, d ^ 0xff);
773	764	break;
774	765	case 3:
775		wd17xx_data_w(machine().device("wd1771"), space, 0, d ^ 0xff);
	766	wd17xx_data_w(m_wd1771, space, 0, d ^ 0xff);
776	767	LOG(("lx390_fdc_w, WD17xx data3:   %02x\n", d));
777	768	break;
778	769	case 6:
r20524	r20525
781	772	break;
782	773	case 7:
783	774	LOG(("lx390_fdc_w, WD17xx data7, force:   %02x\n", d));
784		wd17xx_data_w(machine().device("wd1771"), space, 3, d ^ 0xff);
	775	wd17xx_data_w(m_wd1771, space, 3, d ^ 0xff);
785	776	break;
786	777	}
787	778	}

trunk/src/mess/includes/z80ne.h

r20524	r20525
12	12	#define Z80NE_H_
13	13
14	14	#include "video/mc6847.h"
	15	#include "imagedev/cassette.h"
15	16
16	17
17	18	/***************************************************************************
r20524	r20525
63	64	{
64	65	public:
65	66	z80ne_state(const machine_config &mconfig, device_type type, const char *tag)
66		: driver_device(mconfig, type, tag),
67		m_vdg(*this, "mc6847"),
68		m_videoram(*this,"videoram") {}
	67	: driver_device(mconfig, type, tag)
	68	, m_vdg(*this, "mc6847")
	69	, m_videoram(*this, "videoram")
	70	, m_ay31015(*this, "ay_3_1015")
	71	, m_lx388_kr2376(*this, "lx388_kr2376")
	72	, m_maincpu(*this, "z80ne")
	73	, m_cassette1(*this, CASSETTE_TAG)
	74	, m_cassette2(*this, CASSETTE2_TAG)
	75	, m_wd1771(*this, "wd1771")
	76	, m_region_z80ne(*this, "z80ne")
	77	, m_bank1(*this, "bank1")
	78	, m_bank2(*this, "bank2")
	79	, m_bank3(*this, "bank3")
	80	, m_bank4(*this, "bank4")
	81	, m_io_row0(*this, "ROW0")
	82	, m_io_row1(*this, "ROW1")
	83	, m_io_ctrl(*this, "CTRL")
	84	, m_io_rst(*this, "RST")
	85	, m_io_lx_385(*this, "LX.385")
	86	, m_io_lx388_brk(*this, "LX388_BRK")
	87	, m_io_x0(*this, "X0")
	88	, m_io_x1(*this, "X1")
	89	, m_io_x2(*this, "X2")
	90	, m_io_x3(*this, "X3")
	91	, m_io_x4(*this, "X4")
	92	, m_io_x5(*this, "X5")
	93	, m_io_x6(*this, "X6")
	94	, m_io_x7(*this, "X7")
	95	, m_io_modifiers(*this, "MODIFIERS")
	96	, m_io_config(*this, "CONFIG")
	97	{ }
69	98
70	99	optional_device<mc6847_base_device> m_vdg;
71	100	optional_shared_ptr<UINT8> m_videoram;
	101	required_device<device_t> m_ay31015;
	102	optional_device<device_t> m_lx388_kr2376;
72	103	UINT8 m_lx383_scan_counter;
73	104	UINT8 m_lx383_key[LX383_KEYS];
74	105	int m_lx383_downsampler;
75	106	int m_nmi_delay_counter;
76	107	int m_reset_delay_counter;
77		device_t *m_ay31015;
78	108	UINT8 m_lx385_ctrl;
79		device_t *m_lx388_kr2376;
80	109	emu_timer *m_cassette_timer;
81	110	cass_data_t m_cass_data;
82	111	wd17xx_state_t m_wd17xx_state;
r20524	r20525
113	142	DECLARE_READ8_MEMBER(lx390_reset_bank);
114	143	DECLARE_READ8_MEMBER(lx390_fdc_r);
115	144	DECLARE_WRITE8_MEMBER(lx390_fdc_w);
	145
	146	protected:
	147	required_device<cpu_device> m_maincpu;
	148	required_device<cassette_image_device> m_cassette1;
	149	required_device<cassette_image_device> m_cassette2;
	150	optional_device<device_t> m_wd1771;
	151	required_memory_region m_region_z80ne;
	152	required_memory_bank m_bank1;
	153	required_memory_bank m_bank2;
	154	optional_memory_bank m_bank3;
	155	optional_memory_bank m_bank4;
	156	required_ioport m_io_row0;
	157	required_ioport m_io_row1;
	158	required_ioport m_io_ctrl;
	159	required_ioport m_io_rst;
	160	required_ioport m_io_lx_385;
	161	optional_ioport m_io_lx388_brk;
	162	optional_ioport m_io_x0;
	163	optional_ioport m_io_x1;
	164	optional_ioport m_io_x2;
	165	optional_ioport m_io_x3;
	166	optional_ioport m_io_x4;
	167	optional_ioport m_io_x5;
	168	optional_ioport m_io_x6;
	169	optional_ioport m_io_x7;
	170	optional_ioport m_io_modifiers;
	171	optional_ioport m_io_config;
	172
	173	cassette_image_device *cassette_device_image();
	174	void reset_lx388();
	175	void reset_lx382_banking();
	176	void reset_lx390_banking();
116	177	};
117	178
118	179	#endif /* Z80NE_H_ */

trunk/src/mess/drivers/z80ne.c

r20524	r20525
93	93	#include "cpu/z80/z80.h"
94	94	#include "includes/z80ne.h"
95	95	#include "imagedev/flopdrv.h"
96		#include "imagedev/cassette.h"
97	96	#include "formats/z80ne_dsk.h"
98	97	#include "machine/ram.h"
99	98
100	99	/* peripheral chips */
101	100	#include "machine/ay31015.h"
102	101	#include "machine/kr2376.h"
103		#include "video/mc6847.h"
104	102	#include "machine/wd17xx.h"
105	103
106	104	/* Layout */

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