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r20509 Saturday 26th January, 2013 at 20:23:50 UTC by Ryan Holtz
[CDI] Modernized CD-i and removed tag lookups [MooglyGuy]

[src/mame/drivers]	cdi.c
[src/mame/includes]	cdi.h
[src/mame/machine]	cdi070.c cdi070.h cdicdic.c cdicdic.h cdislave.c cdislave.h
[src/mame/video]	mcd212.c

trunk/src/mame/machine/cdislave.c

r20508	r20509
50	50	//  MEMBER FUNCTIONS
51	51	//**************************************************************************
52	52
53		TIMER_CALLBACK( cdislave_device::trigger_readback_int )
	53	TIMER_CALLBACK_MEMBER( cdislave_device::trigger_readback_int )
54	54	{
55		cdislave_device *slave = static_cast<cdislave_device *>(machine.device("slave"));
56		slave->readback_trigger();
57		}
	55	cdi_state *state = machine().driver_data<cdi_state>();
58	56
59		void cdislave_device::readback_trigger()
60		{
61	57	verboselog(machine(), 0, "Asserting IRQ2\n" );
62		machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_2, 26);
63		machine().device("maincpu")->execute().set_input_line(M68K_IRQ_2, ASSERT_LINE);
	58	state->m_maincpu->set_input_line_vector(M68K_IRQ_2, 26);
	59	state->m_maincpu->set_input_line(M68K_IRQ_2, ASSERT_LINE);
64	60	m_interrupt_timer->adjust(attotime::never);
65	61	}
66	62
r20508	r20509
79	75
80	76	void cdislave_device::perform_mouse_update()
81	77	{
82		UINT16 x = machine().root_device().ioport("MOUSEX")->read();
83		UINT16 y = machine().root_device().ioport("MOUSEY")->read();
84		UINT8 buttons = machine().root_device().ioport("MOUSEBTN")->read();
	78	cdi_state *state = machine().driver_data<cdi_state>();
85	79
	80	UINT16 x = state->m_mousex->read();
	81	UINT16 y = state->m_mousey->read();
	82	UINT8 buttons = state->m_mousebtn->read();
	83
86	84	UINT16 old_mouse_x = m_real_mouse_x;
87	85	UINT16 old_mouse_y = m_real_mouse_y;
88	86
r20508	r20509
122	120	perform_mouse_update();
123	121	}
124	122
125		READ16_DEVICE_HANDLER( slave_r )
	123	READ16_MEMBER( cdislave_device::slave_r )
126	124	{
127		return downcast<cdislave_device *>(device)->register_read(offset, mem_mask);
128		}
	125	cdi_state *state = machine().driver_data<cdi_state>();
129	126
130		UINT16 cdislave_device::register_read(const UINT32 offset, const UINT16 mem_mask)
131		{
132	127	if(m_channel[offset].m_out_count)
133	128	{
134	129	UINT8 ret = m_channel[offset].m_out_buf[m_channel[offset].m_out_index];
r20508	r20509
144	139	case 0xf4:
145	140	case 0xf7:
146	141	verboselog(machine(), 0, "slave_r: De-asserting IRQ2\n" );
147		machine().device("maincpu")->execute().set_input_line(M68K_IRQ_2, CLEAR_LINE);
	142	state->m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
148	143	break;
149	144	}
150	145	}
r20508	r20509
180	175	}
181	176	}
182	177
183		WRITE16_DEVICE_HANDLER( slave_w )
	178	WRITE16_MEMBER( cdislave_device::slave_w )
184	179	{
185		downcast<cdislave_device *>(device)->register_write(offset, data, mem_mask);
186		}
187
188		void cdislave_device::register_write(const UINT32 offset, const UINT16 data, const UINT16 mem_mask)
189		{
190	180	cdi_state *state = machine().driver_data<cdi_state>();
191	181
192	182	switch(offset)
r20508	r20509
429	419	cdislave_device::cdislave_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
430	420	: device_t(mconfig, MACHINE_CDISLAVE, "CDISLAVE", tag, owner, clock)
431	421	{
432		init();
433	422	}
434	423
435	424	//-------------------------------------------------
r20508	r20509
438	427
439	428	void cdislave_device::device_start()
440	429	{
441		register_globals();
442
443		m_interrupt_timer = machine().scheduler().timer_alloc(FUNC(trigger_readback_int));
444		m_interrupt_timer->adjust(attotime::never);
445		}
446
447		//-------------------------------------------------
448		//  device_reset - device-specific reset
449		//-------------------------------------------------
450
451		void cdislave_device::device_reset()
452		{
453		init();
454		}
455
456		void cdislave_device::init()
457		{
458		for(INT32 index = 0; index < 4; index++)
459		{
460		m_channel[index].m_out_buf[0] = 0;
461		m_channel[index].m_out_buf[1] = 0;
462		m_channel[index].m_out_buf[2] = 0;
463		m_channel[index].m_out_buf[3] = 0;
464		m_channel[index].m_out_index = 0;
465		m_channel[index].m_out_count = 0;
466		m_channel[index].m_out_cmd = 0;
467		}
468
469		memset(m_in_buf, 0, 17);
470		m_in_index = 0;
471		m_in_count = 0;
472
473		m_polling_active = 0;
474
475		m_xbus_interrupt_enable = 0;
476
477		memset(m_lcd_state, 0, 16);
478
479		m_real_mouse_x = 0xffff;
480		m_real_mouse_y = 0xffff;
481
482		m_fake_mouse_x = 0;
483		m_fake_mouse_y = 0;
484		}
485
486		void cdislave_device::register_globals()
487		{
488	430	save_item(NAME(m_channel[0].m_out_buf[0]));
489	431	save_item(NAME(m_channel[0].m_out_buf[1]));
490	432	save_item(NAME(m_channel[0].m_out_buf[2]));
r20508	r20509
529	471
530	472	save_item(NAME(m_fake_mouse_x));
531	473	save_item(NAME(m_fake_mouse_y));
	474
	475	m_interrupt_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(cdislave_device::trigger_readback_int), this));
	476	m_interrupt_timer->adjust(attotime::never);
532	477	}
	478
	479	//-------------------------------------------------
	480	//  device_reset - device-specific reset
	481	//-------------------------------------------------
	482
	483	void cdislave_device::device_reset()
	484	{
	485	for(INT32 index = 0; index < 4; index++)
	486	{
	487	m_channel[index].m_out_buf[0] = 0;
	488	m_channel[index].m_out_buf[1] = 0;
	489	m_channel[index].m_out_buf[2] = 0;
	490	m_channel[index].m_out_buf[3] = 0;
	491	m_channel[index].m_out_index = 0;
	492	m_channel[index].m_out_count = 0;
	493	m_channel[index].m_out_cmd = 0;
	494	}
	495
	496	memset(m_in_buf, 0, 17);
	497	m_in_index = 0;
	498	m_in_count = 0;
	499
	500	m_polling_active = 0;
	501
	502	m_xbus_interrupt_enable = 0;
	503
	504	memset(m_lcd_state, 0, 16);
	505
	506	m_real_mouse_x = 0xffff;
	507	m_real_mouse_y = 0xffff;
	508
	509	m_fake_mouse_x = 0;
	510	m_fake_mouse_y = 0;
	511	}

trunk/src/mame/machine/cdislave.h

r20508	r20509
51	51
52	52	UINT8* get_lcd_state() { return m_lcd_state; }
53	53	void readback_trigger();
54		void register_write(const UINT32 offset, const UINT16 data, const UINT16 mem_mask);
55		UINT16 register_read(const UINT32 offset, const UINT16 mem_mask);
56	54
	55	DECLARE_READ16_MEMBER( slave_r );
	56	DECLARE_WRITE16_MEMBER( slave_w );
	57
57	58	protected:
58	59	// device-level overrides
59	60	virtual void device_start();
r20508	r20509
62	63	virtual void device_clock_changed() { }
63	64
64	65	// internal callbacks
65		static TIMER_CALLBACK( trigger_readback_int );
	66	TIMER_CALLBACK_MEMBER( trigger_readback_int );
66	67
67	68	private:
68	69	// internal state
r20508	r20509
96	97	UINT16 m_fake_mouse_x;
97	98	UINT16 m_fake_mouse_y;
98	99
99		void register_globals();
100		void init();
101
102	100	// static internal members
103	101
104	102	// non-static internal members
r20508	r20509
111	109	// device type definition
112	110	extern const device_type MACHINE_CDISLAVE;
113	111
114
115
116		//**************************************************************************
117		//  READ/WRITE HANDLERS
118		//**************************************************************************
119
120		DECLARE_READ16_DEVICE_HANDLER( slave_r );
121		DECLARE_WRITE16_DEVICE_HANDLER( slave_w );
122
123
124	112	#endif // __CDISLAVE_H__

trunk/src/mame/machine/cdicdic.c

r20508	r20509
530	530	}
531	531
532	532	// After an appropriate delay for decoding to take place...
533		TIMER_CALLBACK( cdicdic_device::audio_sample_trigger )
	533	TIMER_CALLBACK_MEMBER( cdicdic_device::audio_sample_trigger )
534	534	{
535		cdicdic_device *cdic = static_cast<cdicdic_device *>(machine.device("cdic"));
536		cdic->sample_trigger();
	535	sample_trigger();
537	536	}
538	537
539	538	void cdicdic_device::sample_trigger()
540	539	{
	540	cdi_state *state = machine().driver_data<cdi_state>();
	541
541	542	if(m_decode_addr == 0xffff)
542	543	{
543	544	verboselog(machine(), 0, "Decode stop requested, stopping playback\n" );
r20508	r20509
553	554
554	555	// Set the CDIC interrupt line
555	556	verboselog(machine(), 0, "Setting CDIC interrupt line for soundmap decode\n" );
556		machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_4, 128);
557		machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, ASSERT_LINE);
	557	state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
	558	state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
558	559	}
559	560	else
560	561	{
r20508	r20509
590	591	}
591	592	}
592	593
593		TIMER_CALLBACK( cdicdic_device::trigger_readback_int )
	594	TIMER_CALLBACK_MEMBER( cdicdic_device::trigger_readback_int )
594	595	{
595		cdicdic_device *cdic = static_cast<cdicdic_device *>(machine.device("cdic"));
596		cdic->process_delayed_command();
	596	process_delayed_command();
597	597	}
598	598
599	599	void cdicdic_device::process_delayed_command()
600	600	{
	601	cdi_state *state = machine().driver_data<cdi_state>();
	602
601	603	switch(m_command)
602	604	{
603	605	case 0x23: // Reset Mode 1
r20508	r20509
707	709
708	710	//printf( "Setting CDIC interrupt line\n" );
709	711	verboselog(machine(), 0, "Setting CDIC interrupt line for audio sector\n" );
710		machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_4, 128);
711		machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, ASSERT_LINE);
	712	state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
	713	state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
712	714	}
713	715	else if((buffer[CDIC_SECTOR_SUBMODE2] & (CDIC_SUBMODE_DATA | CDIC_SUBMODE_AUDIO | CDIC_SUBMODE_VIDEO)) == 0x00)
714	716	{
r20508	r20509
726	728	{
727	729	//printf( "Setting CDIC interrupt line\n" );
728	730	verboselog(machine(), 0, "Setting CDIC interrupt line for message sector\n" );
729		machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_4, 128);
730		machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, ASSERT_LINE);
	731	state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
	732	state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
731	733	}
732	734	else
733	735	{
r20508	r20509
746	748
747	749	//printf( "Setting CDIC interrupt line\n" );
748	750	verboselog(machine(), 0, "Setting CDIC interrupt line for data sector\n" );
749		machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_4, 128);
750		machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, ASSERT_LINE);
	751	state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
	752	state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
751	753	}
752	754
753	755	if((buffer[CDIC_SECTOR_SUBMODE2] & CDIC_SUBMODE_EOF) == 0 && m_command != 0x23)
r20508	r20509
803	805
804	806	if(!cdrom_read_data(m_cd, lba, buffer, CD_TRACK_RAW_DONTCARE))
805	807	{
806		printf( "liajfoaijsdofiaodf\n");
	808	mame_printf_verbose("Unable to read CD-ROM data.\n");
807	809	}
808	810
809	811	if(!(msf & 0x0000ff))
r20508	r20509
811	813	//              next_lba = next_nybbles[0] + next_nybbles[1]*10 + ((next_nybbles[2] + next_nybbles[3]*10)*75) + ((next_nybbles[4] + next_nybbles[5]*10)*75*60);
812	814	verboselog(machine(), 0, "Playing CDDA sector from MSF location %06x\n", m_time | 2 );
813	815
814		cdda_start_audio(machine().device("cdda"), lba, rounded_next_msf);
	816	cdda_start_audio(state->m_cdda, lba, rounded_next_msf);
815	817	}
816	818
817	819	m_ram[(m_data_buffer & 5) * (0xa00/2) + 0x924/2] = 0x0001;                      //  CTRL
r20508	r20509
841	843	}
842	844
843	845	verboselog(machine(), 0, "Setting CDIC interrupt line for CDDA sector\n" );
844		machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_4, 128);
845		machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, ASSERT_LINE);
	846	state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
	847	state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
846	848	break;
847	849	}
848	850	case 0x2c: // Seek
r20508	r20509
892	894	m_time = next_msf << 8;
893	895
894	896	verboselog(machine(), 0, "Setting CDIC interrupt line for Seek sector\n" );
895		machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_4, 128);
896		machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, ASSERT_LINE);
	897	state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
	898	state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
897	899	break;
898	900	}
899	901	}
900	902	}
901	903
902		READ16_DEVICE_HANDLER( cdic_r )
	904	READ16_MEMBER( cdicdic_device::regs_r )
903	905	{
904		return downcast<cdicdic_device *>(device)->register_read(offset, mem_mask);
905		}
906
907		UINT16 cdicdic_device::register_read(const UINT32 offset, const UINT16 mem_mask)
908		{
	906	cdi_state *state = machine().driver_data<cdi_state>();
909	907	UINT32 addr = offset + 0x3c00/2;
910	908
911	909	switch(addr)
r20508	r20509
944	942	m_audio_buffer &= 0x7fff;
945	943	if(!((m_audio_buffer | m_x_buffer) & 0x8000))
946	944	{
947		machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, CLEAR_LINE);
	945	state->m_maincpu->set_input_line(M68K_IRQ_4, CLEAR_LINE);
948	946	verboselog(machine(), 0, "Clearing CDIC interrupt line\n" );
949	947	////printf("Clearing CDIC interrupt line\n" );
950	948	}
r20508	r20509
958	956	m_x_buffer &= 0x7fff;
959	957	if(!((m_audio_buffer | m_x_buffer) & 0x8000))
960	958	{
961		machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, CLEAR_LINE);
	959	state->m_maincpu->set_input_line(M68K_IRQ_4, CLEAR_LINE);
962	960	verboselog(machine(), 0, "Clearing CDIC interrupt line\n" );
963	961	////printf("Clearing CDIC interrupt line\n" );
964	962	}
r20508	r20509
987	985	}
988	986	}
989	987
990		WRITE16_DEVICE_HANDLER( cdic_w )
	988	WRITE16_MEMBER( cdicdic_device::regs_w )
991	989	{
992		downcast<cdicdic_device *>(device)->register_write(offset, data, mem_mask);
993		}
994
995		void cdicdic_device::register_write(const UINT32 offset, const UINT16 data, const UINT16 mem_mask)
996		{
997	990	cdi_state *state = machine().driver_data<cdi_state>();
998	991
999	992	UINT32 addr = offset + 0x3c00/2;
r20508	r20509
1051	1044
1052	1045	case 0x3ff8/2:
1053	1046	{
1054		scc68070_regs_t *scc68070 = &state->m_scc68070_regs;
1055		UINT32 start = scc68070->dma.channel[0].memory_address_counter;
1056		UINT32 count = scc68070->dma.channel[0].transfer_counter;
	1047	UINT32 start = state->m_scc->dma().channel[0].memory_address_counter;
	1048	UINT32 count = state->m_scc->dma().channel[0].transfer_counter;
1057	1049	UINT32 index = 0;
1058	1050	UINT32 device_index = (data & 0x3fff) >> 1;
1059	1051	UINT16 *memory = state->m_planea;
r20508	r20509
1068	1060	}
1069	1061	for(index = start / 2; index < (start / 2 + count); index++)
1070	1062	{
1071		if(scc68070->dma.channel[0].operation_control & OCR_D)
	1063	if(state->m_scc->dma().channel[0].operation_control & OCR_D)
1072	1064	{
1073	1065	memory[index] = m_ram[device_index++];
1074	1066	}
r20508	r20509
1077	1069	m_ram[device_index++] = memory[index];
1078	1070	}
1079	1071	}
1080		scc68070->dma.channel[0].memory_address_counter += scc68070->dma.channel[0].transfer_counter * 2;
	1072	state->m_scc->dma().channel[0].memory_address_counter += state->m_scc->dma().channel[0].transfer_counter * 2;
1081	1073	break;
1082	1074	}
1083	1075
r20508	r20509
1123	1115	break;
1124	1116	}
1125	1117	case 0x2b: // Stop CDDA
1126		cdda_stop_audio(machine().device("cdda"));
	1118	cdda_stop_audio(state->m_cdda);
1127	1119	m_interrupt_timer->adjust(attotime::never);
1128	1120	break;
1129	1121	case 0x23: // Reset Mode 1
r20508	r20509
1171	1163	cdicdic_device::cdicdic_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
1172	1164	: device_t(mconfig, MACHINE_CDICDIC, "CDICDIC", tag, owner, clock)
1173	1165	{
1174		init();
1175	1166	}
1176	1167
1177	1168	//-------------------------------------------------
r20508	r20509
1180	1171
1181	1172	void cdicdic_device::device_start()
1182	1173	{
1183		register_globals();
	1174	save_item(NAME(m_command));
	1175	save_item(NAME(m_time));
	1176	save_item(NAME(m_file));
	1177	save_item(NAME(m_channel));
	1178	save_item(NAME(m_audio_channel));
	1179	save_item(NAME(m_audio_buffer));
	1180	save_item(NAME(m_x_buffer));
	1181	save_item(NAME(m_dma_control));
	1182	save_item(NAME(m_z_buffer));
	1183	save_item(NAME(m_interrupt_vector));
	1184	save_item(NAME(m_data_buffer));
1184	1185
1185		m_interrupt_timer = machine().scheduler().timer_alloc(FUNC(trigger_readback_int));
	1186	save_item(NAME(m_audio_sample_freq));
	1187	save_item(NAME(m_audio_sample_size));
	1188
	1189	m_interrupt_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(cdicdic_device::trigger_readback_int), this));
1186	1190	m_interrupt_timer->adjust(attotime::never);
1187	1191
1188		m_audio_sample_timer = machine().scheduler().timer_alloc(FUNC(audio_sample_trigger));
	1192	m_audio_sample_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(cdicdic_device::audio_sample_trigger), this));
1189	1193	m_audio_sample_timer->adjust(attotime::never);
1190	1194
1191	1195	m_ram = auto_alloc_array(machine(), UINT16, 0x3c00/2);
r20508	r20509
1197	1201
1198	1202	void cdicdic_device::device_reset()
1199	1203	{
1200		init();
	1204	cdi_state *state = machine().driver_data<cdi_state>();
1201	1205
1202		cdrom_image_device *cdrom_dev = machine().device<cdrom_image_device>("cdrom");
1203		if( cdrom_dev )
1204		{
1205		// MESS case (has CDROM device)
1206		m_cd = cdrom_dev->get_cdrom_file();
1207		cdda_set_cdrom(machine().device("cdda"), m_cd);
1208		}
1209		else
1210		{
1211		// MAME case
1212		m_cd = cdrom_open(get_disk_handle(machine(), ":cdrom"));
1213		cdda_set_cdrom(machine().device("cdda"), m_cd);
1214		}
1215		}
1216
1217		void cdicdic_device::init()
1218		{
1219	1206	m_command = 0;
1220	1207	m_time = 0;
1221	1208	m_file = 0;
r20508	r20509
1233	1220
1234	1221	m_decode_addr = 0;
1235	1222	m_decode_delay = 0;
1236		}
1237	1223
1238		void cdicdic_device::register_globals()
1239		{
1240		save_item(NAME(m_command));
1241		save_item(NAME(m_time));
1242		save_item(NAME(m_file));
1243		save_item(NAME(m_channel));
1244		save_item(NAME(m_audio_channel));
1245		save_item(NAME(m_audio_buffer));
1246		save_item(NAME(m_x_buffer));
1247		save_item(NAME(m_dma_control));
1248		save_item(NAME(m_z_buffer));
1249		save_item(NAME(m_interrupt_vector));
1250		save_item(NAME(m_data_buffer));
1251
1252		save_item(NAME(m_audio_sample_freq));
1253		save_item(NAME(m_audio_sample_size));
	1224	cdrom_image_device *cdrom_dev = machine().device<cdrom_image_device>("cdrom");
	1225	if( cdrom_dev )
	1226	{
	1227	// MESS case (has CDROM device)
	1228	m_cd = cdrom_dev->get_cdrom_file();
	1229	cdda_set_cdrom(state->m_cdda, m_cd);
	1230	}
	1231	else
	1232	{
	1233	// MAME case
	1234	m_cd = cdrom_open(get_disk_handle(machine(), ":cdrom"));
	1235	cdda_set_cdrom(state->m_cdda, m_cd);
	1236	}
1254	1237	}
1255	1238
1256		WRITE16_DEVICE_HANDLER( cdic_ram_w )
	1239	WRITE16_MEMBER( cdicdic_device::ram_w )
1257	1240	{
1258		downcast<cdicdic_device *>(device)->ram_write(offset, data, mem_mask);
1259		}
1260
1261		void cdicdic_device::ram_write(const UINT32 offset, const UINT16 data, const UINT16 mem_mask)
1262		{
1263		verboselog(machine(), 5, "cdic_ram_w: %08x = %04x & %04x\n", 0x00300000 + offset*2, data, mem_mask);
1264	1241	COMBINE_DATA(&m_ram[offset]);
1265	1242	}
1266	1243
1267		READ16_DEVICE_HANDLER( cdic_ram_r )
	1244	READ16_MEMBER( cdicdic_device::ram_r )
1268	1245	{
1269		return downcast<cdicdic_device *>(device)->ram_read(offset, mem_mask);
1270		}
1271
1272		UINT16 cdicdic_device::ram_read(const UINT32 offset, const UINT16 mem_mask)
1273		{
1274		verboselog(machine(), 5, "cdic_ram_r: %08x = %04x & %04x\n", 0x00300000 + offset * 2, m_ram[offset], mem_mask);
1275	1246	return m_ram[offset];
1276	1247	}

trunk/src/mame/machine/cdi070.c

r20508	r20509
1	1	/******************************************************************************
2	2
3	3
4		CD-i-specific SCC68070 SoC peripheral emulation
	4	CD-i-specific cdi68070 SoC peripheral emulation
5	5	-------------------
6	6
7	7	MESS implementation by Harmony
r20508	r20509
24	24	#include "machine/cdi070.h"
25	25	#include "includes/cdi.h"
26	26
	27	// device type definition
	28	const device_type MACHINE_CDI68070 = &device_creator<cdi68070_device>;
	29
27	30	#if ENABLE_VERBOSE_LOG
28	31	INLINE void verboselog(running_machine &machine, int n_level, const char *s_fmt, ...)
29	32	{
r20508	r20509
41	44	#define verboselog(x,y,z,...)
42	45	#endif
43	46
44		static UINT16 mcu_value = 0;
45		static UINT8 mcu_ack = 0;
	47	//**************************************************************************
	48	//  LIVE DEVICE
	49	//**************************************************************************
46	50
47		static void scc68070_set_timer_callback(scc68070_regs_t *scc68070, int channel)
	51	//-------------------------------------------------
	52	//  cdi68070_device - constructor
	53	//-------------------------------------------------
	54
	55	cdi68070_device::cdi68070_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	56	: device_t(mconfig, MACHINE_CDI68070, "CDI68070", tag, owner, clock)
48	57	{
49		UINT32 compare = 0;
50		attotime period;
	58	}
	59
	60	//-------------------------------------------------
	61	//  device_start - device-specific startup
	62	//-------------------------------------------------
	63
	64	void cdi68070_device::device_start()
	65	{
	66	save_item(NAME(m_lir));
	67
	68	save_item(NAME(m_picr1));
	69	save_item(NAME(m_picr2));
	70
	71	save_item(NAME(m_i2c.data_register));
	72	save_item(NAME(m_i2c.address_register));
	73	save_item(NAME(m_i2c.status_register));
	74	save_item(NAME(m_i2c.control_register));
	75	save_item(NAME(m_i2c.clock_control_register));
	76
	77	save_item(NAME(m_uart.mode_register));
	78	save_item(NAME(m_uart.status_register));
	79	save_item(NAME(m_uart.clock_select));
	80	save_item(NAME(m_uart.command_register));
	81	save_item(NAME(m_uart.transmit_holding_register));
	82	save_item(NAME(m_uart.receive_holding_register));
	83
	84	save_item(NAME(m_timers.timer_status_register));
	85	save_item(NAME(m_timers.timer_control_register));
	86	save_item(NAME(m_timers.reload_register));
	87	save_item(NAME(m_timers.timer0));
	88	save_item(NAME(m_timers.timer1));
	89	save_item(NAME(m_timers.timer2));
	90
	91	save_item(NAME(m_dma.channel[0].channel_status));
	92	save_item(NAME(m_dma.channel[0].channel_error));
	93	save_item(NAME(m_dma.channel[0].device_control));
	94	save_item(NAME(m_dma.channel[0].operation_control));
	95	save_item(NAME(m_dma.channel[0].sequence_control));
	96	save_item(NAME(m_dma.channel[0].channel_control));
	97	save_item(NAME(m_dma.channel[0].transfer_counter));
	98	save_item(NAME(m_dma.channel[0].memory_address_counter));
	99	save_item(NAME(m_dma.channel[0].device_address_counter));
	100	save_item(NAME(m_dma.channel[1].channel_status));
	101	save_item(NAME(m_dma.channel[1].channel_error));
	102	save_item(NAME(m_dma.channel[1].device_control));
	103	save_item(NAME(m_dma.channel[1].operation_control));
	104	save_item(NAME(m_dma.channel[1].sequence_control));
	105	save_item(NAME(m_dma.channel[1].channel_control));
	106	save_item(NAME(m_dma.channel[1].transfer_counter));
	107	save_item(NAME(m_dma.channel[1].memory_address_counter));
	108	save_item(NAME(m_dma.channel[1].device_address_counter));
	109
	110	save_item(NAME(m_mmu.status));
	111	save_item(NAME(m_mmu.control));
	112	save_item(NAME(m_mmu.desc[0].attr));
	113	save_item(NAME(m_mmu.desc[0].length));
	114	save_item(NAME(m_mmu.desc[0].segment));
	115	save_item(NAME(m_mmu.desc[0].base));
	116	save_item(NAME(m_mmu.desc[1].attr));
	117	save_item(NAME(m_mmu.desc[1].length));
	118	save_item(NAME(m_mmu.desc[1].segment));
	119	save_item(NAME(m_mmu.desc[1].base));
	120	save_item(NAME(m_mmu.desc[2].attr));
	121	save_item(NAME(m_mmu.desc[2].length));
	122	save_item(NAME(m_mmu.desc[2].segment));
	123	save_item(NAME(m_mmu.desc[2].base));
	124	save_item(NAME(m_mmu.desc[3].attr));
	125	save_item(NAME(m_mmu.desc[3].length));
	126	save_item(NAME(m_mmu.desc[3].segment));
	127	save_item(NAME(m_mmu.desc[3].base));
	128	save_item(NAME(m_mmu.desc[4].attr));
	129	save_item(NAME(m_mmu.desc[4].length));
	130	save_item(NAME(m_mmu.desc[4].segment));
	131	save_item(NAME(m_mmu.desc[4].base));
	132	save_item(NAME(m_mmu.desc[5].attr));
	133	save_item(NAME(m_mmu.desc[5].length));
	134	save_item(NAME(m_mmu.desc[5].segment));
	135	save_item(NAME(m_mmu.desc[5].base));
	136	save_item(NAME(m_mmu.desc[6].attr));
	137	save_item(NAME(m_mmu.desc[6].length));
	138	save_item(NAME(m_mmu.desc[6].segment));
	139	save_item(NAME(m_mmu.desc[6].base));
	140	save_item(NAME(m_mmu.desc[7].attr));
	141	save_item(NAME(m_mmu.desc[7].length));
	142	save_item(NAME(m_mmu.desc[7].segment));
	143	save_item(NAME(m_mmu.desc[7].base));
	144
	145	m_timers.timer0_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(cdi68070_device::timer0_callback), this));
	146	m_timers.timer0_timer->adjust(attotime::never);
	147
	148	m_uart.rx_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(cdi68070_device::rx_callback), this));
	149	m_uart.rx_timer->adjust(attotime::never);
	150
	151	m_uart.tx_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(cdi68070_device::tx_callback), this));
	152	m_uart.tx_timer->adjust(attotime::never);
	153	}
	154
	155	//-------------------------------------------------
	156	//  device_reset - device-specific reset
	157	//-------------------------------------------------
	158
	159	void cdi68070_device::device_reset()
	160	{
	161	m_lir = 0;
	162
	163	m_picr1 = 0;
	164	m_picr2 = 0;
	165
	166	m_i2c.data_register = 0;
	167	m_i2c.address_register = 0;
	168	m_i2c.status_register = 0;
	169	m_i2c.control_register = 0;
	170	m_i2c.clock_control_register = 0;
	171
	172	m_uart.mode_register = 0;
	173	m_uart.status_register = USR_TXRDY;
	174	m_uart.clock_select = 0;
	175	m_uart.command_register = 0;
	176	m_uart.transmit_holding_register = 0;
	177	m_uart.receive_holding_register = 0;
	178	m_uart.receive_pointer = -1;
	179	m_uart.transmit_pointer = -1;
	180
	181	m_timers.timer_status_register = 0;
	182	m_timers.timer_control_register = 0;
	183	m_timers.reload_register = 0;
	184	m_timers.timer0 = 0;
	185	m_timers.timer1 = 0;
	186	m_timers.timer2 = 0;
	187
	188	for(int index = 0; index < 2; index++)
	189	{
	190	m_dma.channel[index].channel_status = 0;
	191	m_dma.channel[index].channel_error = 0;
	192	m_dma.channel[index].device_control = 0;
	193	m_dma.channel[index].operation_control = 0;
	194	m_dma.channel[index].sequence_control = 0;
	195	m_dma.channel[index].channel_control = 0;
	196	m_dma.channel[index].transfer_counter = 0;
	197	m_dma.channel[index].memory_address_counter = 0;
	198	m_dma.channel[index].device_address_counter = 0;
	199	}
	200
	201	m_mmu.status = 0;
	202	m_mmu.control = 0;
	203	for(int index = 0; index < 8; index++)
	204	{
	205	m_mmu.desc[index].attr = 0;
	206	m_mmu.desc[index].length = 0;
	207	m_mmu.desc[index].segment = 0;
	208	m_mmu.desc[index].base = 0;
	209	}
	210
	211	memset(m_seeds, 0, 10 * sizeof(UINT16));
	212	memset(m_state, 0, 8 * sizeof(UINT8));
	213	m_mcu_value = 0;
	214	m_mcu_ack = 0;
	215	}
	216
	217	void cdi68070_device::set_timer_callback(int channel)
	218	{
51	219	switch(channel)
52	220	{
53	221	case 0:
54		compare = 0x10000 - scc68070->timers.timer0;
55		period = attotime::from_hz(CLOCK_A/192) * compare;
56		scc68070->timers.timer0_timer->adjust(period);
	222	{
	223	UINT32 compare = 0x10000 - m_timers.timer0;
	224	attotime period = attotime::from_hz(CLOCK_A/192) * compare;
	225	m_timers.timer0_timer->adjust(period);
57	226	break;
	227	}
58	228	default:
59		fatalerror( "Unsupported timer channel to scc68070_set_timer_callback!\n" );
	229	{
	230	fatalerror( "Unsupported timer channel to set_timer_callback!\n" );
	231	}
60	232	}
61	233	}
62	234
63		void scc68070_set_quizard_mcu_ack(running_machine &machine, UINT8 ack)
	235	void cdi68070_device::set_quizard_mcu_ack(UINT8 ack)
64	236	{
65		mcu_ack = ack;
	237	m_mcu_ack = ack;
66	238	}
67	239
68		void scc68070_set_quizard_mcu_value(running_machine &machine, UINT16 value)
	240	void cdi68070_device::set_quizard_mcu_value(UINT16 value)
69	241	{
70		mcu_value = value;
	242	m_mcu_value = value;
71	243	}
72	244
73		TIMER_CALLBACK( scc68070_timer0_callback )
	245	TIMER_CALLBACK_MEMBER( cdi68070_device::timer0_callback )
74	246	{
75		cdi_state *state = machine.driver_data<cdi_state>();
76		scc68070_regs_t *scc68070 = &state->m_scc68070_regs;
	247	cdi_state *state = machine().driver_data<cdi_state>();
77	248
78		scc68070->timers.timer0 = scc68070->timers.reload_register;
79		scc68070->timers.timer_status_register |= TSR_OV0;
80		if(scc68070->picr1 & 7)
	249	m_timers.timer0 = m_timers.reload_register;
	250	m_timers.timer_status_register |= TSR_OV0;
	251	if(m_picr1 & 7)
81	252	{
82		UINT8 interrupt = scc68070->picr1 & 7;
83		scc68070->timers.timer_status_register |= TSR_OV0;
	253	UINT8 interrupt = m_picr1 & 7;
	254	m_timers.timer_status_register |= TSR_OV0;
84	255	if(interrupt)
85	256	{
86		machine.device("maincpu")->execute().set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
87		machine.device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
	257	state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
	258	state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
88	259	}
89	260	}
90	261
91		scc68070_set_timer_callback(&state->m_scc68070_regs, 0);
	262	set_timer_callback(0);
92	263	}
93	264
94		static void scc68070_uart_rx_check(running_machine &machine, scc68070_regs_t *scc68070)
	265	void cdi68070_device::uart_rx_check()
95	266	{
96		if((scc68070->uart.command_register & 3) == 1)
	267	if((m_uart.command_register & 3) == 1)
97	268	{
98		UINT32 div = 0x10000 >> ((scc68070->uart.clock_select >> 4) & 7);
99		scc68070->uart.rx_timer->adjust(attotime::from_hz((49152000 / div) / 8));
	269	UINT32 div = 0x10000 >> ((m_uart.clock_select >> 4) & 7);
	270	m_uart.rx_timer->adjust(attotime::from_hz((49152000 / div) / 8));
100	271	}
101	272	else
102	273	{
103		scc68070->uart.status_register &= ~USR_RXRDY;
104		scc68070->uart.rx_timer->adjust(attotime::never);
	274	m_uart.status_register &= ~USR_RXRDY;
	275	m_uart.rx_timer->adjust(attotime::never);
105	276	}
106	277	}
107	278
108		static void scc68070_uart_tx_check(running_machine &machine, scc68070_regs_t *scc68070)
	279	void cdi68070_device::uart_tx_check()
109	280	{
110		if(((scc68070->uart.command_register >> 2) & 3) == 1)
	281	if(((m_uart.command_register >> 2) & 3) == 1)
111	282	{
112		if(scc68070->uart.transmit_pointer >= 0)
	283	if(m_uart.transmit_pointer >= 0)
113	284	{
114		scc68070->uart.status_register &= ~USR_TXRDY;
	285	m_uart.status_register &= ~USR_TXRDY;
115	286	}
116	287	else
117	288	{
118		scc68070->uart.status_register |= USR_TXRDY;
	289	m_uart.status_register |= USR_TXRDY;
119	290	}
120	291
121		if(scc68070->uart.tx_timer->remaining() == attotime::never)
	292	if(m_uart.tx_timer->remaining() == attotime::never)
122	293	{
123		UINT32 div = 0x10000 >> (scc68070->uart.clock_select & 7);
124		scc68070->uart.tx_timer->adjust(attotime::from_hz((49152000 / div) / 8));
	294	UINT32 div = 0x10000 >> (m_uart.clock_select & 7);
	295	m_uart.tx_timer->adjust(attotime::from_hz((49152000 / div) / 8));
125	296	}
126	297	}
127	298	else
128	299	{
129		scc68070->uart.tx_timer->adjust(attotime::never);
	300	m_uart.tx_timer->adjust(attotime::never);
130	301	}
131	302	}
132	303
133		void scc68070_uart_rx(running_machine &machine, scc68070_regs_t *scc68070, UINT8 data)
	304	void cdi68070_device::uart_rx(UINT8 data)
134	305	{
135		//printf("%d: %02x\n", scc68070->uart.receive_pointer + 1, data);
136		scc68070->uart.receive_pointer++;
137		scc68070->uart.receive_buffer[scc68070->uart.receive_pointer] = data;
138		scc68070_uart_rx_check(machine, scc68070);
	306	m_uart.receive_pointer++;
	307	m_uart.receive_buffer[m_uart.receive_pointer] = data;
	308	uart_rx_check();
139	309	}
140	310
141		void scc68070_uart_tx(running_machine &machine, scc68070_regs_t *scc68070, UINT8 data)
	311	void cdi68070_device::uart_tx(UINT8 data)
142	312	{
143		scc68070->uart.transmit_pointer++;
144		scc68070->uart.transmit_buffer[scc68070->uart.transmit_pointer] = data;
145		scc68070_uart_tx_check(machine, scc68070);
	313	m_uart.transmit_pointer++;
	314	m_uart.transmit_buffer[m_uart.transmit_pointer] = data;
	315	uart_tx_check();
146	316	}
147	317
148		TIMER_CALLBACK( scc68070_rx_callback )
	318	TIMER_CALLBACK_MEMBER( cdi68070_device::rx_callback )
149	319	{
150		cdi_state *state = machine.driver_data<cdi_state>();
151		scc68070_regs_t *scc68070 = &state->m_scc68070_regs;
	320	cdi_state *state = machine().driver_data<cdi_state>();
152	321
153		if((scc68070->uart.command_register & 3) == 1)
	322	if((m_uart.command_register & 3) == 1)
154	323	{
155		if(scc68070->uart.receive_pointer >= 0)
	324	if(m_uart.receive_pointer >= 0)
156	325	{
157		scc68070->uart.status_register |= USR_RXRDY;
	326	m_uart.status_register |= USR_RXRDY;
158	327	}
159	328	else
160	329	{
161		scc68070->uart.status_register &= ~USR_RXRDY;
	330	m_uart.status_register &= ~USR_RXRDY;
162	331	}
163	332
164		scc68070->uart.receive_holding_register = scc68070->uart.receive_buffer[0];
	333	m_uart.receive_holding_register = m_uart.receive_buffer[0];
165	334
166		if(scc68070->uart.receive_pointer > -1)
	335	if(m_uart.receive_pointer > -1)
167	336	{
168		verboselog(machine, 2, "scc68070_rx_callback: Receiving %02x\n", scc68070->uart.receive_holding_register);
	337	verboselog(machine(), 2, "scc68070_rx_callback: Receiving %02x\n", m_uart.receive_holding_register);
169	338
170		UINT8 interrupt = (scc68070->picr2 >> 4) & 7;
	339	UINT8 interrupt = (m_picr2 >> 4) & 7;
171	340	if(interrupt)
172	341	{
173		machine.device("maincpu")->execute().set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
174		machine.device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
	342	state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
	343	state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
175	344	}
176	345
177		scc68070->uart.status_register |= USR_RXRDY;
178		UINT32 div = 0x10000 >> ((scc68070->uart.clock_select >> 4) & 7);
179		scc68070->uart.rx_timer->adjust(attotime::from_hz((49152000 / div) / 8));
	346	m_uart.status_register |= USR_RXRDY;
	347	UINT32 div = 0x10000 >> ((m_uart.clock_select >> 4) & 7);
	348	m_uart.rx_timer->adjust(attotime::from_hz((49152000 / div) / 8));
180	349	}
181	350	else
182	351	{
183		scc68070->uart.status_register &= ~USR_RXRDY;
	352	m_uart.status_register &= ~USR_RXRDY;
184	353	}
185	354	}
186	355	else
187	356	{
188		scc68070->uart.status_register &= ~USR_RXRDY;
	357	m_uart.status_register &= ~USR_RXRDY;
189	358	}
190	359
191		scc68070_uart_rx_check(machine, scc68070);
	360	uart_rx_check();
192	361	}
193	362
194		static UINT16 seeds[10] = { 0 };
195		static UINT8 g_state[8] = { 0 };
196
197		void scc68070_quizard_rx(running_machine &machine, scc68070_regs_t *scc68070, UINT8 data)
	363	void cdi68070_device::quizard_rx(UINT8 data)
198	364	{
199		scc68070_uart_rx(machine, scc68070, 0x5a);
200		scc68070_uart_rx(machine, scc68070, data);
	365	uart_rx(0x5a);
	366	uart_rx(data);
201	367	}
202	368
203		static void quizard_set_seeds(UINT8 *rx)
	369	void cdi68070_device::quizard_set_seeds(UINT8 *rx)
204	370	{
205		seeds[0] = (rx[1] << 8) | rx[0];
206		seeds[1] = (rx[3] << 8) | rx[2];
207		seeds[2] = (rx[5] << 8) | rx[4];
208		seeds[3] = (rx[7] << 8) | rx[6];
209		seeds[4] = (rx[9] << 8) | rx[8];
210		seeds[5] = (rx[11] << 8) | rx[10];
211		seeds[6] = (rx[13] << 8) | rx[12];
212		seeds[7] = (rx[15] << 8) | rx[14];
213		seeds[8] = (rx[17] << 8) | rx[16];
214		seeds[9] = (rx[19] << 8) | rx[18];
	371	m_seeds[0] = (rx[1] << 8) | rx[0];
	372	m_seeds[1] = (rx[3] << 8) | rx[2];
	373	m_seeds[2] = (rx[5] << 8) | rx[4];
	374	m_seeds[3] = (rx[7] << 8) | rx[6];
	375	m_seeds[4] = (rx[9] << 8) | rx[8];
	376	m_seeds[5] = (rx[11] << 8) | rx[10];
	377	m_seeds[6] = (rx[13] << 8) | rx[12];
	378	m_seeds[7] = (rx[15] << 8) | rx[14];
	379	m_seeds[8] = (rx[17] << 8) | rx[16];
	380	m_seeds[9] = (rx[19] << 8) | rx[18];
215	381	}
216	382
217		static void quizard_calculate_state(running_machine &machine, scc68070_regs_t *scc68070)
	383	void cdi68070_device::quizard_calculate_state()
218	384	{
219	385	//const UINT16 desired_bitfield = mcu_value;
220	386	const UINT16 field0 = 0x00ff;
221		const UINT16 field1 = mcu_value ^ 0x00ff;
	387	const UINT16 field1 = m_mcu_value ^ 0x00ff;
222	388
223	389	UINT16 total0 = 0;
224	390	UINT16 total1 = 0;
r20508	r20509
227	393	{
228	394	if(field0 & (1 << index))
229	395	{
230		total0 += seeds[index];
	396	total0 += m_seeds[index];
231	397	}
232	398	if(field1 & (1 << index))
233	399	{
234		total1 += seeds[index];
	400	total1 += m_seeds[index];
235	401	}
236	402	}
237	403
238	404	UINT16 hi0 = (total0 >> 8) + 0x40;
239		g_state[2] = hi0 / 2;
240		g_state[3] = hi0 - g_state[2];
	405	m_state[2] = hi0 / 2;
	406	m_state[3] = hi0 - m_state[2];
241	407
242	408	UINT16 lo0 = (total0 & 0x00ff) + 0x40;
243		g_state[0] = lo0 / 2;
244		g_state[1] = lo0 - g_state[0];
	409	m_state[0] = lo0 / 2;
	410	m_state[1] = lo0 - m_state[0];
245	411
246	412	UINT16 hi1 = (total1 >> 8) + 0x40;
247		g_state[6] = hi1 / 2;
248		g_state[7] = hi1 - g_state[6];
	413	m_state[6] = hi1 / 2;
	414	m_state[7] = hi1 - m_state[6];
249	415
250	416	UINT16 lo1 = (total1 & 0x00ff) + 0x40;
251		g_state[4] = lo1 / 2;
252		g_state[5] = lo1 - g_state[4];
	417	m_state[4] = lo1 / 2;
	418	m_state[5] = lo1 - m_state[4];
253	419	}
254	420
255		INTERRUPT_GEN( scc68070_mcu_frame )
	421	void cdi68070_device::mcu_frame()
256	422	{
257		cdi_state *state = device->machine().driver_data<cdi_state>();
258		scc68070_regs_t *scc68070 = &state->m_scc68070_regs;
259
260	423	if(0)//mcu_active)
261	424	{
262		quizard_calculate_state(device->machine(), scc68070);
263		scc68070_uart_rx(device->machine(), scc68070, 0x5a);
	425	quizard_calculate_state();
	426	uart_rx(0x5a);
264	427	for(int index = 0; index < 8; index++)
265	428	{
266		scc68070_uart_rx(device->machine(), scc68070, g_state[index]);
	429	uart_rx(m_state[index]);
267	430	}
268	431	}
269	432	}
270	433
271		static void quizard_handle_byte_tx(running_machine &machine, scc68070_regs_t *scc68070)
	434	void cdi68070_device::quizard_handle_byte_tx()
272	435	{
273	436	static int state = 0;
274	437	static UINT8 rx[0x100];
275	438	static UINT8 rx_ptr = 0xff;
276		UINT8 tx = scc68070->uart.transmit_holding_register;
	439	UINT8 tx = m_uart.transmit_holding_register;
277	440
278		//printf("%02x ", tx );
279		if((tx >= 0x20 && tx < 0x7f) || tx == 0x0d || tx == 0x0a)
280		{
281		//printf("%c ", tx);
282		}
283		//printf("\n");
284
285	441	switch(state)
286	442	{
287	443	case 0: // Waiting for a leadoff byte
288		if(tx == mcu_ack) // Sequence end
	444	if(tx == m_mcu_ack) // Sequence end
289	445	{
290	446	//scc68070_uart_rx(machine, scc68070, 0x5a);
291	447	//scc68070_uart_rx(machine, scc68070, 0x42);
r20508	r20509
319	475	{
320	476	//printf("Calculating seeds\n");
321	477	quizard_set_seeds(rx);
322		quizard_calculate_state(machine, scc68070);
	478	quizard_calculate_state();
323	479	state = 2;
324	480	}
325	481	break;
326	482
327	483	case 2: // Receiving the seed acknowledge
328	484	case 4:
329		if(tx == mcu_ack)
	485	if(tx == m_mcu_ack)
330	486	{
331	487	if(state == 2)
332	488	{
r20508	r20509
337	493	state = 0;
338	494	}
339	495	//printf("Sending seed ack\n");
340		scc68070_uart_rx(machine, scc68070, 0x5a);
341		scc68070_uart_rx(machine, scc68070, g_state[0]);
342		scc68070_uart_rx(machine, scc68070, g_state[1]);
343		scc68070_uart_rx(machine, scc68070, g_state[2]);
344		scc68070_uart_rx(machine, scc68070, g_state[3]);
345		scc68070_uart_rx(machine, scc68070, g_state[4]);
346		scc68070_uart_rx(machine, scc68070, g_state[5]);
347		scc68070_uart_rx(machine, scc68070, g_state[6]);
348		scc68070_uart_rx(machine, scc68070, g_state[7]);
	496	uart_rx(0x5a);
	497	uart_rx(m_state[0]);
	498	uart_rx(m_state[1]);
	499	uart_rx(m_state[2]);
	500	uart_rx(m_state[3]);
	501	uart_rx(m_state[4]);
	502	uart_rx(m_state[5]);
	503	uart_rx(m_state[6]);
	504	uart_rx(m_state[7]);
349	505	}
350	506	break;
351	507
r20508	r20509
371	527	}
372	528	}
373	529
374		TIMER_CALLBACK( scc68070_tx_callback )
	530	TIMER_CALLBACK_MEMBER( cdi68070_device::tx_callback )
375	531	{
376		cdi_state *state = machine.driver_data<cdi_state>();
377		scc68070_regs_t *scc68070 = &state->m_scc68070_regs;
	532	cdi_state *state = machine().driver_data<cdi_state>();
378	533
379		if(((scc68070->uart.command_register >> 2) & 3) == 1)
	534	if(((m_uart.command_register >> 2) & 3) == 1)
380	535	{
381		UINT8 interrupt = scc68070->picr2 & 7;
	536	UINT8 interrupt = m_picr2 & 7;
382	537	if(interrupt)
383	538	{
384		machine.device("maincpu")->execute().set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
385		machine.device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
	539	state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
	540	state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
386	541	}
387	542
388		if(scc68070->uart.transmit_pointer > -1)
	543	if(m_uart.transmit_pointer > -1)
389	544	{
390		scc68070->uart.transmit_holding_register = scc68070->uart.transmit_buffer[0];
391		quizard_handle_byte_tx(machine, scc68070);
	545	m_uart.transmit_holding_register = m_uart.transmit_buffer[0];
	546	quizard_handle_byte_tx();
392	547
393		verboselog(machine, 2, "scc68070_tx_callback: Transmitting %02x\n", scc68070->uart.transmit_holding_register);
394		for(int index = 0; index < scc68070->uart.transmit_pointer; index++)
	548	verboselog(machine(), 2, "cdi68070_tx_callback: Transmitting %02x\n", m_uart.transmit_holding_register);
	549	for(int index = 0; index < m_uart.transmit_pointer; index++)
395	550	{
396		scc68070->uart.transmit_buffer[index] = scc68070->uart.transmit_buffer[index+1];
	551	m_uart.transmit_buffer[index] = m_uart.transmit_buffer[index+1];
397	552	}
398		scc68070->uart.transmit_pointer--;
	553	m_uart.transmit_pointer--;
399	554
400		UINT32 div = 0x10000 >> (scc68070->uart.clock_select & 7);
401		scc68070->uart.tx_timer->adjust(attotime::from_hz((49152000 / div) / 8));
	555	UINT32 div = 0x10000 >> (m_uart.clock_select & 7);
	556	m_uart.tx_timer->adjust(attotime::from_hz((49152000 / div) / 8));
402	557	}
403	558	else
404	559	{
405		scc68070->uart.tx_timer->adjust(attotime::never);
	560	m_uart.tx_timer->adjust(attotime::never);
406	561	}
407	562	}
408	563	else
409	564	{
410		scc68070->uart.tx_timer->adjust(attotime::never);
	565	m_uart.tx_timer->adjust(attotime::never);
411	566	}
412	567
413		scc68070_uart_tx_check(machine, scc68070);
	568	uart_tx_check();
414	569	}
415	570
416		READ16_HANDLER( scc68070_periphs_r )
	571	READ16_MEMBER( cdi68070_device::periphs_r )
417	572	{
418		cdi_state *state = space.machine().driver_data<cdi_state>();
419		scc68070_regs_t *scc68070 = &state->m_scc68070_regs;
	573	cdi_state *state = machine().driver_data<cdi_state>();
420	574
421	575	switch(offset)
422	576	{
423	577	// Interrupts: 80001001
424	578	case 0x1000/2: // LIR priority level
425		return scc68070->lir;
	579	return m_lir;
426	580
427	581	// I2C interface: 80002001 to 80002009
428	582	case 0x2000/2:
429	583	if(ACCESSING_BITS_0_7)
430	584	{
431		verboselog(space.machine(), 2, "scc68070_periphs_w: I2C Data Register: %04x & %04x\n", scc68070->i2c.data_register, mem_mask);
	585	verboselog(machine(), 2, "cdi68070_periphs_w: I2C Data Register: %04x & %04x\n", m_i2c.data_register, mem_mask);
432	586	}
433		return scc68070->i2c.data_register;
	587	return m_i2c.data_register;
434	588	case 0x2002/2:
435	589	if(ACCESSING_BITS_0_7)
436	590	{
437		verboselog(space.machine(), 2, "scc68070_periphs_w: I2C Address Register: %04x & %04x\n", scc68070->i2c.address_register, mem_mask);
	591	verboselog(machine(), 2, "cdi68070_periphs_w: I2C Address Register: %04x & %04x\n", m_i2c.address_register, mem_mask);
438	592	}
439		return scc68070->i2c.address_register;
	593	return m_i2c.address_register;
440	594	case 0x2004/2:
441	595	if(ACCESSING_BITS_0_7)
442	596	{
443		verboselog(space.machine(), 2, "scc68070_periphs_w: I2C Status Register: %04x & %04x\n", scc68070->i2c.status_register, mem_mask);
	597	verboselog(machine(), 2, "cdi68070_periphs_w: I2C Status Register: %04x & %04x\n", m_i2c.status_register, mem_mask);
444	598	}
445		return scc68070->i2c.status_register;
	599	return m_i2c.status_register;
446	600	case 0x2006/2:
447	601	if(ACCESSING_BITS_0_7)
448	602	{
449		verboselog(space.machine(), 2, "scc68070_periphs_w: I2C Control Register: %04x & %04x\n", scc68070->i2c.control_register, mem_mask);
	603	verboselog(machine(), 2, "cdi68070_periphs_w: I2C Control Register: %04x & %04x\n", m_i2c.control_register, mem_mask);
450	604	}
451		return scc68070->i2c.control_register;
	605	return m_i2c.control_register;
452	606	case 0x2008/2:
453	607	if(ACCESSING_BITS_0_7)
454	608	{
455		verboselog(space.machine(), 2, "scc68070_periphs_w: I2C Clock Control Register: %04x & %04x\n", scc68070->i2c.clock_control_register, mem_mask);
	609	verboselog(machine(), 2, "cdi68070_periphs_w: I2C Clock Control Register: %04x & %04x\n", m_i2c.clock_control_register, mem_mask);
456	610	}
457		return scc68070->i2c.clock_control_register;
	611	return m_i2c.clock_control_register;
458	612
459	613	// UART interface: 80002011 to 8000201b
460	614	case 0x2010/2:
461	615	if(ACCESSING_BITS_0_7)
462	616	{
463		verboselog(space.machine(), 2, "scc68070_periphs_r: UART Mode Register: %04x & %04x\n", scc68070->uart.mode_register, mem_mask);
	617	verboselog(machine(), 2, "cdi68070_periphs_r: UART Mode Register: %04x & %04x\n", m_uart.mode_register, mem_mask);
464	618	}
465	619	else
466	620	{
467		verboselog(space.machine(), 0, "scc68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
	621	verboselog(machine(), 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
468	622	}
469		return scc68070->uart.mode_register | 0x20;
	623	return m_uart.mode_register | 0x20;
470	624	case 0x2012/2:
471		scc68070->uart.status_register |= (1 << 1);
	625	m_uart.status_register |= (1 << 1);
472	626	if(ACCESSING_BITS_0_7)
473	627	{
474		verboselog(space.machine(), 2, "scc68070_periphs_r: UART Status Register: %04x & %04x\n", scc68070->uart.status_register, mem_mask);
	628	verboselog(machine(), 2, "cdi68070_periphs_r: UART Status Register: %04x & %04x\n", m_uart.status_register, mem_mask);
475	629	}
476	630	else
477	631	{
478		verboselog(space.machine(), 0, "scc68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
	632	verboselog(space.machine(), 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
479	633	}
480	634
481		if((scc68070->picr2 >> 4) & 7)
	635	if((m_picr2 >> 4) & 7)
482	636	{
483		space.machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (((scc68070->picr2 >> 4) & 7) - 1), ASSERT_LINE);
	637	state->m_maincpu->set_input_line(M68K_IRQ_1 + (((m_picr2 >> 4) & 7) - 1), ASSERT_LINE);
484	638	}
485	639
486		if(scc68070->picr2 & 7)
	640	if(m_picr2 & 7)
487	641	{
488		space.machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1 + ((scc68070->picr2 & 7) - 1), ASSERT_LINE);
	642	state->m_maincpu->set_input_line(M68K_IRQ_1 + ((m_picr2 & 7) - 1), ASSERT_LINE);
489	643	}
490	644
491		return scc68070->uart.status_register;
	645	return m_uart.status_register;
492	646
493	647	case 0x2014/2:
494	648	if(ACCESSING_BITS_0_7)
495	649	{
496		verboselog(space.machine(), 2, "scc68070_periphs_r: UART Clock Select: %04x & %04x\n", scc68070->uart.clock_select, mem_mask);
	650	verboselog(machine(), 2, "cdi68070_periphs_r: UART Clock Select: %04x & %04x\n", m_uart.clock_select, mem_mask);
497	651	}
498	652	else
499	653	{
500		verboselog(space.machine(), 0, "scc68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
	654	verboselog(machine(), 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
501	655	}
502		return scc68070->uart.clock_select | 0x08;
	656	return m_uart.clock_select | 0x08;
503	657	case 0x2016/2:
504	658	if(ACCESSING_BITS_0_7)
505	659	{
506		verboselog(space.machine(), 2, "scc68070_periphs_r: UART Command Register: %02x & %04x\n", scc68070->uart.command_register, mem_mask);
	660	verboselog(machine(), 2, "cdi68070_periphs_r: UART Command Register: %02x & %04x\n", m_uart.command_register, mem_mask);
507	661	}
508	662	else
509	663	{
510		verboselog(space.machine(), 0, "scc68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
	664	verboselog(machine(), 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
511	665	}
512		return scc68070->uart.command_register | 0x80;
	666	return m_uart.command_register | 0x80;
513	667	case 0x2018/2:
514	668	if(ACCESSING_BITS_0_7)
515	669	{
516		verboselog(space.machine(), 2, "scc68070_periphs_r: UART Transmit Holding Register: %02x & %04x\n", scc68070->uart.transmit_holding_register, mem_mask);
	670	verboselog(machine(), 2, "cdi68070_periphs_r: UART Transmit Holding Register: %02x & %04x\n", m_uart.transmit_holding_register, mem_mask);
517	671	}
518	672	else
519	673	{
520		verboselog(space.machine(), 0, "scc68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
	674	verboselog(machine(), 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
521	675	}
522		return scc68070->uart.transmit_holding_register;
	676	return m_uart.transmit_holding_register;
523	677	case 0x201a/2:
524	678	if(ACCESSING_BITS_0_7)
525	679	{
526		verboselog(space.machine(), 2, "scc68070_periphs_r: UART Receive Holding Register: %02x & %04x\n", scc68070->uart.receive_holding_register, mem_mask);
	680	verboselog(machine(), 2, "cdi68070_periphs_r: UART Receive Holding Register: %02x & %04x\n", m_uart.receive_holding_register, mem_mask);
527	681	}
528	682	else
529	683	{
530		verboselog(space.machine(), 0, "scc68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
	684	verboselog(machine(), 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
531	685	}
532		if((scc68070->picr2 >> 4) & 7)
	686	if((m_picr2 >> 4) & 7)
533	687	{
534		space.machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (((scc68070->picr2 >> 4) & 7) - 1), CLEAR_LINE);
	688	state->m_maincpu->set_input_line(M68K_IRQ_1 + (((m_picr2 >> 4) & 7) - 1), CLEAR_LINE);
535	689	}
536	690
537		scc68070->uart.receive_holding_register = scc68070->uart.receive_buffer[0];
538		if(scc68070->uart.receive_pointer >= 0)
	691	m_uart.receive_holding_register = m_uart.receive_buffer[0];
	692	if(m_uart.receive_pointer >= 0)
539	693	{
540		for(int index = 0; index < scc68070->uart.receive_pointer; index++)
	694	for(int index = 0; index < m_uart.receive_pointer; index++)
541	695	{
542		scc68070->uart.receive_buffer[index] = scc68070->uart.receive_buffer[index + 1];
	696	m_uart.receive_buffer[index] = m_uart.receive_buffer[index + 1];
543	697	}
544		scc68070->uart.receive_pointer--;
	698	m_uart.receive_pointer--;
545	699	}
546		//printf("R: %02x\n", scc68070->uart.receive_holding_register);
547		return scc68070->uart.receive_holding_register;
	700	//printf("R: %02x\n", m_uart.receive_holding_register);
	701	return m_uart.receive_holding_register;
548	702
549	703	// Timers: 80002020 to 80002029
550	704	case 0x2020/2:
551	705	if(ACCESSING_BITS_0_7)
552	706	{
553		verboselog(space.machine(), 2, "scc68070_periphs_r: Timer Control Register: %02x & %04x\n", scc68070->timers.timer_control_register, mem_mask);
	707	verboselog(machine(), 2, "cdi68070_periphs_r: Timer Control Register: %02x & %04x\n", m_timers.timer_control_register, mem_mask);
554	708	}
555	709	if(ACCESSING_BITS_8_15)
556	710	{
557		verboselog(space.machine(), 12, "scc68070_periphs_r: Timer Status Register: %02x & %04x\n", scc68070->timers.timer_status_register, mem_mask);
	711	verboselog(machine(), 12, "cdi68070_periphs_r: Timer Status Register: %02x & %04x\n", m_timers.timer_status_register, mem_mask);
558	712	}
559		return (scc68070->timers.timer_status_register << 8) | scc68070->timers.timer_control_register;
	713	return (m_timers.timer_status_register << 8) | m_timers.timer_control_register;
560	714	case 0x2022/2:
561		verboselog(space.machine(), 2, "scc68070_periphs_r: Timer Reload Register: %04x & %04x\n", scc68070->timers.reload_register, mem_mask);
562		return scc68070->timers.reload_register;
	715	verboselog(machine(), 2, "cdi68070_periphs_r: Timer Reload Register: %04x & %04x\n", m_timers.reload_register, mem_mask);
	716	return m_timers.reload_register;
563	717	case 0x2024/2:
564		verboselog(space.machine(), 2, "scc68070_periphs_r: Timer 0: %04x & %04x\n", scc68070->timers.timer0, mem_mask);
565		return scc68070->timers.timer0;
	718	verboselog(machine(), 2, "cdi68070_periphs_r: Timer 0: %04x & %04x\n", m_timers.timer0, mem_mask);
	719	return m_timers.timer0;
566	720	case 0x2026/2:
567		verboselog(space.machine(), 2, "scc68070_periphs_r: Timer 1: %04x & %04x\n", scc68070->timers.timer1, mem_mask);
568		return scc68070->timers.timer1;
	721	verboselog(machine(), 2, "cdi68070_periphs_r: Timer 1: %04x & %04x\n", m_timers.timer1, mem_mask);
	722	return m_timers.timer1;
569	723	case 0x2028/2:
570		verboselog(space.machine(), 2, "scc68070_periphs_r: Timer 2: %04x & %04x\n", scc68070->timers.timer2, mem_mask);
571		return scc68070->timers.timer2;
	724	verboselog(machine(), 2, "cdi68070_periphs_r: Timer 2: %04x & %04x\n", m_timers.timer2, mem_mask);
	725	return m_timers.timer2;
572	726
573	727	// PICR1: 80002045
574	728	case 0x2044/2:
575	729	if(ACCESSING_BITS_0_7)
576	730	{
577		verboselog(space.machine(), 2, "scc68070_periphs_r: Peripheral Interrupt Control Register 1: %02x & %04x\n", scc68070->picr1, mem_mask);
	731	verboselog(machine(), 2, "cdi68070_periphs_r: Peripheral Interrupt Control Register 1: %02x & %04x\n", m_picr1, mem_mask);
578	732	}
579		return scc68070->picr1;
	733	return m_picr1;
580	734
581	735	// PICR2: 80002047
582	736	case 0x2046/2:
583	737	if(ACCESSING_BITS_0_7)
584	738	{
585		verboselog(space.machine(), 2, "scc68070_periphs_r: Peripheral Interrupt Control Register 2: %02x & %04x\n", scc68070->picr2, mem_mask);
	739	verboselog(machine(), 2, "cdi68070_periphs_r: Peripheral Interrupt Control Register 2: %02x & %04x\n", m_picr2, mem_mask);
586	740	}
587		return scc68070->picr2 & 0x77;
	741	return m_picr2 & 0x77;
588	742
589	743	// DMA controller: 80004000 to 8000406d
590	744	case 0x4000/2:
591	745	case 0x4040/2:
592	746	if(ACCESSING_BITS_0_7)
593	747	{
594		verboselog(space.machine(), 2, "scc68070_periphs_r: DMA(%d) Error Register: %04x & %04x\n", (offset - 0x2000) / 32, scc68070->dma.channel[(offset - 0x2000) / 32].channel_error, mem_mask);
	748	verboselog(machine(), 2, "cdi68070_periphs_r: DMA(%d) Error Register: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_error, mem_mask);
595	749	}
596	750	if(ACCESSING_BITS_8_15)
597	751	{
598		verboselog(space.machine(), 2, "scc68070_periphs_r: DMA(%d) Status Register: %04x & %04x\n", (offset - 0x2000) / 32, scc68070->dma.channel[(offset - 0x2000) / 32].channel_status, mem_mask);
	752	verboselog(machine(), 2, "cdi68070_periphs_r: DMA(%d) Status Register: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_status, mem_mask);
599	753	}
600		return (scc68070->dma.channel[(offset - 0x2000) / 32].channel_status << 8) | scc68070->dma.channel[(offset - 0x2000) / 32].channel_error;
	754	return (m_dma.channel[(offset - 0x2000) / 32].channel_status << 8) | m_dma.channel[(offset - 0x2000) / 32].channel_error;
601	755	case 0x4004/2:
602	756	case 0x4044/2:
603	757	if(ACCESSING_BITS_0_7)
604	758	{
605		verboselog(space.machine(), 2, "scc68070_periphs_r: DMA(%d) Operation Control Register: %02x & %04x\n", (offset - 0x2000) / 32, scc68070->dma.channel[(offset - 0x2000) / 32].operation_control, mem_mask);
	759	verboselog(machine(), 2, "cdi68070_periphs_r: DMA(%d) Operation Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].operation_control, mem_mask);
606	760	}
607	761	if(ACCESSING_BITS_8_15)
608	762	{
609		verboselog(space.machine(), 2, "scc68070_periphs_r: DMA(%d) Device Control Register: %02x & %04x\n", (offset - 0x2000) / 32, scc68070->dma.channel[(offset - 0x2000) / 32].device_control, mem_mask);
	763	verboselog(machine(), 2, "cdi68070_periphs_r: DMA(%d) Device Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].device_control, mem_mask);
610	764	}
611		return (scc68070->dma.channel[(offset - 0x2000) / 32].device_control << 8) | scc68070->dma.channel[(offset - 0x2000) / 32].operation_control;
	765	return (m_dma.channel[(offset - 0x2000) / 32].device_control << 8) | m_dma.channel[(offset - 0x2000) / 32].operation_control;
612	766	case 0x4006/2:
613	767	case 0x4046/2:
614	768	if(ACCESSING_BITS_0_7)
615	769	{
616		verboselog(space.machine(), 2, "scc68070_periphs_r: DMA(%d) Channel Control Register: %02x & %04x\n", (offset - 0x2000) / 32, scc68070->dma.channel[(offset - 0x2000) / 32].channel_control, mem_mask);
	770	verboselog(machine(), 2, "cdi68070_periphs_r: DMA(%d) Channel Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_control, mem_mask);
617	771	}
618	772	if(ACCESSING_BITS_8_15)
619	773	{
620		verboselog(space.machine(), 2, "scc68070_periphs_r: DMA(%d) Sequence Control Register: %02x & %04x\n", (offset - 0x2000) / 32, scc68070->dma.channel[(offset - 0x2000) / 32].sequence_control, mem_mask);
	774	verboselog(machine(), 2, "cdi68070_periphs_r: DMA(%d) Sequence Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].sequence_control, mem_mask);
621	775	}
622		return (scc68070->dma.channel[(offset - 0x2000) / 32].sequence_control << 8) | scc68070->dma.channel[(offset - 0x2000) / 32].channel_control;
	776	return (m_dma.channel[(offset - 0x2000) / 32].sequence_control << 8) | m_dma.channel[(offset - 0x2000) / 32].channel_control;
623	777	case 0x400a/2:
624		verboselog(space.machine(), 2, "scc68070_periphs_r: DMA(%d) Memory Transfer Counter: %04x & %04x\n", (offset - 0x2000) / 32, scc68070->dma.channel[(offset - 0x2000) / 32].transfer_counter, mem_mask);
625		return scc68070->dma.channel[(offset - 0x2000) / 32].transfer_counter;
	778	verboselog(machine(), 2, "cdi68070_periphs_r: DMA(%d) Memory Transfer Counter: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].transfer_counter, mem_mask);
	779	return m_dma.channel[(offset - 0x2000) / 32].transfer_counter;
626	780	case 0x400c/2:
627	781	case 0x404c/2:
628		verboselog(space.machine(), 2, "scc68070_periphs_r: DMA(%d) Memory Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, (scc68070->dma.channel[(offset - 0x2000) / 32].memory_address_counter >> 16), mem_mask);
629		return (scc68070->dma.channel[(offset - 0x2000) / 32].memory_address_counter >> 16);
	782	verboselog(machine(), 2, "cdi68070_periphs_r: DMA(%d) Memory Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, (m_dma.channel[(offset - 0x2000) / 32].memory_address_counter >> 16), mem_mask);
	783	return (m_dma.channel[(offset - 0x2000) / 32].memory_address_counter >> 16);
630	784	case 0x400e/2:
631	785	case 0x404e/2:
632		verboselog(space.machine(), 2, "scc68070_periphs_r: DMA(%d) Memory Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, scc68070->dma.channel[(offset - 0x2000) / 32].memory_address_counter, mem_mask);
633		return scc68070->dma.channel[(offset - 0x2000) / 32].memory_address_counter;
	786	verboselog(machine(), 2, "cdi68070_periphs_r: DMA(%d) Memory Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].memory_address_counter, mem_mask);
	787	return m_dma.channel[(offset - 0x2000) / 32].memory_address_counter;
634	788	case 0x4014/2:
635	789	case 0x4054/2:
636		verboselog(space.machine(), 2, "scc68070_periphs_r: DMA(%d) Device Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, (scc68070->dma.channel[(offset - 0x2000) / 32].device_address_counter >> 16), mem_mask);
637		return (scc68070->dma.channel[(offset - 0x2000) / 32].device_address_counter >> 16);
	790	verboselog(machine(), 2, "cdi68070_periphs_r: DMA(%d) Device Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, (m_dma.channel[(offset - 0x2000) / 32].device_address_counter >> 16), mem_mask);
	791	return (m_dma.channel[(offset - 0x2000) / 32].device_address_counter >> 16);
638	792	case 0x4016/2:
639	793	case 0x4056/2:
640		verboselog(space.machine(), 2, "scc68070_periphs_r: DMA(%d) Device Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, scc68070->dma.channel[(offset - 0x2000) / 32].device_address_counter, mem_mask);
641		return scc68070->dma.channel[(offset - 0x2000) / 32].device_address_counter;
	794	verboselog(machine(), 2, "cdi68070_periphs_r: DMA(%d) Device Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].device_address_counter, mem_mask);
	795	return m_dma.channel[(offset - 0x2000) / 32].device_address_counter;
642	796
643	797	// MMU: 80008000 to 8000807f
644	798	case 0x8000/2:  // Status / Control register
645	799	if(ACCESSING_BITS_0_7)
646	800	{   // Control
647		verboselog(space.machine(), 2, "scc68070_periphs_r: MMU Control: %02x & %04x\n", scc68070->mmu.control, mem_mask);
648		return scc68070->mmu.control;
	801	verboselog(machine(), 2, "cdi68070_periphs_r: MMU Control: %02x & %04x\n", m_mmu.control, mem_mask);
	802	return m_mmu.control;
649	803	}   // Status
650	804	else
651	805	{
652		verboselog(space.machine(), 2, "scc68070_periphs_r: MMU Status: %02x & %04x\n", scc68070->mmu.status, mem_mask);
653		return scc68070->mmu.status;
	806	verboselog(machine(), 2, "cdi68070_periphs_r: MMU Status: %02x & %04x\n", m_mmu.status, mem_mask);
	807	return m_mmu.status;
654	808	}
655	809	break;
656	810	case 0x8040/2:
r20508	r20509
661	815	case 0x8068/2:
662	816	case 0x8070/2:
663	817	case 0x8078/2:  // Attributes (SD0-7)
664		verboselog(space.machine(), 2, "scc68070_periphs_r: MMU descriptor %d attributes: %04x & %04x\n", (offset - 0x4020) / 4, scc68070->mmu.desc[(offset - 0x4020) / 4].attr, mem_mask);
665		return scc68070->mmu.desc[(offset - 0x4020) / 4].attr;
	818	verboselog(machine(), 2, "cdi68070_periphs_r: MMU descriptor %d attributes: %04x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].attr, mem_mask);
	819	return m_mmu.desc[(offset - 0x4020) / 4].attr;
666	820	case 0x8042/2:
667	821	case 0x804a/2:
668	822	case 0x8052/2:
r20508	r20509
671	825	case 0x806a/2:
672	826	case 0x8072/2:
673	827	case 0x807a/2:  // Segment Length (SD0-7)
674		verboselog(space.machine(), 2, "scc68070_periphs_r: MMU descriptor %d length: %04x & %04x\n", (offset - 0x4020) / 4, scc68070->mmu.desc[(offset - 0x4020) / 4].length, mem_mask);
675		return scc68070->mmu.desc[(offset - 0x4020) / 4].length;
	828	verboselog(machine(), 2, "cdi68070_periphs_r: MMU descriptor %d length: %04x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].length, mem_mask);
	829	return m_mmu.desc[(offset - 0x4020) / 4].length;
676	830	case 0x8044/2:
677	831	case 0x804c/2:
678	832	case 0x8054/2:
r20508	r20509
683	837	case 0x807c/2:  // Segment Number (SD0-7, A0=1 only)
684	838	if(ACCESSING_BITS_0_7)
685	839	{
686		verboselog(space.machine(), 2, "scc68070_periphs_r: MMU descriptor %d segment: %02x & %04x\n", (offset - 0x4020) / 4, scc68070->mmu.desc[(offset - 0x4020) / 4].segment, mem_mask);
687		return scc68070->mmu.desc[(offset - 0x4020) / 4].segment;
	840	verboselog(machine(), 2, "cdi68070_periphs_r: MMU descriptor %d segment: %02x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].segment, mem_mask);
	841	return m_mmu.desc[(offset - 0x4020) / 4].segment;
688	842	}
689	843	break;
690	844	case 0x8046/2:
r20508	r20509
695	849	case 0x806e/2:
696	850	case 0x8076/2:
697	851	case 0x807e/2:  // Base Address (SD0-7)
698		verboselog(space.machine(), 2, "scc68070_periphs_r: MMU descriptor %d base: %04x & %04x\n", (offset - 0x4020) / 4, scc68070->mmu.desc[(offset - 0x4020) / 4].base, mem_mask);
699		return scc68070->mmu.desc[(offset - 0x4020) / 4].base;
	852	verboselog(machine(), 2, "cdi68070_periphs_r: MMU descriptor %d base: %04x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].base, mem_mask);
	853	return m_mmu.desc[(offset - 0x4020) / 4].base;
700	854	default:
701		verboselog(space.machine(), 0, "scc68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
	855	verboselog(space.machine(), 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
702	856	break;
703	857	}
704	858
705	859	return 0;
706	860	}
707	861
708		WRITE16_HANDLER( scc68070_periphs_w )
	862	WRITE16_MEMBER( cdi68070_device::periphs_w )
709	863	{
710		cdi_state *state = space.machine().driver_data<cdi_state>();
711		scc68070_regs_t *scc68070 = &state->m_scc68070_regs;
	864	cdi_state *state = machine().driver_data<cdi_state>();
712	865
713	866	switch(offset)
714	867	{
715	868	// Interrupts: 80001001
716	869	case 0x1000/2: // LIR priority level
717		verboselog(space.machine(), 2, "scc68070_periphs_w: LIR: %04x & %04x\n", data, mem_mask);
718		COMBINE_DATA(&scc68070->lir);
	870	verboselog(machine(), 2, "cdi68070_periphs_w: LIR: %04x & %04x\n", data, mem_mask);
	871	COMBINE_DATA(&m_lir);
719	872	break;
720	873
721	874	// I2C interface: 80002001 to 80002009
722	875	case 0x2000/2:
723	876	if(ACCESSING_BITS_0_7)
724	877	{
725		verboselog(space.machine(), 2, "scc68070_periphs_w: I2C Data Register: %04x & %04x\n", data, mem_mask);
726		scc68070->i2c.data_register = data & 0x00ff;
	878	verboselog(machine(), 2, "cdi68070_periphs_w: I2C Data Register: %04x & %04x\n", data, mem_mask);
	879	m_i2c.data_register = data & 0x00ff;
727	880	}
728	881	break;
729	882	case 0x2002/2:
730	883	if(ACCESSING_BITS_0_7)
731	884	{
732		verboselog(space.machine(), 2, "scc68070_periphs_w: I2C Address Register: %04x & %04x\n", data, mem_mask);
733		scc68070->i2c.address_register = data & 0x00ff;
	885	verboselog(machine(), 2, "cdi68070_periphs_w: I2C Address Register: %04x & %04x\n", data, mem_mask);
	886	m_i2c.address_register = data & 0x00ff;
734	887	}
735	888	break;
736	889	case 0x2004/2:
737	890	if(ACCESSING_BITS_0_7)
738	891	{
739		verboselog(space.machine(), 2, "scc68070_periphs_w: I2C Status Register: %04x & %04x\n", data, mem_mask);
740		scc68070->i2c.status_register = data & 0x00ff;
	892	verboselog(machine(), 2, "cdi68070_periphs_w: I2C Status Register: %04x & %04x\n", data, mem_mask);
	893	m_i2c.status_register = data & 0x00ff;
741	894	}
742	895	break;
743	896	case 0x2006/2:
744	897	if(ACCESSING_BITS_0_7)
745	898	{
746		verboselog(space.machine(), 2, "scc68070_periphs_w: I2C Control Register: %04x & %04x\n", data, mem_mask);
747		scc68070->i2c.control_register = data & 0x00ff;
	899	verboselog(machine(), 2, "cdi68070_periphs_w: I2C Control Register: %04x & %04x\n", data, mem_mask);
	900	m_i2c.control_register = data & 0x00ff;
748	901	}
749	902	break;
750	903	case 0x2008/2:
751	904	if(ACCESSING_BITS_0_7)
752	905	{
753		verboselog(space.machine(), 2, "scc68070_periphs_w: I2C Clock Control Register: %04x & %04x\n", data, mem_mask);
754		scc68070->i2c.clock_control_register = data & 0x00ff;
	906	verboselog(machine(), 2, "cdi68070_periphs_w: I2C Clock Control Register: %04x & %04x\n", data, mem_mask);
	907	m_i2c.clock_control_register = data & 0x00ff;
755	908	}
756	909	break;
757	910
r20508	r20509
759	912	case 0x2010/2:
760	913	if(ACCESSING_BITS_0_7)
761	914	{
762		verboselog(space.machine(), 2, "scc68070_periphs_w: UART Mode Register: %04x & %04x\n", data, mem_mask);
763		scc68070->uart.mode_register = data & 0x00ff;
	915	verboselog(machine(), 2, "cdi68070_periphs_w: UART Mode Register: %04x & %04x\n", data, mem_mask);
	916	m_uart.mode_register = data & 0x00ff;
764	917	}
765	918	else
766	919	{
767		verboselog(space.machine(), 0, "scc68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
	920	verboselog(machine(), 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
768	921	}
769	922	break;
770	923	case 0x2012/2:
771	924	if(ACCESSING_BITS_0_7)
772	925	{
773		verboselog(space.machine(), 2, "scc68070_periphs_w: UART Status Register: %04x & %04x\n", data, mem_mask);
774		scc68070->uart.status_register = data & 0x00ff;
	926	verboselog(machine(), 2, "cdi68070_periphs_w: UART Status Register: %04x & %04x\n", data, mem_mask);
	927	m_uart.status_register = data & 0x00ff;
775	928	}
776	929	else
777	930	{
778		verboselog(space.machine(), 0, "scc68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
	931	verboselog(machine(), 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
779	932	}
780	933	break;
781	934	case 0x2014/2:
782	935	if(ACCESSING_BITS_0_7)
783	936	{
784		verboselog(space.machine(), 2, "scc68070_periphs_w: UART Clock Select: %04x & %04x\n", data, mem_mask);
785		scc68070->uart.clock_select = data & 0x00ff;
	937	verboselog(machine(), 2, "cdi68070_periphs_w: UART Clock Select: %04x & %04x\n", data, mem_mask);
	938	m_uart.clock_select = data & 0x00ff;
786	939	}
787	940	else
788	941	{
789		verboselog(space.machine(), 0, "scc68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
	942	verboselog(machine(), 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
790	943	}
791	944	break;
792	945	case 0x2016/2:
793	946	if(ACCESSING_BITS_0_7)
794	947	{
795		verboselog(space.machine(), 2, "scc68070_periphs_w: UART Command Register: %04x & %04x\n", data, mem_mask);
796		scc68070->uart.command_register = data & 0x00ff;
797		scc68070_uart_rx_check(space.machine(), scc68070);
798		scc68070_uart_tx_check(space.machine(), scc68070);
	948	verboselog(machine(), 2, "cdi68070_periphs_w: UART Command Register: %04x & %04x\n", data, mem_mask);
	949	m_uart.command_register = data & 0x00ff;
	950	uart_rx_check();
	951	uart_tx_check();
799	952	}
800	953	else
801	954	{
802		verboselog(space.machine(), 0, "scc68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
	955	verboselog(machine(), 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
803	956	}
804	957	break;
805	958	case 0x2018/2:
806	959	if(ACCESSING_BITS_0_7)
807	960	{
808		verboselog(space.machine(), 2, "scc68070_periphs_w: UART Transmit Holding Register: %04x & %04x: %c\n", data, mem_mask, (data >= 0x20 && data < 0x7f) ? (data & 0x00ff) : ' ');
809		scc68070_uart_tx(space.machine(), scc68070, data & 0x00ff);
810		scc68070->uart.transmit_holding_register = data & 0x00ff;
	961	verboselog(machine(), 2, "cdi68070_periphs_w: UART Transmit Holding Register: %04x & %04x: %c\n", data, mem_mask, (data >= 0x20 && data < 0x7f) ? (data & 0x00ff) : ' ');
	962	uart_tx(data & 0x00ff);
	963	m_uart.transmit_holding_register = data & 0x00ff;
811	964	}
812	965	else
813	966	{
814		verboselog(space.machine(), 0, "scc68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
	967	verboselog(machine(), 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
815	968	}
816	969	break;
817	970	case 0x201a/2:
818	971	if(ACCESSING_BITS_0_7)
819	972	{
820		verboselog(space.machine(), 2, "scc68070_periphs_w: UART Receive Holding Register: %04x & %04x\n", data, mem_mask);
821		scc68070->uart.receive_holding_register = data & 0x00ff;
	973	verboselog(machine(), 2, "cdi68070_periphs_w: UART Receive Holding Register: %04x & %04x\n", data, mem_mask);
	974	m_uart.receive_holding_register = data & 0x00ff;
822	975	}
823	976	else
824	977	{
825		verboselog(space.machine(), 0, "scc68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
	978	verboselog(machine(), 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
826	979	}
827	980	break;
828	981
r20508	r20509
830	983	case 0x2020/2:
831	984	if(ACCESSING_BITS_0_7)
832	985	{
833		verboselog(space.machine(), 2, "scc68070_periphs_w: Timer Control Register: %04x & %04x\n", data, mem_mask);
834		scc68070->timers.timer_control_register = data & 0x00ff;
	986	verboselog(machine(), 2, "cdi68070_periphs_w: Timer Control Register: %04x & %04x\n", data, mem_mask);
	987	m_timers.timer_control_register = data & 0x00ff;
835	988	}
836	989	if(ACCESSING_BITS_8_15)
837	990	{
838		verboselog(space.machine(), 12, "scc68070_periphs_w: Timer Status Register: %04x & %04x\n", data, mem_mask);
839		scc68070->timers.timer_status_register &= ~(data >> 8);
840		if(!scc68070->timers.timer_status_register)
	991	verboselog(machine(), 12, "cdi68070_periphs_w: Timer Status Register: %04x & %04x\n", data, mem_mask);
	992	m_timers.timer_status_register &= ~(data >> 8);
	993	if(!m_timers.timer_status_register)
841	994	{
842		UINT8 interrupt = scc68070->picr1 & 7;
843		space.machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt - 1), CLEAR_LINE);
	995	UINT8 interrupt = m_picr1 & 7;
	996	state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), CLEAR_LINE);
844	997	}
845	998	}
846	999	break;
847	1000	case 0x2022/2:
848		verboselog(space.machine(), 2, "scc68070_periphs_w: Timer Reload Register: %04x & %04x\n", data, mem_mask);
849		COMBINE_DATA(&scc68070->timers.reload_register);
	1001	verboselog(machine(), 2, "cdi68070_periphs_w: Timer Reload Register: %04x & %04x\n", data, mem_mask);
	1002	COMBINE_DATA(&m_timers.reload_register);
850	1003	break;
851	1004	case 0x2024/2:
852		verboselog(space.machine(), 2, "scc68070_periphs_w: Timer 0: %04x & %04x\n", data, mem_mask);
853		COMBINE_DATA(&scc68070->timers.timer0);
854		scc68070_set_timer_callback(&state->m_scc68070_regs, 0);
	1005	verboselog(machine(), 2, "cdi68070_periphs_w: Timer 0: %04x & %04x\n", data, mem_mask);
	1006	COMBINE_DATA(&m_timers.timer0);
	1007	set_timer_callback(0);
855	1008	break;
856	1009	case 0x2026/2:
857		verboselog(space.machine(), 2, "scc68070_periphs_w: Timer 1: %04x & %04x\n", data, mem_mask);
858		COMBINE_DATA(&scc68070->timers.timer1);
	1010	verboselog(machine(), 2, "cdi68070_periphs_w: Timer 1: %04x & %04x\n", data, mem_mask);
	1011	COMBINE_DATA(&m_timers.timer1);
859	1012	break;
860	1013	case 0x2028/2:
861		verboselog(space.machine(), 2, "scc68070_periphs_w: Timer 2: %04x & %04x\n", data, mem_mask);
862		COMBINE_DATA(&scc68070->timers.timer2);
	1014	verboselog(machine(), 2, "cdi68070_periphs_w: Timer 2: %04x & %04x\n", data, mem_mask);
	1015	COMBINE_DATA(&m_timers.timer2);
863	1016	break;
864	1017
865	1018	// PICR1: 80002045
866	1019	case 0x2044/2:
867	1020	if(ACCESSING_BITS_0_7)
868	1021	{
869		verboselog(space.machine(), 2, "scc68070_periphs_w: Peripheral Interrupt Control Register 1: %04x & %04x\n", data, mem_mask);
870		scc68070->picr1 = data & 0x00ff;
	1022	verboselog(machine(), 2, "cdi68070_periphs_w: Peripheral Interrupt Control Register 1: %04x & %04x\n", data, mem_mask);
	1023	m_picr1 = data & 0x00ff;
871	1024	}
872	1025	break;
873	1026
r20508	r20509
875	1028	case 0x2046/2:
876	1029	if(ACCESSING_BITS_0_7)
877	1030	{
878		verboselog(space.machine(), 2, "scc68070_periphs_w: Peripheral Interrupt Control Register 2: %04x & %04x\n", data, mem_mask);
879		scc68070->picr2 = data & 0x00ff;
	1031	verboselog(machine(), 2, "cdi68070_periphs_w: Peripheral Interrupt Control Register 2: %04x & %04x\n", data, mem_mask);
	1032	m_picr2 = data & 0x00ff;
880	1033	}
881	1034	break;
882	1035
r20508	r20509
885	1038	case 0x4040/2:
886	1039	if(ACCESSING_BITS_0_7)
887	1040	{
888		verboselog(space.machine(), 2, "scc68070_periphs_w: DMA(%d) Error (invalid): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
	1041	verboselog(machine(), 2, "cdi68070_periphs_w: DMA(%d) Error (invalid): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
889	1042	}
890	1043	if(ACCESSING_BITS_8_15)
891	1044	{
892		verboselog(space.machine(), 2, "scc68070_periphs_w: DMA(%d) Status: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
893		scc68070->dma.channel[(offset - 0x2000) / 32].channel_status &= ~(data & 0xb0);
	1045	verboselog(machine(), 2, "cdi68070_periphs_w: DMA(%d) Status: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
	1046	m_dma.channel[(offset - 0x2000) / 32].channel_status &= ~(data & 0xb0);
894	1047	}
895	1048	break;
896	1049	case 0x4004/2:
897	1050	case 0x4044/2:
898	1051	if(ACCESSING_BITS_0_7)
899	1052	{
900		verboselog(space.machine(), 2, "scc68070_periphs_w: DMA(%d) Operation Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
901		scc68070->dma.channel[(offset - 0x2000) / 32].operation_control = data & 0x00ff;
	1053	verboselog(machine(), 2, "cdi68070_periphs_w: DMA(%d) Operation Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
	1054	m_dma.channel[(offset - 0x2000) / 32].operation_control = data & 0x00ff;
902	1055	}
903	1056	if(ACCESSING_BITS_8_15)
904	1057	{
905		verboselog(space.machine(), 2, "scc68070_periphs_w: DMA(%d) Device Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
906		scc68070->dma.channel[(offset - 0x2000) / 32].device_control = data >> 8;
	1058	verboselog(machine(), 2, "cdi68070_periphs_w: DMA(%d) Device Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
	1059	m_dma.channel[(offset - 0x2000) / 32].device_control = data >> 8;
907	1060	}
908	1061	break;
909	1062	case 0x4006/2:
910	1063	case 0x4046/2:
911	1064	if(ACCESSING_BITS_0_7)
912	1065	{
913		verboselog(space.machine(), 2, "scc68070_periphs_w: DMA(%d) Channel Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
914		scc68070->dma.channel[(offset - 0x2000) / 32].channel_control = data & 0x007f;
	1066	verboselog(machine(), 2, "cdi68070_periphs_w: DMA(%d) Channel Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
	1067	m_dma.channel[(offset - 0x2000) / 32].channel_control = data & 0x007f;
915	1068	if(data & CCR_SO)
916	1069	{
917		scc68070->dma.channel[(offset - 0x2000) / 32].channel_status |= CSR_COC;
	1070	m_dma.channel[(offset - 0x2000) / 32].channel_status |= CSR_COC;
918	1071	}
919	1072	}
920	1073	if(ACCESSING_BITS_8_15)
921	1074	{
922		verboselog(space.machine(), 2, "scc68070_periphs_w: DMA(%d) Sequence Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
923		scc68070->dma.channel[(offset - 0x2000) / 32].sequence_control = data >> 8;
	1075	verboselog(machine(), 2, "cdi68070_periphs_w: DMA(%d) Sequence Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
	1076	m_dma.channel[(offset - 0x2000) / 32].sequence_control = data >> 8;
924	1077	}
925	1078	break;
926	1079	case 0x400a/2:
927		verboselog(space.machine(), 2, "scc68070_periphs_w: DMA(%d) Memory Transfer Counter: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
928		COMBINE_DATA(&scc68070->dma.channel[(offset - 0x2000) / 32].transfer_counter);
	1080	verboselog(machine(), 2, "cdi68070_periphs_w: DMA(%d) Memory Transfer Counter: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
	1081	COMBINE_DATA(&m_dma.channel[(offset - 0x2000) / 32].transfer_counter);
929	1082	break;
930	1083	case 0x400c/2:
931	1084	case 0x404c/2:
932		verboselog(space.machine(), 2, "scc68070_periphs_w: DMA(%d) Memory Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
933		scc68070->dma.channel[(offset - 0x2000) / 32].memory_address_counter &= ~(mem_mask << 16);
934		scc68070->dma.channel[(offset - 0x2000) / 32].memory_address_counter |= data << 16;
	1085	verboselog(machine(), 2, "cdi68070_periphs_w: DMA(%d) Memory Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
	1086	m_dma.channel[(offset - 0x2000) / 32].memory_address_counter &= ~(mem_mask << 16);
	1087	m_dma.channel[(offset - 0x2000) / 32].memory_address_counter |= data << 16;
935	1088	break;
936	1089	case 0x400e/2:
937	1090	case 0x404e/2:
938		verboselog(space.machine(), 2, "scc68070_periphs_w: DMA(%d) Memory Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
939		scc68070->dma.channel[(offset - 0x2000) / 32].memory_address_counter &= ~mem_mask;
940		scc68070->dma.channel[(offset - 0x2000) / 32].memory_address_counter |= data;
	1091	verboselog(machine(), 2, "cdi68070_periphs_w: DMA(%d) Memory Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
	1092	m_dma.channel[(offset - 0x2000) / 32].memory_address_counter &= ~mem_mask;
	1093	m_dma.channel[(offset - 0x2000) / 32].memory_address_counter |= data;
941	1094	break;
942	1095	case 0x4014/2:
943	1096	case 0x4054/2:
944		verboselog(space.machine(), 2, "scc68070_periphs_w: DMA(%d) Device Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
945		scc68070->dma.channel[(offset - 0x2000) / 32].device_address_counter &= ~(mem_mask << 16);
946		scc68070->dma.channel[(offset - 0x2000) / 32].device_address_counter |= data << 16;
	1097	verboselog(machine(), 2, "cdi68070_periphs_w: DMA(%d) Device Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
	1098	m_dma.channel[(offset - 0x2000) / 32].device_address_counter &= ~(mem_mask << 16);
	1099	m_dma.channel[(offset - 0x2000) / 32].device_address_counter |= data << 16;
947	1100	break;
948	1101	case 0x4016/2:
949	1102	case 0x4056/2:
950		verboselog(space.machine(), 2, "scc68070_periphs_w: DMA(%d) Device Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
951		scc68070->dma.channel[(offset - 0x2000) / 32].device_address_counter &= ~mem_mask;
952		scc68070->dma.channel[(offset - 0x2000) / 32].device_address_counter |= data;
	1103	verboselog(machine(), 2, "cdi68070_periphs_w: DMA(%d) Device Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
	1104	m_dma.channel[(offset - 0x2000) / 32].device_address_counter &= ~mem_mask;
	1105	m_dma.channel[(offset - 0x2000) / 32].device_address_counter |= data;
953	1106	break;
954	1107
955	1108	// MMU: 80008000 to 8000807f
956	1109	case 0x8000/2:  // Status / Control register
957	1110	if(ACCESSING_BITS_0_7)
958	1111	{   // Control
959		verboselog(space.machine(), 2, "scc68070_periphs_w: MMU Control: %04x & %04x\n", data, mem_mask);
960		scc68070->mmu.control = data & 0x00ff;
	1112	verboselog(machine(), 2, "cdi68070_periphs_w: MMU Control: %04x & %04x\n", data, mem_mask);
	1113	m_mmu.control = data & 0x00ff;
961	1114	}   // Status
962	1115	else
963	1116	{
964		verboselog(space.machine(), 0, "scc68070_periphs_w: MMU Status (invalid): %04x & %04x\n", data, mem_mask);
	1117	verboselog(machine(), 0, "cdi68070_periphs_w: MMU Status (invalid): %04x & %04x\n", data, mem_mask);
965	1118	}
966	1119	break;
967	1120	case 0x8040/2:
r20508	r20509
972	1125	case 0x8068/2:
973	1126	case 0x8070/2:
974	1127	case 0x8078/2:  // Attributes (SD0-7)
975		verboselog(space.machine(), 2, "scc68070_periphs_w: MMU descriptor %d attributes: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask);
976		COMBINE_DATA(&scc68070->mmu.desc[(offset - 0x4020) / 4].attr);
	1128	verboselog(machine(), 2, "cdi68070_periphs_w: MMU descriptor %d attributes: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask);
	1129	COMBINE_DATA(&m_mmu.desc[(offset - 0x4020) / 4].attr);
977	1130	break;
978	1131	case 0x8042/2:
979	1132	case 0x804a/2:
r20508	r20509
983	1136	case 0x806a/2:
984	1137	case 0x8072/2:
985	1138	case 0x807a/2:  // Segment Length (SD0-7)
986		verboselog(space.machine(), 2, "scc68070_periphs_w: MMU descriptor %d length: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask);
987		COMBINE_DATA(&scc68070->mmu.desc[(offset - 0x4020) / 4].length);
	1139	verboselog(machine(), 2, "cdi68070_periphs_w: MMU descriptor %d length: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask);
	1140	COMBINE_DATA(&m_mmu.desc[(offset - 0x4020) / 4].length);
988	1141	break;
989	1142	case 0x8044/2:
990	1143	case 0x804c/2:
r20508	r20509
996	1149	case 0x807c/2:  // Segment Number (SD0-7, A0=1 only)
997	1150	if(ACCESSING_BITS_0_7)
998	1151	{
999		verboselog(space.machine(), 2, "scc68070_periphs_w: MMU descriptor %d segment: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask);
1000		scc68070->mmu.desc[(offset - 0x4020) / 4].segment = data & 0x00ff;
	1152	verboselog(machine(), 2, "cdi68070_periphs_w: MMU descriptor %d segment: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask);
	1153	m_mmu.desc[(offset - 0x4020) / 4].segment = data & 0x00ff;
1001	1154	}
1002	1155	break;
1003	1156	case 0x8046/2:
r20508	r20509
1008	1161	case 0x806e/2:
1009	1162	case 0x8076/2:
1010	1163	case 0x807e/2:  // Base Address (SD0-7)
1011		verboselog(space.machine(), 2, "scc68070_periphs_w: MMU descriptor %d base: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask);
1012		COMBINE_DATA(&scc68070->mmu.desc[(offset - 0x4020) / 4].base);
	1164	verboselog(machine(), 2, "cdi68070_periphs_w: MMU descriptor %d base: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask);
	1165	COMBINE_DATA(&m_mmu.desc[(offset - 0x4020) / 4].base);
1013	1166	break;
1014	1167	default:
1015		verboselog(space.machine(), 0, "scc68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
	1168	verboselog(machine(), 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
1016	1169	break;
1017	1170	}
1018	1171	}
1019	1172
1020		void scc68070_init(running_machine &machine, scc68070_regs_t *scc68070)
1021		{
1022		int index = 0;
1023		scc68070->lir = 0;
1024
1025		scc68070->picr1 = 0;
1026		scc68070->picr2 = 0;
1027
1028		scc68070->i2c.data_register = 0;
1029		scc68070->i2c.address_register = 0;
1030		scc68070->i2c.status_register = 0;
1031		scc68070->i2c.control_register = 0;
1032		scc68070->i2c.clock_control_register = 0;
1033
1034		scc68070->uart.mode_register = 0;
1035		scc68070->uart.status_register = USR_TXRDY;
1036		scc68070->uart.clock_select = 0;
1037		scc68070->uart.command_register = 0;
1038		scc68070->uart.transmit_holding_register = 0;
1039		scc68070->uart.receive_holding_register = 0;
1040		scc68070->uart.receive_pointer = -1;
1041		scc68070->uart.transmit_pointer = -1;
1042
1043		scc68070->timers.timer_status_register = 0;
1044		scc68070->timers.timer_control_register = 0;
1045		scc68070->timers.reload_register = 0;
1046		scc68070->timers.timer0 = 0;
1047		scc68070->timers.timer1 = 0;
1048		scc68070->timers.timer2 = 0;
1049
1050		for(index = 0; index < 2; index++)
1051		{
1052		scc68070->dma.channel[index].channel_status = 0;
1053		scc68070->dma.channel[index].channel_error = 0;
1054		scc68070->dma.channel[index].device_control = 0;
1055		scc68070->dma.channel[index].operation_control = 0;
1056		scc68070->dma.channel[index].sequence_control = 0;
1057		scc68070->dma.channel[index].channel_control = 0;
1058		scc68070->dma.channel[index].transfer_counter = 0;
1059		scc68070->dma.channel[index].memory_address_counter = 0;
1060		scc68070->dma.channel[index].device_address_counter = 0;
1061		}
1062
1063		scc68070->mmu.status = 0;
1064		scc68070->mmu.control = 0;
1065		for(index = 0; index < 8; index++)
1066		{
1067		scc68070->mmu.desc[index].attr = 0;
1068		scc68070->mmu.desc[index].length = 0;
1069		scc68070->mmu.desc[index].segment = 0;
1070		scc68070->mmu.desc[index].base = 0;
1071		}
1072		}
1073
1074		void scc68070_register_globals(running_machine &machine, scc68070_regs_t *scc68070)
1075		{
1076		state_save_register_global(machine, scc68070->lir);
1077
1078		state_save_register_global(machine, scc68070->picr1);
1079		state_save_register_global(machine, scc68070->picr2);
1080
1081		state_save_register_global(machine, scc68070->i2c.data_register);
1082		state_save_register_global(machine, scc68070->i2c.address_register);
1083		state_save_register_global(machine, scc68070->i2c.status_register);
1084		state_save_register_global(machine, scc68070->i2c.control_register);
1085		state_save_register_global(machine, scc68070->i2c.clock_control_register);
1086
1087		state_save_register_global(machine, scc68070->uart.mode_register);
1088		state_save_register_global(machine, scc68070->uart.status_register);
1089		state_save_register_global(machine, scc68070->uart.clock_select);
1090		state_save_register_global(machine, scc68070->uart.command_register);
1091		state_save_register_global(machine, scc68070->uart.transmit_holding_register);
1092		state_save_register_global(machine, scc68070->uart.receive_holding_register);
1093
1094		state_save_register_global(machine, scc68070->timers.timer_status_register);
1095		state_save_register_global(machine, scc68070->timers.timer_control_register);
1096		state_save_register_global(machine, scc68070->timers.reload_register);
1097		state_save_register_global(machine, scc68070->timers.timer0);
1098		state_save_register_global(machine, scc68070->timers.timer1);
1099		state_save_register_global(machine, scc68070->timers.timer2);
1100
1101		state_save_register_global(machine, scc68070->dma.channel[0].channel_status);
1102		state_save_register_global(machine, scc68070->dma.channel[0].channel_error);
1103		state_save_register_global(machine, scc68070->dma.channel[0].device_control);
1104		state_save_register_global(machine, scc68070->dma.channel[0].operation_control);
1105		state_save_register_global(machine, scc68070->dma.channel[0].sequence_control);
1106		state_save_register_global(machine, scc68070->dma.channel[0].channel_control);
1107		state_save_register_global(machine, scc68070->dma.channel[0].transfer_counter);
1108		state_save_register_global(machine, scc68070->dma.channel[0].memory_address_counter);
1109		state_save_register_global(machine, scc68070->dma.channel[0].device_address_counter);
1110		state_save_register_global(machine, scc68070->dma.channel[1].channel_status);
1111		state_save_register_global(machine, scc68070->dma.channel[1].channel_error);
1112		state_save_register_global(machine, scc68070->dma.channel[1].device_control);
1113		state_save_register_global(machine, scc68070->dma.channel[1].operation_control);
1114		state_save_register_global(machine, scc68070->dma.channel[1].sequence_control);
1115		state_save_register_global(machine, scc68070->dma.channel[1].channel_control);
1116		state_save_register_global(machine, scc68070->dma.channel[1].transfer_counter);
1117		state_save_register_global(machine, scc68070->dma.channel[1].memory_address_counter);
1118		state_save_register_global(machine, scc68070->dma.channel[1].device_address_counter);
1119
1120		state_save_register_global(machine, scc68070->mmu.status);
1121		state_save_register_global(machine, scc68070->mmu.control);
1122		state_save_register_global(machine, scc68070->mmu.desc[0].attr);
1123		state_save_register_global(machine, scc68070->mmu.desc[0].length);
1124		state_save_register_global(machine, scc68070->mmu.desc[0].segment);
1125		state_save_register_global(machine, scc68070->mmu.desc[0].base);
1126		state_save_register_global(machine, scc68070->mmu.desc[1].attr);
1127		state_save_register_global(machine, scc68070->mmu.desc[1].length);
1128		state_save_register_global(machine, scc68070->mmu.desc[1].segment);
1129		state_save_register_global(machine, scc68070->mmu.desc[1].base);
1130		state_save_register_global(machine, scc68070->mmu.desc[2].attr);
1131		state_save_register_global(machine, scc68070->mmu.desc[2].length);
1132		state_save_register_global(machine, scc68070->mmu.desc[2].segment);
1133		state_save_register_global(machine, scc68070->mmu.desc[2].base);
1134		state_save_register_global(machine, scc68070->mmu.desc[3].attr);
1135		state_save_register_global(machine, scc68070->mmu.desc[3].length);
1136		state_save_register_global(machine, scc68070->mmu.desc[3].segment);
1137		state_save_register_global(machine, scc68070->mmu.desc[3].base);
1138		state_save_register_global(machine, scc68070->mmu.desc[4].attr);
1139		state_save_register_global(machine, scc68070->mmu.desc[4].length);
1140		state_save_register_global(machine, scc68070->mmu.desc[4].segment);
1141		state_save_register_global(machine, scc68070->mmu.desc[4].base);
1142		state_save_register_global(machine, scc68070->mmu.desc[5].attr);
1143		state_save_register_global(machine, scc68070->mmu.desc[5].length);
1144		state_save_register_global(machine, scc68070->mmu.desc[5].segment);
1145		state_save_register_global(machine, scc68070->mmu.desc[5].base);
1146		state_save_register_global(machine, scc68070->mmu.desc[6].attr);
1147		state_save_register_global(machine, scc68070->mmu.desc[6].length);
1148		state_save_register_global(machine, scc68070->mmu.desc[6].segment);
1149		state_save_register_global(machine, scc68070->mmu.desc[6].base);
1150		state_save_register_global(machine, scc68070->mmu.desc[7].attr);
1151		state_save_register_global(machine, scc68070->mmu.desc[7].length);
1152		state_save_register_global(machine, scc68070->mmu.desc[7].segment);
1153		state_save_register_global(machine, scc68070->mmu.desc[7].base);
1154
1155		scc68070->timers.timer0_timer = machine.scheduler().timer_alloc(FUNC(scc68070_timer0_callback));
1156		scc68070->timers.timer0_timer->adjust(attotime::never);
1157
1158		scc68070->uart.rx_timer = machine.scheduler().timer_alloc(FUNC(scc68070_rx_callback));
1159		scc68070->uart.rx_timer->adjust(attotime::never);
1160
1161		scc68070->uart.tx_timer = machine.scheduler().timer_alloc(FUNC(scc68070_tx_callback));
1162		scc68070->uart.tx_timer->adjust(attotime::never);
1163		}
1164
1165	1173	#if ENABLE_UART_PRINTING
1166	1174	READ16_HANDLER( uart_loopback_enable )
1167	1175	{

trunk/src/mame/machine/cdicdic.h

r20508	r20509
26	26
27	27	#include "emu.h"
28	28	#include "cdrom.h"
	29	#include "sound/cdda.h"
29	30
30	31
31
32	32	//**************************************************************************
33	33	//  INTERFACE CONFIGURATION MACROS
34	34	//**************************************************************************
r20508	r20509
59	59	void register_write(const UINT32 offset, const UINT16 data, const UINT16 mem_mask);
60	60	UINT16 register_read(const UINT32 offset, const UINT16 mem_mask);
61	61
	62	DECLARE_READ16_MEMBER( regs_r );
	63	DECLARE_WRITE16_MEMBER( regs_w );
	64	DECLARE_READ16_MEMBER( ram_r );
	65	DECLARE_WRITE16_MEMBER( ram_w );
	66
	67
62	68	protected:
63	69	// device-level overrides
64	70	virtual void device_start();
r20508	r20509
67	73	virtual void device_clock_changed() { }
68	74
69	75	// internal callbacks
70		static TIMER_CALLBACK( audio_sample_trigger );
71		static TIMER_CALLBACK( trigger_readback_int );
	76	TIMER_CALLBACK_MEMBER( audio_sample_trigger );
	77	TIMER_CALLBACK_MEMBER( trigger_readback_int );
72	78
73	79	private:
74	80	// internal state
r20508	r20509
99	105	int m_xa_last[4];
100	106	UINT16 *m_ram;
101	107
102		void register_globals();
103		void init();
104
105	108	// static internal members
106	109	static void decode_xa_mono(INT32 *cdic_xa_last, const UINT8 *xa, INT16 *dp);
107	110	static void decode_xa_mono8(INT32 *cdic_xa_last, const UINT8 *xa, INT16 *dp);
r20508	r20509
120	123	// device type definition
121	124	extern const device_type MACHINE_CDICDIC;
122	125
123
124
125		//**************************************************************************
126		//  READ/WRITE HANDLERS
127		//**************************************************************************
128
129		DECLARE_READ16_DEVICE_HANDLER( cdic_r );
130		DECLARE_WRITE16_DEVICE_HANDLER( cdic_w );
131		DECLARE_READ16_DEVICE_HANDLER( cdic_ram_r );
132		DECLARE_WRITE16_DEVICE_HANDLER( cdic_ram_w );
133
134
135	126	#endif // __CDICDIC_H__

trunk/src/mame/machine/cdi070.h

r20508	r20509
19	19
20	20	*******************************************************************************/
21	21
22		#ifndef _MACHINE_CDI070_H_
23		#define _MACHINE_CDI070_H_
	22	#ifndef _MACHINE_CDI68070_H_
	23	#define _MACHINE_CDI68070_H_
24	24
25	25	#include "emu.h"
26	26
27		struct scc68070_i2c_regs_t
28		{
29		UINT8 reserved0;
30		UINT8 data_register;
31		UINT8 reserved1;
32		UINT8 address_register;
33		UINT8 reserved2;
34		UINT8 status_register;
35		UINT8 reserved3;
36		UINT8 control_register;
37		UINT8 reserved;
38		UINT8 clock_control_register;
39		};
40
41	27	#define ISR_MST     0x80    // Master
42	28	#define ISR_TRX     0x40    // Transmitter
43	29	#define ISR_BB      0x20    // Busy
r20508	r20509
47	33	#define ISR_AD0     0x02    // Address Zero
48	34	#define ISR_LRB     0x01    // Last Received Bit
49	35
50		struct scc68070_uart_regs_t
51		{
52		UINT8 reserved0;
53		UINT8 mode_register;
54		UINT8 reserved1;
55		UINT8 status_register;
56		UINT8 reserved2;
57		UINT8 clock_select;
58		UINT8 reserved3;
59		UINT8 command_register;
60		UINT8 reserved4;
61		UINT8 transmit_holding_register;
62		UINT8 reserved5;
63		UINT8 receive_holding_register;
64
65		INT16 receive_pointer;
66		UINT8 receive_buffer[32768];
67		emu_timer* rx_timer;
68
69		INT16 transmit_pointer;
70		UINT8 transmit_buffer[32768];
71		emu_timer* tx_timer;
72		};
73
74	36	#define UMR_OM          0xc0
75	37	#define UMR_OM_NORMAL   0x00
76	38	#define UMR_OM_ECHO     0x40
r20508	r20509
90	52	#define USR_TXRDY       0x04
91	53	#define USR_RXRDY       0x01
92	54
93		struct scc68070_timer_regs_t
94		{
95		UINT8 timer_status_register;
96		UINT8 timer_control_register;
97		UINT16 reload_register;
98		UINT16 timer0;
99		UINT16 timer1;
100		UINT16 timer2;
101		emu_timer* timer0_timer;
102		};
103
104	55	#define TSR_OV0         0x80
105	56	#define TSR_MA1         0x40
106	57	#define TSR_CAP1        0x20
r20508	r20509
130	81	#define TCR_M2_CAPTURE  0x02
131	82	#define TCR_M2_COUNT    0x03
132	83
133		struct scc68070_dma_channel_t
134		{
135		UINT8 channel_status;
136		UINT8 channel_error;
137
138		UINT8 reserved0[2];
139
140		UINT8 device_control;
141		UINT8 operation_control;
142		UINT8 sequence_control;
143		UINT8 channel_control;
144
145		UINT8 reserved1[3];
146
147		UINT16 transfer_counter;
148
149		UINT32 memory_address_counter;
150
151		UINT8 reserved2[4];
152
153		UINT32 device_address_counter;
154
155		UINT8 reserved3[40];
156		};
157
158	84	#define CSR_COC         0x80
159	85	#define CSR_NDT         0x20
160	86	#define CSR_ERR         0x10
r20508	r20509
193	119	#define CCR_INE         0x08
194	120	#define CCR_IPL         0x07
195	121
196		struct scc68070_dma_regs_t
197		{
198		scc68070_dma_channel_t channel[2];
199		};
	122	//**************************************************************************
	123	//  INTERFACE CONFIGURATION MACROS
	124	//**************************************************************************
200	125
201		struct scc68070_mmu_desc_t
202		{
203		UINT16 attr;
204		UINT16 length;
205		UINT8  undefined;
206		UINT8  segment;
207		UINT16 base;
208		};
	126	#define MCFG_CDI68070_ADD(_tag) \
	127	MCFG_DEVICE_ADD(_tag, MACHINE_CDI68070, 0)
	128	#define MCFG_CDI68070_REPLACE(_tag) \
	129	MCFG_DEVICE_REPLACE(_tag, MACHINE_CDI68070, 0)
209	130
210		struct scc68070_mmu_regs_t
	131	//**************************************************************************
	132	//  TYPE DEFINITIONS
	133	//**************************************************************************
	134
	135	// ======================> cdi68070_device
	136
	137	class cdi68070_device : public device_t
211	138	{
212		UINT8 status;
213		UINT8 control;
	139	public:
	140	// construction/destruction
	141	cdi68070_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
214	142
215		UINT8 reserved[0x3e];
	143	// external callbacks
	144	void init();
	145	void uart_rx(UINT8 data);
	146	void uart_tx(UINT8 data);
216	147
217		scc68070_mmu_desc_t desc[8];
218		};
	148	// UART Access for Quizard
	149	void set_quizard_mcu_value(UINT16 value);
	150	void set_quizard_mcu_ack(UINT8 ack);
	151	void quizard_rx(UINT8 data);
219	152
220		struct scc68070_regs_t
221		{
222		UINT16 lir;
223		UINT8 picr1;
224		UINT8 picr2;
	153	void mcu_frame();
225	154
226		scc68070_i2c_regs_t i2c;
227		scc68070_uart_regs_t uart;
228		scc68070_timer_regs_t timers;
229		scc68070_dma_regs_t dma;
230		scc68070_mmu_regs_t mmu;
231		};
	155	DECLARE_READ16_MEMBER(periphs_r);
	156	DECLARE_WRITE16_MEMBER(periphs_w);
232	157
233		// Member functions
234		TIMER_CALLBACK( scc68070_timer0_callback );
235		TIMER_CALLBACK( scc68070_rx_callback );
236		TIMER_CALLBACK( scc68070_tx_callback );
237		DECLARE_READ16_HANDLER( scc68070_periphs_r );
238		DECLARE_WRITE16_HANDLER( scc68070_periphs_w );
239		//DECLARE_READ16_HANDLER( uart_loopback_enable );
	158	TIMER_CALLBACK_MEMBER( timer0_callback );
	159	TIMER_CALLBACK_MEMBER( rx_callback );
	160	TIMER_CALLBACK_MEMBER( tx_callback );
240	161
241		void scc68070_init(running_machine &machine, scc68070_regs_t *scc68070);
242		void scc68070_uart_rx(running_machine &machine, scc68070_regs_t *scc68070, UINT8 data);
243		void scc68070_uart_tx(running_machine &machine, scc68070_regs_t *scc68070, UINT8 data);
244		void scc68070_register_globals(running_machine &machine, scc68070_regs_t *scc68070);
	162	// register structures
	163	struct i2c_regs_t
	164	{
	165	UINT8 reserved0;
	166	UINT8 data_register;
	167	UINT8 reserved1;
	168	UINT8 address_register;
	169	UINT8 reserved2;
	170	UINT8 status_register;
	171	UINT8 reserved3;
	172	UINT8 control_register;
	173	UINT8 reserved;
	174	UINT8 clock_control_register;
	175	};
245	176
246		// UART Access for Quizard
247		void scc68070_set_quizard_mcu_value(running_machine &machine, UINT16 value);
248		void scc68070_set_quizard_mcu_ack(running_machine &machine, UINT8 ack);
249		void scc68070_quizard_rx(running_machine &machine, scc68070_regs_t *scc68070, UINT8 data);
	177	struct uart_regs_t
	178	{
	179	UINT8 reserved0;
	180	UINT8 mode_register;
	181	UINT8 reserved1;
	182	UINT8 status_register;
	183	UINT8 reserved2;
	184	UINT8 clock_select;
	185	UINT8 reserved3;
	186	UINT8 command_register;
	187	UINT8 reserved4;
	188	UINT8 transmit_holding_register;
	189	UINT8 reserved5;
	190	UINT8 receive_holding_register;
250	191
251		INTERRUPT_GEN( scc68070_mcu_frame );
	192	INT16 receive_pointer;
	193	UINT8 receive_buffer[32768];
	194	emu_timer* rx_timer;
252	195
253		#endif // _MACHINE_CDI070_H_
	196	INT16 transmit_pointer;
	197	UINT8 transmit_buffer[32768];
	198	emu_timer* tx_timer;
	199	};
	200
	201	struct timer_regs_t
	202	{
	203	UINT8 timer_status_register;
	204	UINT8 timer_control_register;
	205	UINT16 reload_register;
	206	UINT16 timer0;
	207	UINT16 timer1;
	208	UINT16 timer2;
	209	emu_timer* timer0_timer;
	210	};
	211
	212	struct dma_channel_t
	213	{
	214	UINT8 channel_status;
	215	UINT8 channel_error;
	216
	217	UINT8 reserved0[2];
	218
	219	UINT8 device_control;
	220	UINT8 operation_control;
	221	UINT8 sequence_control;
	222	UINT8 channel_control;
	223
	224	UINT8 reserved1[3];
	225
	226	UINT16 transfer_counter;
	227
	228	UINT32 memory_address_counter;
	229
	230	UINT8 reserved2[4];
	231
	232	UINT32 device_address_counter;
	233
	234	UINT8 reserved3[40];
	235	};
	236
	237	struct dma_regs_t
	238	{
	239	dma_channel_t channel[2];
	240	};
	241
	242	struct mmu_desc_t
	243	{
	244	UINT16 attr;
	245	UINT16 length;
	246	UINT8  undefined;
	247	UINT8  segment;
	248	UINT16 base;
	249	};
	250
	251	struct mmu_regs_t
	252	{
	253	UINT8 status;
	254	UINT8 control;
	255
	256	UINT8 reserved[0x3e];
	257
	258	mmu_desc_t desc[8];
	259	};
	260
	261	dma_regs_t& dma() { return m_dma; }
	262
	263	UINT16 get_lir() { return m_lir; }
	264
	265	protected:
	266	// device-level overrides
	267	virtual void device_start();
	268	virtual void device_reset();
	269
	270	private:
	271
	272	void uart_rx_check();
	273	void uart_tx_check();
	274	void set_timer_callback(int channel);
	275
	276	// internal state
	277	emu_timer *m_interrupt_timer;
	278
	279	UINT16 m_seeds[10];
	280	UINT8 m_state[8];
	281
	282	UINT16 m_mcu_value;
	283	UINT8 m_mcu_ack;
	284
	285	UINT16 m_lir;
	286	UINT8 m_picr1;
	287	UINT8 m_picr2;
	288
	289	i2c_regs_t m_i2c;
	290	uart_regs_t m_uart;
	291	timer_regs_t m_timers;
	292	dma_regs_t m_dma;
	293	mmu_regs_t m_mmu;
	294
	295	// non-static internal members
	296	void quizard_calculate_state();
	297	void quizard_set_seeds(UINT8 *rx);
	298	void quizard_handle_byte_tx();
	299	};
	300
	301	// device type definition
	302	extern const device_type MACHINE_CDI68070;
	303
	304	#endif // _MACHINE_CDI68070_H_

trunk/src/mame/video/mcd212.c

r20508	r20509
620	620	mcd212->channel[1].csrr |= 1 << (2 - channel);
621	621	if(mcd212->channel[1].csrr & (MCD212_CSR2R_IT1 | MCD212_CSR2R_IT2))
622	622	{
623		UINT8 interrupt = (state->m_scc68070_regs.lir >> 4) & 7;
	623	UINT8 interrupt = (state->m_scc->get_lir() >> 4) & 7;
624	624	if(interrupt)
625	625	{
626		machine.device("maincpu")->execute().set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
627		machine.device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
	626	state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
	627	state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
628	628	}
629	629	}
630	630	#if 0
r20508	r20509
633	633	UINT8 interrupt = state->m_scc68070_regs.lir & 7;
634	634	if(interrupt)
635	635	{
636		machine.device("maincpu")->execute().set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 24 + interrupt);
637		machine.device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
	636	state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 24 + interrupt);
	637	state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
638	638	}
639	639	}
640	640	#endif
r20508	r20509
711	711	mcd212->channel[1].csrr |= 1 << (2 - channel);
712	712	if(mcd212->channel[1].csrr & (MCD212_CSR2R_IT1 | MCD212_CSR2R_IT2))
713	713	{
714		UINT8 interrupt = (state->m_scc68070_regs.lir >> 4) & 7;
	714	UINT8 interrupt = (state->m_scc->get_lir() >> 4) & 7;
715	715	if(interrupt)
716	716	{
717		machine.device("maincpu")->execute().set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
718		machine.device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
	717	state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
	718	state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
719	719	}
720	720	}
721	721	#if 0
r20508	r20509
724	724	UINT8 interrupt = state->m_scc68070_regs.lir & 7;
725	725	if(interrupt)
726	726	{
727		machine.device("maincpu")->execute().set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 24 + interrupt);
728		machine.device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
	727	state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 24 + interrupt);
	728	state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
729	729	}
730	730	}
731	731	#endif
r20508	r20509
1371	1371	else
1372	1372	{
1373	1373	UINT8 old_csr = mcd212->channel[1].csrr;
1374		UINT8 interrupt1 = (state->m_scc68070_regs.lir >> 4) & 7;
	1374	UINT8 interrupt1 = (state->m_scc->get_lir() >> 4) & 7;
1375	1375	//UINT8 interrupt2 = state->m_scc68070_regs.lir & 7;
1376	1376	mcd212->channel[1].csrr &= ~(MCD212_CSR2R_IT1 | MCD212_CSR2R_IT2);
1377	1377	if(interrupt1)
1378	1378	{
1379		space.machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt1 - 1), CLEAR_LINE);
	1379	state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt1 - 1), CLEAR_LINE);
1380	1380	}
1381	1381	//if(interrupt2)
1382	1382	//{
1383		//  space.machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt2 - 1), CLEAR_LINE);
	1383	//  state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt2 - 1), CLEAR_LINE);
1384	1384	//}
1385	1385	return old_csr;
1386	1386	}

trunk/src/mame/includes/cdi.h

r20508	r20509
16	16	{
17	17	public:
18	18	cdi_state(const machine_config &mconfig, device_type type, const char *tag)
19		: driver_device(mconfig, type, tag) ,
	19	: driver_device(mconfig, type, tag),
	20	m_maincpu(*this, "maincpu"),
20	21	m_planea(*this, "planea"),
21		m_planeb(*this, "planeb"){ }
	22	m_planeb(*this, "planeb"),
	23	m_input1(*this, "INPUT1"),
	24	m_input2(*this, "INPUT2"),
	25	m_mousex(*this, "MOUSEX"),
	26	m_mousey(*this, "MOUSEY"),
	27	m_mousebtn(*this, "MOUSEBTN"),
	28	m_slave(*this, "slave"),
	29	m_scc(*this, "scc68070"),
	30	m_cdic(*this, "cdic"),
	31	m_cdda(*this, "cdda"){ }
22	32
	33	required_device<cpu_device> m_maincpu;
23	34	required_shared_ptr<UINT16> m_planea;
24	35	required_shared_ptr<UINT16> m_planeb;
	36	optional_device<ioport_port> m_input1;
	37	optional_device<ioport_port> m_input2;
	38	required_ioport m_mousex;
	39	required_ioport m_mousey;
	40	required_ioport m_mousebtn;
	41	required_device<cdislave_device> m_slave;
	42	required_device<cdi68070_device> m_scc;
	43	required_device<cdicdic_device> m_cdic;
	44	required_device<cdda_device> m_cdda;
25	45
26	46	dmadac_sound_device *m_dmadac[2];
27	47
	48	INTERRUPT_GEN_MEMBER( mcu_frame );
	49
28	50	UINT8 m_timer_set;
29	51	emu_timer *m_test_timer;
30	52	bitmap_rgb32 m_lcdbitmap;
31		scc68070_regs_t m_scc68070_regs;
32	53	mcd212_regs_t m_mcd212_regs;
33	54	mcd212_ab_t m_mcd212_ab;
34	55	DECLARE_INPUT_CHANGED_MEMBER(mcu_input);

trunk/src/mame/drivers/cdi.c

r20508	r20509
61	61	#if ENABLE_UART_PRINTING
62	62	AM_RANGE(0x00301400, 0x00301403) AM_READ_LEGACY(uart_loopback_enable)
63	63	#endif
64		AM_RANGE(0x00300000, 0x00303bff) AM_DEVREADWRITE_LEGACY("cdic", cdic_ram_r, cdic_ram_w)
65		//AM_RANGE(0x00300000, 0x00303bff) AM_RAM AM_SHARE("cdic_regs.ram")
66		AM_RANGE(0x00303c00, 0x00303fff) AM_DEVREADWRITE_LEGACY("cdic", cdic_r, cdic_w)
67		AM_RANGE(0x00310000, 0x00317fff) AM_DEVREADWRITE_LEGACY("slave", slave_r, slave_w)
	64	AM_RANGE(0x00300000, 0x00303bff) AM_DEVREADWRITE("cdic", cdicdic_device, ram_r, ram_w)
	65	AM_RANGE(0x00303c00, 0x00303fff) AM_DEVREADWRITE("cdic", cdicdic_device, regs_r, regs_w)
	66	AM_RANGE(0x00310000, 0x00317fff) AM_DEVREADWRITE("slave", cdislave_device, slave_r, slave_w)
68	67	//AM_RANGE(0x00318000, 0x0031ffff) AM_NOP
69	68	AM_RANGE(0x00320000, 0x00323fff) AM_DEVREADWRITE8_LEGACY("mk48t08", timekeeper_r, timekeeper_w, 0xff00)    /* nvram (only low bytes used) */
70	69	AM_RANGE(0x00400000, 0x0047ffff) AM_ROM AM_REGION("maincpu", 0)
r20508	r20509
72	71	//AM_RANGE(0x00500000, 0x0057ffff) AM_RAM
73	72	AM_RANGE(0x00500000, 0x00ffffff) AM_NOP
74	73	//AM_RANGE(0x00e00000, 0x00efffff) AM_RAM // DVC
75		AM_RANGE(0x80000000, 0x8000807f) AM_READWRITE_LEGACY(scc68070_periphs_r, scc68070_periphs_w)
	74	AM_RANGE(0x80000000, 0x8000807f) AM_DEVREADWRITE("scc68070", cdi68070_device, periphs_r, periphs_w)
76	75	ADDRESS_MAP_END
77	76
78	77	/*************************
r20508	r20509
81	80
82	81	INPUT_CHANGED_MEMBER(cdi_state::mcu_input)
83	82	{
84		scc68070_regs_t *scc68070 = &m_scc68070_regs;
85	83	bool send = false;
86	84
87	85	switch((FPTR)param)
88	86	{
89	87	case 0x39:
90		if(ioport("INPUT1")->read() & 0x01) send = true;
	88	if(m_input1->read() & 0x01) send = true;
91	89	break;
92	90	case 0x37:
93		if(ioport("INPUT1")->read() & 0x02) send = true;
	91	if(m_input1->read() & 0x02) send = true;
94	92	break;
95	93	case 0x31:
96		if(ioport("INPUT1")->read() & 0x04) send = true;
	94	if(m_input1->read() & 0x04) send = true;
97	95	break;
98	96	case 0x32:
99		if(ioport("INPUT1")->read() & 0x08) send = true;
	97	if(m_input1->read() & 0x08) send = true;
100	98	break;
101	99	case 0x33:
102		if(ioport("INPUT1")->read() & 0x10) send = true;
	100	if(m_input1->read() & 0x10) send = true;
103	101	break;
104	102
105	103	case 0x30:
106		if(ioport("INPUT2")->read() & 0x01) send = true;
	104	if(m_input2->read() & 0x01) send = true;
107	105	break;
108	106	case 0x38:
109		if(ioport("INPUT2")->read() & 0x02) send = true;
	107	if(m_input2->read() & 0x02) send = true;
110	108	break;
111	109	case 0x34:
112		if(ioport("INPUT2")->read() & 0x04) send = true;
	110	if(m_input2->read() & 0x04) send = true;
113	111	break;
114	112	case 0x35:
115		if(ioport("INPUT2")->read() & 0x08) send = true;
	113	if(m_input2->read() & 0x08) send = true;
116	114	break;
117	115	case 0x36:
118		if(ioport("INPUT2")->read() & 0x10) send = true;
	116	if(m_input2->read() & 0x10) send = true;
119	117	break;
120	118	}
121	119
122	120	if(send)
123	121	{
124	122	UINT8 data = (UINT8)((FPTR)param & 0x000000ff);
125		scc68070_quizard_rx(machine(), scc68070, data);
	123	m_scc->quizard_rx(data);
126	124	}
127	125	}
128	126
r20508	r20509
191	189
192	190	void cdi_state::machine_start()
193	191	{
194		scc68070_register_globals(machine(), &m_scc68070_regs);
195	192	}
196	193
	194	INTERRUPT_GEN_MEMBER( cdi_state::mcu_frame )
	195	{
	196	m_scc->mcu_frame();
	197	}
	198
197	199	MACHINE_RESET_MEMBER(cdi_state,cdi)
198	200	{
199	201	UINT16 *src   = (UINT16*)memregion("maincpu")->base();
r20508	r20509
201	203	//device_t *cdrom_dev = machine().device("cdrom");
202	204	memcpy(dst, src, 0x8);
203	205
204		scc68070_init(machine(), &m_scc68070_regs);
	206	m_maincpu->reset();
205	207
206		machine().device("maincpu")->reset();
207
208	208	m_dmadac[0] = machine().device<dmadac_sound_device>("dac1");
209	209	m_dmadac[1] = machine().device<dmadac_sound_device>("dac2");
210	210	}
r20508	r20509
213	213	{
214	214	MACHINE_RESET_CALL_MEMBER( cdi );
215	215
216		scc68070_set_quizard_mcu_value(machine(), 0x021f);
217		scc68070_set_quizard_mcu_ack(machine(), 0x5a);
	216	m_scc->set_quizard_mcu_value(0x021f);
	217	m_scc->set_quizard_mcu_ack(0x5a);
218	218	}
219	219
220	220	MACHINE_RESET_MEMBER(cdi_state,quizrd17)
221	221	{
222	222	MACHINE_RESET_CALL_MEMBER( cdi );
223	223
224		scc68070_set_quizard_mcu_value(machine(), 0x021f);
225		scc68070_set_quizard_mcu_ack(machine(), 0x5a);
	224	m_scc->set_quizard_mcu_value(0x021f);
	225	m_scc->set_quizard_mcu_ack(0x5a);
226	226	}
227	227
228	228	/* Untested - copied from quizrd17 */
r20508	r20509
230	230	{
231	231	MACHINE_RESET_CALL_MEMBER( cdi );
232	232
233		scc68070_set_quizard_mcu_value(machine(), 0x021f);
234		scc68070_set_quizard_mcu_ack(machine(), 0x5a);
	233	m_scc->set_quizard_mcu_value(0x021f);
	234	m_scc->set_quizard_mcu_ack(0x5a);
235	235	}
236	236
237	237	MACHINE_RESET_MEMBER(cdi_state,quizrd22)
r20508	r20509
242	242	// 0x001: French
243	243	// 0x188: German
244	244
245		scc68070_set_quizard_mcu_value(machine(), 0x188);
246		scc68070_set_quizard_mcu_ack(machine(), 0x59);
	245	m_scc->set_quizard_mcu_value(0x188);
	246	m_scc->set_quizard_mcu_ack(0x59);
247	247	}
248	248
249	249	/* Untested - copied from quizrd22 */
r20508	r20509
255	255	// 0x001: French
256	256	// 0x188: German
257	257
258		scc68070_set_quizard_mcu_value(machine(), 0x188);
259		scc68070_set_quizard_mcu_ack(machine(), 0x59);
	258	m_scc->set_quizard_mcu_value(0x188);
	259	m_scc->set_quizard_mcu_ack(0x59);
260	260	}
261	261
262	262	MACHINE_RESET_MEMBER(cdi_state,quizrd32)
263	263	{
264	264	MACHINE_RESET_CALL_MEMBER( cdi );
265	265
266		scc68070_set_quizard_mcu_value(machine(), 0x00ae);
267		scc68070_set_quizard_mcu_ack(machine(), 0x58);
	266	m_scc->set_quizard_mcu_value(0x00ae);
	267	m_scc->set_quizard_mcu_ack(0x58);
268	268	}
269	269
270	270	/* Untested - copied from quizrd32 */
r20508	r20509
272	272	{
273	273	MACHINE_RESET_CALL_MEMBER( cdi );
274	274
275		scc68070_set_quizard_mcu_value(machine(), 0x00ae);
276		scc68070_set_quizard_mcu_ack(machine(), 0x58);
	275	m_scc->set_quizard_mcu_value(0x00ae);
	276	m_scc->set_quizard_mcu_ack(0x58);
277	277	}
278	278
279	279	/* Untested - copied from quizrr41 */
r20508	r20509
281	281	{
282	282	MACHINE_RESET_CALL_MEMBER( cdi );
283	283
284		//scc68070_set_quizard_mcu_value(machine(), 0x0139);
285		scc68070_set_quizard_mcu_value(machine(), 0x011f);
286		scc68070_set_quizard_mcu_ack(machine(), 0x57);
	284	//m_scc->set_quizard_mcu_value(0x0139);
	285	m_scc->set_quizard_mcu_value(0x011f);
	286	m_scc->set_quizard_mcu_ack(0x57);
287	287	}
288	288
289	289	MACHINE_RESET_MEMBER(cdi_state,quizrr41)
290	290	{
291	291	MACHINE_RESET_CALL_MEMBER( cdi );
292	292
293		//scc68070_set_quizard_mcu_value(machine(), 0x0139);
294		scc68070_set_quizard_mcu_value(machine(), 0x011f);
295		scc68070_set_quizard_mcu_ack(machine(), 0x57);
	293	//m_scc->set_quizard_mcu_value(0x0139);
	294	m_scc->set_quizard_mcu_value(0x011f);
	295	m_scc->set_quizard_mcu_ack(0x57);
296	296	}
297	297
298	298	MACHINE_RESET_MEMBER(cdi_state,quizrr42)
299	299	{
300	300	MACHINE_RESET_CALL_MEMBER( cdi );
301	301
302		scc68070_set_quizard_mcu_value(machine(), 0x01ae);
303		scc68070_set_quizard_mcu_ack(machine(), 0x57);
	302	m_scc->set_quizard_mcu_value(0x01ae);
	303	m_scc->set_quizard_mcu_ack(0x57);
304	304	}
305	305
306	306	static DEVICE_IMAGE_DISPLAY_INFO(cdi_cdinfo)
r20508	r20509
343	343
344	344	MCFG_DEFAULT_LAYOUT(layout_cdi)
345	345
	346	MCFG_CDI68070_ADD("scc68070")
	347	MCFG_CDICDIC_ADD("cdic")
	348	MCFG_CDISLAVE_ADD("slave")
346	349
347
348		MCFG_CDICDIC_ADD( "cdic" )
349		MCFG_CDISLAVE_ADD( "slave" )
350
351	350	/* sound hardware */
352	351	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
353	352
r20508	r20509
384	383	static MACHINE_CONFIG_DERIVED( quizard, cdi_base )
385	384	MCFG_CPU_MODIFY("maincpu")
386	385	MCFG_CPU_PROGRAM_MAP(cdimono1_mem)
387		MCFG_CPU_VBLANK_INT("screen", scc68070_mcu_frame)
	386	MCFG_CPU_VBLANK_INT_DRIVER("screen", cdi_state, mcu_frame)
388	387	MACHINE_CONFIG_END
389	388
390	389	static MACHINE_CONFIG_DERIVED( quizrd12, quizard )

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