trunk/src/mess/machine/ondra.c
| r20484 | r20485 | |
| 9 | 9 | |
| 10 | 10 | #include "emu.h" |
| 11 | 11 | #include "cpu/z80/z80.h" |
| 12 | | #include "imagedev/cassette.h" |
| 13 | 12 | #include "includes/ondra.h" |
| 14 | | #include "machine/ram.h" |
| 15 | 13 | |
| 16 | 14 | |
| 17 | | static cassette_image_device *cassette_device_image(running_machine &machine) |
| 18 | | { |
| 19 | | return machine.device<cassette_image_device>(CASSETTE_TAG); |
| 20 | | } |
| 21 | | |
| 22 | | |
| 23 | 15 | READ8_MEMBER(ondra_state::ondra_keyboard_r) |
| 24 | 16 | { |
| 25 | 17 | UINT8 retVal = 0x00; |
| 26 | | UINT8 ondra_keyboard_line = offset & 0x000f; |
| 27 | | static const char *const keynames[] = { "LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7", "LINE8", "LINE9" }; |
| 28 | | double valcas = (cassette_device_image(machine())->input()); |
| 18 | double valcas = m_cassette->input(); |
| 19 | |
| 29 | 20 | if ( valcas < 0.00) { |
| 30 | 21 | retVal = 0x80; |
| 31 | 22 | } |
| 32 | | if (ondra_keyboard_line > 9) { |
| 33 | | retVal |= 0x1f; |
| 34 | | } else { |
| 35 | | retVal |= ioport(keynames[ondra_keyboard_line])->read(); |
| 23 | |
| 24 | switch ( offset & 0x0f ) |
| 25 | { |
| 26 | case 0: retVal |= m_line0->read(); break; |
| 27 | case 1: retVal |= m_line1->read(); break; |
| 28 | case 2: retVal |= m_line2->read(); break; |
| 29 | case 3: retVal |= m_line3->read(); break; |
| 30 | case 4: retVal |= m_line4->read(); break; |
| 31 | case 5: retVal |= m_line5->read(); break; |
| 32 | case 6: retVal |= m_line6->read(); break; |
| 33 | case 7: retVal |= m_line7->read(); break; |
| 34 | case 8: retVal |= m_line8->read(); break; |
| 35 | case 9: retVal |= m_line9->read(); break; |
| 36 | default: retVal |= 0x1f; break; |
| 36 | 37 | } |
| 38 | |
| 37 | 39 | return retVal; |
| 38 | 40 | } |
| 39 | 41 | |
| 40 | | static void ondra_update_banks(running_machine &machine) |
| 42 | void ondra_state::ondra_update_banks() |
| 41 | 43 | { |
| 42 | | ondra_state *state = machine.driver_data<ondra_state>(); |
| 43 | | UINT8 *mem = state->memregion("maincpu")->base(); |
| 44 | | if (state->m_bank1_status==0) { |
| 45 | | machine.device("maincpu")->memory().space(AS_PROGRAM).unmap_write(0x0000, 0x3fff); |
| 46 | | state->membank("bank1")->set_base(mem + 0x010000); |
| 44 | address_space &space = m_maincpu->space(AS_PROGRAM); |
| 45 | UINT8 *mem = m_region_maincpu->base(); |
| 46 | |
| 47 | if (m_bank1_status==0) { |
| 48 | space.unmap_write(0x0000, 0x3fff); |
| 49 | m_bank1->set_base(mem + 0x010000); |
| 47 | 50 | } else { |
| 48 | | machine.device("maincpu")->memory().space(AS_PROGRAM).install_write_bank(0x0000, 0x3fff, "bank1"); |
| 49 | | state->membank("bank1")->set_base(machine.device<ram_device>(RAM_TAG)->pointer() + 0x0000); |
| 51 | space.install_write_bank(0x0000, 0x3fff, "bank1"); |
| 52 | m_bank1->set_base(m_ram->pointer() + 0x0000); |
| 50 | 53 | } |
| 51 | | state->membank("bank2")->set_base(machine.device<ram_device>(RAM_TAG)->pointer() + 0x4000); |
| 52 | | if (state->m_bank2_status==0) { |
| 53 | | machine.device("maincpu")->memory().space(AS_PROGRAM).install_readwrite_bank(0xe000, 0xffff, "bank3"); |
| 54 | | state->membank("bank3")->set_base(machine.device<ram_device>(RAM_TAG)->pointer() + 0xe000); |
| 54 | m_bank2->set_base(m_ram->pointer() + 0x4000); |
| 55 | if (m_bank2_status==0) { |
| 56 | space.install_readwrite_bank(0xe000, 0xffff, "bank3"); |
| 57 | m_bank3->set_base(m_ram->pointer() + 0xe000); |
| 55 | 58 | } else { |
| 56 | | machine.device("maincpu")->memory().space(AS_PROGRAM).unmap_write(0xe000, 0xffff); |
| 57 | | machine.device("maincpu")->memory().space(AS_PROGRAM).install_read_handler (0xe000, 0xffff, read8_delegate(FUNC(ondra_state::ondra_keyboard_r),state)); |
| 59 | space.unmap_write(0xe000, 0xffff); |
| 60 | space.install_read_handler (0xe000, 0xffff, read8_delegate(FUNC(ondra_state::ondra_keyboard_r),this)); |
| 58 | 61 | } |
| 59 | 62 | } |
| 60 | 63 | |
| r20484 | r20485 | |
| 63 | 66 | m_video_enable = data & 1; |
| 64 | 67 | m_bank1_status = (data >> 1) & 1; |
| 65 | 68 | m_bank2_status = (data >> 2) & 1; |
| 66 | | ondra_update_banks(machine()); |
| 67 | | cassette_device_image(machine())->output(((data >> 3) & 1) ? -1.0 : +1.0); |
| 69 | ondra_update_banks(); |
| 70 | m_cassette->output(((data >> 3) & 1) ? -1.0 : +1.0); |
| 68 | 71 | } |
| 69 | 72 | |
| 70 | 73 | WRITE8_MEMBER(ondra_state::ondra_port_09_w) |
| r20484 | r20485 | |
| 77 | 80 | |
| 78 | 81 | TIMER_CALLBACK_MEMBER(ondra_state::nmi_check_callback) |
| 79 | 82 | { |
| 80 | | if ((machine().root_device().ioport("NMI")->read() & 1) == 1) |
| 83 | if ((m_nmi->read() & 1) == 1) |
| 81 | 84 | { |
| 82 | | machine().device("maincpu")->execute().set_input_line(INPUT_LINE_NMI, PULSE_LINE); |
| 85 | m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE); |
| 83 | 86 | } |
| 84 | 87 | } |
| 85 | 88 | |
| r20484 | r20485 | |
| 87 | 90 | { |
| 88 | 91 | m_bank1_status = 0; |
| 89 | 92 | m_bank2_status = 0; |
| 90 | | ondra_update_banks(machine()); |
| 93 | ondra_update_banks(); |
| 91 | 94 | } |
| 92 | 95 | |
| 93 | 96 | void ondra_state::machine_start() |
trunk/src/mess/includes/ondra.h
| r20484 | r20485 | |
| 7 | 7 | #ifndef ONDRA_H_ |
| 8 | 8 | #define ONDRA_H_ |
| 9 | 9 | |
| 10 | #include "imagedev/cassette.h" |
| 11 | #include "machine/ram.h" |
| 12 | |
| 10 | 13 | class ondra_state : public driver_device |
| 11 | 14 | { |
| 12 | 15 | public: |
| 13 | 16 | ondra_state(const machine_config &mconfig, device_type type, const char *tag) |
| 14 | | : driver_device(mconfig, type, tag) { } |
| 17 | : driver_device(mconfig, type, tag) |
| 18 | , m_maincpu(*this, "maincpu") |
| 19 | , m_cassette(*this, CASSETTE_TAG) |
| 20 | , m_ram(*this, RAM_TAG) |
| 21 | , m_region_maincpu(*this, "maincpu") |
| 22 | , m_bank1(*this, "bank1") |
| 23 | , m_bank2(*this, "bank2") |
| 24 | , m_bank3(*this, "bank3") |
| 25 | , m_line0(*this, "LINE0") |
| 26 | , m_line1(*this, "LINE1") |
| 27 | , m_line2(*this, "LINE2") |
| 28 | , m_line3(*this, "LINE3") |
| 29 | , m_line4(*this, "LINE4") |
| 30 | , m_line5(*this, "LINE5") |
| 31 | , m_line6(*this, "LINE6") |
| 32 | , m_line7(*this, "LINE7") |
| 33 | , m_line8(*this, "LINE8") |
| 34 | , m_line9(*this, "LINE9") |
| 35 | , m_nmi(*this, "NMI") |
| 36 | { } |
| 15 | 37 | |
| 16 | 38 | UINT8 m_video_enable; |
| 17 | 39 | UINT8 m_bank1_status; |
| r20484 | r20485 | |
| 26 | 48 | UINT32 screen_update_ondra(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); |
| 27 | 49 | INTERRUPT_GEN_MEMBER(ondra_interrupt); |
| 28 | 50 | TIMER_CALLBACK_MEMBER(nmi_check_callback); |
| 51 | |
| 52 | protected: |
| 53 | required_device<cpu_device> m_maincpu; |
| 54 | required_device<cassette_image_device> m_cassette; |
| 55 | required_device<ram_device> m_ram; |
| 56 | required_memory_region m_region_maincpu; |
| 57 | required_memory_bank m_bank1; |
| 58 | required_memory_bank m_bank2; |
| 59 | required_memory_bank m_bank3; |
| 60 | required_ioport m_line0; |
| 61 | required_ioport m_line1; |
| 62 | required_ioport m_line2; |
| 63 | required_ioport m_line3; |
| 64 | required_ioport m_line4; |
| 65 | required_ioport m_line5; |
| 66 | required_ioport m_line6; |
| 67 | required_ioport m_line7; |
| 68 | required_ioport m_line8; |
| 69 | required_ioport m_line9; |
| 70 | required_ioport m_nmi; |
| 71 | |
| 72 | void ondra_update_banks(); |
| 29 | 73 | }; |
| 30 | 74 | |
| 31 | 75 | #endif |