trunk/src/mess/machine/pokemini.c
| r20482 | r20483 | |
| 10 | 10 | #include "includes/pokemini.h" |
| 11 | 11 | |
| 12 | 12 | |
| 13 | | static void pokemini_check_irqs( running_machine &machine ) |
| 13 | void pokemini_state::pokemini_check_irqs() |
| 14 | 14 | { |
| 15 | | pokemini_state *state = machine.driver_data<pokemini_state>(); |
| 16 | 15 | int irq_set[4] = { 1, 0, 0, 0 }; |
| 17 | 16 | int prio, vector; |
| 18 | 17 | |
| 19 | 18 | /* Check IRQ $03-$04 */ |
| 20 | | prio = ( state->m_pm_reg[0x20] >> 6 ) & 0x03; |
| 19 | prio = ( m_pm_reg[0x20] >> 6 ) & 0x03; |
| 21 | 20 | if ( ! irq_set[prio] ) |
| 22 | 21 | { |
| 23 | | if ( state->m_pm_reg[0x23] & state->m_pm_reg[0x27] & 0x40 ) |
| 22 | if ( m_pm_reg[0x23] & m_pm_reg[0x27] & 0x40 ) |
| 24 | 23 | irq_set[prio] = 0x04; |
| 25 | 24 | |
| 26 | | if ( state->m_pm_reg[0x23] & state->m_pm_reg[0x27] & 0x80 ) |
| 25 | if ( m_pm_reg[0x23] & m_pm_reg[0x27] & 0x80 ) |
| 27 | 26 | irq_set[prio] = 0x03; |
| 28 | 27 | } |
| 29 | 28 | |
| 30 | 29 | /* Check IRQ $05-$06 */ |
| 31 | | prio = ( state->m_pm_reg[0x20] >> 4 ) & 0x03; |
| 30 | prio = ( m_pm_reg[0x20] >> 4 ) & 0x03; |
| 32 | 31 | if ( ! irq_set[prio] ) |
| 33 | 32 | { |
| 34 | | if ( state->m_pm_reg[0x23] & state->m_pm_reg[0x27] & 0x10 ) |
| 33 | if ( m_pm_reg[0x23] & m_pm_reg[0x27] & 0x10 ) |
| 35 | 34 | irq_set[prio] = 0x06; |
| 36 | 35 | |
| 37 | | if ( state->m_pm_reg[0x23] & state->m_pm_reg[0x27] & 0x20 ) |
| 36 | if ( m_pm_reg[0x23] & m_pm_reg[0x27] & 0x20 ) |
| 38 | 37 | irq_set[prio] = 0x05; |
| 39 | 38 | } |
| 40 | 39 | |
| 41 | 40 | /* Check IRQ $07-$08 */ |
| 42 | | prio = ( state->m_pm_reg[0x20] >> 2 ) & 0x03; |
| 41 | prio = ( m_pm_reg[0x20] >> 2 ) & 0x03; |
| 43 | 42 | if ( ! irq_set[prio] ) |
| 44 | 43 | { |
| 45 | | if ( state->m_pm_reg[0x23] & state->m_pm_reg[0x27] & 0x04 ) |
| 44 | if ( m_pm_reg[0x23] & m_pm_reg[0x27] & 0x04 ) |
| 46 | 45 | irq_set[prio] = 0x08; |
| 47 | 46 | |
| 48 | | if ( state->m_pm_reg[0x23] & state->m_pm_reg[0x27] & 0x08 ) |
| 47 | if ( m_pm_reg[0x23] & m_pm_reg[0x27] & 0x08 ) |
| 49 | 48 | irq_set[prio] = 0x07; |
| 50 | 49 | } |
| 51 | 50 | |
| 52 | 51 | /* Check IRQ $09-$0A */ |
| 53 | | prio = ( state->m_pm_reg[0x20] >> 0 ) & 0x03; |
| 52 | prio = ( m_pm_reg[0x20] >> 0 ) & 0x03; |
| 54 | 53 | if ( ! irq_set[prio] ) |
| 55 | 54 | { |
| 56 | | if ( state->m_pm_reg[0x23] & state->m_pm_reg[0x27] & 0x01 ) |
| 55 | if ( m_pm_reg[0x23] & m_pm_reg[0x27] & 0x01 ) |
| 57 | 56 | irq_set[prio] = 0x0A; |
| 58 | 57 | |
| 59 | | if ( state->m_pm_reg[0x23] & state->m_pm_reg[0x27] & 0x02 ) |
| 58 | if ( m_pm_reg[0x23] & m_pm_reg[0x27] & 0x02 ) |
| 60 | 59 | irq_set[prio] = 0x09; |
| 61 | 60 | } |
| 62 | 61 | |
| 63 | 62 | /* Check IRQ $0B-$0E */ |
| 64 | | prio = ( state->m_pm_reg[0x21] >> 6 ) & 0x03; |
| 63 | prio = ( m_pm_reg[0x21] >> 6 ) & 0x03; |
| 65 | 64 | if ( ! irq_set[prio] ) |
| 66 | 65 | { |
| 67 | | if ( state->m_pm_reg[0x24] & state->m_pm_reg[0x28] & 0x04 ) |
| 66 | if ( m_pm_reg[0x24] & m_pm_reg[0x28] & 0x04 ) |
| 68 | 67 | irq_set[prio] = 0x0E; |
| 69 | 68 | |
| 70 | | if ( state->m_pm_reg[0x24] & state->m_pm_reg[0x28] & 0x08 ) |
| 69 | if ( m_pm_reg[0x24] & m_pm_reg[0x28] & 0x08 ) |
| 71 | 70 | irq_set[prio] = 0x0D; |
| 72 | 71 | |
| 73 | | if ( state->m_pm_reg[0x24] & state->m_pm_reg[0x28] & 0x10 ) |
| 72 | if ( m_pm_reg[0x24] & m_pm_reg[0x28] & 0x10 ) |
| 74 | 73 | irq_set[prio] = 0x0C; |
| 75 | 74 | |
| 76 | | if ( state->m_pm_reg[0x24] & state->m_pm_reg[0x28] & 0x20 ) |
| 75 | if ( m_pm_reg[0x24] & m_pm_reg[0x28] & 0x20 ) |
| 77 | 76 | irq_set[prio] = 0x0B; |
| 78 | 77 | } |
| 79 | 78 | |
| 80 | 79 | /* Check IRQ $0F-$10 */ |
| 81 | | prio = ( state->m_pm_reg[0x22] >> 0 ) & 0x03; |
| 80 | prio = ( m_pm_reg[0x22] >> 0 ) & 0x03; |
| 82 | 81 | if ( ! irq_set[prio] ) |
| 83 | 82 | { |
| 84 | | if ( state->m_pm_reg[0x26] & state->m_pm_reg[0x2A] & 0x40 ) |
| 83 | if ( m_pm_reg[0x26] & m_pm_reg[0x2A] & 0x40 ) |
| 85 | 84 | irq_set[prio] = 0x10; |
| 86 | 85 | |
| 87 | | if ( state->m_pm_reg[0x26] & state->m_pm_reg[0x2A] & 0x80 ) |
| 86 | if ( m_pm_reg[0x26] & m_pm_reg[0x2A] & 0x80 ) |
| 88 | 87 | irq_set[prio] = 0x0F; |
| 89 | 88 | } |
| 90 | 89 | |
| 91 | 90 | /* Check IRQ $13-$14 */ |
| 92 | | prio = ( state->m_pm_reg[0x21] >> 4 ) & 0x03; |
| 91 | prio = ( m_pm_reg[0x21] >> 4 ) & 0x03; |
| 93 | 92 | if ( ! irq_set[prio] ) |
| 94 | 93 | { |
| 95 | | if ( state->m_pm_reg[0x24] & state->m_pm_reg[0x28] & 0x01 ) |
| 94 | if ( m_pm_reg[0x24] & m_pm_reg[0x28] & 0x01 ) |
| 96 | 95 | irq_set[prio] = 0x14; |
| 97 | 96 | |
| 98 | | if ( state->m_pm_reg[0x24] & state->m_pm_reg[0x28] & 0x02 ) |
| 97 | if ( m_pm_reg[0x24] & m_pm_reg[0x28] & 0x02 ) |
| 99 | 98 | irq_set[prio] = 0x13; |
| 100 | 99 | } |
| 101 | 100 | |
| 102 | 101 | /* Check IRQ $15-$1C */ |
| 103 | | prio = ( state->m_pm_reg[0x21] >> 2 ) & 0x03; |
| 102 | prio = ( m_pm_reg[0x21] >> 2 ) & 0x03; |
| 104 | 103 | if ( ! irq_set[prio] ) |
| 105 | 104 | { |
| 106 | | if ( state->m_pm_reg[0x25] & state->m_pm_reg[0x29] & 0x01 ) |
| 105 | if ( m_pm_reg[0x25] & m_pm_reg[0x29] & 0x01 ) |
| 107 | 106 | irq_set[prio] = 0x1C; |
| 108 | 107 | |
| 109 | | if ( state->m_pm_reg[0x25] & state->m_pm_reg[0x29] & 0x02 ) |
| 108 | if ( m_pm_reg[0x25] & m_pm_reg[0x29] & 0x02 ) |
| 110 | 109 | irq_set[prio] = 0x1B; |
| 111 | 110 | |
| 112 | | if ( state->m_pm_reg[0x25] & state->m_pm_reg[0x29] & 0x04 ) |
| 111 | if ( m_pm_reg[0x25] & m_pm_reg[0x29] & 0x04 ) |
| 113 | 112 | irq_set[prio] = 0x1A; |
| 114 | 113 | |
| 115 | | if ( state->m_pm_reg[0x25] & state->m_pm_reg[0x29] & 0x08 ) |
| 114 | if ( m_pm_reg[0x25] & m_pm_reg[0x29] & 0x08 ) |
| 116 | 115 | irq_set[prio] = 0x19; |
| 117 | 116 | |
| 118 | | if ( state->m_pm_reg[0x25] & state->m_pm_reg[0x29] & 0x10 ) |
| 117 | if ( m_pm_reg[0x25] & m_pm_reg[0x29] & 0x10 ) |
| 119 | 118 | irq_set[prio] = 0x18; |
| 120 | 119 | |
| 121 | | if ( state->m_pm_reg[0x25] & state->m_pm_reg[0x29] & 0x20 ) |
| 120 | if ( m_pm_reg[0x25] & m_pm_reg[0x29] & 0x20 ) |
| 122 | 121 | irq_set[prio] = 0x17; |
| 123 | 122 | |
| 124 | | if ( state->m_pm_reg[0x25] & state->m_pm_reg[0x29] & 0x40 ) |
| 123 | if ( m_pm_reg[0x25] & m_pm_reg[0x29] & 0x40 ) |
| 125 | 124 | irq_set[prio] = 0x16; |
| 126 | 125 | |
| 127 | | if ( state->m_pm_reg[0x25] & state->m_pm_reg[0x29] & 0x80 ) |
| 126 | if ( m_pm_reg[0x25] & m_pm_reg[0x29] & 0x80 ) |
| 128 | 127 | irq_set[prio] = 0x15; |
| 129 | 128 | } |
| 130 | 129 | |
| 131 | 130 | /* Check IRQ $1D-$1F */ |
| 132 | | prio = ( state->m_pm_reg[0x21] >> 0 ) & 0x03; |
| 133 | | if ( ! irq_set[prio] && ( state->m_pm_reg[0x26] & state->m_pm_reg[0x2A] & 0x07 ) ) |
| 131 | prio = ( m_pm_reg[0x21] >> 0 ) & 0x03; |
| 132 | if ( ! irq_set[prio] && ( m_pm_reg[0x26] & m_pm_reg[0x2A] & 0x07 ) ) |
| 134 | 133 | { |
| 135 | | if ( state->m_pm_reg[0x26] & state->m_pm_reg[0x2A] & 0x01 ) |
| 134 | if ( m_pm_reg[0x26] & m_pm_reg[0x2A] & 0x01 ) |
| 136 | 135 | irq_set[prio] = 0x1F; |
| 137 | 136 | |
| 138 | | if ( state->m_pm_reg[0x26] & state->m_pm_reg[0x2A] & 0x02 ) |
| 137 | if ( m_pm_reg[0x26] & m_pm_reg[0x2A] & 0x02 ) |
| 139 | 138 | irq_set[prio] = 0x1E; |
| 140 | 139 | |
| 141 | | if ( state->m_pm_reg[0x26] & state->m_pm_reg[0x2A] & 0x04 ) |
| 140 | if ( m_pm_reg[0x26] & m_pm_reg[0x2A] & 0x04 ) |
| 142 | 141 | irq_set[prio] = 0x1D; |
| 143 | 142 | } |
| 144 | 143 | |
| r20482 | r20483 | |
| 155 | 154 | { |
| 156 | 155 | //logerror("Triggering IRQ with vector %02x\n", vector ); |
| 157 | 156 | /* Trigger interrupt and set vector */ |
| 158 | | machine.device("maincpu")->execute().set_input_line_and_vector(0, ASSERT_LINE, vector ); |
| 157 | m_maincpu->set_input_line_and_vector(0, ASSERT_LINE, vector ); |
| 159 | 158 | } |
| 160 | 159 | else |
| 161 | 160 | { |
| 162 | | machine.device("maincpu")->execute().set_input_line(0, CLEAR_LINE ); |
| 161 | m_maincpu->set_input_line(0, CLEAR_LINE ); |
| 163 | 162 | } |
| 164 | 163 | } |
| 165 | 164 | |
| 166 | 165 | |
| 167 | | static void pokemini_update_sound( running_machine &machine ) |
| 166 | void pokemini_state::pokemini_update_sound() |
| 168 | 167 | { |
| 169 | | pokemini_state *state = machine.driver_data<pokemini_state>(); |
| 170 | | device_t *speaker = machine.device(SPEAKER_TAG); |
| 171 | 168 | /* Check if sound should be muted */ |
| 172 | | if ( state->m_pm_reg[0x70] & 0x03 ) |
| 169 | if ( m_pm_reg[0x70] & 0x03 ) |
| 173 | 170 | { |
| 174 | | speaker_level_w( speaker, 0 ); |
| 171 | speaker_level_w( m_speaker, 0 ); |
| 175 | 172 | } |
| 176 | 173 | else |
| 177 | 174 | { |
| 178 | 175 | ///static const int levels[4] = { 0, 1, 1, 2 }; |
| 179 | | int level; /// silence clang warning/// = levels[ state->m_pm_reg[0x71] & 0x03 ]; |
| 176 | int level; /// silence clang warning/// = levels[ m_pm_reg[0x71] & 0x03 ]; |
| 180 | 177 | |
| 181 | | // if ( ( ( state->m_pm_reg[0x48] & 0x80 ) && ( state->m_pm_reg[0x4E] | ( state->m_pm_reg[0x4F] << 8 ) ) > ( state->m_pm_reg[0x4C] | ( state->m_pm_reg[0x4D] << 8 ) ) ) |
| 182 | | // || ( ( state->m_pm_reg[0x48] & 0x80 ) && state->m_pm_reg[0x4F] > state->m_pm_reg[0x4D] ) ) |
| 178 | // if ( ( ( m_pm_reg[0x48] & 0x80 ) && ( m_pm_reg[0x4E] | ( m_pm_reg[0x4F] << 8 ) ) > ( m_pm_reg[0x4C] | ( m_pm_reg[0x4D] << 8 ) ) ) |
| 179 | // || ( ( m_pm_reg[0x48] & 0x80 ) && m_pm_reg[0x4F] > m_pm_reg[0x4D] ) ) |
| 183 | 180 | // { |
| 184 | 181 | level = 0; |
| 185 | 182 | // } |
| 186 | 183 | |
| 187 | | speaker_level_w( speaker, level ); |
| 184 | speaker_level_w( m_speaker, level ); |
| 188 | 185 | } |
| 189 | 186 | } |
| 190 | 187 | |
| r20482 | r20483 | |
| 234 | 231 | } |
| 235 | 232 | } |
| 236 | 233 | |
| 237 | | pokemini_check_irqs( machine() ); |
| 234 | pokemini_check_irqs(); |
| 238 | 235 | } |
| 239 | 236 | } |
| 240 | 237 | } |
| r20482 | r20483 | |
| 253 | 250 | if ( m_pm_reg[0x37] == 0xFF ) |
| 254 | 251 | { |
| 255 | 252 | m_pm_reg[0x27] |= 0x08; |
| 256 | | pokemini_check_irqs( machine() ); |
| 253 | pokemini_check_irqs(); |
| 257 | 254 | m_pm_reg[0x36] = m_pm_reg[0x32]; |
| 258 | 255 | m_pm_reg[0x37] = m_pm_reg[0x33]; |
| 259 | 256 | } |
| r20482 | r20483 | |
| 261 | 258 | else |
| 262 | 259 | { |
| 263 | 260 | m_pm_reg[0x27] |= 0x04; |
| 264 | | pokemini_check_irqs( machine() ); |
| 261 | pokemini_check_irqs(); |
| 265 | 262 | m_pm_reg[0x36] = m_pm_reg[0x32]; |
| 266 | 263 | } |
| 267 | 264 | } |
| r20482 | r20483 | |
| 275 | 272 | if ( m_pm_reg[0x37] == 0xFF ) |
| 276 | 273 | { |
| 277 | 274 | m_pm_reg[0x27] |= 0x08; |
| 278 | | pokemini_check_irqs( machine() ); |
| 275 | pokemini_check_irqs(); |
| 279 | 276 | m_pm_reg[0x37] = m_pm_reg[0x33]; |
| 280 | 277 | } |
| 281 | 278 | } |
| r20482 | r20483 | |
| 294 | 291 | if ( m_pm_reg[0x3F] == 0xFF ) |
| 295 | 292 | { |
| 296 | 293 | m_pm_reg[0x27] |= 0x20; |
| 297 | | pokemini_check_irqs( machine() ); |
| 294 | pokemini_check_irqs(); |
| 298 | 295 | m_pm_reg[0x3E] = m_pm_reg[0x3A]; |
| 299 | 296 | m_pm_reg[0x3F] = m_pm_reg[0x3B]; |
| 300 | 297 | } |
| r20482 | r20483 | |
| 302 | 299 | else |
| 303 | 300 | { |
| 304 | 301 | m_pm_reg[0x27] |= 0x10; |
| 305 | | pokemini_check_irqs( machine() ); |
| 302 | pokemini_check_irqs(); |
| 306 | 303 | m_pm_reg[0x3E] = m_pm_reg[0x3A]; |
| 307 | 304 | } |
| 308 | 305 | } |
| r20482 | r20483 | |
| 316 | 313 | if ( m_pm_reg[0x3F] == 0xFF ) |
| 317 | 314 | { |
| 318 | 315 | m_pm_reg[0x27] |= 0x20; |
| 319 | | pokemini_check_irqs( machine() ); |
| 316 | pokemini_check_irqs(); |
| 320 | 317 | m_pm_reg[0x3F] = m_pm_reg[0x3B]; |
| 321 | 318 | } |
| 322 | 319 | } |
| r20482 | r20483 | |
| 335 | 332 | if ( m_pm_reg[0x4F] == 0xFF ) |
| 336 | 333 | { |
| 337 | 334 | m_pm_reg[0x27] |= 0x02; |
| 338 | | pokemini_check_irqs( machine() ); |
| 335 | pokemini_check_irqs(); |
| 339 | 336 | m_pm_reg[0x4E] = m_pm_reg[0x4A]; |
| 340 | 337 | m_pm_reg[0x4F] = m_pm_reg[0x4B]; |
| 341 | 338 | } |
| r20482 | r20483 | |
| 351 | 348 | if ( ( m_pm_reg[0x4E] == m_pm_reg[0x4C] ) && ( m_pm_reg[0x4F] == m_pm_reg[0x4D] ) ) |
| 352 | 349 | { |
| 353 | 350 | m_pm_reg[0x27] |= 0x01; |
| 354 | | pokemini_check_irqs( machine() ); |
| 351 | pokemini_check_irqs(); |
| 355 | 352 | } |
| 356 | | pokemini_update_sound( machine() ); |
| 353 | pokemini_update_sound(); |
| 357 | 354 | } |
| 358 | 355 | } |
| 359 | 356 | |
| r20482 | r20483 | |
| 365 | 362 | if ( m_pm_reg[0x4F] == 0xFF ) |
| 366 | 363 | { |
| 367 | 364 | m_pm_reg[0x27] |= 0x02; |
| 368 | | pokemini_check_irqs( machine() ); |
| 365 | pokemini_check_irqs(); |
| 369 | 366 | m_pm_reg[0x4F] = m_pm_reg[0x4B]; |
| 370 | 367 | } |
| 371 | 368 | |
| r20482 | r20483 | |
| 374 | 371 | if( m_pm_reg[0x4F] == m_pm_reg[0x4D] ) |
| 375 | 372 | { |
| 376 | 373 | m_pm_reg[0x27] |= 0x01; |
| 377 | | pokemini_check_irqs( machine() ); |
| 374 | pokemini_check_irqs(); |
| 378 | 375 | } |
| 379 | | pokemini_update_sound( machine() ); |
| 376 | pokemini_update_sound(); |
| 380 | 377 | } |
| 381 | 378 | } |
| 382 | 379 | |
| r20482 | r20483 | |
| 454 | 451 | int index = data & 0x07; |
| 455 | 452 | int cycles = ( m_pm_reg[0x19] & 0x01 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index]; |
| 456 | 453 | |
| 457 | | m_timers.timer1->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(cycles)); |
| 454 | m_timers.timer1->adjust(attotime::zero, 0, m_maincpu->cycles_to_attotime(cycles)); |
| 458 | 455 | } |
| 459 | 456 | |
| 460 | 457 | /* Check for prescaler change for the high counter */ |
| r20482 | r20483 | |
| 463 | 460 | int index = ( data >> 4 ) & 0x07; |
| 464 | 461 | int cycles = ( m_pm_reg[0x19] & 0x02 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index]; |
| 465 | 462 | |
| 466 | | m_timers.timer1_hi->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(cycles)); |
| 463 | m_timers.timer1_hi->adjust(attotime::zero, 0, m_maincpu->cycles_to_attotime(cycles)); |
| 467 | 464 | } |
| 468 | 465 | |
| 469 | 466 | /* Check if timer1 low should be enabled */ |
| r20482 | r20483 | |
| 504 | 501 | int index = m_pm_reg[0x18] & 0x07; |
| 505 | 502 | int cycles = ( data & 0x01 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index]; |
| 506 | 503 | |
| 507 | | m_timers.timer1->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(cycles)); |
| 504 | m_timers.timer1->adjust(attotime::zero, 0, m_maincpu->cycles_to_attotime(cycles)); |
| 508 | 505 | } |
| 509 | 506 | |
| 510 | 507 | /* Check for prescaler change for the low counter */ |
| r20482 | r20483 | |
| 513 | 510 | int index = ( m_pm_reg[0x18] >> 4 ) & 0x07; |
| 514 | 511 | int cycles = ( data & 0x02 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index]; |
| 515 | 512 | |
| 516 | | m_timers.timer1_hi->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(cycles)); |
| 513 | m_timers.timer1_hi->adjust(attotime::zero, 0, m_maincpu->cycles_to_attotime(cycles)); |
| 517 | 514 | } |
| 518 | 515 | |
| 519 | 516 | { |
| r20482 | r20483 | |
| 583 | 580 | int index = data & 0x07; |
| 584 | 581 | int cycles = ( m_pm_reg[0x1B] & 0x01 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index]; |
| 585 | 582 | |
| 586 | | m_timers.timer2->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(cycles)); |
| 583 | m_timers.timer2->adjust(attotime::zero, 0, m_maincpu->cycles_to_attotime(cycles)); |
| 587 | 584 | } |
| 588 | 585 | |
| 589 | 586 | /* Check for prescaler change for the high counter */ |
| r20482 | r20483 | |
| 592 | 589 | int index = ( data >> 4 ) & 0x07; |
| 593 | 590 | int cycles = ( m_pm_reg[0x1B] & 0x02 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index]; |
| 594 | 591 | |
| 595 | | m_timers.timer2_hi->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(cycles)); |
| 592 | m_timers.timer2_hi->adjust(attotime::zero, 0, m_maincpu->cycles_to_attotime(cycles)); |
| 596 | 593 | } |
| 597 | 594 | |
| 598 | 595 | /* Check if timer2 low should be enabled */ |
| r20482 | r20483 | |
| 629 | 626 | int index = m_pm_reg[0x1A] & 0x07; |
| 630 | 627 | int cycles = ( data & 0x01 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index]; |
| 631 | 628 | |
| 632 | | m_timers.timer2->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(cycles)); |
| 629 | m_timers.timer2->adjust(attotime::zero, 0, m_maincpu->cycles_to_attotime(cycles)); |
| 633 | 630 | |
| 634 | 631 | if ( ( m_pm_reg[0x1A] & 0x08 ) && ( m_pm_reg[0x38] & 0x04 ) && |
| 635 | 632 | ( ( ( m_pm_reg[0x19] & 0x10 ) && ( data & 0x01 ) ) || |
| r20482 | r20483 | |
| 649 | 646 | int index = ( m_pm_reg[0x1A] >> 4 ) & 0x07; |
| 650 | 647 | int cycles = ( data & 0x02 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index]; |
| 651 | 648 | |
| 652 | | m_timers.timer2_hi->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(cycles)); |
| 649 | m_timers.timer2_hi->adjust(attotime::zero, 0, m_maincpu->cycles_to_attotime(cycles)); |
| 653 | 650 | |
| 654 | 651 | if ( ( m_pm_reg[0x1A] & 0x80 ) && ( m_pm_reg[0x39] & 0x04 ) && ! ( m_pm_reg[0x38] & 0x80 ) && |
| 655 | 652 | ( ( ( m_pm_reg[0x19] & 0x10 ) && ( data & 0x02 ) ) || |
| r20482 | r20483 | |
| 683 | 680 | int index = data & 0x07; |
| 684 | 681 | int cycles = ( m_pm_reg[0x1D] & 0x01 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index]; |
| 685 | 682 | |
| 686 | | m_timers.timer3->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(cycles)); |
| 683 | m_timers.timer3->adjust(attotime::zero, 0, m_maincpu->cycles_to_attotime(cycles)); |
| 687 | 684 | } |
| 688 | 685 | |
| 689 | 686 | /* Check for prescaler change for the high counter */ |
| r20482 | r20483 | |
| 692 | 689 | int index = ( data >> 4 ) & 0x07; |
| 693 | 690 | int cycles = ( m_pm_reg[0x1D] & 0x02 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index]; |
| 694 | 691 | |
| 695 | | m_timers.timer3_hi->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(cycles)); |
| 692 | m_timers.timer3_hi->adjust(attotime::zero, 0, m_maincpu->cycles_to_attotime(cycles)); |
| 696 | 693 | } |
| 697 | 694 | |
| 698 | 695 | /* Check if timer2 low should be enabled */ |
| r20482 | r20483 | |
| 729 | 726 | int index = m_pm_reg[0x1C] & 0x07; |
| 730 | 727 | int cycles = ( data & 0x01 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index]; |
| 731 | 728 | |
| 732 | | m_timers.timer3->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(cycles)); |
| 729 | m_timers.timer3->adjust(attotime::zero, 0, m_maincpu->cycles_to_attotime(cycles)); |
| 733 | 730 | |
| 734 | 731 | if ( ( m_pm_reg[0x1C] & 0x08 ) && ( m_pm_reg[0x48] & 0x04 ) && |
| 735 | 732 | ( ( ( m_pm_reg[0x19] & 0x10 ) && ( data & 0x01 ) ) || |
| r20482 | r20483 | |
| 749 | 746 | int index = ( m_pm_reg[0x1C] >> 4 ) & 0x07; |
| 750 | 747 | int cycles = ( data & 0x02 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index]; |
| 751 | 748 | |
| 752 | | m_timers.timer3_hi->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(cycles)); |
| 749 | m_timers.timer3_hi->adjust(attotime::zero, 0, m_maincpu->cycles_to_attotime(cycles)); |
| 753 | 750 | |
| 754 | 751 | if ( ( m_pm_reg[0x1C] & 0x80 ) && ( m_pm_reg[0x49] & 0x04 ) && ! ( m_pm_reg[0x48] & 0x80 ) && |
| 755 | 752 | ( ( ( m_pm_reg[0x19] & 0x10 ) && ( data & 0x02 ) ) || |
| r20482 | r20483 | |
| 770 | 767 | Bit 6-7 R/W VDraw/VBlank trigger Interrupt #1-#2 |
| 771 | 768 | */ |
| 772 | 769 | m_pm_reg[0x20] = data; |
| 773 | | pokemini_check_irqs(machine()); |
| 770 | pokemini_check_irqs(); |
| 774 | 771 | break; |
| 775 | 772 | case 0x21: /* Event #15-#22 priority |
| 776 | 773 | Bit 0-1 R/W Unknown |
| r20482 | r20483 | |
| 778 | 775 | Bit 4-7 R/W Unknown |
| 779 | 776 | */ |
| 780 | 777 | m_pm_reg[0x21] = data; |
| 781 | | pokemini_check_irqs(machine()); |
| 778 | pokemini_check_irqs(); |
| 782 | 779 | break; |
| 783 | 780 | case 0x22: /* Event #9-#14 priority |
| 784 | 781 | Bit 0-1 R/W All #9 - #14 events - Interrupt #9-#14 |
| 785 | 782 | Bit 2-7 Unused |
| 786 | 783 | */ |
| 787 | 784 | m_pm_reg[0x22] = data; |
| 788 | | pokemini_check_irqs(machine()); |
| 785 | pokemini_check_irqs(); |
| 789 | 786 | break; |
| 790 | 787 | case 0x23: /* Event #1-#8 enable |
| 791 | 788 | Bit 0 R/W Timer 3 overflow (mirror) - Enable Interrupt #8 |
| r20482 | r20483 | |
| 798 | 795 | Bit 7 R/W V-Blank trigger - Enable Interrupt #1 |
| 799 | 796 | */ |
| 800 | 797 | m_pm_reg[0x23] = data; |
| 801 | | pokemini_check_irqs(machine()); |
| 798 | pokemini_check_irqs(); |
| 802 | 799 | break; |
| 803 | 800 | case 0x24: /* Event #9-#12 enable |
| 804 | 801 | Bit 0-5 R/W Unknown |
| 805 | 802 | Bit 6-7 Unused |
| 806 | 803 | */ |
| 807 | 804 | m_pm_reg[0x24] = data; |
| 808 | | pokemini_check_irqs(machine()); |
| 805 | pokemini_check_irqs(); |
| 809 | 806 | break; |
| 810 | 807 | case 0x25: /* Event #15-#22 enable |
| 811 | 808 | Bit 0 R/W Press key "A" event - Enable interrupt #22 |
| r20482 | r20483 | |
| 818 | 815 | Bit 7 R/W Press power button event - Enable interrupt #15 |
| 819 | 816 | */ |
| 820 | 817 | m_pm_reg[0x25] = data; |
| 821 | | pokemini_check_irqs(machine()); |
| 818 | pokemini_check_irqs(); |
| 822 | 819 | break; |
| 823 | 820 | case 0x26: /* Event #13-#14 enable |
| 824 | 821 | Bit 0-2 R/W Unknown |
| r20482 | r20483 | |
| 828 | 825 | Bit 7 R/W IR receiver - low to high trigger - Enable interrupt #13 |
| 829 | 826 | */ |
| 830 | 827 | m_pm_reg[0x26] = data; |
| 831 | | pokemini_check_irqs(machine()); |
| 828 | pokemini_check_irqs(); |
| 832 | 829 | break; |
| 833 | 830 | case 0x27: /* Interrupt active flag #1-#8 |
| 834 | 831 | Bit 0 Timer 3 overflow (mirror) / Clear interrupt #8 |
| r20482 | r20483 | |
| 841 | 838 | Bit 7 VBlank trigger / Clear interrupt #1 |
| 842 | 839 | */ |
| 843 | 840 | m_pm_reg[0x27] &= ~data; |
| 844 | | pokemini_check_irqs(machine()); |
| 841 | pokemini_check_irqs(); |
| 845 | 842 | return; |
| 846 | 843 | case 0x28: /* Interrupt active flag #9-#12 |
| 847 | 844 | Bit 0-1 Unknown |
| r20482 | r20483 | |
| 852 | 849 | Bit 6-7 Unknown |
| 853 | 850 | */ |
| 854 | 851 | m_pm_reg[0x28] &= ~data; |
| 855 | | pokemini_check_irqs(machine()); |
| 852 | pokemini_check_irqs(); |
| 856 | 853 | return; |
| 857 | 854 | case 0x29: /* Interrupt active flag #15-#22 |
| 858 | 855 | Bit 0 Press key "A" event / Clear interrupt #22 |
| r20482 | r20483 | |
| 865 | 862 | Bit 7 Press power button event / Clear interrupt #15 |
| 866 | 863 | */ |
| 867 | 864 | m_pm_reg[0x29] &= ~data; |
| 868 | | pokemini_check_irqs(machine()); |
| 865 | pokemini_check_irqs(); |
| 869 | 866 | return; |
| 870 | 867 | case 0x2A: /* Interrupt active flag #13-#14 |
| 871 | 868 | Bit 0-5 Unknown |
| r20482 | r20483 | |
| 873 | 870 | Bit 7 Unknown / Clear interrupt #13 |
| 874 | 871 | */ |
| 875 | 872 | m_pm_reg[0x2A] &= ~data; |
| 876 | | pokemini_check_irqs(machine()); |
| 873 | pokemini_check_irqs(); |
| 877 | 874 | return; |
| 878 | 875 | case 0x30: /* Timer 1 control 1 |
| 879 | 876 | Bit 0 R/W Unknown |
| r20482 | r20483 | |
| 947 | 944 | */ |
| 948 | 945 | case 0x35: /* Timer 1 sound-pivot (high, unused) |
| 949 | 946 | */ |
| 950 | | logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", machine().firstcpu->pc( ), offset, data ); |
| 947 | logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", m_maincpu->pc(), offset, data ); |
| 951 | 948 | break; |
| 952 | 949 | case 0x36: /* Timer 1 counter (low), read only |
| 953 | 950 | */ |
| r20482 | r20483 | |
| 1026 | 1023 | */ |
| 1027 | 1024 | case 0x3D: /* Timer 2 sound-pivot (high, unused) |
| 1028 | 1025 | */ |
| 1029 | | logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", machine().firstcpu->pc( ), offset, data ); |
| 1026 | logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", m_maincpu->pc(), offset, data ); |
| 1030 | 1027 | break; |
| 1031 | 1028 | case 0x3E: /* Timer 2 counter (low), read only |
| 1032 | 1029 | Bit 0-7 R/W Timer 2 counter value bit 0-7 |
| r20482 | r20483 | |
| 1086 | 1083 | m_timers.timer3_hi->enable( 0 ); |
| 1087 | 1084 | } |
| 1088 | 1085 | m_pm_reg[0x48] = data; |
| 1089 | | pokemini_update_sound(machine()); |
| 1086 | pokemini_update_sound(); |
| 1090 | 1087 | break; |
| 1091 | 1088 | case 0x49: /* Timer 3 control 2 |
| 1092 | 1089 | Bit 0 R/W Unknown |
| r20482 | r20483 | |
| 1112 | 1109 | m_timers.timer3_hi->enable( 0 ); |
| 1113 | 1110 | } |
| 1114 | 1111 | m_pm_reg[0x49] = data; |
| 1115 | | pokemini_update_sound(machine()); |
| 1112 | pokemini_update_sound(); |
| 1116 | 1113 | break; |
| 1117 | 1114 | case 0x4A: /* Timer 3 preset value (low) |
| 1118 | 1115 | Bit 0-7 R/W Timer 3 preset value bit 0-7 |
| 1119 | 1116 | */ |
| 1120 | 1117 | m_pm_reg[0x4A] = data; |
| 1121 | | pokemini_update_sound(machine()); |
| 1118 | pokemini_update_sound(); |
| 1122 | 1119 | break; |
| 1123 | 1120 | case 0x4B: /* Timer 3 preset value (high) |
| 1124 | 1121 | Bit 0-7 R/W Timer 3 preset value bit 8-15 |
| 1125 | 1122 | */ |
| 1126 | 1123 | m_pm_reg[0x4B] = data; |
| 1127 | | pokemini_update_sound(machine()); |
| 1124 | pokemini_update_sound(); |
| 1128 | 1125 | break; |
| 1129 | 1126 | case 0x4C: /* Timer 3 sound-pivot (low) |
| 1130 | 1127 | Bit 0-7 R/W Timer 3 sound-pivot value bit 0-7 |
| 1131 | 1128 | */ |
| 1132 | 1129 | m_pm_reg[0x4C] = data; |
| 1133 | | pokemini_update_sound(machine()); |
| 1130 | pokemini_update_sound(); |
| 1134 | 1131 | break; |
| 1135 | 1132 | case 0x4D: /* Timer 3 sound-pivot (high) |
| 1136 | 1133 | Bit 0-7 R/W Timer 3 sound-pivot value bit 8-15 |
| r20482 | r20483 | |
| 1141 | 1138 | Pulse-Width of 100% = Same as preset-value |
| 1142 | 1139 | */ |
| 1143 | 1140 | m_pm_reg[0x4D] = data; |
| 1144 | | pokemini_update_sound(machine()); |
| 1141 | pokemini_update_sound(); |
| 1145 | 1142 | break; |
| 1146 | 1143 | case 0x4E: /* Timer 3 counter (low), read only |
| 1147 | 1144 | Bit 0-7 R/W Timer 3 counter value bit 0-7 |
| r20482 | r20483 | |
| 1184 | 1181 | Bit 7 R/W IR received bit (mirror, if device not selected: 0) |
| 1185 | 1182 | */ |
| 1186 | 1183 | if ( m_pm_reg[0x60] & 0x04 ) |
| 1187 | | i2cmem_sda_write(machine().device("i2cmem"), ( data & 0x04 ) ? 1 : 0 ); |
| 1184 | m_i2cmem->set_sda_line( ( data & 0x04 ) ? 1 : 0 ); |
| 1188 | 1185 | |
| 1189 | 1186 | if ( m_pm_reg[0x60] & 0x08 ) |
| 1190 | | i2cmem_scl_write(machine().device("i2cmem"), ( data & 0x08 ) ? 1 : 0 ); |
| 1187 | m_i2cmem->set_scl_line( ( data & 0x08 ) ? 1 : 0 ); |
| 1191 | 1188 | break; |
| 1192 | 1189 | case 0x70: /* Sound related */ |
| 1193 | 1190 | m_pm_reg[0x70] = data; |
| 1194 | | pokemini_update_sound(machine()); |
| 1191 | pokemini_update_sound(); |
| 1195 | 1192 | break; |
| 1196 | 1193 | case 0x71: /* Sound volume |
| 1197 | 1194 | Bit 0-1 R/W Sound volume |
| r20482 | r20483 | |
| 1203 | 1200 | Bit 3-7 Unused |
| 1204 | 1201 | */ |
| 1205 | 1202 | m_pm_reg[0x71] = data; |
| 1206 | | pokemini_update_sound(machine()); |
| 1203 | pokemini_update_sound(); |
| 1207 | 1204 | break; |
| 1208 | 1205 | case 0x80: /* LCD control |
| 1209 | 1206 | Bit 0 R/W Invert colors; 0 - normal, 1 - inverted |
| r20482 | r20483 | |
| 1344 | 1341 | |
| 1345 | 1342 | switch( offset ) |
| 1346 | 1343 | { |
| 1347 | | case 0x52: return ioport("INPUTS")->read(); |
| 1344 | case 0x52: return m_inputs->read(); |
| 1348 | 1345 | case 0x61: |
| 1349 | 1346 | if ( ! ( m_pm_reg[0x60] & 0x04 ) ) |
| 1350 | 1347 | { |
| 1351 | | data = ( data & ~ 0x04 ) | ( i2cmem_sda_read( machine().device("i2cmem")) ? 0x04 : 0x00 ); |
| 1348 | data = ( data & ~ 0x04 ) | ( m_i2cmem->read_sda_line() ? 0x04 : 0x00 ); |
| 1352 | 1349 | } |
| 1353 | 1350 | |
| 1354 | 1351 | if ( ! ( m_pm_reg[0x60] & 0x08 ) ) |
| r20482 | r20483 | |
| 1405 | 1402 | |
| 1406 | 1403 | TIMER_CALLBACK_MEMBER(pokemini_state::pokemini_prc_counter_callback) |
| 1407 | 1404 | { |
| 1408 | | address_space &space = machine().device( "maincpu")->memory().space( AS_PROGRAM ); |
| 1405 | address_space &space = m_maincpu->space( AS_PROGRAM ); |
| 1409 | 1406 | m_prc.count++; |
| 1410 | 1407 | |
| 1411 | 1408 | /* Check for overflow */ |
| r20482 | r20483 | |
| 1511 | 1508 | |
| 1512 | 1509 | /* Set PRC Render interrupt */ |
| 1513 | 1510 | m_pm_reg[0x27] |= 0x40; |
| 1514 | | pokemini_check_irqs( machine() ); |
| 1511 | pokemini_check_irqs(); |
| 1515 | 1512 | |
| 1516 | 1513 | /* Check if the rendered data should be copied to the LCD */ |
| 1517 | 1514 | if ( m_prc.copy_enabled ) |
| r20482 | r20483 | |
| 1535 | 1532 | |
| 1536 | 1533 | /* Set PRC Copy interrupt */ |
| 1537 | 1534 | m_pm_reg[0x27] |= 0x80; |
| 1538 | | pokemini_check_irqs( machine() ); |
| 1535 | pokemini_check_irqs(); |
| 1539 | 1536 | } |
| 1540 | 1537 | } |
| 1541 | 1538 | |
| 1542 | 1539 | /* Set possible input irqs */ |
| 1543 | | m_pm_reg[0x29] |= ~ machine().root_device().ioport( "INPUTS" )->read(); |
| 1540 | m_pm_reg[0x29] |= ~ m_inputs->read(); |
| 1544 | 1541 | } |
| 1545 | 1542 | } |
| 1546 | 1543 | |