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r20480 Saturday 26th January, 2013 at 10:27:26 UTC by Wilbert Pol
(MESS) sym1.c: cleanups (nw)
[src/mess/includes]sym1.h
[src/mess/machine]sym1.c

trunk/src/mess/machine/sym1.c
r20479r20480
7878   int data = 0x7f;
7979
8080   /* scan keypad rows */
81   if (!(m_riot_port_a & 0x80)) data &= machine().root_device().ioport("ROW-0")->read();
82   if (!(m_riot_port_b & 0x01)) data &= machine().root_device().ioport("ROW-1")->read();
83   if (!(m_riot_port_b & 0x02)) data &= machine().root_device().ioport("ROW-2")->read();
84   if (!(m_riot_port_b & 0x04)) data &= machine().root_device().ioport("ROW-3")->read();
81   if (!(m_riot_port_a & 0x80)) data &= m_row0->read();
82   if (!(m_riot_port_b & 0x01)) data &= m_row1->read();
83   if (!(m_riot_port_b & 0x02)) data &= m_row2->read();
84   if (!(m_riot_port_b & 0x04)) data &= m_row3->read();
8585
8686   /* determine column */
87   if ( ((m_riot_port_a ^ 0xff) & (ioport("ROW-0")->read() ^ 0xff)) & 0x7f )
87   if ( ((m_riot_port_a ^ 0xff) & (m_row0->read() ^ 0xff)) & 0x7f )
8888      data &= ~0x80;
8989
9090   return data;
r20479r20480
9696   int data = 0xff;
9797
9898   /* determine column */
99   if ( ((m_riot_port_a ^ 0xff) & (machine().root_device().ioport("ROW-1")->read() ^ 0xff)) & 0x7f )
99   if ( ((m_riot_port_a ^ 0xff) & (m_row1->read() ^ 0xff)) & 0x7f )
100100      data &= ~0x01;
101101
102   if ( ((m_riot_port_a ^ 0xff) & (machine().root_device().ioport("ROW-2")->read() ^ 0xff)) & 0x3f )
102   if ( ((m_riot_port_a ^ 0xff) & (m_row2->read() ^ 0xff)) & 0x3f )
103103      data &= ~0x02;
104104
105   if ( ((m_riot_port_a ^ 0xff) & (ioport("ROW-3")->read() ^ 0xff)) & 0x1f )
105   if ( ((m_riot_port_a ^ 0xff) & (m_row3->read() ^ 0xff)) & 0x1f )
106106      data &= ~0x04;
107107
108108   data &= ~0x80; // else hangs 8b02
r20479r20480
113113
114114WRITE8_MEMBER(sym1_state::sym1_riot_a_w)
115115{
116   logerror("%x: riot_a_w 0x%02x\n", machine().device("maincpu") ->safe_pc( ), data);
116   logerror("%x: riot_a_w 0x%02x\n", m_maincpu->pc(), data);
117117
118118   /* save for later use */
119119   m_riot_port_a = data;
r20479r20480
122122
123123WRITE8_MEMBER(sym1_state::sym1_riot_b_w)
124124{
125   logerror("%x: riot_b_w 0x%02x\n", machine().device("maincpu") ->safe_pc( ), data);
125   logerror("%x: riot_b_w 0x%02x\n", m_maincpu->pc(), data);
126126
127127   /* save for later use */
128128   m_riot_port_b = data;
129129
130130   /* first 4 pins are connected to the 74145 */
131   machine().device<ttl74145_device>("ttl74145")->write(data & 0x0f);
131   m_ttl74145->write(data & 0x0f);
132132}
133133
134134
r20479r20480
161161******************************************************************************/
162162
163163
164static void sym1_irq(device_t *device, int level)
164WRITE_LINE_MEMBER(sym1_state::sym1_irq)
165165{
166   device->machine().device("maincpu")->execute().set_input_line(M6502_IRQ_LINE, level);
166   m_maincpu->set_input_line(M6502_IRQ_LINE, state);
167167}
168168
169169
r20479r20480
186186 */
187187WRITE8_MEMBER(sym1_state::sym1_via2_a_w)
188188{
189   address_space &cpu0space = machine().device( "maincpu")->memory().space( AS_PROGRAM );
189   address_space &cpu0space = m_maincpu->space( AS_PROGRAM );
190190
191191   logerror("SYM1 VIA2 W 0x%02x\n", data);
192192
193   if ((machine().root_device().ioport("WP")->read() & 0x01) && !(data & 0x01)) {
193   if ((m_wp->read() & 0x01) && !(data & 0x01)) {
194194      cpu0space.nop_write(0xa600, 0xa67f);
195195   } else {
196196      cpu0space.install_write_bank(0xa600, 0xa67f, "bank5");
197197   }
198   if ((machine().root_device().ioport("WP")->read() & 0x02) && !(data & 0x02)) {
198   if ((m_wp->read() & 0x02) && !(data & 0x02)) {
199199      cpu0space.nop_write(0x0400, 0x07ff);
200200   } else {
201201      cpu0space.install_write_bank(0x0400, 0x07ff, "bank2");
202202   }
203   if ((machine().root_device().ioport("WP")->read() & 0x04) && !(data & 0x04)) {
203   if ((m_wp->read() & 0x04) && !(data & 0x04)) {
204204      cpu0space.nop_write(0x0800, 0x0bff);
205205   } else {
206206      cpu0space.install_write_bank(0x0800, 0x0bff, "bank3");
207207   }
208   if ((machine().root_device().ioport("WP")->read() & 0x08) && !(data & 0x08)) {
208   if ((m_wp->read() & 0x08) && !(data & 0x08)) {
209209      cpu0space.nop_write(0x0c00, 0x0fff);
210210   } else {
211211      cpu0space.install_write_bank(0x0c00, 0x0fff, "bank4");
r20479r20480
227227   DEVCB_NULL,           /* VIA Port CB1 Output */
228228   DEVCB_NULL,           /* VIA Port CA2 Output */
229229   DEVCB_NULL,           /* VIA Port CB2 Output */
230   DEVCB_LINE(sym1_irq)        /* VIA IRQ Callback */
230   DEVCB_DRIVER_LINE_MEMBER(sym1_state,sym1_irq)        /* VIA IRQ Callback */
231231};
232232
233233
r20479r20480
245245   DEVCB_NULL,           /* VIA Port CB1 Output */
246246   DEVCB_NULL,           /* VIA Port CA2 Output */
247247   DEVCB_NULL,           /* VIA Port CB2 Output */
248   DEVCB_LINE(sym1_irq)        /* VIA IRQ Callback */
248   DEVCB_DRIVER_LINE_MEMBER(sym1_state,sym1_irq)        /* VIA IRQ Callback */
249249};
250250
251251
r20479r20480
263263   DEVCB_NULL,           /* VIA Port CB1 Output */
264264   DEVCB_NULL,           /* VIA Port CA2 Output */
265265   DEVCB_NULL,           /* VIA Port CB2 Output */
266   DEVCB_LINE(sym1_irq)        /* VIA IRQ Callback */
266   DEVCB_DRIVER_LINE_MEMBER(sym1_state,sym1_irq)        /* VIA IRQ Callback */
267267};
268268
269269
r20479r20480
276276DRIVER_INIT_MEMBER(sym1_state,sym1)
277277{
278278   /* wipe expansion memory banks that are not installed */
279   if (machine().device<ram_device>(RAM_TAG)->size() < 4*1024)
279   if (m_ram->size() < 4*1024)
280280   {
281      machine().device( "maincpu")->memory().space( AS_PROGRAM ).nop_readwrite(
282         machine().device<ram_device>(RAM_TAG)->size(), 0x0fff);
281      m_maincpu->space(AS_PROGRAM).nop_readwrite(m_ram->size(), 0x0fff);
283282   }
284283
285284   /* allocate a timer to refresh the led display */
r20479r20480
291290{
292291   /* make 0xf800 to 0xffff point to the last half of the monitor ROM
293292      so that the CPU can find its reset vectors */
294   machine().device( "maincpu")->memory().space( AS_PROGRAM ).install_read_bank(0xf800, 0xffff, "bank1");
295   machine().device( "maincpu")->memory().space( AS_PROGRAM ).nop_write(0xf800, 0xffff);
293   m_maincpu->space( AS_PROGRAM ).install_read_bank(0xf800, 0xffff, "bank1");
294   m_maincpu->space( AS_PROGRAM ).nop_write(0xf800, 0xffff);
296295   membank("bank1")->set_base(m_monitor + 0x800);
297   machine().device("maincpu")->reset();
296   m_maincpu->reset();
298297}
trunk/src/mess/includes/sym1.h
r20479r20480
1515#include "machine/6532riot.h"
1616#include "machine/6522via.h"
1717#include "machine/74145.h"
18#include "machine/ram.h"
1819
1920/* SYM-1 main (and only) oscillator Y1 */
2021#define SYM1_CLOCK  XTAL_1MHz
r20479r20480
2425{
2526public:
2627   sym1_state(const machine_config &mconfig, device_type type, const char *tag)
27      : driver_device(mconfig, type, tag) ,
28      m_ram_1k(*this, "ram_1k"),
29      m_ram_2k(*this, "ram_2k"),
30      m_ram_3k(*this, "ram_3k"),
31      m_monitor(*this, "monitor"),
32      m_riot_ram(*this, "riot_ram"){ }
28      : driver_device(mconfig, type, tag)
29      , m_ram_1k(*this, "ram_1k")
30      , m_ram_2k(*this, "ram_2k")
31      , m_ram_3k(*this, "ram_3k")
32      , m_monitor(*this, "monitor")
33      , m_riot_ram(*this, "riot_ram")
34      , m_maincpu(*this, "maincpu")
35      , m_ram(*this, RAM_TAG)
36      , m_ttl74145(*this, "ttl74145")
37      , m_row0(*this, "ROW-0")
38      , m_row1(*this, "ROW-1")
39      , m_row2(*this, "ROW-2")
40      , m_row3(*this, "ROW-3")
41      , m_wp(*this, "WP")
42   { }
3343
3444   required_shared_ptr<UINT8> m_ram_1k;
3545   required_shared_ptr<UINT8> m_ram_2k;
r20479r20480
5565   DECLARE_READ8_MEMBER(sym1_via0_b_r);
5666   DECLARE_WRITE8_MEMBER(sym1_via0_b_w);
5767   DECLARE_WRITE8_MEMBER(sym1_via2_a_w);
68   DECLARE_WRITE_LINE_MEMBER(sym1_irq);
69
70protected:
71   required_device<cpu_device> m_maincpu;
72   required_device<ram_device> m_ram;
73   required_device<ttl74145_device> m_ttl74145;
74   required_ioport m_row0;
75   required_ioport m_row1;
76   required_ioport m_row2;
77   required_ioport m_row3;
78   required_ioport m_wp;
5879};
5980
6081/*----------- defined in machine/sym1.c -----------*/

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