trunk/src/mess/machine/gamecom.c
| r20475 | r20476 | |
| 7 | 7 | |
| 8 | 8 | TIMER_CALLBACK_MEMBER(gamecom_state::gamecom_clock_timer_callback) |
| 9 | 9 | { |
| 10 | | UINT8 * RAM = machine().root_device().memregion("maincpu")->base(); |
| 10 | UINT8 * RAM = m_region_maincpu->base(); |
| 11 | 11 | UINT8 val = ( ( RAM[SM8521_CLKT] & 0x3F ) + 1 ) & 0x3F; |
| 12 | 12 | RAM[SM8521_CLKT] = ( RAM[SM8521_CLKT] & 0xC0 ) | val; |
| 13 | | machine().device("maincpu")->execute().set_input_line(CK_INT, ASSERT_LINE ); |
| 13 | m_maincpu->set_input_line(CK_INT, ASSERT_LINE ); |
| 14 | 14 | } |
| 15 | 15 | |
| 16 | 16 | void gamecom_state::machine_reset() |
| 17 | 17 | { |
| 18 | | UINT8 *rom = memregion("kernel")->base(); |
| 19 | | membank( "bank1" )->set_base( rom ); |
| 20 | | membank( "bank2" )->set_base( rom ); |
| 21 | | membank( "bank3" )->set_base( rom ); |
| 22 | | membank( "bank4" )->set_base( rom ); |
| 18 | UINT8 *rom = m_region_kernel->base(); |
| 19 | m_bank1->set_base( rom ); |
| 20 | m_bank2->set_base( rom ); |
| 21 | m_bank3->set_base( rom ); |
| 22 | m_bank4->set_base( rom ); |
| 23 | 23 | |
| 24 | 24 | m_cartridge = NULL; |
| 25 | 25 | } |
| 26 | 26 | |
| 27 | 27 | void gamecom_state::gamecom_set_mmu(UINT8 mmu, UINT8 data ) |
| 28 | 28 | { |
| 29 | | char bank[8]; |
| 30 | | sprintf(bank,"bank%d",mmu); |
| 31 | 29 | if (data < 0x20) |
| 32 | 30 | { |
| 33 | 31 | /* select internal ROM bank */ |
| 34 | | membank( bank )->set_base( memregion("kernel")->base() + (data << 13) ); |
| 32 | switch ( mmu ) |
| 33 | { |
| 34 | case 1: m_bank1->set_base( m_region_kernel->base() + (data << 13) ); break; |
| 35 | case 2: m_bank2->set_base( m_region_kernel->base() + (data << 13) ); break; |
| 36 | case 3: m_bank3->set_base( m_region_kernel->base() + (data << 13) ); break; |
| 37 | case 4: m_bank4->set_base( m_region_kernel->base() + (data << 13) ); break; |
| 38 | } |
| 35 | 39 | } |
| 36 | 40 | else |
| 37 | 41 | { |
| 38 | 42 | /* select cartridge bank */ |
| 39 | 43 | if ( m_cartridge ) |
| 40 | | membank( bank )->set_base( m_cartridge + ( data << 13 ) ); |
| 44 | { |
| 45 | switch ( mmu ) |
| 46 | { |
| 47 | case 1: m_bank1->set_base( m_cartridge + ( data << 13 ) ); break; |
| 48 | case 2: m_bank2->set_base( m_cartridge + ( data << 13 ) ); break; |
| 49 | case 3: m_bank3->set_base( m_cartridge + ( data << 13 ) ); break; |
| 50 | case 4: m_bank4->set_base( m_cartridge + ( data << 13 ) ); break; |
| 51 | } |
| 52 | } |
| 41 | 53 | } |
| 42 | 54 | } |
| 43 | 55 | |
| r20475 | r20476 | |
| 47 | 59 | |
| 48 | 60 | if ( column == 0 ) |
| 49 | 61 | { |
| 50 | | if ( !BIT( ioport("IN2")->read(), 2) ) |
| 62 | if ( !BIT( m_io_in2->read(), 2) ) |
| 51 | 63 | { |
| 52 | | m_stylus_x = ioport("STYX")->read() >> 4; |
| 53 | | m_stylus_y = ioport("STYY")->read() >> 4; |
| 64 | m_stylus_x = m_io_styx->read() >> 4; |
| 65 | m_stylus_y = m_io_styy->read() >> 4; |
| 54 | 66 | } |
| 55 | 67 | else |
| 56 | 68 | { |
| r20475 | r20476 | |
| 139 | 151 | /* P0 bit 7 cleared => 8B (button A) */ |
| 140 | 152 | /* P1 bit 0 cleared => 8C (button B) */ |
| 141 | 153 | /* P1 bit 1 cleared => 8D (button C) */ |
| 142 | | m_p_ram[SM8521_P0] = ioport("IN0")->read(); |
| 143 | | m_p_ram[SM8521_P1] = (m_p_ram[SM8521_P1] & 0xFC) | ( ioport("IN1")->read() & 3 ); |
| 154 | m_p_ram[SM8521_P0] = m_io_in0->read(); |
| 155 | m_p_ram[SM8521_P1] = (m_p_ram[SM8521_P1] & 0xFC) | ( m_io_in1->read() & 3 ); |
| 144 | 156 | break; |
| 145 | 157 | case 0xFFFF: /* keys #2 */ |
| 146 | 158 | /* P0 bit 0 cleared => 88 (power) */ |
| r20475 | r20476 | |
| 153 | 165 | /* P0 bit 7 cleared => A0 */ |
| 154 | 166 | /* P1 bit 0 cleared => A0 */ |
| 155 | 167 | /* P1 bit 1 cleared => A0 */ |
| 156 | | m_p_ram[SM8521_P0] = (m_p_ram[SM8521_P0] & 0xFC) | ( ioport("IN2")->read() & 3 ); |
| 168 | m_p_ram[SM8521_P0] = (m_p_ram[SM8521_P0] & 0xFC) | ( m_io_in2->read() & 3 ); |
| 157 | 169 | m_p_ram[SM8521_P1] = 0xFF; |
| 158 | 170 | break; |
| 159 | 171 | } |
| r20475 | r20476 | |
| 537 | 549 | DRIVER_INIT_MEMBER(gamecom_state,gamecom) |
| 538 | 550 | { |
| 539 | 551 | m_clock_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(gamecom_state::gamecom_clock_timer_callback),this)); |
| 540 | | m_p_ram = memregion("maincpu")->base(); // required here because pio_w gets called before machine_reset |
| 552 | m_p_ram = m_region_maincpu->base(); // required here because pio_w gets called before machine_reset |
| 541 | 553 | } |
| 542 | 554 | |
| 543 | 555 | DEVICE_IMAGE_LOAD( gamecom_cart1 ) |
trunk/src/mess/includes/gamecom.h
| r20475 | r20476 | |
| 209 | 209 | { |
| 210 | 210 | public: |
| 211 | 211 | gamecom_state(const machine_config &mconfig, device_type type, const char *tag) |
| 212 | | : driver_device(mconfig, type, tag), |
| 213 | | m_maincpu(*this, "maincpu"), |
| 214 | | m_p_nvram(*this,"p_nvram"), |
| 215 | | m_p_videoram(*this,"p_videoram") { } |
| 212 | : driver_device(mconfig, type, tag) |
| 213 | , m_maincpu(*this, "maincpu") |
| 214 | , m_p_nvram(*this,"p_nvram") |
| 215 | , m_p_videoram(*this,"p_videoram") |
| 216 | , m_bank1(*this, "bank1") |
| 217 | , m_bank2(*this, "bank2") |
| 218 | , m_bank3(*this, "bank3") |
| 219 | , m_bank4(*this, "bank4") |
| 220 | , m_region_maincpu(*this, "maincpu") |
| 221 | , m_region_kernel(*this, "kernel") |
| 222 | , m_io_in0(*this, "IN0") |
| 223 | , m_io_in1(*this, "IN1") |
| 224 | , m_io_in2(*this, "IN2") |
| 225 | , m_io_styx(*this, "STYX") |
| 226 | , m_io_styy(*this, "STYY") |
| 227 | { } |
| 216 | 228 | |
| 217 | 229 | required_device<cpu_device> m_maincpu; |
| 218 | 230 | DECLARE_READ8_MEMBER( gamecom_internal_r ); |
| r20475 | r20476 | |
| 246 | 258 | INTERRUPT_GEN_MEMBER(gamecom_interrupt); |
| 247 | 259 | TIMER_CALLBACK_MEMBER(gamecom_clock_timer_callback); |
| 248 | 260 | TIMER_CALLBACK_MEMBER(gamecom_scanline); |
| 261 | |
| 262 | protected: |
| 263 | required_memory_bank m_bank1; |
| 264 | required_memory_bank m_bank2; |
| 265 | required_memory_bank m_bank3; |
| 266 | required_memory_bank m_bank4; |
| 267 | required_memory_region m_region_maincpu; |
| 268 | required_memory_region m_region_kernel; |
| 269 | required_ioport m_io_in0; |
| 270 | required_ioport m_io_in1; |
| 271 | required_ioport m_io_in2; |
| 272 | required_ioport m_io_styx; |
| 273 | required_ioport m_io_styy; |
| 249 | 274 | }; |
| 250 | 275 | |
| 251 | 276 | |