Previous

199869 Revisions

Next

r20466 Friday 25th January, 2013 at 19:07:58 UTC by Wilbert Pol
(MESS) osborne1.c: Cleanupss (nw)

[src/mess/includes]	osborne1.h
[src/mess/machine]	osborne1.c

trunk/src/mess/machine/osborne1.c

r20465	r20466
23	23	{
24	24	/* Check whether regular RAM is enabled */
25	25	if ( ! m_bank2_enabled || ( m_in_irq_handler && m_bankswitch == RAMMODE ) )
26		machine().device<ram_device>(RAM_TAG)->pointer()[ offset ] = data;
	26	{
	27	m_ram->pointer()[ offset ] = data;
	28	}
27	29	}
28	30
29	31
r20465	r20466
31	33	{
32	34	/* Check whether regular RAM is enabled */
33	35	if ( ! m_bank2_enabled || ( m_in_irq_handler && m_bankswitch == RAMMODE ) )
34		machine().device<ram_device>(RAM_TAG)->pointer()[ 0x1000 + offset ] = data;
	36	{
	37	m_ram->pointer()[ 0x1000 + offset ] = data;
	38	}
35	39	}
36	40
37	41
r20465	r20466
41	45
42	46	/* Check whether regular RAM is enabled */
43	47	if ( ! m_bank2_enabled )
44		data = machine().device<ram_device>(RAM_TAG)->pointer()[ 0x2000 + offset ];
	48	{
	49	data = m_ram->pointer()[ 0x2000 + offset ];
	50	}
45	51	else
46	52	{
47	53	switch( offset & 0x0F00 )
r20465	r20466
51	57	break;
52	58	case 0x200: /* Keyboard */
53	59	/* Row 0 */
54		if ( offset & 0x01 )    data &= ioport("ROW0")->read();
	60	if ( offset & 0x01 )    data &= m_row0->read();
55	61	/* Row 1 */
56		if ( offset & 0x02 )    data &= ioport("ROW1")->read();
	62	if ( offset & 0x02 )    data &= m_row1->read();
57	63	/* Row 2 */
58		if ( offset & 0x04 )    data &= ioport("ROW3")->read();
	64	if ( offset & 0x04 )    data &= m_row3->read();
59	65	/* Row 3 */
60		if ( offset & 0x08 )    data &= ioport("ROW4")->read();
	66	if ( offset & 0x08 )    data &= m_row4->read();
61	67	/* Row 4 */
62		if ( offset & 0x10 )    data &= ioport("ROW5")->read();
	68	if ( offset & 0x10 )    data &= m_row5->read();
63	69	/* Row 5 */
64		if ( offset & 0x20 )    data &= ioport("ROW2")->read();
	70	if ( offset & 0x20 )    data &= m_row2->read();
65	71	/* Row 6 */
66		if ( offset & 0x40 )    data &= ioport("ROW6")->read();
	72	if ( offset & 0x40 )    data &= m_row6->read();
67	73	/* Row 7 */
68		if ( offset & 0x80 )    data &= ioport("ROW7")->read();
	74	if ( offset & 0x80 )    data &= m_row7->read();
69	75	break;
70	76	case 0x900: /* IEEE488 PIA */
71	77	data = m_pia0->read(space, offset & 0x03 );
r20465	r20466
85	91	{
86	92	/* Check whether regular RAM is enabled */
87	93	if ( ! m_bank2_enabled )
88		machine().device<ram_device>(RAM_TAG)->pointer()[ 0x2000 + offset ] = data;
	94	{
	95	m_ram->pointer()[ 0x2000 + offset ] = data;
	96	}
89	97	else
90	98	{
91	99	if ( m_in_irq_handler && m_bankswitch == RAMMODE )
92	100	{
93		machine().device<ram_device>(RAM_TAG)->pointer()[ 0x2000 + offset ] = data;
	101	m_ram->pointer()[ 0x2000 + offset ] = data;
94	102	}
95	103	/* Handle writes to the I/O area */
96	104	switch( offset & 0x0F00 )
r20465	r20466
115	123	{
116	124	/* Check whether regular RAM is enabled */
117	125	if ( ! m_bank2_enabled || ( m_in_irq_handler && m_bankswitch == RAMMODE ) )
118		machine().device<ram_device>(RAM_TAG)->pointer()[ 0x3000 + offset ] = data;
	126	{
	127	m_ram->pointer()[ 0x3000 + offset ] = data;
	128	}
119	129	}
120	130
121	131
r20465	r20466
152	162	}
153	163	if ( m_bank2_enabled )
154	164	{
155		membank("bank1")->set_base(machine().root_device().memregion("maincpu")->base() );
156		membank("bank2")->set_base(m_empty_4K );
157		membank("bank3")->set_base(m_empty_4K );
	165	m_bank1->set_base(m_region_maincpu->base() );
	166	m_bank2->set_base(m_empty_4K );
	167	m_bank3->set_base(m_empty_4K );
158	168	}
159	169	else
160	170	{
161		membank("bank1")->set_base(machine().device<ram_device>(RAM_TAG)->pointer() );
162		membank("bank2")->set_base(machine().device<ram_device>(RAM_TAG)->pointer() + 0x1000 );
163		membank("bank3")->set_base(machine().device<ram_device>(RAM_TAG)->pointer() + 0x3000 );
	171	m_bank1->set_base(m_ram->pointer() );
	172	m_bank2->set_base(m_ram->pointer() + 0x1000 );
	173	m_bank3->set_base(m_ram->pointer() + 0x3000 );
164	174	}
165		m_bank4_ptr = machine().device<ram_device>(RAM_TAG)->pointer() + ( ( m_bank3_enabled ) ? 0x10000 : 0xF000 );
166		membank("bank4")->set_base(m_bank4_ptr );
	175	m_bank4_ptr = m_ram->pointer() + ( ( m_bank3_enabled ) ? 0x10000 : 0xF000 );
	176	m_bank4->set_base(m_bank4_ptr );
167	177	m_bankswitch = offset;
168	178	m_in_irq_handler = 0;
169	179	}
r20465	r20466
175	185	{
176	186	if ( ! m_bank2_enabled )
177	187	{
178		direct.explicit_configure(0x2000, 0x2fff, 0x0fff, machine().device<ram_device>(RAM_TAG)->pointer() + 0x2000);
	188	direct.explicit_configure(0x2000, 0x2fff, 0x0fff, m_ram->pointer() + 0x2000);
179	189	return ~0;
180	190	}
181	191	}
r20465	r20466
186	196	WRITE_LINE_MEMBER( osborne1_state::ieee_pia_irq_a_func )
187	197	{
188	198	m_pia_0_irq_state = state;
189		machine().device("maincpu")->execute().set_input_line(0, ( m_pia_1_irq_state ) ? ASSERT_LINE : CLEAR_LINE);
	199	m_maincpu->set_input_line(0, ( m_pia_1_irq_state ) ? ASSERT_LINE : CLEAR_LINE);
190	200	}
191	201
192	202
r20465	r20466
297	307	WRITE_LINE_MEMBER( osborne1_state::video_pia_irq_a_func )
298	308	{
299	309	m_pia_1_irq_state = state;
300		machine().device("maincpu")->execute().set_input_line(0, ( m_pia_1_irq_state ) ? ASSERT_LINE : CLEAR_LINE);
	310	m_maincpu->set_input_line(0, ( m_pia_1_irq_state ) ? ASSERT_LINE : CLEAR_LINE);
301	311	}
302	312
303	313
r20465	r20466
357	367
358	368	for ( x = 0; x < 52; x++ )
359	369	{
360		chr = machine().device<ram_device>(RAM_TAG)->pointer()[ 0xF000 + ( (ma+x) & 0xFFF ) ];
361		dim = machine().device<ram_device>(RAM_TAG)->pointer()[ 0x10000 + ( (ma+x) & 0xFFF ) ] & 0x80;
	370	chr = m_ram->pointer()[ 0xF000 + ( (ma+x) & 0xFFF ) ];
	371	dim = m_ram->pointer()[ 0x10000 + ( (ma+x) & 0xFFF ) ] & 0x80;
362	372
363	373	if ( (chr & 0x80) && (ra == 9) )
364	374	gfx = 0xFF;
r20465	r20466
424	434	void osborne1_state::machine_reset()
425	435	{
426	436	int drive;
427		address_space& space = machine().device("maincpu")->memory().space(AS_PROGRAM);
	437	address_space& space = m_maincpu->space(AS_PROGRAM);
428	438	/* Initialize memory configuration */
429	439	osborne1_bankswitch_w( space, 0x00, 0 );
430	440
r20465	r20466
434	444
435	445	m_p_chargen = memregion( "chargen" )->base();
436	446
437		memset( machine().device<ram_device>(RAM_TAG)->pointer() + 0x10000, 0xFF, 0x1000 );
	447	memset( m_ram->pointer() + 0x10000, 0xFF, 0x1000 );
438	448
439	449	for(drive=0;drive<2;drive++)
440	450	floppy_install_load_proc(floppy_get_device(machine(), drive), osborne1_load_proc);
r20465	r20466
521	531	osborne1_state *state = machine().driver_data<osborne1_state>();
522	532	/* Enable ROM and I/O when IRQ is acknowledged */
523	533	UINT8 old_bankswitch = state->m_bankswitch;
524		address_space& space = device().machine().device("maincpu")->memory().space(AS_PROGRAM);
	534	address_space& space = state->m_maincpu->space(AS_PROGRAM);
525	535
526	536	state->osborne1_bankswitch_w( space, 0, 0 );
527	537	state->m_bankswitch = old_bankswitch;

trunk/src/mess/includes/osborne1.h

r20465	r20466
23	23	{
24	24	public:
25	25	osborne1_state(const machine_config &mconfig, device_type type, const char *tag)
26		: driver_device(mconfig, type, tag),
27		m_maincpu(*this, "maincpu"),
28		m_pia0(*this, "pia_0"),
29		m_pia1(*this, "pia_1"),
30		m_fdc(*this, "mb8877"),
31		m_beep(*this, BEEPER_TAG),
32		m_ram(*this, RAM_TAG),
33		m_ieee(*this, IEEE488_TAG)
	26	: driver_device(mconfig, type, tag)
	27	, m_maincpu(*this, "maincpu")
	28	, m_pia0(*this, "pia_0")
	29	, m_pia1(*this, "pia_1")
	30	, m_fdc(*this, "mb8877")
	31	, m_beep(*this, BEEPER_TAG)
	32	, m_ram(*this, RAM_TAG)
	33	, m_ieee(*this, IEEE488_TAG)
	34	, m_row0(*this, "ROW0")
	35	, m_row1(*this, "ROW1")
	36	, m_row2(*this, "ROW2")
	37	, m_row3(*this, "ROW3")
	38	, m_row4(*this, "ROW4")
	39	, m_row5(*this, "ROW5")
	40	, m_row6(*this, "ROW6")
	41	, m_row7(*this, "ROW7")
	42	, m_bank1(*this, "bank1")
	43	, m_bank2(*this, "bank2")
	44	, m_bank3(*this, "bank3")
	45	, m_bank4(*this, "bank4")
	46	, m_region_maincpu(*this, "maincpu")
34	47	{ }
35	48
36	49	virtual void video_start();
r20465	r20466
84	97	virtual void palette_init();
85	98	TIMER_CALLBACK_MEMBER(osborne1_video_callback);
86	99	TIMER_CALLBACK_MEMBER(setup_osborne1);
	100
	101	protected:
	102	required_ioport m_row0;
	103	required_ioport m_row1;
	104	required_ioport m_row2;
	105	required_ioport m_row3;
	106	required_ioport m_row4;
	107	required_ioport m_row5;
	108	required_ioport m_row6;
	109	required_ioport m_row7;
	110	required_memory_bank m_bank1;
	111	required_memory_bank m_bank2;
	112	required_memory_bank m_bank3;
	113	required_memory_bank m_bank4;
	114	required_memory_region m_region_maincpu;
87	115	};
88	116
89	117

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team