trunk/src/emu/cpu/sh2/sh2comn.c
| r20398 | r20399 | |
|---|
| 26 | 26 | |
| 27 | 27 | INLINE UINT32 RL(sh2_state *sh2, offs_t A) |
| 28 | 28 | { |
| 29 | | if (A >= 0xe0000000) |
| 29 | if (A >= 0xe0000000) /* I/O */ |
| 30 | 30 | return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffffffff); |
| 31 | 31 | |
| 32 | | if (A >= 0xc0000000) |
| 32 | if (A >= 0xc0000000) /* Cache Data Array */ |
| 33 | 33 | return sh2->program->read_dword(A); |
| 34 | 34 | |
| 35 | | if (A >= 0x40000000) |
| 35 | /* 0x60000000 Cache Address Data Array */ |
| 36 | |
| 37 | if (A >= 0x40000000) /* Cache Associative Purge Area */ |
| 36 | 38 | return 0xa5a5a5a5; |
| 37 | 39 | |
| 40 | /* 0x20000000 no Cache */ |
| 41 | /* 0x00000000 read thru Cache if CE bit is 1 */ |
| 38 | 42 | return sh2->program->read_dword(A & AM); |
| 39 | 43 | } |
| 40 | 44 | |
| 41 | 45 | INLINE void WL(sh2_state *sh2, offs_t A, UINT32 V) |
| 42 | 46 | { |
| 43 | | if (A >= 0xe0000000) |
| 47 | if (A >= 0xe0000000) /* I/O */ |
| 44 | 48 | { |
| 45 | 49 | sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V, 0xffffffff); |
| 46 | 50 | return; |
| 47 | 51 | } |
| 48 | 52 | |
| 49 | | if (A >= 0xc0000000) |
| 53 | if (A >= 0xc0000000) /* Cache Data Array */ |
| 50 | 54 | { |
| 51 | 55 | sh2->program->write_dword(A,V); |
| 52 | 56 | return; |
| 53 | 57 | } |
| 54 | 58 | |
| 55 | | if (A >= 0x40000000) |
| 59 | /* 0x60000000 Cache Address Data Array */ |
| 60 | |
| 61 | if (A >= 0x40000000) /* Cache Associative Purge Area */ |
| 56 | 62 | return; |
| 57 | 63 | |
| 64 | /* 0x20000000 no Cache */ |
| 65 | /* 0x00000000 read thru Cache if CE bit is 1 */ |
| 58 | 66 | sh2->program->write_dword(A & AM,V); |
| 59 | 67 | } |
| 60 | 68 | |
| r20398 | r20399 | |
|---|
| 566 | 574 | |
| 567 | 575 | // Standby and cache |
| 568 | 576 | case 0x24: // SBYCR, CCR |
| 577 | /* |
| 578 | CCR |
| 579 | xx-- ---- ---- ---- Way 0/1 |
| 580 | ---x ---- ---- ---- Cache Purge (CP) |
| 581 | ---- x--- ---- ---- Two-Way Mode (TW) |
| 582 | ---- -x-- ---- ---- Data Replacement Disable (OD) |
| 583 | ---- --x- ---- ---- Instruction Replacement Disable (ID) |
| 584 | ---- ---x ---- ---- Cache Enable (CE) |
| 585 | */ |
| 569 | 586 | break; |
| 570 | 587 | |
| 571 | 588 | // Interrupt vectors cont. |
| r20398 | r20399 | |
|---|
| 711 | 728 | case 0x06: // ICR |
| 712 | 729 | return sh2->icr << 16; |
| 713 | 730 | |
| 731 | case 0x24: // SBYCR, CCR |
| 732 | return sh2->m[0x24] & ~0x3000; /* bit 4-5 of CCR are always zero */ |
| 733 | |
| 714 | 734 | case 0x38: // ICR, IPRA |
| 715 | 735 | return (sh2->m[0x38] & 0x7fffffff) | (sh2->nmi_line_state == ASSERT_LINE ? 0 : 0x80000000); |
| 716 | 736 | |