trunk/src/emu/cpu/psx/psx.c
| r20378 | r20379 | |
| 1538 | 1538 | AM_RANGE(0x1f801800, 0x1f801803) AM_READWRITE8( cd_r, cd_w, 0xffffffff ) |
| 1539 | 1539 | AM_RANGE(0x1f801810, 0x1f801817) AM_READWRITE( gpu_r, gpu_w ) |
| 1540 | 1540 | AM_RANGE(0x1f801820, 0x1f801827) AM_DEVREADWRITE( "mdec", psxmdec_device, read, write ) |
| 1541 | | AM_RANGE(0x1f801c00, 0x1f801dff) AM_READWRITE16_LEGACY( spu_r, spu_w, 0xffffffff ) |
| 1541 | AM_RANGE(0x1f801c00, 0x1f801dff) AM_READWRITE16( spu_r, spu_w, 0xffffffff ) |
| 1542 | 1542 | AM_RANGE(0x1f802020, 0x1f802033) AM_RAM /* ?? */ |
| 1543 | 1543 | /* 1f802030 int 2000 */ |
| 1544 | 1544 | /* 1f802040 dip switches */ |
| r20378 | r20379 | |
| 1566 | 1566 | AM_RANGE(0x1f801800, 0x1f801803) AM_READWRITE8( cd_r, cd_w, 0xffffffff ) |
| 1567 | 1567 | AM_RANGE(0x1f801810, 0x1f801817) AM_READWRITE( gpu_r, gpu_w ) |
| 1568 | 1568 | AM_RANGE(0x1f801820, 0x1f801827) AM_DEVREADWRITE( "mdec", psxmdec_device, read, write ) |
| 1569 | | AM_RANGE(0x1f801c00, 0x1f801dff) AM_READWRITE16_LEGACY( spu_r, spu_w, 0xffffffff ) |
| 1569 | AM_RANGE(0x1f801c00, 0x1f801dff) AM_READWRITE16( spu_r, spu_w, 0xffffffff ) |
| 1570 | 1570 | AM_RANGE(0x1f802020, 0x1f802033) AM_RAM /* ?? */ |
| 1571 | 1571 | AM_RANGE(0x1f802040, 0x1f802043) AM_WRITENOP |
| 1572 | 1572 | AM_RANGE(0x20000000, 0x7fffffff) AM_READWRITE( berr_r, berr_w ) |
| r20378 | r20379 | |
| 1590 | 1590 | m_program_config("program", ENDIANNESS_LITTLE, 32, 32, 0, internal_map), |
| 1591 | 1591 | m_gpu_read_handler(*this), |
| 1592 | 1592 | m_gpu_write_handler(*this), |
| 1593 | m_spu_read_handler(*this), |
| 1594 | m_spu_write_handler(*this), |
| 1593 | 1595 | m_cd_read_handler(*this), |
| 1594 | 1596 | m_cd_write_handler(*this) |
| 1595 | 1597 | { |
| r20378 | r20379 | |
| 1778 | 1780 | |
| 1779 | 1781 | m_gpu_read_handler.resolve_safe(0); |
| 1780 | 1782 | m_gpu_write_handler.resolve_safe(); |
| 1783 | m_spu_read_handler.resolve_safe(0); |
| 1784 | m_spu_write_handler.resolve_safe(); |
| 1781 | 1785 | m_cd_read_handler.resolve_safe(0); |
| 1782 | 1786 | m_cd_write_handler.resolve_safe(); |
| 1783 | 1787 | } |
| r20378 | r20379 | |
| 3178 | 3182 | m_gpu_write_handler( space, offset, data, mem_mask ); |
| 3179 | 3183 | } |
| 3180 | 3184 | |
| 3185 | READ16_HANDLER( psxcpu_device::spu_r ) |
| 3186 | { |
| 3187 | return m_spu_read_handler( space, offset, mem_mask ); |
| 3188 | } |
| 3189 | |
| 3190 | WRITE16_HANDLER( psxcpu_device::spu_w ) |
| 3191 | { |
| 3192 | m_spu_write_handler( space, offset, data, mem_mask ); |
| 3193 | } |
| 3194 | |
| 3181 | 3195 | READ8_HANDLER( psxcpu_device::cd_r ) |
| 3182 | 3196 | { |
| 3183 | 3197 | return m_cd_read_handler( space, offset, mem_mask ); |
trunk/src/emu/cpu/psx/psx.h
| r20378 | r20379 | |
| 115 | 115 | #define MCFG_PSX_GPU_WRITE_HANDLER(_devcb) \ |
| 116 | 116 | devcb = &psxcpu_device::set_gpu_write_handler(*device, DEVCB2_##_devcb); |
| 117 | 117 | |
| 118 | #define MCFG_PSX_SPU_READ_HANDLER(_devcb) \ |
| 119 | devcb = &psxcpu_device::set_spu_read_handler(*device, DEVCB2_##_devcb); |
| 120 | #define MCFG_PSX_SPU_WRITE_HANDLER(_devcb) \ |
| 121 | devcb = &psxcpu_device::set_spu_write_handler(*device, DEVCB2_##_devcb); |
| 122 | |
| 118 | 123 | #define MCFG_PSX_CD_READ_HANDLER(_devcb) \ |
| 119 | 124 | devcb = &psxcpu_device::set_cd_read_handler(*device, DEVCB2_##_devcb); |
| 120 | 125 | #define MCFG_PSX_CD_WRITE_HANDLER(_devcb) \ |
| r20378 | r20379 | |
| 135 | 140 | // static configuration helpers |
| 136 | 141 | template<class _Object> static devcb2_base &set_gpu_read_handler(device_t &device, _Object object) { return downcast<psxcpu_device &>(device).m_gpu_read_handler.set_callback(object); } |
| 137 | 142 | template<class _Object> static devcb2_base &set_gpu_write_handler(device_t &device, _Object object) { return downcast<psxcpu_device &>(device).m_gpu_write_handler.set_callback(object); } |
| 143 | template<class _Object> static devcb2_base &set_spu_read_handler(device_t &device, _Object object) { return downcast<psxcpu_device &>(device).m_spu_read_handler.set_callback(object); } |
| 144 | template<class _Object> static devcb2_base &set_spu_write_handler(device_t &device, _Object object) { return downcast<psxcpu_device &>(device).m_spu_write_handler.set_callback(object); } |
| 138 | 145 | template<class _Object> static devcb2_base &set_cd_read_handler(device_t &device, _Object object) { return downcast<psxcpu_device &>(device).m_cd_read_handler.set_callback(object); } |
| 139 | 146 | template<class _Object> static devcb2_base &set_cd_write_handler(device_t &device, _Object object) { return downcast<psxcpu_device &>(device).m_cd_write_handler.set_callback(object); } |
| 140 | 147 | |
| r20378 | r20379 | |
| 147 | 154 | DECLARE_WRITE32_MEMBER( gpu_w ); |
| 148 | 155 | DECLARE_READ32_MEMBER( gpu_r ); |
| 149 | 156 | |
| 157 | DECLARE_WRITE16_MEMBER( spu_w ); |
| 158 | DECLARE_READ16_MEMBER( spu_r ); |
| 159 | |
| 150 | 160 | DECLARE_WRITE8_MEMBER( cd_w ); |
| 151 | 161 | DECLARE_READ8_MEMBER( cd_r ); |
| 152 | 162 | |
| r20378 | r20379 | |
| 291 | 301 | |
| 292 | 302 | devcb2_read32 m_gpu_read_handler; |
| 293 | 303 | devcb2_write32 m_gpu_write_handler; |
| 304 | devcb2_read16 m_spu_read_handler; |
| 305 | devcb2_write16 m_spu_write_handler; |
| 294 | 306 | devcb2_read8 m_cd_read_handler; |
| 295 | 307 | devcb2_write8 m_cd_write_handler; |
| 296 | 308 | }; |
trunk/src/emu/sound/spu.c
| r20378 | r20379 | |
| 1152 | 1152 | // |
| 1153 | 1153 | // |
| 1154 | 1154 | |
| 1155 | | unsigned short spu_device::read_word(const unsigned int addr) |
| 1155 | READ16_MEMBER( spu_device::read ) |
| 1156 | 1156 | { |
| 1157 | | unsigned short ret=0, *rp=(unsigned short *)(reg+(addr&0x1ff)); |
| 1157 | unsigned short ret=0, *rp=(unsigned short *)(reg+((offset*2)&0x1ff)); |
| 1158 | 1158 | |
| 1159 | 1159 | assert((addr&1)==0); |
| 1160 | 1160 | |
| r20378 | r20379 | |
| 1164 | 1164 | |
| 1165 | 1165 | #ifdef debug_spu_registers |
| 1166 | 1166 | printf("spu: read word %08x = %04x [%s]\n", |
| 1167 | | addr, |
| 1167 | offset*2, |
| 1168 | 1168 | ret, |
| 1169 | | get_register_name(addr)); |
| 1169 | get_register_name(offset*2)); |
| 1170 | 1170 | #endif |
| 1171 | 1171 | |
| 1172 | 1172 | return ret; |
| r20378 | r20379 | |
| 1176 | 1176 | // |
| 1177 | 1177 | // |
| 1178 | 1178 | |
| 1179 | | unsigned char spu_device::read_byte(const unsigned int addr) |
| 1179 | WRITE16_MEMBER( spu_device::write ) |
| 1180 | 1180 | { |
| 1181 | | unsigned char ret=0, |
| 1182 | | *rp=reg+(addr&0x1ff); |
| 1183 | | |
| 1184 | | ret=*rp; |
| 1185 | | |
| 1186 | 1181 | #ifdef debug_spu_registers |
| 1187 | | printf("spu: read byte %08x\n",addr); |
| 1188 | | #endif |
| 1189 | | |
| 1190 | | return ret; |
| 1191 | | } |
| 1192 | | |
| 1193 | | // |
| 1194 | | // |
| 1195 | | // |
| 1196 | | |
| 1197 | | void spu_device::write_word(const unsigned int addr, const unsigned short data) |
| 1198 | | { |
| 1199 | | #ifdef debug_spu_registers |
| 1200 | 1182 | printf("spu: write %08x = %04x [%s]\n", |
| 1201 | | addr, |
| 1183 | offset*2, |
| 1202 | 1184 | data, |
| 1203 | | get_register_name(addr)); |
| 1185 | get_register_name(offset*2)); |
| 1204 | 1186 | #endif |
| 1205 | 1187 | |
| 1206 | | assert((addr&1)==0); |
| 1207 | | |
| 1208 | 1188 | m_stream->update(); |
| 1209 | 1189 | |
| 1210 | | const unsigned int a=addr&0x1ff; |
| 1190 | const unsigned int a=(offset*2)&0x1ff; |
| 1211 | 1191 | switch (a) |
| 1212 | 1192 | { |
| 1213 | 1193 | case spureg_trans_addr: |
| r20378 | r20379 | |
| 1222 | 1202 | |
| 1223 | 1203 | default: |
| 1224 | 1204 | { |
| 1225 | | unsigned short *rp=(unsigned short *)(reg+(addr&0x1ff)); |
| 1205 | unsigned short *rp=(unsigned short *)(reg+a); |
| 1226 | 1206 | |
| 1227 | 1207 | if ((a==spureg_irq_addr) || |
| 1228 | 1208 | ((a==spureg_ctrl) && ((rp[0]^data)&spuctrl_irq_enable))) |
| r20378 | r20379 | |
| 1257 | 1237 | // |
| 1258 | 1238 | // |
| 1259 | 1239 | |
| 1260 | | void spu_device::write_byte(const unsigned int addr, const unsigned char data) |
| 1261 | | { |
| 1262 | | #ifdef debug_spu_registers |
| 1263 | | printf("spu: write %08x = %02x\n",addr,data); |
| 1264 | | #endif |
| 1265 | | |
| 1266 | | const unsigned int a=addr&0x1ff; |
| 1267 | | reg[a]=data; |
| 1268 | | if ((a>spureg_reverb_config) && (a<=spureg_last)) |
| 1269 | | dirty_flags|=dirtyflag_reverb; |
| 1270 | | update_key(); |
| 1271 | | } |
| 1272 | | |
| 1273 | | // |
| 1274 | | // |
| 1275 | | // |
| 1276 | | |
| 1277 | 1240 | void spu_device::update_vol(const unsigned int addr) |
| 1278 | 1241 | { |
| 1279 | 1242 | if (addr<0x180) |
| r20378 | r20379 | |
| 3104 | 3067 | |
| 3105 | 3068 | start_dma(psxram + n_address, true, n_size*4); |
| 3106 | 3069 | } |
| 3107 | | |
| 3108 | | READ16_HANDLER( spu_r ) |
| 3109 | | { |
| 3110 | | spu_device *spu = space.machine().device<spu_device>("spu"); |
| 3111 | | |
| 3112 | | if (spu == NULL ) |
| 3113 | | { |
| 3114 | | return 0; |
| 3115 | | } |
| 3116 | | |
| 3117 | | return spu->read_word(offset*2); |
| 3118 | | } |
| 3119 | | |
| 3120 | | WRITE16_HANDLER( spu_w ) |
| 3121 | | { |
| 3122 | | spu_device *spu = space.machine().device<spu_device>("spu"); |
| 3123 | | |
| 3124 | | if (spu == NULL) |
| 3125 | | { |
| 3126 | | return; |
| 3127 | | } |
| 3128 | | |
| 3129 | | spu->write_word(offset*2, data); |
| 3130 | | } |
trunk/src/emu/sound/spu.h
| r20378 | r20379 | |
| 13 | 13 | devcb = &spu_device::set_irq_handler(*device, DEVCB2_##_devcb); |
| 14 | 14 | |
| 15 | 15 | #define MCFG_SPU_ADD(_tag, _clock) \ |
| 16 | MCFG_DEVICE_MODIFY( "maincpu" ) \ |
| 17 | MCFG_PSX_SPU_READ_HANDLER(DEVREAD16(_tag, spu_device, read)) \ |
| 18 | MCFG_PSX_SPU_WRITE_HANDLER(DEVWRITE16(_tag, spu_device, write)) \ |
| 16 | 19 | MCFG_DEVICE_ADD(_tag, SPU, _clock) \ |
| 17 | 20 | MCFG_SPU_IRQ_HANDLER(DEVWRITELINE("maincpu:irq", psxirq_device, intin9)) \ |
| 18 | 21 | MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 4, psx_dma_read_delegate( FUNC( spu_device::dma_read ), (spu_device *) device ) ) \ |
| r20378 | r20379 | |
| 234 | 237 | void flush_xa(const unsigned int sector=0); |
| 235 | 238 | void flush_cdda(const unsigned int sector=0); |
| 236 | 239 | |
| 237 | | unsigned char read_byte(const unsigned int addr); |
| 238 | | unsigned short read_word(const unsigned int addr); |
| 239 | | void write_byte(const unsigned int addr, const unsigned char byte); |
| 240 | | void write_word(const unsigned int addr, const unsigned short word); |
| 241 | | |
| 242 | 240 | sound_stream *m_stream; |
| 241 | |
| 242 | DECLARE_READ16_MEMBER( read ); |
| 243 | DECLARE_WRITE16_MEMBER( write ); |
| 243 | 244 | }; |
| 244 | 245 | |
| 245 | 246 | extern reverb_params *spu_reverb_cfg; |
| r20378 | r20379 | |
| 247 | 248 | // device type definition |
| 248 | 249 | extern const device_type SPU; |
| 249 | 250 | |
| 250 | | // MAME old-style interface |
| 251 | | DECLARE_READ16_HANDLER( spu_r ); |
| 252 | | DECLARE_WRITE16_HANDLER( spu_w ); |
| 253 | | |
| 254 | 251 | #endif |
trunk/src/mame/drivers/taitogn.c
| r20378 | r20379 | |
| 812 | 812 | AM_RANGE(0x1fa10300, 0x1fa10303) AM_READWRITE(znsecsel_r, znsecsel_w) |
| 813 | 813 | AM_RANGE(0x1fa20000, 0x1fa20003) AM_READWRITE(coin_r, coin_w) |
| 814 | 814 | AM_RANGE(0x1fa30000, 0x1fa30003) AM_READWRITE(control3_r, control3_w) |
| 815 | | AM_RANGE(0x1fa51c00, 0x1fa51dff) AM_READWRITE16_LEGACY(spu_r, spu_w, 0xffffffff) // systematic read at spu_address + 250000, result dropped, maybe other accesses |
| 815 | AM_RANGE(0x1fa51c00, 0x1fa51dff) AM_READNOP // systematic read at spu_address + 250000, result dropped, maybe other accesses |
| 816 | 816 | AM_RANGE(0x1fa60000, 0x1fa60003) AM_READ(hack1_r) |
| 817 | 817 | AM_RANGE(0x1faf0000, 0x1faf07ff) AM_DEVREADWRITE8_LEGACY("at28c16", at28c16_r, at28c16_w, 0xffffffff) /* eeprom */ |
| 818 | 818 | AM_RANGE(0x1fb00000, 0x1fb0ffff) AM_READWRITE(rf5c296_io_r, rf5c296_io_w) |