MAME SVN History

199869 Revisions

r20340 Saturday 19th January, 2013 at 12:25:09 UTC by Phil Bennett
Modernised the R3000 core: [Phil Bennett] * The following variants are supported: R3041, R3051, R3052, R3071 and R3081 * Endianness is now specified by MCFG_R3000_ENDIANNESS() (default is big-endian) * Removed configuration struct. Cache sizes and FPU availability are now determined from the CPU type * Added state saving * Added BrCond input callbacks

[src/emu/cpu/mips]	r3000.c r3000.h
[src/mame/drivers]	jaguar.c policetr.c speglsht.c srmp5.c turrett.c

trunk/src/emu/cpu/mips/r3000.c
r20339	r20340
1	1	/***************************************************************************
2	2
3		r3000->c
	3	r3000.c
4	4	Core implementation for the portable MIPS R3000 emulator.
5	5	Written by Aaron Giles
6	6
r20339	r20340
10	10	#include "debugger.h"
11	11	#include "r3000.h"
12	12
13		CPU_DISASSEMBLE( r3000be );
14		CPU_DISASSEMBLE( r3000le );
15	13
16	14	#define ENABLE_OVERFLOWS 0
17	15
r20339	r20340
73	71	#define EXCEPTION_TRAP 13
74	72
75	73
76
77	74	/***************************************************************************
78	75	HELPER MACROS
79	76	***************************************************************************/
80	77
81		#define RSREG ((op >> 21) & 31)
82		#define RTREG ((op >> 16) & 31)
83		#define RDREG ((op >> 11) & 31)
84		#define SHIFT ((op >> 6) & 31)
	78	#define RSREG ((m_op >> 21) & 31)
	79	#define RTREG ((m_op >> 16) & 31)
	80	#define RDREG ((m_op >> 11) & 31)
	81	#define SHIFT ((m_op >> 6) & 31)
85	82
86		#define RSVAL r[RSREG]
87		#define RTVAL r[RTREG]
88		#define RDVAL r[RDREG]
	83	#define RSVAL m_r[RSREG]
	84	#define RTVAL m_r[RTREG]
	85	#define RDVAL m_r[RDREG]
89	86
90		#define SIMMVAL ((INT16)op)
91		#define UIMMVAL ((UINT16)op)
92		#define LIMMVAL (op & 0x03ffffff)
	87	#define SIMMVAL ((INT16)m_op)
	88	#define UIMMVAL ((UINT16)m_op)
	89	#define LIMMVAL (m_op & 0x03ffffff)
93	90
94		#define ADDPC(R,x) do { (R)->nextpc = (R)->pc + ((x) << 2); } while (0)
95		#define ADDPCL(R,x,l) do { (R)->nextpc = (R)->pc + ((x) << 2); (R)->r[l] = (R)->pc + 4; } while (0)
96		#define ABSPC(R,x) do { (R)->nextpc = ((R)->pc & 0xf0000000) \| ((x) << 2); } while (0)
97		#define ABSPCL(R,x,l) do { (R)->nextpc = ((R)->pc & 0xf0000000) \| ((x) << 2); (R)->r[l] = (R)->pc + 4; } while (0)
98		#define SETPC(R,x) do { (R)->nextpc = (x); } while (0)
99		#define SETPCL(R,x,l) do { (R)->nextpc = (x); (R)->r[l] = (R)->pc + 4; } while (0)
	91	#define ADDPC(x) do { m_nextpc = m_pc + ((x) << 2); } while (0)
	92	#define ADDPCL(x,l) do { m_nextpc = m_pc + ((x) << 2); m_r[l] = m_pc + 4; } while (0)
	93	#define ABSPC(x) do { m_nextpc = (m_pc & 0xf0000000) \| ((x) << 2); } while (0)
	94	#define ABSPCL(x,l) do { m_nextpc = (m_pc & 0xf0000000) \| ((x) << 2); m_r[l] = m_pc + 4; } while (0)
	95	#define SETPC(x) do { m_nextpc = (x); } while (0)
	96	#define SETPCL(x,l) do { m_nextpc = (x); m_r[l] = m_pc + 4; } while (0)
100	97
101		#define RBYTE(R,x) ((R)->cur.read_byte)((R)->program, x)
102		#define RWORD(R,x) ((R)->cur.read_word)((R)->program, x)
103		#define RLONG(R,x) ((R)->cur.read_dword)((R)->program, x)
	98	#define RBYTE(x) (this->*m_cur->m_read_byte)(x)
	99	#define RWORD(x) (this->*m_cur->m_read_word)(x)
	100	#define RLONG(x) (this->*m_cur->m_read_dword)(x)
104	101
105		#define WBYTE(R,x,v) ((R)->cur.write_byte)((R)->program, x, v)
106		#define WWORD(R,x,v) ((R)->cur.write_word)((R)->program, x, v)
107		#define WLONG(R,x,v) ((R)->cur.write_dword)((R)->program, x, v)
	102	#define WBYTE(x,v) (this->*m_cur->m_write_byte)(x, v)
	103	#define WWORD(x,v) (this->*m_cur->m_write_word)(x, v)
	104	#define WLONG(x,v) (this->*m_cur->m_write_dword)(x, v)
108	105
109		#define SR cpr[0][COP0_Status]
110		#define CAUSE cpr[0][COP0_Cause]
	106	#define SR m_cpr[0][COP0_Status]
	107	#define CAUSE m_cpr[0][COP0_Cause]
111	108
112	109
	110	//**************************************************************************
	111	// DEVICE INTERFACE
	112	//**************************************************************************
113	113
114		/***************************************************************************
115		STRUCTURES & TYPEDEFS
116		***************************************************************************/
	114	const device_type R3041 = &device_creator<r3041_device>;
	115	const device_type R3051 = &device_creator<r3051_device>;
	116	const device_type R3052 = &device_creator<r3052_device>;
	117	const device_type R3071 = &device_creator<r3071_device>;
	118	const device_type R3081 = &device_creator<r3081_device>;
117	119
118		/* R3000 Registers */
119		struct r3000_state
120		{
121		/* core registers */
122		UINT32 pc;
123		UINT32 hi;
124		UINT32 lo;
125		UINT32 r[32];
126	120
127		/* COP registers */
128		UINT32 cpr[4][32];
129		UINT32 ccr[4][32];
130		UINT8 cf[4];
	121	//-------------------------------------------------
	122	// r3000_device - constructor
	123	//-------------------------------------------------
131	124
132		/* internal stuff */
133		UINT32 ppc;
134		UINT32 nextpc;
135		int op;
136		int icount;
137		int interrupt_cycles;
138		int hasfpu;
139		device_irq_acknowledge_callback irq_callback;
140		legacy_cpu_device *device;
141		address_space *program;
142		direct_read_data *direct;
	125	r3000_device::r3000_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock, chip_type chiptype)
	126	: cpu_device(mconfig, type, name, tag, owner, clock),
	127	m_program_config_be("program", ENDIANNESS_BIG, 32, 29),
	128	m_program_config_le("program", ENDIANNESS_LITTLE, 32, 29),
	129	m_program(NULL),
	130	m_direct(NULL),
	131	m_chip_type(chiptype),
	132	m_hasfpu(false),
	133	m_endianness(ENDIANNESS_BIG),
	134	m_pc(0),
	135	m_nextpc(0),
	136	m_hi(0),
	137	m_lo(0),
	138	m_ppc(0),
	139	m_op(0),
	140	m_icount(0),
	141	m_interrupt_cycles(0),
	142	m_in_brcond0(*this),
	143	m_in_brcond1(*this),
	144	m_in_brcond2(*this),
	145	m_in_brcond3(*this)
	146	{
	147	// set our instruction counter
	148	m_icountptr = &m_icount;
143	149
144		/* endian-dependent load/store */
145		void (lwl)(r3000_state r3000, UINT32 op);
146		void (lwr)(r3000_state r3000, UINT32 op);
147		void (swl)(r3000_state r3000, UINT32 op);
148		void (swr)(r3000_state r3000, UINT32 op);
	150	// clear some additional state
	151	memset(m_r, 0, sizeof(m_r));
	152	memset(m_cpr, 0, sizeof(m_cpr));
	153	memset(m_ccr, 0, sizeof(m_ccr));
	154	}
149	155
150		/* memory accesses */
151		UINT8 bigendian;
152		data_accessors cur;
153		data_accessors memory_hand;
154		const data_accessors *cache_hand;
155	156
156		/* cache memory */
157		UINT32 * cache;
158		UINT32 * icache;
159		UINT32 * dcache;
160		size_t cache_size;
161		size_t icache_size;
162		size_t dcache_size;
163		};
	157	//-------------------------------------------------
	158	// ~r3000_device - destructor
	159	//-------------------------------------------------
164	160
165		~~INLINE~~ r3000_~~state get_safe_token(~~device_t device)
	161	r3000_device::~r3000_device()
166	162	{
167		assert(device != NULL);
168		assert(device->type() == R3000BE \|\|
169		device->type() == R3000LE \|\|
170		device->type() == R3041BE \|\|
171		device->type() == R3041LE);
172		return (r3000_state )downcast<legacy_cpu_device >(device)->token();
173	163	}
174	164
175	165
176		/***************************************************************************
177		FUNCTION PROTOTYPES
178		***************************************************************************/
	166	//-------------------------------------------------
	167	// r3041_device - constructor
	168	//-------------------------------------------------
179	169
180		static void lwl_be(r3000_state *r3000, UINT32 op);
181		static void lwr_be(r3000_state *r3000, UINT32 op);
182		static void swl_be(r3000_state *r3000, UINT32 op);
183		static void swr_be(r3000_state *r3000, UINT32 op);
	170	r3041_device::r3041_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	171	: r3000_device(mconfig, R3041, "R3041", tag, owner, clock, CHIP_TYPE_R3041) { }
184	172
185		static void lwl_le(r3000_state *r3000, UINT32 op);
186		static void lwr_le(r3000_state *r3000, UINT32 op);
187		static void swl_le(r3000_state *r3000, UINT32 op);
188		static void swr_le(r3000_state *r3000, UINT32 op);
189	173
190		static UINT8 readcache_be(address_space &space, offs_t offset);
191		static UINT16 readcache_be_word(address_space &space, offs_t offset);
192		static UINT32 readcache_be_dword(address_space &space, offs_t offset);
193		static void writecache_be(address_space &space, offs_t offset, UINT8 data);
194		static void writecache_be_word(address_space &space, offs_t offset, UINT16 data);
195		static void writecache_be_dword(address_space &space, offs_t offset, UINT32 data);
	174	//-------------------------------------------------
	175	// r3051_device - constructor
	176	//-------------------------------------------------
196	177
197		static UINT8 readcache_le(address_space &space, offs_t offset);
198		static UINT16 readcache_le_word(address_space &space, offs_t offset);
199		static UINT32 readcache_le_dword(address_space &space, offs_t offset);
200		static void writecache_le(address_space &space, offs_t offset, UINT8 data);
201		static void writecache_le_word(address_space &space, offs_t offset, UINT16 data);
202		static void writecache_le_dword(address_space &space, offs_t offset, UINT32 data);
	178	r3051_device::r3051_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	179	: r3000_device(mconfig, R3051, "R3051", tag, owner, clock, CHIP_TYPE_R3051) { }
203	180
204	181
	182	//-------------------------------------------------
	183	// r3052_device - constructor
	184	//-------------------------------------------------
205	185
206		/***************************************************************************
207		PRIVATE GLOBAL VARIABLES
208		***************************************************************************/
	186	r3052_device::r3052_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	187	: r3000_device(mconfig, R3052, "R3052", tag, owner, clock, CHIP_TYPE_R3052) { }
209	188
210		static const data_accessors be_cache =
	189
	190	//-------------------------------------------------
	191	// r3071_device - constructor
	192	//-------------------------------------------------
	193
	194	r3071_device::r3071_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	195	: r3000_device(mconfig, R3071, "R3071", tag, owner, clock, CHIP_TYPE_R3071) { }
	196
	197
	198	//-------------------------------------------------
	199	// r3081_device - constructor
	200	//-------------------------------------------------
	201
	202	r3081_device::r3081_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	203	: r3000_device(mconfig, R3081, "R3081", tag, owner, clock, CHIP_TYPE_R3081) { }
	204
	205
	206	//-------------------------------------------------
	207	// device_start - start up the device
	208	//-------------------------------------------------
	209
	210	void r3000_device::device_start()
211	211	{
212		readcache_be, readcache_be_word, NULL, readcache_be_dword, NULL, NULL, NULL,
213		writecache_be, writecache_be_word, NULL, writecache_be_dword, NULL, NULL, NULL
214		};
	212	// get our address spaces
	213	m_program = &space(AS_PROGRAM);
	214	m_direct = &m_program->direct();
215	215
216		static const data_accessors le_cache =
	216	// determine the cache sizes
	217	switch (m_chip_type)
	218	{
	219	case CHIP_TYPE_R3041:
	220	{
	221	m_icache_size = 2048;
	222	m_dcache_size = 512;
	223	break;
	224	}
	225	case CHIP_TYPE_R3051:
	226	{
	227	m_icache_size = 4096;
	228	m_dcache_size = 2048;
	229	break;
	230	}
	231	case CHIP_TYPE_R3052:
	232	{
	233	m_icache_size = 8192;
	234	m_dcache_size = 2048;
	235	break;
	236	}
	237
	238	// TODO: R3071 and R3081 have configurable cache sizes
	239	case CHIP_TYPE_R3071:
	240	{
	241	m_icache_size = 16384; // or 8kB
	242	m_dcache_size = 4096; // or 8kB
	243	break;
	244	}
	245	case CHIP_TYPE_R3081:
	246	{
	247	m_icache_size = 16384; // or 8kB
	248	m_dcache_size = 4096; // or 8kB
	249	m_hasfpu = true;
	250	break;
	251	}
	252	}
	253
	254	// allocate cache memory
	255	m_icache = auto_alloc_array(machine(), UINT32, m_icache_size/4);
	256	m_dcache = auto_alloc_array(machine(), UINT32, m_dcache_size/4);
	257
	258	m_cache = m_dcache;
	259	m_cache_size = m_dcache_size;
	260
	261	// set up memory handlers
	262	m_memory_hand.m_read_byte = &r3000_device::readmem;
	263	m_memory_hand.m_read_word = &r3000_device::readmem_word;
	264	m_memory_hand.m_read_dword = &r3000_device::readmem_dword;
	265	m_memory_hand.m_write_byte = &r3000_device::writemem;
	266	m_memory_hand.m_write_word = &r3000_device::writemem_word;
	267	m_memory_hand.m_write_dword = &r3000_device::writemem_dword;
	268
	269	if (m_endianness == ENDIANNESS_BIG)
	270	{
	271	m_lwl = &r3000_device::lwl_be;
	272	m_lwr = &r3000_device::lwr_be;
	273	m_swl = &r3000_device::swl_be;
	274	m_swr = &r3000_device::swr_be;
	275
	276	m_cache_hand.m_read_byte = &r3000_device::readcache_be;
	277	m_cache_hand.m_read_word = &r3000_device::readcache_be_word;
	278	m_cache_hand.m_read_dword = &r3000_device::readcache_be_dword;
	279	m_cache_hand.m_write_byte = &r3000_device::writecache_be;
	280	m_cache_hand.m_write_word = &r3000_device::writecache_be_word;
	281	m_cache_hand.m_write_dword = &r3000_device::writecache_be_dword;
	282	}
	283	else
	284	{
	285	m_lwl = &r3000_device::lwl_le;
	286	m_lwr = &r3000_device::lwr_le;
	287	m_swl = &r3000_device::swl_le;
	288	m_swr = &r3000_device::swr_le;
	289
	290	m_cache_hand.m_read_byte = &r3000_device::readcache_le;
	291	m_cache_hand.m_read_word = &r3000_device::readcache_le_word;
	292	m_cache_hand.m_read_dword = &r3000_device::readcache_le_dword;
	293	m_cache_hand.m_write_byte = &r3000_device::writecache_le;
	294	m_cache_hand.m_write_word = &r3000_device::writecache_le_word;
	295	m_cache_hand.m_write_dword = &r3000_device::writecache_le_dword;
	296	}
	297
	298	// resolve conditional branch input handlers
	299	m_in_brcond0.resolve_safe(0);
	300	m_in_brcond1.resolve_safe(0);
	301	m_in_brcond2.resolve_safe(0);
	302	m_in_brcond3.resolve_safe(0);
	303
	304	// register our state for the debugger
	305	state_add(STATE_GENPC, "GENPC", m_pc).noshow();
	306	state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc).noshow();
	307	state_add(STATE_GENSP, "GENSP", m_r[31]).noshow();
	308	state_add(STATE_GENFLAGS, "GENFLAGS", SR).callimport().callexport().formatstr("%6s").noshow();
	309	state_add(R3000_PC, "PC", m_pc);
	310	state_add(R3000_SR, "SR", SR);
	311	state_add(R3000_R0, "R0", m_r[0]);
	312	state_add(R3000_R1, "R1", m_r[1]);
	313	state_add(R3000_R2, "R2", m_r[2]);
	314	state_add(R3000_R3, "R3", m_r[3]);
	315	state_add(R3000_R4, "R4", m_r[4]);
	316	state_add(R3000_R5, "R5", m_r[5]);
	317	state_add(R3000_R6, "R6", m_r[6]);
	318	state_add(R3000_R7, "R7", m_r[7]);
	319	state_add(R3000_R8, "R8", m_r[8]);
	320	state_add(R3000_R9, "R9", m_r[9]);
	321	state_add(R3000_R10, "R10", m_r[10]);
	322	state_add(R3000_R11, "R11", m_r[11]);
	323	state_add(R3000_R12, "R12", m_r[12]);
	324	state_add(R3000_R13, "R13", m_r[13]);
	325	state_add(R3000_R14, "R14", m_r[14]);
	326	state_add(R3000_R15, "R15", m_r[15]);
	327	state_add(R3000_R16, "R16", m_r[16]);
	328	state_add(R3000_R17, "R17", m_r[17]);
	329	state_add(R3000_R18, "R18", m_r[18]);
	330	state_add(R3000_R19, "R19", m_r[19]);
	331	state_add(R3000_R20, "R20", m_r[20]);
	332	state_add(R3000_R21, "R21", m_r[21]);
	333	state_add(R3000_R22, "R22", m_r[22]);
	334	state_add(R3000_R23, "R23", m_r[23]);
	335	state_add(R3000_R24, "R24", m_r[24]);
	336	state_add(R3000_R25, "R25", m_r[25]);
	337	state_add(R3000_R26, "R26", m_r[26]);
	338	state_add(R3000_R27, "R27", m_r[27]);
	339	state_add(R3000_R28, "R28", m_r[28]);
	340	state_add(R3000_R29, "R29", m_r[29]);
	341	state_add(R3000_R30, "R30", m_r[30]);
	342	state_add(R3000_R31, "R31", m_r[31]);
	343
	344	// register our state for saving
	345	save_item(NAME(m_pc));
	346	save_item(NAME(m_nextpc));
	347	save_item(NAME(m_hi));
	348	save_item(NAME(m_lo));
	349	save_item(NAME(m_r));
	350	save_item(NAME(m_cpr));
	351	save_item(NAME(m_ccr));
	352	save_item(NAME(m_ppc));
	353	save_item(NAME(m_op));
	354	save_item(NAME(m_interrupt_cycles));
	355	save_pointer(NAME(m_icache), m_icache_size/4);
	356	save_pointer(NAME(m_dcache), m_dcache_size/4);
	357	}
	358
	359
	360	//-------------------------------------------------
	361	// device_post_load -
	362	//-------------------------------------------------
	363	void r3000_device::device_post_load()
217	364	{
218		readcache_le, readcache_le_word, NULL, readcache_le_dword, NULL, NULL, NULL,
219		writecache_le, writecache_le_word, NULL, writecache_le_dword, NULL, NULL, NULL
220		};
	365	if (m_cpr[0][COP0_Status] & SR_IsC)
	366	m_cur = &m_cache_hand;
	367	else
	368	m_cur = &m_memory_hand;
	369	}
221	370
222	371
	372	//-------------------------------------------------
	373	// device_reset - reset the device
	374	//-------------------------------------------------
223	375
224		/***************************************************************************
225		MEMORY ACCESSORS
226		***************************************************************************/
	376	void r3000_device::device_reset()
	377	{
	378	// initialize the rest of the config
	379	m_cur = &m_memory_hand;
227	380
228		#define ROPCODE(R,pc) (R)->direct->read_decrypted_dword(pc)
	381	// initialize the state
	382	m_pc = 0xbfc00000;
	383	m_nextpc = ~0;
	384	m_cpr[0][COP0_PRId] = 0x0200;
	385	m_cpr[0][COP0_Status] = 0x0000;
	386	}
229	387
230	388
	389	//-------------------------------------------------
	390	// memory_space_config - return the configuration
	391	// of the specified address space, or NULL if
	392	// the space doesn't exist
	393	//-------------------------------------------------
231	394
232		/***************************************************************************
233		EXECEPTION HANDLING
234		***************************************************************************/
	395	const address_space_config *r3000_device::memory_space_config(address_spacenum spacenum) const
	396	{
	397	if (spacenum == AS_PROGRAM)
	398	return (m_endianness == ENDIANNESS_BIG) ? &m_program_config_be : &m_program_config_le;
	399	else
	400	return NULL;
	401	}
235	402
236		INLINE void generate_exception(r3000_state *r3000, int exception)
	403
	404	//-------------------------------------------------
	405	// state_import - import state into the device,
	406	// after it has been set
	407	//-------------------------------------------------
	408
	409	void r3000_device::state_import(const device_state_entry &entry)
237	410	{
238		/* set the exception PC */
239		r3000->cpr[0][COP0_EPC] = r3000->pc;
	411	switch (entry.index())
	412	{
	413	case STATE_GENFLAGS:
	414	break;
240	415
241		/* put the cause in the low 8 bits and clear the branch delay flag */
242		r3000->CAUSE = (r3000->CAUSE & ~0x800000ff) \| (exception << 2);
	416	default:
	417	fatalerror("r3000_device::state_import called for unexpected value\n");
	418	break;
	419	}
	420	}
243	421
244		/* if we were in a branch delay slot, adjust */
245		if (r3000->nextpc != ~0)
	422
	423	//-------------------------------------------------
	424	// state_export - export state out of the device
	425	//-------------------------------------------------
	426
	427	void r3000_device::state_export(const device_state_entry &entry)
	428	{
	429	switch (entry.index())
246	430	{
247		r3000->nextpc = ~0;
248		r3000->cpr[0][COP0_EPC] -= 4;
249		r3000->CAUSE \|= 0x80000000;
	431	case STATE_GENFLAGS:
	432	break;
	433
	434	default:
	435	fatalerror("r3000_device::state_export called for unexpected value\n");
	436	break;
250	437	}
	438	}
251	439
252		/* shift the exception bits */
253		r3000->SR = (r3000->SR & 0xffffffc0) \| ((r3000->SR << 2) & 0x3c);
254	440
255		/* based on the BEV bit, we either go to ROM or RAM */
256		r3000->pc = (r3000->SR & SR_BEV) ? 0xbfc00000 : 0x80000000;
	441	//-------------------------------------------------
	442	// state_string_export - export state as a string
	443	// for the debugger
	444	//-------------------------------------------------
257	445
258		/* most exceptions go to offset 0x180, except for TLB stuff */
259		if (exception >= EXCEPTION_TLBMOD && exception <= EXCEPTION_TLBSTORE)
260		r3000->pc += 0x80;
	446	void r3000_device::state_string_export(const device_state_entry &entry, astring &string)
	447	{
	448	switch (entry.index())
	449	{
	450	case STATE_GENFLAGS:
	451	break;
	452	}
	453	}
	454
	455
	456	//-------------------------------------------------
	457	// disasm_min_opcode_bytes - return the length
	458	// of the shortest instruction, in bytes
	459	//-------------------------------------------------
	460
	461	UINT32 r3000_device::disasm_min_opcode_bytes() const
	462	{
	463	return 4;
	464	}
	465
	466
	467	//-------------------------------------------------
	468	// disasm_max_opcode_bytes - return the length
	469	// of the longest instruction, in bytes
	470	//-------------------------------------------------
	471
	472	UINT32 r3000_device::disasm_max_opcode_bytes() const
	473	{
	474	return 4;
	475	}
	476
	477
	478	//-------------------------------------------------
	479	// disasm_disassemble - call the disassembly
	480	// helper function
	481	//-------------------------------------------------
	482
	483	offs_t r3000_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
	484	{
	485	extern CPU_DISASSEMBLE( r3000le );
	486	extern CPU_DISASSEMBLE( r3000be );
	487
	488	if (m_endianness == ENDIANNESS_BIG)
	489	return CPU_DISASSEMBLE_NAME(r3000be)(NULL, buffer, pc, oprom, opram, 0);
261	490	else
262		r3000->pc += 0~~x180~~;
	491	return CPU_DISASSEMBLE_NAME(r3000le)(NULL, buffer, pc, oprom, opram, 0);
263	492	}
264	493
265	494
266		INLINE void invalid_instruction(r3000_state *r3000, UINT32 op)
	495	/***************************************************************************
	496	MEMORY ACCESSORS
	497	***************************************************************************/
	498
	499	inline UINT32 r3000_device::readop(off_t pc)
267	500	{
268		generate_exception(r~~3000, EXCEPTION_INVALIDOP~~);
	501	return m_direct->read_decrypted_dword(pc);
269	502	}
270	503
	504	UINT8 r3000_device::readmem(offs_t offset)
	505	{
	506	return m_program->read_byte(offset);
	507	}
271	508
	509	UINT16 r3000_device::readmem_word(offs_t offset)
	510	{
	511	return m_program->read_word(offset);
	512	}
272	513
	514	UINT32 r3000_device::readmem_dword(offs_t offset)
	515	{
	516	return m_program->read_dword(offset);
	517	}
	518
	519	void r3000_device::writemem(offs_t offset, UINT8 data)
	520	{
	521	m_program->write_byte(offset, data);
	522	}
	523
	524	void r3000_device::writemem_word(offs_t offset, UINT16 data)
	525	{
	526	m_program->write_word(offset, data);
	527	}
	528
	529	void r3000_device::writemem_dword(offs_t offset, UINT32 data)
	530	{
	531	m_program->write_dword(offset, data);
	532	}
	533
	534
273	535	/***************************************************************************
274		IRQ HANDLING
	536	BIG ENDIAN CACHE I/O
275	537	***************************************************************************/
276	538
277		~~static~~ void check_~~irqs~~(~~r3000_~~st~~ate~~ *r3000)
	539	UINT8 r3000_device::readcache_be(offs_t offset)
278	540	{
279		if ((r3000->CAUSE & r3000->SR & 0xff00) && (r3000->SR & SR_IEc))
280		generate_exception(r3000, EXCEPTION_INTERRUPT);
	541	offset &= 0x1fffffff;
	542	return (offset * 4 < m_cache_size) ? m_cache[BYTE4_XOR_BE(offset)] : 0xff;
281	543	}
282	544
	545	UINT16 r3000_device::readcache_be_word(offs_t offset)
	546	{
	547	offset &= 0x1fffffff;
	548	return (offset * 4 < m_cache_size) ? (UINT16 )&m_cache[WORD_XOR_BE(offset)] : 0xffff;
	549	}
283	550
284		~~static~~ ~~void set_i~~r~~q_line(r~~3000_~~stat~~e *r3000, i~~nt i~~r~~qlin~~e~~, in~~t s~~tat~~e)
	551	UINT32 r3000_device::readcache_be_dword(offs_t offset)
285	552	{
286		if (state != CLEAR_LINE)
287		r3000->CAUSE \|= 0x400 << irqline;
288		else
289		r3000->CAUSE &= ~(0x400 << irqline);
290		check_irqs(r3000);
	553	offset &= 0x1fffffff;
	554	return (offset * 4 < m_cache_size) ? (UINT32 )&m_cache[offset] : 0xffffffff;
291	555	}
292	556
	557	void r3000_device::writecache_be(offs_t offset, UINT8 data)
	558	{
	559	offset &= 0x1fffffff;
	560	if (offset * 4 < m_cache_size) m_cache[BYTE4_XOR_BE(offset)] = data;
	561	}
293	562
	563	void r3000_device::writecache_be_word(offs_t offset, UINT16 data)
	564	{
	565	offset &= 0x1fffffff;
	566	if (offset * 4 < m_cache_size) (UINT16 )&m_cache[WORD_XOR_BE(offset)] = data;
	567	}
294	568
	569	void r3000_device::writecache_be_dword(offs_t offset, UINT32 data)
	570	{
	571	offset &= 0x1fffffff;
	572	if (offset * 4 < m_cache_size) (UINT32 )&m_cache[offset] = data;
	573	}
	574
	575	UINT8 r3000_device::readcache_le(offs_t offset)
	576	{
	577	offset &= 0x1fffffff;
	578	return (offset * 4 < m_cache_size) ? m_cache[BYTE4_XOR_LE(offset)] : 0xff;
	579	}
	580
	581
295	582	/***************************************************************************
296		INITIALIZA~~TIO~~N A~~ND S~~H~~UTD~~OWN
	583	LITTLE ENDIAN CACHE I/O
297	584	***************************************************************************/
298	585
299		~~static CP~~U_INIT( r3000 )
	586	UINT16 r3000_device::readcache_le_word(offs_t offset)
300	587	{
301		const r3000_cpu_core configdata = (const r3000_cpu_core )device->static_config();
302		r3000_state *r3000 = get_safe_token(device);
	588	offset &= 0x1fffffff;
	589	return (offset * 4 < m_cache_size) ? (UINT16 )&m_cache[WORD_XOR_LE(offset)] : 0xffff;
	590	}
303	591
304		/* allocate memory */
305		r3000->icache = auto_alloc_array(device->machine(), UINT32, configdata->icache/4);
306		r3000->dcache = auto_alloc_array(device->machine(), UINT32, configdata->dcache/4);
	592	UINT32 r3000_device::readcache_le_dword(offs_t offset)
	593	{
	594	offset &= 0x1fffffff;
	595	return (offset * 4 < m_cache_size) ? (UINT32 )&m_cache[offset] : 0xffffffff;
	596	}
307	597
308		r3000->icache_size = configdata->icache;
309		r3000->dcache_size = configdata->dcache;
310		r3000->hasfpu = configdata->hasfpu;
	598	void r3000_device::writecache_le(offs_t offset, UINT8 data)
	599	{
	600	offset &= 0x1fffffff;
	601	if (offset * 4 < m_cache_size) m_cache[BYTE4_XOR_LE(offset)] = data;
	602	}
311	603
312		r3000->irq_callback = irqcallback;
313		r3000->device = device;
314		r3000->program = &device->space(AS_PROGRAM);
315		r3000->direct = &r3000->program->direct();
	604	void r3000_device::writecache_le_word(offs_t offset, UINT16 data)
	605	{
	606	offset &= 0x1fffffff;
	607	if (offset * 4 < m_cache_size) (UINT16 )&m_cache[WORD_XOR_LE(offset)] = data;
316	608	}
317	609
	610	void r3000_device::writecache_le_dword(offs_t offset, UINT32 data)
	611	{
	612	offset &= 0x1fffffff;
	613	if (offset * 4 < m_cache_size) (UINT32 )&m_cache[offset] = data;
	614	}
318	615
319		static void r3000_reset(r3000_state *r3000, int bigendian)
	616
	617	/***************************************************************************
	618	EXECEPTION HANDLING
	619	***************************************************************************/
	620
	621	inline void r3000_device::generate_exception(int exception)
320	622	{
321		/* set up the endianness */
322		r3000->bigendian = bigendian;
323		r3000->program->accessors(r3000->memory_hand);
324		if (r3000->bigendian)
	623	// set the exception PC
	624	m_cpr[0][COP0_EPC] = m_pc;
	625
	626	// put the cause in the low 8 bits and clear the branch delay flag
	627	CAUSE = (CAUSE & ~0x800000ff) \| (exception << 2);
	628
	629	// if we were in a branch delay slot, adjust
	630	if (m_nextpc != ~0)
325	631	{
326		r3000->cache_hand = &be_cache;
327		r3000->lwl = lwl_be;
328		r3000->lwr = lwr_be;
329		r3000->swl = swl_be;
330		r3000->swr = swr_be;
	632	m_nextpc = ~0;
	633	m_cpr[0][COP0_EPC] -= 4;
	634	CAUSE \|= 0x80000000;
331	635	}
332		else
333		{
334		r3000->cache_hand = &le_cache;
335		r3000->lwl = lwl_le;
336		r3000->lwr = lwr_le;
337		r3000->swl = swl_le;
338		r3000->swr = swr_le;
339		}
340	636
341		/* initialize the rest of the config */
342		r3000->cur = r3000->memory_hand;
343		r3000->cache = r3000->dcache;
344		r3000->cache_size = r3000->dcache_size;
	637	// shift the exception bits
	638	SR = (SR & 0xffffffc0) \| ((SR << 2) & 0x3c);
345	639
346		/* initialize the state */
347		r3000->pc = 0xbfc00000;
348		r3000->nextpc = ~0;
349		r3000->cpr[0][COP0_PRId] = 0x0200;
350		r3000->cpr[0][COP0_Status] = 0x0000;
	640	// based on the BEV bit, we either go to ROM or RAM
	641	m_pc = (SR & SR_BEV) ? 0xbfc00000 : 0x80000000;
	642
	643	// most exceptions go to offset 0x180, except for TLB stuff
	644	if (exception >= EXCEPTION_TLBMOD && exception <= EXCEPTION_TLBSTORE)
	645	m_pc += 0x80;
	646	else
	647	m_pc += 0x180;
351	648	}
352	649
353		static CPU_RESET( r3000be )
	650
	651	inline void r3000_device::invalid_instruction()
354	652	{
355		~~r3000_r~~eset(get_~~saf~~e_token(~~device), 1~~);
	653	generate_exception(EXCEPTION_INVALIDOP);
356	654	}
357	655
358		static CPU_RESET( r3000le )
	656
	657	/***************************************************************************
	658	IRQ HANDLING
	659	***************************************************************************/
	660
	661	void r3000_device::check_irqs()
359	662	{
360		r3000_reset(get_safe_token(device), 0);
	663	if ((CAUSE & SR & 0xff00) && (SR & SR_IEc))
	664	generate_exception(EXCEPTION_INTERRUPT);
361	665	}
362	666
363	667
364		~~stat~~ic ~~CPU_EXIT(~~ r3000 )
	668	void r3000_device::set_irq_line(int irqline, int state)
365	669	{
	670	if (state != CLEAR_LINE)
	671	CAUSE \|= 0x400 << irqline;
	672	else
	673	CAUSE &= ~(0x400 << irqline);
	674
	675	check_irqs();
366	676	}
367	677
368	678
369
370	679	/***************************************************************************
371	680	COP0 (SYSTEM) EXECUTION HANDLING
372	681	***************************************************************************/
373	682
374		~~INLINE~~ UINT32 get_cop0_reg(~~r3000_state *r3000,~~ int idx)
	683	inline UINT32 r3000_device::get_cop0_reg(int idx)
375	684	{
376		return ~~r3000->~~cpr[0][idx];
	685	return m_cpr[0][idx];
377	686	}
378	687
379		~~INLINE~~ void set_cop0_reg(~~r3000_state *r3000,~~ int idx, UINT32 val)
	688	inline void r3000_device::set_cop0_reg(int idx, UINT32 val)
380	689	{
381	690	if (idx == COP0_Cause)
382	691	{
383		~~r3000->~~CAUSE = (~~r3000->~~CAUSE & 0xfc00) \| (val & ~0xfc00);
	692	CAUSE = (CAUSE & 0xfc00) \| (val & ~0xfc00);
384	693
385		/* update interrupts -- software ints can occur this way */
386		check_irqs(r3000);
	694	// update interrupts -- software ints can occur this way
	695	check_irqs();
387	696	}
388	697	else if (idx == COP0_Status)
389	698	{
390		UINT32 oldsr = ~~r3000->~~cpr[0][idx];
	699	UINT32 oldsr = m_cpr[0][idx];
391	700	UINT32 diff = oldsr ^ val;
392	701
393		/* handle cache isolation */
	702	// handle cache isolation
394	703	if (diff & SR_IsC)
395	704	{
396	705	if (val & SR_IsC)
397		~~r3000->~~cur = *r3000->cache_hand;
	706	m_cur = &m_cache_hand;
398	707	else
399		~~r3000->~~cur = ~~r3000->~~memory_hand;
	708	m_cur = &m_memory_hand;
400	709	}
401	710
402		/* handle cache switching */
	711	// handle cache switching
403	712	if (diff & SR_SwC)
404	713	{
405	714	if (val & SR_SwC)
406		~~r3000->~~cache = ~~r3000->~~icache, ~~r3000->~~cache_size = ~~r3000->~~icache_size;
	715	m_cache = m_icache, m_cache_size = m_icache_size;
407	716	else
408		~~r3000->~~cache = ~~r3000->~~dcache, ~~r3000->~~cache_size = ~~r3000->~~dcache_size;
	717	m_cache = m_dcache, m_cache_size = m_dcache_size;
409	718	}
410		~~r3000->~~cpr[0][idx] = val;
	719	m_cpr[0][idx] = val;
411	720
412		/* update interrupts */
413		check_irqs(r3000);
	721	// update interrupts
	722	check_irqs();
414	723	}
415	724	else
416		~~r3000->~~cpr[0][idx] = val;
	725	m_cpr[0][idx] = val;
417	726	}
418	727
419		~~INLINE~~ UINT32 get_cop0_creg(~~r3000_state *r3000,~~ int idx)
	728	inline UINT32 r3000_device::get_cop0_creg(int idx)
420	729	{
421		return ~~r3000->~~ccr[0][idx];
	730	return m_ccr[0][idx];
422	731	}
423	732
424		~~INLINE~~ void set_cop0_creg(~~r3000_state *r3000,~~ int idx, UINT32 val)
	733	inline void r3000_device::set_cop0_creg(int idx, UINT32 val)
425	734	{
426		~~r3000->~~ccr[0][idx] = val;
	735	m_ccr[0][idx] = val;
427	736	}
428	737
429		~~INLINE~~ void handle_cop0(~~r3000_state *r3000, UINT32 op~~)
	738	inline void r3000_device::handle_cop0()
430	739	{
431		if (!(r3000->SR & SR_COP0) && (r3000->SR & SR_KUc))
432		generate_exception(r3000, EXCEPTION_BADCOP);
	740	if (!(SR & SR_COP0) && (SR & SR_KUc))
	741	generate_exception(EXCEPTION_BADCOP);
433	742
434	743	switch (RSREG)
435	744	{
436		case 0x00: /* MFCz */ if (RTREG) r3000->RTVAL = get_cop0_reg(r3000, RDREG); break;
437		case 0x02: /* CFCz */ if (RTREG) r3000->RTVAL = get_cop0_creg(r3000, RDREG); break;
438		case 0x04: /* MTCz */ set_cop0_reg(r3000, RDREG, r3000->RTVAL); break;
439		case 0x06: /* CTCz */ set_cop0_creg(r3000, RDREG, r3000->RTVAL); break;
	745	case 0x00: /* MFCz */ if (RTREG) RTVAL = get_cop0_reg(RDREG); break;
	746	case 0x02: /* CFCz */ if (RTREG) RTVAL = get_cop0_creg(RDREG); break;
	747	case 0x04: /* MTCz */ set_cop0_reg(RDREG, RTVAL); break;
	748	case 0x06: /* CTCz */ set_cop0_creg(RDREG, RTVAL); break;
440	749	case 0x08: /* BC */
441	750	switch (RTREG)
442	751	{
443		case 0x00: /* BCzF */ if (!r3000->cf[0]) ADDPC(r3000, SIMMVAL); break;
444		case 0x01: /* BCzF */ if (r3000->cf[0]) ADDPC(r3000, SIMMVAL); break;
445		case 0x02: /* BCzFL */ invalid_instruction(r3000, op); break;
446		case 0x03: /* BCzTL */ invalid_instruction(r3000, op); break;
447		default: invalid_instruction(r3000, op); break;
	752	case 0x00: /* BCzF */ if (!m_in_brcond0()) ADDPC(SIMMVAL); break;
	753	case 0x01: /* BCzT */ if (m_in_brcond0()) ADDPC(SIMMVAL); break;
	754	case 0x02: /* BCzFL */ invalid_instruction(); break;
	755	case 0x03: /* BCzTL */ invalid_instruction(); break;
	756	default: invalid_instruction(); break;
448	757	}
449	758	break;
450	759	case 0x10:
r20339	r20340
463	772	case 0x1d:
464	773	case 0x1e:
465	774	case 0x1f: /* COP */
466		switch (op & 0x01ffffff)
	775	switch (m_op & 0x01ffffff)
467	776	{
468	777	case 0x01: /* TLBR */ break;
469	778	case 0x02: /* TLBWI */ break;
470	779	case 0x06: /* TLBWR */ break;
471	780	case 0x08: /* TLBP */ break;
472		case 0x10: /* RFE */ r3000->SR = (r3000->SR & 0xfffffff0) \| ((r3000->SR >> 2) & 0x0f); break;
473		case 0x18: /* ERET */ invalid_instruction(r3000, op); break;
474		default: invalid_instruction(r3000, op); break;
	781	case 0x10: /* RFE */ SR = (SR & 0xfffffff0) \| ((SR >> 2) & 0x0f); break;
	782	case 0x18: /* ERET */ invalid_instruction(); break;
	783	default: invalid_instruction(); break;
475	784	}
476	785	break;
477		default: invalid_instruction(~~r3000, op~~); break;
	786	default: invalid_instruction(); break;
478	787	}
479	788	}
480	789
481	790
482
483	791	/***************************************************************************
484	792	COP1 (FPU) EXECUTION HANDLING
485	793	***************************************************************************/
486	794
487		~~INLINE~~ UINT32 get_cop1_reg(~~r3000_state *r3000,~~ int idx)
	795	inline UINT32 r3000_device::get_cop1_reg(int idx)
488	796	{
489		return ~~r3000->~~cpr[1][idx];
	797	return m_cpr[1][idx];
490	798	}
491	799
492		~~INLINE~~ void set_cop1_reg(~~r3000_state *r3000,~~ int idx, UINT32 val)
	800	inline void r3000_device::set_cop1_reg(int idx, UINT32 val)
493	801	{
494		~~r3000->~~cpr[1][idx] = val;
	802	m_cpr[1][idx] = val;
495	803	}
496	804
497		~~INLINE~~ UINT32 get_cop1_creg(~~r3000_state *r3000,~~ int idx)
	805	inline UINT32 r3000_device::get_cop1_creg(int idx)
498	806	{
499		return ~~r3000->~~ccr[1][idx];
	807	return m_ccr[1][idx];
500	808	}
501	809
502		~~INLINE~~ void set_cop1_creg(~~r3000_state *r3000,~~ int idx, UINT32 val)
	810	inline void r3000_device::set_cop1_creg(int idx, UINT32 val)
503	811	{
504		~~r3000->~~ccr[1][idx] = val;
	812	m_ccr[1][idx] = val;
505	813	}
506	814
507		~~INLINE~~ void handle_cop1(~~r3000_state *r3000, UINT32 op~~)
	815	inline void r3000_device::handle_cop1()
508	816	{
509		if (!(r3000->SR & SR_COP1))
510		generate_exception(r3000, EXCEPTION_BADCOP);
511		if (!r3000->hasfpu)
	817	if (!(SR & SR_COP1))
	818	generate_exception(EXCEPTION_BADCOP);
	819	if (!m_hasfpu)
512	820	return;
513	821
514	822	switch (RSREG)
515	823	{
516		case 0x00: /* MFCz */ if (RTREG) r3000->RTVAL = get_cop1_reg(r3000, RDREG); break;
517		case 0x02: /* CFCz */ if (RTREG) r3000->RTVAL = get_cop1_creg(r3000, RDREG); break;
518		case 0x04: /* MTCz */ set_cop1_reg(r3000, RDREG, r3000->RTVAL); break;
519		case 0x06: /* CTCz */ set_cop1_creg(r3000, RDREG, r3000->RTVAL); break;
	824	case 0x00: /* MFCz */ if (RTREG) RTVAL = get_cop1_reg(RDREG); break;
	825	case 0x02: /* CFCz */ if (RTREG) RTVAL = get_cop1_creg(RDREG); break;
	826	case 0x04: /* MTCz */ set_cop1_reg(RDREG, RTVAL); break;
	827	case 0x06: /* CTCz */ set_cop1_creg(RDREG, RTVAL); break;
520	828	case 0x08: /* BC */
521	829	switch (RTREG)
522	830	{
523		case 0x00: /* BCzF */ if (!r3000->cf[1]) ADDPC(r3000, SIMMVAL); break;
524		case 0x01: /* BCzF */ if (r3000->cf[1]) ADDPC(r3000, SIMMVAL); break;
525		case 0x02: /* BCzFL */ invalid_instruction(r3000, op); break;
526		case 0x03: /* BCzTL */ invalid_instruction(r3000, op); break;
527		default: invalid_instruction(r3000, op); break;
	831	case 0x00: /* BCzF */ if (!m_in_brcond1()) ADDPC(SIMMVAL); break;
	832	case 0x01: /* BCzT */ if (m_in_brcond1()) ADDPC(SIMMVAL); break;
	833	case 0x02: /* BCzFL */ invalid_instruction(); break;
	834	case 0x03: /* BCzTL */ invalid_instruction(); break;
	835	default: invalid_instruction(); break;
528	836	}
529	837	break;
530	838	case 0x10:
r20339	r20340
542	850	case 0x1c:
543	851	case 0x1d:
544	852	case 0x1e:
545		case 0x1f: /* COP */ invalid_instruction(r3000, op); break;
546		default: invalid_instruction(r3000, op); break;
	853	case 0x1f: /* COP */ invalid_instruction(); break;
	854	default: invalid_instruction(); break;
547	855	}
548	856	}
549	857
550	858
551
552	859	/***************************************************************************
553	860	COP2 (CUSTOM) EXECUTION HANDLING
554	861	***************************************************************************/
555	862
556		~~INLINE~~ UINT32 get_cop2_reg(~~r3000_state *r3000,~~ int idx)
	863	inline UINT32 r3000_device::get_cop2_reg(int idx)
557	864	{
558		return ~~r3000->~~cpr[2][idx];
	865	return m_cpr[2][idx];
559	866	}
560	867
561		~~INLINE~~ void set_cop2_reg(~~r3000_state *r3000,~~ int idx, UINT32 val)
	868	inline void r3000_device::set_cop2_reg(int idx, UINT32 val)
562	869	{
563		~~r3000->~~cpr[2][idx] = val;
	870	m_cpr[2][idx] = val;
564	871	}
565	872
566		~~INLINE~~ UINT32 get_cop2_creg(~~r3000_state *r3000,~~ int idx)
	873	inline UINT32 r3000_device::get_cop2_creg(int idx)
567	874	{
568		return ~~r3000->~~ccr[2][idx];
	875	return m_ccr[2][idx];
569	876	}
570	877
571		~~INLINE~~ void set_cop2_creg(~~r3000_state *r3000,~~ int idx, UINT32 val)
	878	inline void r3000_device::set_cop2_creg(int idx, UINT32 val)
572	879	{
573		~~r3000->~~ccr[2][idx] = val;
	880	m_ccr[2][idx] = val;
574	881	}
575	882
576		~~INLINE~~ void handle_cop2(~~r3000_state *r3000, UINT32 op~~)
	883	inline void r3000_device::handle_cop2()
577	884	{
578		if (!(r3000->SR & SR_COP2))
579		generate_exception(r3000, EXCEPTION_BADCOP);
	885	if (!(SR & SR_COP2))
	886	generate_exception(EXCEPTION_BADCOP);
580	887
581	888	switch (RSREG)
582	889	{
583		case 0x00: /* MFCz */ if (RTREG) r3000->RTVAL = get_cop2_reg(r3000, RDREG); break;
584		case 0x02: /* CFCz */ if (RTREG) r3000->RTVAL = get_cop2_creg(r3000, RDREG); break;
585		case 0x04: /* MTCz */ set_cop2_reg(r3000, RDREG, r3000->RTVAL); break;
586		case 0x06: /* CTCz */ set_cop2_creg(r3000, RDREG, r3000->RTVAL); break;
	890	case 0x00: /* MFCz */ if (RTREG) RTVAL = get_cop2_reg(RDREG); break;
	891	case 0x02: /* CFCz */ if (RTREG) RTVAL = get_cop2_creg(RDREG); break;
	892	case 0x04: /* MTCz */ set_cop2_reg(RDREG, RTVAL); break;
	893	case 0x06: /* CTCz */ set_cop2_creg(RDREG, RTVAL); break;
587	894	case 0x08: /* BC */
588	895	switch (RTREG)
589	896	{
590		case 0x00: /* BCzF */ if (!r3000->cf[2]) ADDPC(r3000, SIMMVAL); break;
591		case 0x01: /* BCzF */ if (r3000->cf[2]) ADDPC(r3000, SIMMVAL); break;
592		case 0x02: /* BCzFL */ invalid_instruction(r3000, op); break;
593		case 0x03: /* BCzTL */ invalid_instruction(r3000, op); break;
594		default: invalid_instruction(r3000, op); break;
	897	case 0x00: /* BCzF */ if (!m_in_brcond2()) ADDPC(SIMMVAL); break;
	898	case 0x01: /* BCzT */ if (m_in_brcond2()) ADDPC(SIMMVAL); break;
	899	case 0x02: /* BCzFL */ invalid_instruction(); break;
	900	case 0x03: /* BCzTL */ invalid_instruction(); break;
	901	default: invalid_instruction(); break;
595	902	}
596	903	break;
597	904	case 0x10:
r20339	r20340
609	916	case 0x1c:
610	917	case 0x1d:
611	918	case 0x1e:
612		case 0x1f: /* COP */ invalid_instruction(r3000, op); break;
613		default: invalid_instruction(r3000, op); break;
	919	case 0x1f: /* COP */ invalid_instruction(); break;
	920	default: invalid_instruction(); break;
614	921	}
615	922	}
616	923
617	924
618
619	925	/***************************************************************************
620	926	COP3 (CUSTOM) EXECUTION HANDLING
621	927	***************************************************************************/
622	928
623		~~INLINE~~ UINT32 get_cop3_reg(~~r3000_state *r3000,~~ int idx)
	929	inline UINT32 r3000_device::get_cop3_reg(int idx)
624	930	{
625		return ~~r3000->~~cpr[3][idx];
	931	return m_cpr[3][idx];
626	932	}
627	933
628		~~INLINE~~ void set_cop3_reg(~~r3000_state *r3000,~~ int idx, UINT32 val)
	934	inline void r3000_device::set_cop3_reg(int idx, UINT32 val)
629	935	{
630		~~r3000->~~cpr[3][idx] = val;
	936	m_cpr[3][idx] = val;
631	937	}
632	938
633		~~INLINE~~ UINT32 get_cop3_creg(~~r3000_state *r3000,~~ int idx)
	939	inline UINT32 r3000_device::get_cop3_creg(int idx)
634	940	{
635		return ~~r3000->~~ccr[3][idx];
	941	return m_ccr[3][idx];
636	942	}
637	943
638		~~INLINE~~ void set_cop3_creg(~~r3000_state *r3000,~~ int idx, UINT32 val)
	944	inline void r3000_device::set_cop3_creg(int idx, UINT32 val)
639	945	{
640		~~r3000->~~ccr[3][idx] = val;
	946	m_ccr[3][idx] = val;
641	947	}
642	948
643		~~INLINE~~ void handle_cop3(~~r3000_state *r3000, UINT32 op~~)
	949	inline void r3000_device::handle_cop3()
644	950	{
645		if (!(r3000->SR & SR_COP3))
646		generate_exception(r3000, EXCEPTION_BADCOP);
	951	if (!(SR & SR_COP3))
	952	generate_exception(EXCEPTION_BADCOP);
647	953
648	954	switch (RSREG)
649	955	{
650		case 0x00: /* MFCz */ if (RTREG) r3000->RTVAL = get_cop3_reg(r3000, RDREG); break;
651		case 0x02: /* CFCz */ if (RTREG) r3000->RTVAL = get_cop3_creg(r3000, RDREG); break;
652		case 0x04: /* MTCz */ set_cop3_reg(r3000, RDREG, r3000->RTVAL); break;
653		case 0x06: /* CTCz */ set_cop3_creg(r3000, RDREG, r3000->RTVAL); break;
	956	case 0x00: /* MFCz */ if (RTREG) RTVAL = get_cop3_reg(RDREG); break;
	957	case 0x02: /* CFCz */ if (RTREG) RTVAL = get_cop3_creg(RDREG); break;
	958	case 0x04: /* MTCz */ set_cop3_reg(RDREG, RTVAL); break;
	959	case 0x06: /* CTCz */ set_cop3_creg(RDREG, RTVAL); break;
654	960	case 0x08: /* BC */
655	961	switch (RTREG)
656	962	{
657		case 0x00: /* BCzF */ if (!r3000->cf[3]) ADDPC(r3000, SIMMVAL); break;
658		case 0x01: /* BCzF */ if (r3000->cf[3]) ADDPC(r3000, SIMMVAL); break;
659		case 0x02: /* BCzFL */ invalid_instruction(r3000, op); break;
660		case 0x03: /* BCzTL */ invalid_instruction(r3000, op); break;
661		default: invalid_instruction(r3000, op); break;
	963	case 0x00: /* BCzF */ if (!m_in_brcond3()) ADDPC(SIMMVAL); break;
	964	case 0x01: /* BCzT */ if (m_in_brcond3()) ADDPC(SIMMVAL); break;
	965	case 0x02: /* BCzFL */ invalid_instruction(); break;
	966	case 0x03: /* BCzTL */ invalid_instruction(); break;
	967	default: invalid_instruction(); break;
662	968	}
663	969	break;
664	970	case 0x10:
r20339	r20340
676	982	case 0x1c:
677	983	case 0x1d:
678	984	case 0x1e:
679		case 0x1f: /* COP */ invalid_instruction(r3000, op); break;
680		default: invalid_instruction(r3000, op); break;
	985	case 0x1f: /* COP */ invalid_instruction(); break;
	986	default: invalid_instruction(); break;
681	987	}
682	988	}
683	989
684	990
685
686	991	/***************************************************************************
687	992	CORE EXECUTION LOOP
688	993	***************************************************************************/
689	994
690		static CPU_EXECUTE( r3000 )
	995	//-------------------------------------------------
	996	// execute_min_cycles - return minimum number of
	997	// cycles it takes for one instruction to execute
	998	//-------------------------------------------------
	999
	1000	UINT32 r3000_device::execute_min_cycles() const
691	1001	{
692		r3000_state *r3000 = get_safe_token(device);
	1002	return 1;
	1003	}
693	1004
694		/* count cycles and interrupt cycles */
695		r3000->icount -= r3000->interrupt_cycles;
696		r3000->interrupt_cycles = 0;
697	1005
698		/* check for IRQs */
699		check_irqs(r3000);
	1006	//-------------------------------------------------
	1007	// execute_max_cycles - return maximum number of
	1008	// cycles it takes for one instruction to execute
	1009	//-------------------------------------------------
700	1010
701		/* core execution loop */
	1011	UINT32 r3000_device::execute_max_cycles() const
	1012	{
	1013	return 40;
	1014	}
	1015
	1016
	1017	//-------------------------------------------------
	1018	// execute_input_lines - return the number of
	1019	// input/interrupt lines
	1020	//-------------------------------------------------
	1021
	1022	UINT32 r3000_device::execute_input_lines() const
	1023	{
	1024	return 6;
	1025	}
	1026
	1027
	1028	//-------------------------------------------------
	1029	// execute_set_input
	1030	//-------------------------------------------------
	1031
	1032	void r3000_device::execute_set_input(int inputnum, int state)
	1033	{
	1034	set_irq_line(inputnum, state);
	1035	}
	1036
	1037
	1038	//-------------------------------------------------
	1039	// execute_run
	1040	//-------------------------------------------------
	1041
	1042	void r3000_device::execute_run()
	1043	{
	1044	// count cycles and interrupt cycles
	1045	m_icount -= m_interrupt_cycles;
	1046	m_interrupt_cycles = 0;
	1047
	1048	// check for IRQs
	1049	check_irqs();
	1050
	1051	// core execution loop
702	1052	do
703	1053	{
704		UINT32 op;
705	1054	UINT64 temp64;
706	1055	int temp;
707	1056
708		/* debugging */
709		r3000->ppc = r3000->pc;
710		debugger_instruction_hook(device, r3000->pc);
	1057	// debugging
	1058	m_ppc = m_pc;
	1059	debugger_instruction_hook(this, m_pc);
711	1060
712		/* instruction fetch */
713		op = ROPCODE(r3000, r3000->pc);
	1061	// instruction fetch
	1062	m_op = readop(m_pc);
714	1063
715		/* adjust for next PC */
716		if (r3000->nextpc != ~0)
	1064	// adjust for next PC
	1065	if (m_nextpc != ~0)
717	1066	{
718		r3000->pc = r3000->nextpc;
719		r3000->nextpc = ~0;
	1067	m_pc = m_nextpc;
	1068	m_nextpc = ~0;
720	1069	}
721	1070	else
722		~~r3000->~~pc += 4;
	1071	m_pc += 4;
723	1072
724		/* parse the instruction */
725		switch (op >> 26)
	1073	// parse the instruction
	1074	switch (m_op >> 26)
726	1075	{
727	1076	case 0x00: /* SPECIAL */
728		switch (op & 63)
	1077	switch (m_op & 63)
729	1078	{
730		case 0x00: /* SLL */ if (RDREG) r3000->RDVAL = r3000->RTVAL << SHIFT; break;
731		case 0x02: /* SRL */ if (RDREG) r3000->RDVAL = r3000->RTVAL >> SHIFT; break;
732		case 0x03: /* SRA */ if (RDREG) r3000->RDVAL = (INT32)r3000->RTVAL >> SHIFT; break;
733		case 0x04: /* SLLV */ if (RDREG) r3000->RDVAL = r3000->RTVAL << (r3000->RSVAL & 31); break;
734		case 0x06: /* SRLV */ if (RDREG) r3000->RDVAL = r3000->RTVAL >> (r3000->RSVAL & 31); break;
735		case 0x07: /* SRAV */ if (RDREG) r3000->RDVAL = (INT32)r3000->RTVAL >> (r3000->RSVAL & 31); break;
736		case 0x08: /* JR */ SETPC(r3000, r3000->RSVAL); break;
737		case 0x09: /* JALR */ SETPCL(r3000, r3000->RSVAL, RDREG); break;
738		case 0x0c: /* SYSCALL */ generate_exception(r3000, EXCEPTION_SYSCALL); break;
739		case 0x0d: /* BREAK */ generate_exception(r3000, EXCEPTION_BREAK); break;
740		case 0x0f: /* SYNC */ invalid_instruction(r3000, op); break;
741		case 0x10: /* MFHI */ if (RDREG) r3000->RDVAL = r3000->hi; break;
742		case 0x11: /* MTHI */ r3000->hi = r3000->RSVAL; break;
743		case 0x12: /* MFLO */ if (RDREG) r3000->RDVAL = r3000->lo; break;
744		case 0x13: /* MTLO */ r3000->lo = r3000->RSVAL; break;
	1079	case 0x00: /* SLL */ if (RDREG) RDVAL = RTVAL << SHIFT; break;
	1080	case 0x02: /* SRL */ if (RDREG) RDVAL = RTVAL >> SHIFT; break;
	1081	case 0x03: /* SRA */ if (RDREG) RDVAL = (INT32)RTVAL >> SHIFT; break;
	1082	case 0x04: /* SLLV */ if (RDREG) RDVAL = RTVAL << (RSVAL & 31); break;
	1083	case 0x06: /* SRLV */ if (RDREG) RDVAL = RTVAL >> (RSVAL & 31); break;
	1084	case 0x07: /* SRAV */ if (RDREG) RDVAL = (INT32)RTVAL >> (RSVAL & 31); break;
	1085	case 0x08: /* JR */ SETPC(RSVAL); break;
	1086	case 0x09: /* JALR */ SETPCL(RSVAL, RDREG); break;
	1087	case 0x0c: /* SYSCALL */ generate_exception(EXCEPTION_SYSCALL); break;
	1088	case 0x0d: /* BREAK */ generate_exception(EXCEPTION_BREAK); break;
	1089	case 0x0f: /* SYNC */ invalid_instruction(); break;
	1090	case 0x10: /* MFHI */ if (RDREG) RDVAL = m_hi; break;
	1091	case 0x11: /* MTHI */ m_hi = RSVAL; break;
	1092	case 0x12: /* MFLO */ if (RDREG) RDVAL = m_lo; break;
	1093	case 0x13: /* MTLO */ m_lo = RSVAL; break;
745	1094	case 0x18: /* MULT */
746		temp64 = (INT64)(INT32)r3000->RSVAL * (INT64)(INT32)r3000->RTVAL;
747		r3000->lo = (UINT32)temp64;
748		r3000->hi = (UINT32)(temp64 >> 32);
749		r3000->icount -= 11;
	1095	temp64 = (INT64)(INT32)RSVAL * (INT64)(INT32)RTVAL;
	1096	m_lo = (UINT32)temp64;
	1097	m_hi = (UINT32)(temp64 >> 32);
	1098	m_icount -= 11;
750	1099	break;
751	1100	case 0x19: /* MULTU */
752		temp64 = (UINT64)r3000->RSVAL * (UINT64)r3000->RTVAL;
753		r3000->lo = (UINT32)temp64;
754		r3000->hi = (UINT32)(temp64 >> 32);
755		r3000->icount -= 11;
	1101	temp64 = (UINT64)RSVAL * (UINT64)RTVAL;
	1102	m_lo = (UINT32)temp64;
	1103	m_hi = (UINT32)(temp64 >> 32);
	1104	m_icount -= 11;
756	1105	break;
757	1106	case 0x1a: /* DIV */
758		if (~~r3000->~~RTVAL)
	1107	if (RTVAL)
759	1108	{
760		r3000->lo = (INT32)r3000->RSVAL / (INT32)r3000->RTVAL;
761		r3000->hi = (INT32)r3000->RSVAL % (INT32)r3000->RTVAL;
	1109	m_lo = (INT32)RSVAL / (INT32)RTVAL;
	1110	m_hi = (INT32)RSVAL % (INT32)RTVAL;
762	1111	}
763		~~r3000->~~icount -= 34;
	1112	m_icount -= 34;
764	1113	break;
765	1114	case 0x1b: /* DIVU */
766		if (~~r3000->~~RTVAL)
	1115	if (RTVAL)
767	1116	{
768		r3000->lo = r3000->RSVAL / r3000->RTVAL;
769		r3000->hi = r3000->RSVAL % r3000->RTVAL;
	1117	m_lo = RSVAL / RTVAL;
	1118	m_hi = RSVAL % RTVAL;
770	1119	}
771		~~r3000->~~icount -= 34;
	1120	m_icount -= 34;
772	1121	break;
773	1122	case 0x20: /* ADD */
774		if (ENABLE_OVERFLOWS && r3000->RSVAL > ~r3000->RTVAL) generate_exception(r3000, EXCEPTION_OVERFLOW);
775		else r3000->RDVAL = r3000->RSVAL + r3000->RTVAL;
	1123	if (ENABLE_OVERFLOWS && RSVAL > ~RTVAL) generate_exception(EXCEPTION_OVERFLOW);
	1124	else RDVAL = RSVAL + RTVAL;
776	1125	break;
777		case 0x21: /* ADDU */ if (RDREG) ~~r3000->~~RDVAL = ~~r3000->~~RSVAL + ~~r3000->~~RTVAL; break;
	1126	case 0x21: /* ADDU */ if (RDREG) RDVAL = RSVAL + RTVAL; break;
778	1127	case 0x22: /* SUB */
779		if (ENABLE_OVERFLOWS && r3000->RSVAL < r3000->RTVAL) generate_exception(r3000, EXCEPTION_OVERFLOW);
780		else r3000->RDVAL = r3000->RSVAL - r3000->RTVAL;
	1128	if (ENABLE_OVERFLOWS && RSVAL < RTVAL) generate_exception(EXCEPTION_OVERFLOW);
	1129	else RDVAL = RSVAL - RTVAL;
781	1130	break;
782		case 0x23: /* SUBU */ if (RDREG) r3000->RDVAL = r3000->RSVAL - r3000->RTVAL; break;
783		case 0x24: /* AND */ if (RDREG) r3000->RDVAL = r3000->RSVAL & r3000->RTVAL; break;
784		case 0x25: /* OR */ if (RDREG) r3000->RDVAL = r3000->RSVAL \| r3000->RTVAL; break;
785		case 0x26: /* XOR */ if (RDREG) r3000->RDVAL = r3000->RSVAL ^ r3000->RTVAL; break;
786		case 0x27: /* NOR */ if (RDREG) r3000->RDVAL = ~(r3000->RSVAL \| r3000->RTVAL); break;
787		case 0x2a: /* SLT */ if (RDREG) r3000->RDVAL = (INT32)r3000->RSVAL < (INT32)r3000->RTVAL; break;
788		case 0x2b: /* SLTU */ if (RDREG) r3000->RDVAL = (UINT32)r3000->RSVAL < (UINT32)r3000->RTVAL; break;
789		case 0x30: /* TEQ */ invalid_instruction(r3000, op); break;
790		case 0x31: /* TGEU */ invalid_instruction(r3000, op); break;
791		case 0x32: /* TLT */ invalid_instruction(r3000, op); break;
792		case 0x33: /* TLTU */ invalid_instruction(r3000, op); break;
793		case 0x34: /* TGE */ invalid_instruction(r3000, op); break;
794		case 0x36: /* TNE */ invalid_instruction(r3000, op); break;
795		default: /* ??? */ invalid_instruction(r3000, op); break;
	1131	case 0x23: /* SUBU */ if (RDREG) RDVAL = RSVAL - RTVAL; break;
	1132	case 0x24: /* AND */ if (RDREG) RDVAL = RSVAL & RTVAL; break;
	1133	case 0x25: /* OR */ if (RDREG) RDVAL = RSVAL \| RTVAL; break;
	1134	case 0x26: /* XOR */ if (RDREG) RDVAL = RSVAL ^ RTVAL; break;
	1135	case 0x27: /* NOR */ if (RDREG) RDVAL = ~(RSVAL \| RTVAL); break;
	1136	case 0x2a: /* SLT */ if (RDREG) RDVAL = (INT32)RSVAL < (INT32)RTVAL; break;
	1137	case 0x2b: /* SLTU */ if (RDREG) RDVAL = (UINT32)RSVAL < (UINT32)RTVAL; break;
	1138	case 0x30: /* TEQ */ invalid_instruction(); break;
	1139	case 0x31: /* TGEU */ invalid_instruction(); break;
	1140	case 0x32: /* TLT */ invalid_instruction(); break;
	1141	case 0x33: /* TLTU */ invalid_instruction(); break;
	1142	case 0x34: /* TGE */ invalid_instruction(); break;
	1143	case 0x36: /* TNE */ invalid_instruction(); break;
	1144	default: /* ??? */ invalid_instruction(); break;
796	1145	}
797	1146	break;
798	1147
799	1148	case 0x01: /* REGIMM */
800	1149	switch (RTREG)
801	1150	{
802		case 0x00: /* BLTZ */ if ((INT32)r3000->RSVAL < 0) ADDPC(r3000, SIMMVAL); break;
803		case 0x01: /* BGEZ */ if ((INT32)r3000->RSVAL >= 0) ADDPC(r3000, SIMMVAL); break;
804		case 0x02: /* BLTZL */ invalid_instruction(r3000, op); break;
805		case 0x03: /* BGEZL */ invalid_instruction(r3000, op); break;
806		case 0x08: /* TGEI */ invalid_instruction(r3000, op); break;
807		case 0x09: /* TGEIU */ invalid_instruction(r3000, op); break;
808		case 0x0a: /* TLTI */ invalid_instruction(r3000, op); break;
809		case 0x0b: /* TLTIU */ invalid_instruction(r3000, op); break;
810		case 0x0c: /* TEQI */ invalid_instruction(r3000, op); break;
811		case 0x0e: /* TNEI */ invalid_instruction(r3000, op); break;
812		case 0x10: /* BLTZAL */ if ((INT32)r3000->RSVAL < 0) ADDPCL(r3000,SIMMVAL,31); break;
813		case 0x11: /* BGEZAL */ if ((INT32)r3000->RSVAL >= 0) ADDPCL(r3000,SIMMVAL,31); break;
814		case 0x12: /* BLTZALL */ invalid_instruction(r3000, op); break;
815		case 0x13: /* BGEZALL */ invalid_instruction(r3000, op); break;
816		default: /* ??? */ invalid_instruction(r3000, op); break;
	1151	case 0x00: /* BLTZ */ if ((INT32)RSVAL < 0) ADDPC(SIMMVAL); break;
	1152	case 0x01: /* BGEZ */ if ((INT32)RSVAL >= 0) ADDPC(SIMMVAL); break;
	1153	case 0x02: /* BLTZL */ invalid_instruction(); break;
	1154	case 0x03: /* BGEZL */ invalid_instruction(); break;
	1155	case 0x08: /* TGEI */ invalid_instruction(); break;
	1156	case 0x09: /* TGEIU */ invalid_instruction(); break;
	1157	case 0x0a: /* TLTI */ invalid_instruction(); break;
	1158	case 0x0b: /* TLTIU */ invalid_instruction(); break;
	1159	case 0x0c: /* TEQI */ invalid_instruction(); break;
	1160	case 0x0e: /* TNEI */ invalid_instruction(); break;
	1161	case 0x10: /* BLTZAL */ if ((INT32)RSVAL < 0) ADDPCL(SIMMVAL,31); break;
	1162	case 0x11: /* BGEZAL */ if ((INT32)RSVAL >= 0) ADDPCL(SIMMVAL,31); break;
	1163	case 0x12: /* BLTZALL */ invalid_instruction(); break;
	1164	case 0x13: /* BGEZALL */ invalid_instruction(); break;
	1165	default: /* ??? */ invalid_instruction(); break;
817	1166	}
818	1167	break;
819	1168
820		case 0x02: /* J */ ABSPC(r3000, LIMMVAL); break;
821		case 0x03: /* JAL */ ABSPCL(r3000, LIMMVAL,31); break;
822		case 0x04: /* BEQ */ if (r3000->RSVAL == r3000->RTVAL) ADDPC(r3000, SIMMVAL); break;
823		case 0x05: /* BNE */ if (r3000->RSVAL != r3000->RTVAL) ADDPC(r3000, SIMMVAL); break;
824		case 0x06: /* BLEZ */ if ((INT32)r3000->RSVAL <= 0) ADDPC(r3000, SIMMVAL); break;
825		case 0x07: /* BGTZ */ if ((INT32)r3000->RSVAL > 0) ADDPC(r3000, SIMMVAL); break;
	1169	case 0x02: /* J */ ABSPC(LIMMVAL); break;
	1170	case 0x03: /* JAL */ ABSPCL(LIMMVAL,31); break;
	1171	case 0x04: /* BEQ */ if (RSVAL == RTVAL) ADDPC(SIMMVAL); break;
	1172	case 0x05: /* BNE */ if (RSVAL != RTVAL) ADDPC(SIMMVAL); break;
	1173	case 0x06: /* BLEZ */ if ((INT32)RSVAL <= 0) ADDPC(SIMMVAL); break;
	1174	case 0x07: /* BGTZ */ if ((INT32)RSVAL > 0) ADDPC(SIMMVAL); break;
826	1175	case 0x08: /* ADDI */
827		if (ENABLE_OVERFLOWS && r3000->RSVAL > ~SIMMVAL) generate_exception(r3000, EXCEPTION_OVERFLOW);
828		else if (RTREG) r3000->RTVAL = r3000->RSVAL + SIMMVAL;
	1176	if (ENABLE_OVERFLOWS && RSVAL > ~SIMMVAL) generate_exception(EXCEPTION_OVERFLOW);
	1177	else if (RTREG) RTVAL = RSVAL + SIMMVAL;
829	1178	break;
830		case 0x09: /* ADDIU */ if (RTREG) r3000->RTVAL = r3000->RSVAL + SIMMVAL; break;
831		case 0x0a: /* SLTI */ if (RTREG) r3000->RTVAL = (INT32)r3000->RSVAL < (INT32)SIMMVAL; break;
832		case 0x0b: /* SLTIU */ if (RTREG) r3000->RTVAL = (UINT32)r3000->RSVAL < (UINT32)SIMMVAL; break;
833		case 0x0c: /* ANDI */ if (RTREG) r3000->RTVAL = r3000->RSVAL & UIMMVAL; break;
834		case 0x0d: /* ORI */ if (RTREG) r3000->RTVAL = r3000->RSVAL \| UIMMVAL; break;
835		case 0x0e: /* XORI */ if (RTREG) r3000->RTVAL = r3000->RSVAL ^ UIMMVAL; break;
836		case 0x0f: /* LUI */ if (RTREG) r3000->RTVAL = UIMMVAL << 16; break;
837		case 0x10: /* COP0 */ handle_cop0(r3000, op); break;
838		case 0x11: /* COP1 */ handle_cop1(r3000, op); break;
839		case 0x12: /* COP2 */ handle_cop2(r3000, op); break;
840		case 0x13: /* COP3 */ handle_cop3(r3000, op); break;
841		case 0x14: /* BEQL */ invalid_instruction(r3000, op); break;
842		case 0x15: /* BNEL */ invalid_instruction(r3000, op); break;
843		case 0x16: /* BLEZL */ invalid_instruction(r3000, op); break;
844		case 0x17: /* BGTZL */ invalid_instruction(r3000, op); break;
845		case 0x20: /* LB */ temp = RBYTE(r3000, SIMMVAL+r3000->RSVAL); if (RTREG) r3000->RTVAL = (INT8)temp; break;
846		case 0x21: /* LH */ temp = RWORD(r3000, SIMMVAL+r3000->RSVAL); if (RTREG) r3000->RTVAL = (INT16)temp; break;
847		case 0x22: /* LWL / (r3000->lwl)(r3000, op); break;
848		case 0x23: /* LW */ temp = RLONG(r3000, SIMMVAL+r3000->RSVAL); if (RTREG) r3000->RTVAL = temp; break;
849		case 0x24: /* LBU */ temp = RBYTE(r3000, SIMMVAL+r3000->RSVAL); if (RTREG) r3000->RTVAL = (UINT8)temp; break;
850		case 0x25: /* LHU */ temp = RWORD(r3000, SIMMVAL+r3000->RSVAL); if (RTREG) r3000->RTVAL = (UINT16)temp; break;
851		case 0x26: /* LWR / (r3000->lwr)(r3000, op); break;
852		case 0x28: /* SB */ WBYTE(r3000, SIMMVAL+r3000->RSVAL, r3000->RTVAL); break;
853		case 0x29: /* SH */ WWORD(r3000, SIMMVAL+r3000->RSVAL, r3000->RTVAL); break;
854		case 0x2a: /* SWL / (r3000->swl)(r3000, op); break;
855		case 0x2b: /* SW */ WLONG(r3000, SIMMVAL+r3000->RSVAL, r3000->RTVAL); break;
856		case 0x2e: /* SWR / (r3000->swr)(r3000, op); break;
857		case 0x2f: /* CACHE */ invalid_instruction(r3000, op); break;
858		case 0x30: /* LL */ invalid_instruction(r3000, op); break;
859		case 0x31: /* LWC1 */ set_cop1_reg(r3000, RTREG, RLONG(r3000, SIMMVAL+r3000->RSVAL)); break;
860		case 0x32: /* LWC2 */ set_cop2_reg(r3000, RTREG, RLONG(r3000, SIMMVAL+r3000->RSVAL)); break;
861		case 0x33: /* LWC3 */ set_cop3_reg(r3000, RTREG, RLONG(r3000, SIMMVAL+r3000->RSVAL)); break;
862		case 0x34: /* LDC0 */ invalid_instruction(r3000, op); break;
863		case 0x35: /* LDC1 */ invalid_instruction(r3000, op); break;
864		case 0x36: /* LDC2 */ invalid_instruction(r3000, op); break;
865		case 0x37: /* LDC3 */ invalid_instruction(r3000, op); break;
866		case 0x38: /* SC */ invalid_instruction(r3000, op); break;
867		case 0x39: /* LWC1 */ WLONG(r3000, SIMMVAL+r3000->RSVAL, get_cop1_reg(r3000, RTREG)); break;
868		case 0x3a: /* LWC2 */ WLONG(r3000, SIMMVAL+r3000->RSVAL, get_cop2_reg(r3000, RTREG)); break;
869		case 0x3b: /* LWC3 */ WLONG(r3000, SIMMVAL+r3000->RSVAL, get_cop3_reg(r3000, RTREG)); break;
870		case 0x3c: /* SDC0 */ invalid_instruction(r3000, op); break;
871		case 0x3d: /* SDC1 */ invalid_instruction(r3000, op); break;
872		case 0x3e: /* SDC2 */ invalid_instruction(r3000, op); break;
873		case 0x3f: /* SDC3 */ invalid_instruction(r3000, op); break;
874		default: /* ??? */ invalid_instruction(r3000, op); break;
	1179	case 0x09: /* ADDIU */ if (RTREG) RTVAL = RSVAL + SIMMVAL; break;
	1180	case 0x0a: /* SLTI */ if (RTREG) RTVAL = (INT32)RSVAL < (INT32)SIMMVAL; break;
	1181	case 0x0b: /* SLTIU */ if (RTREG) RTVAL = (UINT32)RSVAL < (UINT32)SIMMVAL; break;
	1182	case 0x0c: /* ANDI */ if (RTREG) RTVAL = RSVAL & UIMMVAL; break;
	1183	case 0x0d: /* ORI */ if (RTREG) RTVAL = RSVAL \| UIMMVAL; break;
	1184	case 0x0e: /* XORI */ if (RTREG) RTVAL = RSVAL ^ UIMMVAL; break;
	1185	case 0x0f: /* LUI */ if (RTREG) RTVAL = UIMMVAL << 16; break;
	1186	case 0x10: /* COP0 */ handle_cop0(); break;
	1187	case 0x11: /* COP1 */ handle_cop1(); break;
	1188	case 0x12: /* COP2 */ handle_cop2(); break;
	1189	case 0x13: /* COP3 */ handle_cop3(); break;
	1190	case 0x14: /* BEQL */ invalid_instruction(); break;
	1191	case 0x15: /* BNEL */ invalid_instruction(); break;
	1192	case 0x16: /* BLEZL */ invalid_instruction(); break;
	1193	case 0x17: /* BGTZL */ invalid_instruction(); break;
	1194	case 0x20: /* LB */ temp = RBYTE(SIMMVAL+RSVAL); if (RTREG) RTVAL = (INT8)temp; break;
	1195	case 0x21: /* LH */ temp = RWORD(SIMMVAL+RSVAL); if (RTREG) RTVAL = (INT16)temp; break;
	1196	case 0x22: /* LWL / (this.*m_lwl)(); break;
	1197	case 0x23: /* LW */ temp = RLONG(SIMMVAL+RSVAL); if (RTREG) RTVAL = temp; break;
	1198	case 0x24: /* LBU */ temp = RBYTE(SIMMVAL+RSVAL); if (RTREG) RTVAL = (UINT8)temp; break;
	1199	case 0x25: /* LHU */ temp = RWORD(SIMMVAL+RSVAL); if (RTREG) RTVAL = (UINT16)temp; break;
	1200	case 0x26: /* LWR / (this.*m_lwr)(); break;
	1201	case 0x28: /* SB */ WBYTE(SIMMVAL+RSVAL, RTVAL); break;
	1202	case 0x29: /* SH */ WWORD(SIMMVAL+RSVAL, RTVAL); break;
	1203	case 0x2a: /* SWL / (this.*m_swl)(); break;
	1204	case 0x2b: /* SW */ WLONG(SIMMVAL+RSVAL, RTVAL); break;
	1205	case 0x2e: /* SWR / (this.*m_swr)(); break;
	1206	case 0x2f: /* CACHE */ invalid_instruction(); break;
	1207	case 0x30: /* LL */ invalid_instruction(); break;
	1208	case 0x31: /* LWC1 */ set_cop1_reg(RTREG, RLONG(SIMMVAL+RSVAL)); break;
	1209	case 0x32: /* LWC2 */ set_cop2_reg(RTREG, RLONG(SIMMVAL+RSVAL)); break;
	1210	case 0x33: /* LWC3 */ set_cop3_reg(RTREG, RLONG(SIMMVAL+RSVAL)); break;
	1211	case 0x34: /* LDC0 */ invalid_instruction(); break;
	1212	case 0x35: /* LDC1 */ invalid_instruction(); break;
	1213	case 0x36: /* LDC2 */ invalid_instruction(); break;
	1214	case 0x37: /* LDC3 */ invalid_instruction(); break;
	1215	case 0x38: /* SC */ invalid_instruction(); break;
	1216	case 0x39: /* LWC1 */ WLONG(SIMMVAL+RSVAL, get_cop1_reg(RTREG)); break;
	1217	case 0x3a: /* LWC2 */ WLONG(SIMMVAL+RSVAL, get_cop2_reg(RTREG)); break;
	1218	case 0x3b: /* LWC3 */ WLONG(SIMMVAL+RSVAL, get_cop3_reg(RTREG)); break;
	1219	case 0x3c: /* SDC0 */ invalid_instruction(); break;
	1220	case 0x3d: /* SDC1 */ invalid_instruction(); break;
	1221	case 0x3e: /* SDC2 */ invalid_instruction(); break;
	1222	case 0x3f: /* SDC3 */ invalid_instruction(); break;
	1223	default: /* ??? */ invalid_instruction(); break;
875	1224	}
876		~~r3000->~~icount--;
	1225	m_icount--;
877	1226
878		} while (~~r3000->~~icount > 0 \|\| ~~r3000->~~nextpc != ~0);
	1227	} while (m_icount > 0 \|\| m_nextpc != ~0);
879	1228
880		r3000->icount -= r3000->interrupt_cycles;
881		r3000->interrupt_cycles = 0;
	1229	m_icount -= m_interrupt_cycles;
	1230	m_interrupt_cycles = 0;
882	1231	}
883	1232
884	1233
885
886	1234	/***************************************************************************
887		DISASSEMBLY HOOK
888		***************************************************************************/
889
890
891		/***************************************************************************
892		CACHE I/O
893		***************************************************************************/
894
895		static UINT8 readcache_be(address_space &space, offs_t offset)
896		{
897		r3000_state *r3000 = get_safe_token(&space.device());
898		offset &= 0x1fffffff;
899		return (offset * 4 < r3000->cache_size) ? r3000->cache[BYTE4_XOR_BE(offset)] : 0xff;
900		}
901
902		static UINT16 readcache_be_word(address_space &space, offs_t offset)
903		{
904		r3000_state *r3000 = get_safe_token(&space.device());
905		offset &= 0x1fffffff;
906		return (offset * 4 < r3000->cache_size) ? (UINT16 )&r3000->cache[WORD_XOR_BE(offset)] : 0xffff;
907		}
908
909		static UINT32 readcache_be_dword(address_space &space, offs_t offset)
910		{
911		r3000_state *r3000 = get_safe_token(&space.device());
912		offset &= 0x1fffffff;
913		return (offset * 4 < r3000->cache_size) ? (UINT32 )&r3000->cache[offset] : 0xffffffff;
914		}
915
916		static void writecache_be(address_space &space, offs_t offset, UINT8 data)
917		{
918		r3000_state *r3000 = get_safe_token(&space.device());
919		offset &= 0x1fffffff;
920		if (offset * 4 < r3000->cache_size) r3000->cache[BYTE4_XOR_BE(offset)] = data;
921		}
922
923		static void writecache_be_word(address_space &space, offs_t offset, UINT16 data)
924		{
925		r3000_state *r3000 = get_safe_token(&space.device());
926		offset &= 0x1fffffff;
927		if (offset * 4 < r3000->cache_size) (UINT16 )&r3000->cache[WORD_XOR_BE(offset)] = data;
928		}
929
930		static void writecache_be_dword(address_space &space, offs_t offset, UINT32 data)
931		{
932		r3000_state *r3000 = get_safe_token(&space.device());
933		offset &= 0x1fffffff;
934		if (offset * 4 < r3000->cache_size) (UINT32 )&r3000->cache[offset] = data;
935		}
936
937		static UINT8 readcache_le(address_space &space, offs_t offset)
938		{
939		r3000_state *r3000 = get_safe_token(&space.device());
940		offset &= 0x1fffffff;
941		return (offset * 4 < r3000->cache_size) ? r3000->cache[BYTE4_XOR_LE(offset)] : 0xff;
942		}
943
944		static UINT16 readcache_le_word(address_space &space, offs_t offset)
945		{
946		r3000_state *r3000 = get_safe_token(&space.device());
947		offset &= 0x1fffffff;
948		return (offset * 4 < r3000->cache_size) ? (UINT16 )&r3000->cache[WORD_XOR_LE(offset)] : 0xffff;
949		}
950
951		static UINT32 readcache_le_dword(address_space &space, offs_t offset)
952		{
953		r3000_state *r3000 = get_safe_token(&space.device());
954		offset &= 0x1fffffff;
955		return (offset * 4 < r3000->cache_size) ? (UINT32 )&r3000->cache[offset] : 0xffffffff;
956		}
957
958		static void writecache_le(address_space &space, offs_t offset, UINT8 data)
959		{
960		r3000_state *r3000 = get_safe_token(&space.device());
961		offset &= 0x1fffffff;
962		if (offset * 4 < r3000->cache_size) r3000->cache[BYTE4_XOR_LE(offset)] = data;
963		}
964
965		static void writecache_le_word(address_space &space, offs_t offset, UINT16 data)
966		{
967		r3000_state *r3000 = get_safe_token(&space.device());
968		offset &= 0x1fffffff;
969		if (offset * 4 < r3000->cache_size) (UINT16 )&r3000->cache[WORD_XOR_LE(offset)] = data;
970		}
971
972		static void writecache_le_dword(address_space &space, offs_t offset, UINT32 data)
973		{
974		r3000_state *r3000 = get_safe_token(&space.device());
975		offset &= 0x1fffffff;
976		if (offset * 4 < r3000->cache_size) (UINT32 )&r3000->cache[offset] = data;
977		}
978
979
980
981		/***************************************************************************
982	1235	COMPLEX OPCODE IMPLEMENTATIONS
983	1236	***************************************************************************/
984	1237
985		~~static~~ void ~~lwl_be(~~r3000_~~stat~~e *r3000, UINT32 op)
	1238	void r3000_device::lwl_be()
986	1239	{
987		offs_t offs = SIMMVAL + r3000->RSVAL;
988		UINT32 temp = RLONG(r3000, offs & ~3);
	1240	offs_t offs = SIMMVAL + RSVAL;
	1241	UINT32 temp = RLONG(offs & ~3);
989	1242	if (RTREG)
990	1243	{
991		if (!(offs & 3)) ~~r3000->~~RTVAL = temp;
	1244	if (!(offs & 3)) RTVAL = temp;
992	1245	else
993	1246	{
994	1247	int shift = 8 * (offs & 3);
995		~~r3000->~~RTVAL = (~~r3000->~~RTVAL & (0x00ffffff >> (24 - shift))) \| (temp << shift);
	1248	RTVAL = (RTVAL & (0x00ffffff >> (24 - shift))) \| (temp << shift);
996	1249	}
997	1250	}
998	1251	}
999	1252
1000		~~static~~ void lwr~~_be(r~~3000_~~stat~~e *r~~3000, UINT32 op~~)
	1253	void r3000_device::lwr_be()
1001	1254	{
1002		offs_t offs = SIMMVAL + r3000->RSVAL;
1003		UINT32 temp = RLONG(r3000, offs & ~3);
	1255	offs_t offs = SIMMVAL + RSVAL;
	1256	UINT32 temp = RLONG(offs & ~3);
1004	1257	if (RTREG)
1005	1258	{
1006		if ((offs & 3) == 3) ~~r3000->~~RTVAL = temp;
	1259	if ((offs & 3) == 3) RTVAL = temp;
1007	1260	else
1008	1261	{
1009	1262	int shift = 8 * (offs & 3);
1010		~~r3000->~~RTVAL = (~~r3000->~~RTVAL & (0xffffff00 << shift)) \| (temp >> (24 - shift));
	1263	RTVAL = (RTVAL & (0xffffff00 << shift)) \| (temp >> (24 - shift));
1011	1264	}
1012	1265	}
1013	1266	}
1014	1267
1015		~~static~~ void ~~swl_be(~~r3000_s~~tat~~e *r3000, UINT32 op)
	1268	void r3000_device::swl_be()
1016	1269	{
1017		offs_t offs = SIMMVAL + r3000->RSVAL;
1018		if (!(offs & 3)) WLONG(r3000, offs, r3000->RTVAL);
	1270	offs_t offs = SIMMVAL + RSVAL;
	1271	if (!(offs & 3)) WLONG(offs, RTVAL);
1019	1272	else
1020	1273	{
1021		UINT32 temp = RLONG(~~r3000,~~ offs & ~3);
	1274	UINT32 temp = RLONG(offs & ~3);
1022	1275	int shift = 8 * (offs & 3);
1023		WLONG(~~r3000,~~ offs & ~3, (temp & (0xffffff00 << (24 - shift))) \| (~~r3000->~~RTVAL >> shift));
	1276	WLONG(offs & ~3, (temp & (0xffffff00 << (24 - shift))) \| (RTVAL >> shift));
1024	1277	}
1025	1278	}
1026	1279
1027	1280
1028		~~static~~ void swr~~_be(r~~3000_~~stat~~e *r~~3000, UINT32 op~~)
	1281	void r3000_device::swr_be()
1029	1282	{
1030		offs_t offs = SIMMVAL + r3000->RSVAL;
1031		if ((offs & 3) == 3) WLONG(r3000, offs & ~3, r3000->RTVAL);
	1283	offs_t offs = SIMMVAL + RSVAL;
	1284	if ((offs & 3) == 3) WLONG(offs & ~3, RTVAL);
1032	1285	else
1033	1286	{
1034		UINT32 temp = RLONG(~~r3000,~~ offs & ~3);
	1287	UINT32 temp = RLONG(offs & ~3);
1035	1288	int shift = 8 * (offs & 3);
1036		WLONG(~~r3000,~~ offs & ~3, (temp & (0x00ffffff >> shift)) \| (~~r3000->~~RTVAL << (24 - shift)));
	1289	WLONG(offs & ~3, (temp & (0x00ffffff >> shift)) \| (RTVAL << (24 - shift)));
1037	1290	}
1038	1291	}
1039	1292
1040	1293
1041	1294
1042		~~static~~ void ~~lwl_le(~~r3000_~~stat~~e *r3000, UINT32 op)
	1295	void r3000_device::lwl_le()
1043	1296	{
1044		offs_t offs = SIMMVAL + r3000->RSVAL;
1045		UINT32 temp = RLONG(r3000, offs & ~3);
	1297	offs_t offs = SIMMVAL + RSVAL;
	1298	UINT32 temp = RLONG(offs & ~3);
1046	1299	if (RTREG)
1047	1300	{
1048		if (!(offs & 3)) ~~r3000->~~RTVAL = temp;
	1301	if (!(offs & 3)) RTVAL = temp;
1049	1302	else
1050	1303	{
1051	1304	int shift = 8 * (offs & 3);
1052		~~r3000->~~RTVAL = (~~r3000->~~RTVAL & (0xffffff00 << (24 - shift))) \| (temp >> shift);
	1305	RTVAL = (RTVAL & (0xffffff00 << (24 - shift))) \| (temp >> shift);
1053	1306	}
1054	1307	}
1055	1308	}
1056	1309
1057		~~static~~ void lwr~~_le(r~~3000_~~stat~~e *r~~3000, UINT32 op~~)
	1310	void r3000_device::lwr_le()
1058	1311	{
1059		offs_t offs = SIMMVAL + r3000->RSVAL;
1060		UINT32 temp = RLONG(r3000, offs & ~3);
	1312	offs_t offs = SIMMVAL + RSVAL;
	1313	UINT32 temp = RLONG(offs & ~3);
1061	1314	if (RTREG)
1062	1315	{
1063		if ((offs & 3) == 3) ~~r3000->~~RTVAL = temp;
	1316	if ((offs & 3) == 3) RTVAL = temp;
1064	1317	else
1065	1318	{
1066	1319	int shift = 8 * (offs & 3);
1067		~~r3000->~~RTVAL = (~~r3000->~~RTVAL & (0x00ffffff >> shift)) \| (temp << (24 - shift));
	1320	RTVAL = (RTVAL & (0x00ffffff >> shift)) \| (temp << (24 - shift));
1068	1321	}
1069	1322	}
1070	1323	}
1071	1324
1072		~~static~~ void ~~swl_le(~~r3000_s~~tat~~e *r3000, UINT32 op)
	1325	void r3000_device::swl_le()
1073	1326	{
1074		offs_t offs = SIMMVAL + r3000->RSVAL;
1075		if (!(offs & 3)) WLONG(r3000, offs, r3000->RTVAL);
	1327	offs_t offs = SIMMVAL + RSVAL;
	1328	if (!(offs & 3)) WLONG(offs, RTVAL);
1076	1329	else
1077	1330	{
1078		UINT32 temp = RLONG(~~r3000,~~ offs & ~3);
	1331	UINT32 temp = RLONG(offs & ~3);
1079	1332	int shift = 8 * (offs & 3);
1080		WLONG(~~r3000,~~ offs & ~3, (temp & (0x00ffffff >> (24 - shift))) \| (~~r3000->~~RTVAL << shift));
	1333	WLONG(offs & ~3, (temp & (0x00ffffff >> (24 - shift))) \| (RTVAL << shift));
1081	1334	}
1082	1335	}
1083	1336
1084		~~static~~ void swr~~_le(r~~3000_~~stat~~e *r~~3000, UINT32 op~~)
	1337	void r3000_device::swr_le()
1085	1338	{
1086		offs_t offs = SIMMVAL + r3000->RSVAL;
1087		if ((offs & 3) == 3) WLONG(r3000, offs & ~3, r3000->RTVAL);
	1339	offs_t offs = SIMMVAL + RSVAL;
	1340	if ((offs & 3) == 3) WLONG(offs & ~3, RTVAL);
1088	1341	else
1089	1342	{
1090		UINT32 temp = RLONG(~~r3000,~~ offs & ~3);
	1343	UINT32 temp = RLONG(offs & ~3);
1091	1344	int shift = 8 * (offs & 3);
1092		WLONG(~~r3000,~~ offs & ~3, (temp & (0xffffff00 << shift)) \| (~~r3000->~~RTVAL >> (24 - shift)));
	1345	WLONG(offs & ~3, (temp & (0xffffff00 << shift)) \| (RTVAL >> (24 - shift)));
1093	1346	}
1094	1347	}
1095
1096
1097
1098		/**************************************************************************
1099		* Generic set_info
1100		**************************************************************************/
1101
1102		static CPU_SET_INFO( r3000 )
1103		{
1104		r3000_state *r3000 = get_safe_token(device);
1105		switch (state)
1106		{
1107		/* --- the following bits of info are set as 64-bit signed integers --- */
1108		case CPUINFO_INT_INPUT_STATE + R3000_IRQ0: set_irq_line(r3000, R3000_IRQ0, info->i); break;
1109		case CPUINFO_INT_INPUT_STATE + R3000_IRQ1: set_irq_line(r3000, R3000_IRQ1, info->i); break;
1110		case CPUINFO_INT_INPUT_STATE + R3000_IRQ2: set_irq_line(r3000, R3000_IRQ2, info->i); break;
1111		case CPUINFO_INT_INPUT_STATE + R3000_IRQ3: set_irq_line(r3000, R3000_IRQ3, info->i); break;
1112		case CPUINFO_INT_INPUT_STATE + R3000_IRQ4: set_irq_line(r3000, R3000_IRQ4, info->i); break;
1113		case CPUINFO_INT_INPUT_STATE + R3000_IRQ5: set_irq_line(r3000, R3000_IRQ5, info->i); break;
1114
1115		case CPUINFO_INT_PC:
1116		case CPUINFO_INT_REGISTER + R3000_PC: r3000->pc = info->i; break;
1117		case CPUINFO_INT_REGISTER + R3000_SR: r3000->SR = info->i; break;
1118
1119		case CPUINFO_INT_REGISTER + R3000_R0: r3000->r[0] = info->i; break;
1120		case CPUINFO_INT_REGISTER + R3000_R1: r3000->r[1] = info->i; break;
1121		case CPUINFO_INT_REGISTER + R3000_R2: r3000->r[2] = info->i; break;
1122		case CPUINFO_INT_REGISTER + R3000_R3: r3000->r[3] = info->i; break;
1123		case CPUINFO_INT_REGISTER + R3000_R4: r3000->r[4] = info->i; break;
1124		case CPUINFO_INT_REGISTER + R3000_R5: r3000->r[5] = info->i; break;
1125		case CPUINFO_INT_REGISTER + R3000_R6: r3000->r[6] = info->i; break;
1126		case CPUINFO_INT_REGISTER + R3000_R7: r3000->r[7] = info->i; break;
1127		case CPUINFO_INT_REGISTER + R3000_R8: r3000->r[8] = info->i; break;
1128		case CPUINFO_INT_REGISTER + R3000_R9: r3000->r[9] = info->i; break;
1129		case CPUINFO_INT_REGISTER + R3000_R10: r3000->r[10] = info->i; break;
1130		case CPUINFO_INT_REGISTER + R3000_R11: r3000->r[11] = info->i; break;
1131		case CPUINFO_INT_REGISTER + R3000_R12: r3000->r[12] = info->i; break;
1132		case CPUINFO_INT_REGISTER + R3000_R13: r3000->r[13] = info->i; break;
1133		case CPUINFO_INT_REGISTER + R3000_R14: r3000->r[14] = info->i; break;
1134		case CPUINFO_INT_REGISTER + R3000_R15: r3000->r[15] = info->i; break;
1135		case CPUINFO_INT_REGISTER + R3000_R16: r3000->r[16] = info->i; break;
1136		case CPUINFO_INT_REGISTER + R3000_R17: r3000->r[17] = info->i; break;
1137		case CPUINFO_INT_REGISTER + R3000_R18: r3000->r[18] = info->i; break;
1138		case CPUINFO_INT_REGISTER + R3000_R19: r3000->r[19] = info->i; break;
1139		case CPUINFO_INT_REGISTER + R3000_R20: r3000->r[20] = info->i; break;
1140		case CPUINFO_INT_REGISTER + R3000_R21: r3000->r[21] = info->i; break;
1141		case CPUINFO_INT_REGISTER + R3000_R22: r3000->r[22] = info->i; break;
1142		case CPUINFO_INT_REGISTER + R3000_R23: r3000->r[23] = info->i; break;
1143		case CPUINFO_INT_REGISTER + R3000_R24: r3000->r[24] = info->i; break;
1144		case CPUINFO_INT_REGISTER + R3000_R25: r3000->r[25] = info->i; break;
1145		case CPUINFO_INT_REGISTER + R3000_R26: r3000->r[26] = info->i; break;
1146		case CPUINFO_INT_REGISTER + R3000_R27: r3000->r[27] = info->i; break;
1147		case CPUINFO_INT_REGISTER + R3000_R28: r3000->r[28] = info->i; break;
1148		case CPUINFO_INT_REGISTER + R3000_R29: r3000->r[29] = info->i; break;
1149		case CPUINFO_INT_REGISTER + R3000_R30: r3000->r[30] = info->i; break;
1150		case CPUINFO_INT_SP:
1151		case CPUINFO_INT_REGISTER + R3000_R31: r3000->r[31] = info->i; break;
1152		}
1153		}
1154
1155
1156
1157		/**************************************************************************
1158		* Generic get_info
1159		**************************************************************************/
1160
1161		static CPU_GET_INFO( r3000 )
1162		{
1163		r3000_state *r3000 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
1164		switch (state)
1165		{
1166		/* --- the following bits of info are returned as 64-bit signed integers --- */
1167		case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(r3000_state); break;
1168		case CPUINFO_INT_INPUT_LINES: info->i = 6; break;
1169		case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
1170		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
1171		case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
1172		case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
1173		case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break;
1174		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
1175		case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
1176		case CPUINFO_INT_MAX_CYCLES: info->i = 40; break;
1177
1178		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break;
1179		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 29; break;
1180		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
1181		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
1182		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
1183		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
1184		case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
1185		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
1186		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
1187
1188		case CPUINFO_INT_INPUT_STATE + R3000_IRQ0: info->i = (r3000->cpr[0][COP0_Cause] & 0x400) ? ASSERT_LINE : CLEAR_LINE; break;
1189		case CPUINFO_INT_INPUT_STATE + R3000_IRQ1: info->i = (r3000->cpr[0][COP0_Cause] & 0x800) ? ASSERT_LINE : CLEAR_LINE; break;
1190		case CPUINFO_INT_INPUT_STATE + R3000_IRQ2: info->i = (r3000->cpr[0][COP0_Cause] & 0x1000) ? ASSERT_LINE : CLEAR_LINE; break;
1191		case CPUINFO_INT_INPUT_STATE + R3000_IRQ3: info->i = (r3000->cpr[0][COP0_Cause] & 0x2000) ? ASSERT_LINE : CLEAR_LINE; break;
1192		case CPUINFO_INT_INPUT_STATE + R3000_IRQ4: info->i = (r3000->cpr[0][COP0_Cause] & 0x4000) ? ASSERT_LINE : CLEAR_LINE; break;
1193		case CPUINFO_INT_INPUT_STATE + R3000_IRQ5: info->i = (r3000->cpr[0][COP0_Cause] & 0x8000) ? ASSERT_LINE : CLEAR_LINE; break;
1194
1195		case CPUINFO_INT_PREVIOUSPC: info->i = r3000->ppc; break;
1196
1197		case CPUINFO_INT_PC: info->i = r3000->pc & 0x1fffffff; break;
1198		case CPUINFO_INT_REGISTER + R3000_PC: info->i = r3000->pc; break;
1199		case CPUINFO_INT_REGISTER + R3000_SR: info->i = r3000->SR; break;
1200
1201		case CPUINFO_INT_REGISTER + R3000_R0: info->i = r3000->r[0]; break;
1202		case CPUINFO_INT_REGISTER + R3000_R1: info->i = r3000->r[1]; break;
1203		case CPUINFO_INT_REGISTER + R3000_R2: info->i = r3000->r[2]; break;
1204		case CPUINFO_INT_REGISTER + R3000_R3: info->i = r3000->r[3]; break;
1205		case CPUINFO_INT_REGISTER + R3000_R4: info->i = r3000->r[4]; break;
1206		case CPUINFO_INT_REGISTER + R3000_R5: info->i = r3000->r[5]; break;
1207		case CPUINFO_INT_REGISTER + R3000_R6: info->i = r3000->r[6]; break;
1208		case CPUINFO_INT_REGISTER + R3000_R7: info->i = r3000->r[7]; break;
1209		case CPUINFO_INT_REGISTER + R3000_R8: info->i = r3000->r[8]; break;
1210		case CPUINFO_INT_REGISTER + R3000_R9: info->i = r3000->r[9]; break;
1211		case CPUINFO_INT_REGISTER + R3000_R10: info->i = r3000->r[10]; break;
1212		case CPUINFO_INT_REGISTER + R3000_R11: info->i = r3000->r[11]; break;
1213		case CPUINFO_INT_REGISTER + R3000_R12: info->i = r3000->r[12]; break;
1214		case CPUINFO_INT_REGISTER + R3000_R13: info->i = r3000->r[13]; break;
1215		case CPUINFO_INT_REGISTER + R3000_R14: info->i = r3000->r[14]; break;
1216		case CPUINFO_INT_REGISTER + R3000_R15: info->i = r3000->r[15]; break;
1217		case CPUINFO_INT_REGISTER + R3000_R16: info->i = r3000->r[16]; break;
1218		case CPUINFO_INT_REGISTER + R3000_R17: info->i = r3000->r[17]; break;
1219		case CPUINFO_INT_REGISTER + R3000_R18: info->i = r3000->r[18]; break;
1220		case CPUINFO_INT_REGISTER + R3000_R19: info->i = r3000->r[19]; break;
1221		case CPUINFO_INT_REGISTER + R3000_R20: info->i = r3000->r[20]; break;
1222		case CPUINFO_INT_REGISTER + R3000_R21: info->i = r3000->r[21]; break;
1223		case CPUINFO_INT_REGISTER + R3000_R22: info->i = r3000->r[22]; break;
1224		case CPUINFO_INT_REGISTER + R3000_R23: info->i = r3000->r[23]; break;
1225		case CPUINFO_INT_REGISTER + R3000_R24: info->i = r3000->r[24]; break;
1226		case CPUINFO_INT_REGISTER + R3000_R25: info->i = r3000->r[25]; break;
1227		case CPUINFO_INT_REGISTER + R3000_R26: info->i = r3000->r[26]; break;
1228		case CPUINFO_INT_REGISTER + R3000_R27: info->i = r3000->r[27]; break;
1229		case CPUINFO_INT_REGISTER + R3000_R28: info->i = r3000->r[28]; break;
1230		case CPUINFO_INT_REGISTER + R3000_R29: info->i = r3000->r[29]; break;
1231		case CPUINFO_INT_REGISTER + R3000_R30: info->i = r3000->r[30]; break;
1232		case CPUINFO_INT_SP: info->i = r3000->r[31] & 0x1fffffff; break;
1233		case CPUINFO_INT_REGISTER + R3000_R31: info->i = r3000->r[31]; break;
1234
1235		/* --- the following bits of info are returned as pointers to data or functions --- */
1236		case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(r3000); break;
1237		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r3000); break;
1238		case CPUINFO_FCT_RESET: /* provided per-CPU */ break;
1239		case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(r3000); break;
1240		case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(r3000); break;
1241		case CPUINFO_FCT_BURN: info->burn = NULL; break;
1242		case CPUINFO_FCT_DISASSEMBLE: /* provided per-CPU */ break;
1243		case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &r3000->icount; break;
1244
1245		/* --- the following bits of info are returned as NULL-terminated strings --- */
1246		case CPUINFO_STR_NAME: strcpy(info->s, "R3000"); break;
1247		case CPUINFO_STR_FAMILY: strcpy(info->s, "MIPS II"); break;
1248		case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
1249		case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
1250		case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Aaron Giles"); break;
1251
1252		case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break;
1253
1254		case CPUINFO_STR_REGISTER + R3000_PC: sprintf(info->s, "PC: %08X", r3000->pc); break;
1255		case CPUINFO_STR_REGISTER + R3000_SR: sprintf(info->s, "SR: %08X", r3000->SR); break;
1256
1257		case CPUINFO_STR_REGISTER + R3000_R0: sprintf(info->s, "R0: %08X", r3000->r[0]); break;
1258		case CPUINFO_STR_REGISTER + R3000_R1: sprintf(info->s, "R1: %08X", r3000->r[1]); break;
1259		case CPUINFO_STR_REGISTER + R3000_R2: sprintf(info->s, "R2: %08X", r3000->r[2]); break;
1260		case CPUINFO_STR_REGISTER + R3000_R3: sprintf(info->s, "R3: %08X", r3000->r[3]); break;
1261		case CPUINFO_STR_REGISTER + R3000_R4: sprintf(info->s, "R4: %08X", r3000->r[4]); break;
1262		case CPUINFO_STR_REGISTER + R3000_R5: sprintf(info->s, "R5: %08X", r3000->r[5]); break;
1263		case CPUINFO_STR_REGISTER + R3000_R6: sprintf(info->s, "R6: %08X", r3000->r[6]); break;
1264		case CPUINFO_STR_REGISTER + R3000_R7: sprintf(info->s, "R7: %08X", r3000->r[7]); break;
1265		case CPUINFO_STR_REGISTER + R3000_R8: sprintf(info->s, "R8: %08X", r3000->r[8]); break;
1266		case CPUINFO_STR_REGISTER + R3000_R9: sprintf(info->s, "R9: %08X", r3000->r[9]); break;
1267		case CPUINFO_STR_REGISTER + R3000_R10: sprintf(info->s, "R10:%08X", r3000->r[10]); break;
1268		case CPUINFO_STR_REGISTER + R3000_R11: sprintf(info->s, "R11:%08X", r3000->r[11]); break;
1269		case CPUINFO_STR_REGISTER + R3000_R12: sprintf(info->s, "R12:%08X", r3000->r[12]); break;
1270		case CPUINFO_STR_REGISTER + R3000_R13: sprintf(info->s, "R13:%08X", r3000->r[13]); break;
1271		case CPUINFO_STR_REGISTER + R3000_R14: sprintf(info->s, "R14:%08X", r3000->r[14]); break;
1272		case CPUINFO_STR_REGISTER + R3000_R15: sprintf(info->s, "R15:%08X", r3000->r[15]); break;
1273		case CPUINFO_STR_REGISTER + R3000_R16: sprintf(info->s, "R16:%08X", r3000->r[16]); break;
1274		case CPUINFO_STR_REGISTER + R3000_R17: sprintf(info->s, "R17:%08X", r3000->r[17]); break;
1275		case CPUINFO_STR_REGISTER + R3000_R18: sprintf(info->s, "R18:%08X", r3000->r[18]); break;
1276		case CPUINFO_STR_REGISTER + R3000_R19: sprintf(info->s, "R19:%08X", r3000->r[19]); break;
1277		case CPUINFO_STR_REGISTER + R3000_R20: sprintf(info->s, "R20:%08X", r3000->r[20]); break;
1278		case CPUINFO_STR_REGISTER + R3000_R21: sprintf(info->s, "R21:%08X", r3000->r[21]); break;
1279		case CPUINFO_STR_REGISTER + R3000_R22: sprintf(info->s, "R22:%08X", r3000->r[22]); break;
1280		case CPUINFO_STR_REGISTER + R3000_R23: sprintf(info->s, "R23:%08X", r3000->r[23]); break;
1281		case CPUINFO_STR_REGISTER + R3000_R24: sprintf(info->s, "R24:%08X", r3000->r[24]); break;
1282		case CPUINFO_STR_REGISTER + R3000_R25: sprintf(info->s, "R25:%08X", r3000->r[25]); break;
1283		case CPUINFO_STR_REGISTER + R3000_R26: sprintf(info->s, "R26:%08X", r3000->r[26]); break;
1284		case CPUINFO_STR_REGISTER + R3000_R27: sprintf(info->s, "R27:%08X", r3000->r[27]); break;
1285		case CPUINFO_STR_REGISTER + R3000_R28: sprintf(info->s, "R28:%08X", r3000->r[28]); break;
1286		case CPUINFO_STR_REGISTER + R3000_R29: sprintf(info->s, "R29:%08X", r3000->r[29]); break;
1287		case CPUINFO_STR_REGISTER + R3000_R30: sprintf(info->s, "R30:%08X", r3000->r[30]); break;
1288		case CPUINFO_STR_REGISTER + R3000_R31: sprintf(info->s, "R31:%08X", r3000->r[31]); break;
1289		}
1290		}
1291
1292
1293		/**************************************************************************
1294		* CPU-specific set_info
1295		**************************************************************************/
1296
1297		CPU_GET_INFO( r3000be )
1298		{
1299		switch (state)
1300		{
1301		/* --- the following bits of info are returned as 64-bit signed integers --- */
1302		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
1303
1304		/* --- the following bits of info are returned as pointers to data or functions --- */
1305		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(r3000be); break;
1306		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(r3000be); break;
1307
1308		/* --- the following bits of info are returned as NULL-terminated strings --- */
1309		case CPUINFO_STR_NAME: strcpy(info->s, "R3000 (big)"); break;
1310
1311		default: CPU_GET_INFO_CALL(r3000); break;
1312		}
1313		}
1314
1315
1316		CPU_GET_INFO( r3000le )
1317		{
1318		switch (state)
1319		{
1320		/* --- the following bits of info are returned as 64-bit signed integers --- */
1321		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
1322
1323		/* --- the following bits of info are returned as pointers to data or functions --- */
1324		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(r3000le); break;
1325		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(r3000le); break;
1326
1327		/* --- the following bits of info are returned as NULL-terminated strings --- */
1328		case CPUINFO_STR_NAME: strcpy(info->s, "R3000 (little)"); break;
1329
1330		default: CPU_GET_INFO_CALL(r3000); break;
1331		}
1332		}
1333
1334
1335		CPU_GET_INFO( r3041be )
1336		{
1337		switch (state)
1338		{
1339		/* --- the following bits of info are returned as 64-bit signed integers --- */
1340		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
1341
1342		/* --- the following bits of info are returned as pointers to data or functions --- */
1343		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(r3000be); break;
1344		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(r3000be); break;
1345
1346		/* --- the following bits of info are returned as NULL-terminated strings --- */
1347		case CPUINFO_STR_NAME: strcpy(info->s, "R3041 (big)"); break;
1348
1349		default: CPU_GET_INFO_CALL(r3000); break;
1350		}
1351		}
1352
1353
1354		CPU_GET_INFO( r3041le )
1355		{
1356		switch (state)
1357		{
1358		/* --- the following bits of info are returned as 64-bit signed integers --- */
1359		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
1360
1361		/* --- the following bits of info are returned as pointers to data or functions --- */
1362		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(r3000le); break;
1363		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(r3000le); break;
1364
1365		/* --- the following bits of info are returned as NULL-terminated strings --- */
1366		case CPUINFO_STR_NAME: strcpy(info->s, "R3041 (little)"); break;
1367
1368		default: CPU_GET_INFO_CALL(r3000); break;
1369		}
1370		}
1371
1372		DEFINE_LEGACY_CPU_DEVICE(R3000BE, r3000be);
1373		DEFINE_LEGACY_CPU_DEVICE(R3000LE, r3000le);
1374
1375		DEFINE_LEGACY_CPU_DEVICE(R3041BE, r3041be);
1376		DEFINE_LEGACY_CPU_DEVICE(R3041LE, r3041le);

trunk/src/emu/cpu/mips/r3000.h
r20339	r20340
10	10	#define __R3000_H__
11	11
12	12
13
14	13	/***************************************************************************
15		~~COMP~~I~~LE-~~TIME DEFINITIONS
	14	INTERFACE CONFIGURATION MACROS
16	15	***************************************************************************/
	16
	17	#define MCFG_R3000_ENDIANNESS(_endianness) \
	18	r3000_device::static_set_endianness(*device, _endianness);
17	19
	20	#define MCFG_R3000_BRCOND0_INPUT(_devcb) \
	21	devcb = &r3000_device::static_set_brcond0_input(*device, DEVCB2_##_devcb);
18	22
	23	#define MCFG_R3000_BRCOND1_INPUT(_devcb) \
	24	devcb = &r3000_device::static_set_brcond1_input(*device, DEVCB2_##_devcb);
	25
	26	#define MCFG_R3000_BRCOND2_INPUT(_devcb) \
	27	devcb = &r3000_device::static_set_brcond2_input(*device, DEVCB2_##_devcb);
	28
	29	#define MCFG_R3000_BRCOND3_INPUT(_devcb) \
	30	devcb = &r3000_device::static_set_brcond3_input(*device, DEVCB2_##_devcb);
	31
	32
19	33	/***************************************************************************
20	34	REGISTER ENUMERATION
21	35	***************************************************************************/
r20339	r20340
42	56	#define R3000_IRQ5 5 /* IRQ5 */
43	57
44	58
45		/***************************************************************************
46		STRUCTURES
47		***************************************************************************/
	59	//**************************************************************************
	60	// TYPE DEFINITIONS
	61	//**************************************************************************
48	62
49		struct r3000_cpu_core
	63	// ======================> r3000_device
	64
	65	class r3000_device : public cpu_device
50	66	{
51		UINT8 hasfpu; /* 1 if we have an FPU, 0 otherwise */
52		size_t icache; /* code cache size */
53		size_t dcache; /* data cache size */
	67	protected:
	68	enum chip_type
	69	{
	70	CHIP_TYPE_R3041,
	71	CHIP_TYPE_R3051,
	72	CHIP_TYPE_R3052,
	73	CHIP_TYPE_R3071,
	74	CHIP_TYPE_R3081,
	75	};
	76
	77	// construction/destruction
	78	r3000_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock, chip_type chiptype);
	79	virtual ~r3000_device();
	80
	81	public:
	82	// inline configuration helpers
	83	static void static_set_endianness(device_t &device, endianness_t endianness)
	84	{
	85	downcast<r3000_device &>(device).m_endianness = endianness;
	86	}
	87
	88	template<class _Object> static devcb2_base &static_set_brcond0_input(device_t &device, _Object object)
	89	{
	90	return downcast<r3000_device &>(device).m_in_brcond0.set_callback(object);
	91	}
	92
	93	template<class _Object> static devcb2_base &static_set_brcond1_input(device_t &device, _Object object)
	94	{
	95	return downcast<r3000_device &>(device).m_in_brcond1.set_callback(object);
	96	}
	97
	98	template<class _Object> static devcb2_base &static_set_brcond2_input(device_t &device, _Object object)
	99	{
	100	return downcast<r3000_device &>(device).m_in_brcond2.set_callback(object);
	101	}
	102
	103	template<class _Object> static devcb2_base &static_set_brcond3_input(device_t &device, _Object object)
	104	{
	105	return downcast<r3000_device &>(device).m_in_brcond3.set_callback(object);
	106	}
	107
	108	protected:
	109	// device-level overrides
	110	virtual void device_start();
	111	virtual void device_reset();
	112	virtual void device_post_load();
	113
	114	// device_execute_interface overrides
	115	virtual UINT32 execute_min_cycles() const;
	116	virtual UINT32 execute_max_cycles() const;
	117	virtual UINT32 execute_input_lines() const;
	118	virtual void execute_run();
	119	virtual void execute_set_input(int inputnum, int state);
	120
	121	// device_memory_interface overrides
	122	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
	123
	124	// device_state_interface overrides
	125	virtual void state_import(const device_state_entry &entry);
	126	virtual void state_export(const device_state_entry &entry);
	127	virtual void state_string_export(const device_state_entry &entry, astring &string);
	128
	129	// device_disasm_interface overrides
	130	virtual UINT32 disasm_min_opcode_bytes() const;
	131	virtual UINT32 disasm_max_opcode_bytes() const;
	132	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	133
	134	// memory accessors
	135	struct r3000_data_accessors
	136	{
	137	UINT8 (r3000_device::*m_read_byte)(offs_t byteaddress);
	138	UINT16 (r3000_device::*m_read_word)(offs_t byteaddress);
	139	UINT32 (r3000_device::*m_read_dword)(offs_t byteaddress);
	140	void (r3000_device::*m_write_byte)(offs_t byteaddress, UINT8 data);
	141	void (r3000_device::*m_write_word)(offs_t byteaddress, UINT16 data);
	142	void (r3000_device::*m_write_dword)(offs_t byteaddress, UINT32 data);
	143	};
	144
	145	UINT32 readop(off_t pc);
	146	UINT8 readmem(offs_t offset);
	147	UINT16 readmem_word(offs_t offset);
	148	UINT32 readmem_dword(offs_t offset);
	149	void writemem(offs_t offset, UINT8 data);
	150	void writemem_word(offs_t offset, UINT16 data);
	151	void writemem_dword(offs_t offset, UINT32 data);
	152
	153	UINT8 readcache_be(offs_t offset);
	154	UINT16 readcache_be_word(offs_t offset);
	155	UINT32 readcache_be_dword(offs_t offset);
	156	void writecache_be(offs_t offset, UINT8 data);
	157	void writecache_be_word(offs_t offset, UINT16 data);
	158	void writecache_be_dword(offs_t offset, UINT32 data);
	159
	160	UINT8 readcache_le(offs_t offset);
	161	UINT16 readcache_le_word(offs_t offset);
	162	UINT32 readcache_le_dword(offs_t offset);
	163	void writecache_le(offs_t offset, UINT8 data);
	164	void writecache_le_word(offs_t offset, UINT16 data);
	165	void writecache_le_dword(offs_t offset, UINT32 data);
	166
	167	// interrupts
	168	void generate_exception(int exception);
	169	void check_irqs();
	170	void set_irq_line(int irqline, int state);
	171	void invalid_instruction();
	172
	173	// instructions
	174	UINT32 get_cop0_reg(int idx);
	175	void set_cop0_reg(int idx, UINT32 val);
	176	UINT32 get_cop0_creg(int idx);
	177	void set_cop0_creg(int idx, UINT32 val);
	178	void handle_cop0();
	179
	180	UINT32 get_cop1_reg(int idx);
	181	void set_cop1_reg(int idx, UINT32 val);
	182	UINT32 get_cop1_creg(int idx);
	183	void set_cop1_creg(int idx, UINT32 val);
	184	void handle_cop1();
	185
	186	UINT32 get_cop2_reg(int idx);
	187	void set_cop2_reg(int idx, UINT32 val);
	188	UINT32 get_cop2_creg(int idx);
	189	void set_cop2_creg(int idx, UINT32 val);
	190	void handle_cop2();
	191
	192	UINT32 get_cop3_reg(int idx);
	193	void set_cop3_reg(int idx, UINT32 val);
	194	UINT32 get_cop3_creg(int idx);
	195	void set_cop3_creg(int idx, UINT32 val);
	196	void handle_cop3();
	197
	198	// complex opcodes
	199	void lwl_be();
	200	void lwr_be();
	201	void swl_be();
	202	void swr_be();
	203
	204	void lwl_le();
	205	void lwr_le();
	206	void swl_le();
	207	void swr_le();
	208
	209	// address spaces
	210	const address_space_config m_program_config_be;
	211	const address_space_config m_program_config_le;
	212	address_space *m_program;
	213	direct_read_data *m_direct;
	214
	215	// configuration
	216	chip_type m_chip_type;
	217	bool m_hasfpu;
	218	endianness_t m_endianness;
	219
	220	// core registers
	221	UINT32 m_pc;
	222	UINT32 m_nextpc;
	223	UINT32 m_hi;
	224	UINT32 m_lo;
	225	UINT32 m_r[32];
	226
	227	// COP registers
	228	UINT32 m_cpr[4][32];
	229	UINT32 m_ccr[4][32];
	230
	231	// internal stuff
	232	UINT32 m_ppc;
	233	UINT32 m_op;
	234	int m_icount;
	235	int m_interrupt_cycles;
	236
	237	// endian-dependent load/store
	238	void (r3000_device::*m_lwl)();
	239	void (r3000_device::*m_lwr)();
	240	void (r3000_device::*m_swl)();
	241	void (r3000_device::*m_swr)();
	242
	243	// memory accesses
	244	r3000_data_accessors *m_cur;
	245	r3000_data_accessors m_memory_hand;
	246	r3000_data_accessors m_cache_hand;
	247
	248	// cache memory
	249	UINT32 * m_cache;
	250	UINT32 * m_icache;
	251	UINT32 * m_dcache;
	252	size_t m_cache_size;
	253	size_t m_icache_size;
	254	size_t m_dcache_size;
	255
	256	// I/O
	257	devcb2_read_line m_in_brcond0;
	258	devcb2_read_line m_in_brcond1;
	259	devcb2_read_line m_in_brcond2;
	260	devcb2_read_line m_in_brcond3;
54	261	};
55	262
56	263
57		/***************************************************************************
58		PUBLIC FUNCTIONS
59		***************************************************************************/
	264	// ======================> r3041_device
60	265
61		DECLARE_LEGACY_CPU_DEVICE(R3000BE, r3000be);
62		DECLARE_LEGACY_CPU_DEVICE(R3000LE, r3000le);
	266	class r3041_device : public r3000_device
	267	{
	268	public:
	269	r3041_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	270	};
63	271
64		DECLARE_LEGACY_CPU_DEVICE(R3041BE, r3041be);
65		DECLARE_LEGACY_CPU_DEVICE(R3041LE, r3041le);
66	272
	273	// ======================> r3051_device
	274
	275	class r3051_device : public r3000_device
	276	{
	277	public:
	278	r3051_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	279	};
	280
	281
	282	// ======================> r3052_device
	283
	284	class r3052_device : public r3000_device
	285	{
	286	public:
	287	r3052_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	288	};
	289
	290
	291	// ======================> r3071_device
	292
	293	class r3071_device : public r3000_device
	294	{
	295	public:
	296	r3071_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	297	};
	298
	299
	300	// ======================> r3081_device
	301
	302	class r3081_device : public r3000_device
	303	{
	304	public:
	305	r3081_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	306	};
	307
	308
	309	// device type definition
	310
	311	extern const device_type R3041;
	312	extern const device_type R3051;
	313	extern const device_type R3052;
	314	extern const device_type R3071;
	315	extern const device_type R3081;
	316
67	317	#endif /* __R3000_H__ */

trunk/src/mame/drivers/speglsht.c
r20339	r20340
326	326	&st0016_charram
327	327	};
328	328
329		static const r3000_cpu_core r3000_config =
330		{
331		0,
332		4096, /* code cache size */
333		2048 /* data cache size */
334		};
335
336	329	MACHINE_RESET_MEMBER(speglsht_state,speglsht)
337	330	{
338	331	memset(m_shared,0,0x1000);
r20339	r20340
393	386
394	387	MCFG_CPU_VBLANK_INT_DRIVER("screen", speglsht_state, irq0_line_hold)
395	388
396		MCFG_CPU_ADD("sub", R3000LE, 25000000)
397		MCFG_CPU_CONFIG(r3000_config)
	389	MCFG_CPU_ADD("sub", R3051, 25000000)
	390	MCFG_R3000_ENDIANNESS(ENDIANNESS_LITTLE)
398	391	MCFG_CPU_PROGRAM_MAP(speglsht_mem)
399	392	MCFG_CPU_VBLANK_INT_DRIVER("screen", speglsht_state, irq4_line_assert)
400	393

trunk/src/mame/drivers/turrett.c
r20339	r20340
115	115	INPUT_PORTS_END
116	116
117	117
118		static const r3000_cpu_core r3000_config =
119		{
120		0, /* 1 if we have an FPU, 0 otherwise */
121		2048, /* code cache size */
122		512 /* data cache size */
123		};
124	118
125
126	119	static MACHINE_CONFIG_START( turrett, turrett_state )
127	120	/* basic machine hardware */
128		MCFG_CPU_ADD("maincpu", R3041BE, R3041_CLOCK)
	121	MCFG_CPU_ADD("maincpu", R3041, R3041_CLOCK)
	122	MCFG_R3000_ENDIANNESS(ENDIANNESS_BIG)
129	123	MCFG_CPU_PROGRAM_MAP(cpu_map)
130		MCFG_CPU_CONFIG(r3000_config)
131	124
132	125	/* video hardware */
133	126	MCFG_SCREEN_ADD("screen", RASTER)

trunk/src/mame/drivers/jaguar.c
r20339	r20340
1545	1545	*
1546	1546	*************************************/
1547	1547
1548		static const r~~3000~~_cpu_core ~~r3000~~_config =
	1548	static const jaguar_cpu_config gpu_config =
1549	1549	{
1550		0, /* 1 if we have an FPU, 0 otherwise */
1551		4096, /* code cache size */
1552		4096 /* data cache size */
1553		};
1554
1555
1556		static const jaguar_cpu_config gpu_config =
1557		{
1558	1550	&jaguar_state::gpu_cpu_int
1559	1551	};
1560	1552
r20339	r20340
1567	1559	static MACHINE_CONFIG_START( cojagr3k, jaguar_state )
1568	1560
1569	1561	/* basic machine hardware */
1570		MCFG_CPU_ADD("maincpu", R3041BE, R3000_CLOCK)
1571		MCFG_CPU_CONFIG(r3000_config)
	1562	MCFG_CPU_ADD("maincpu", R3041, R3000_CLOCK)
	1563	MCFG_R3000_ENDIANNESS(ENDIANNESS_BIG)
1572	1564	MCFG_CPU_PROGRAM_MAP(r3000_map)
1573	1565
1574	1566	MCFG_CPU_ADD("gpu", JAGUARGPU, COJAG_CLOCK/2)
r20339	r20340
2263	2255	m_is_cojag = true;
2264	2256
2265	2257	/* copy over the ROM */
2266		m_is_r3000 = (m_main_cpu->type() == R3041BE);
	2258	m_is_r3000 = (m_main_cpu->type() == R3041);
2267	2259
2268	2260	/* install synchronization hooks for GPU */
2269	2261	if (m_is_r3000)

trunk/src/mame/drivers/policetr.c
r20339	r20340
402	402	*
403	403	*************************************/
404	404
405		static const r3000_cpu_core r3000_config =
406		{
407		0, /* 1 if we have an FPU, 0 otherwise */
408		4096, /* code cache size */
409		4096 /* data cache size */
410		};
411
412
413	405	static MACHINE_CONFIG_START( policetr, policetr_state )
414	406
415	407	/* basic machine hardware */
416		MCFG_CPU_ADD("maincpu", R3000BE, MASTER_CLOCK/2)
417		MCFG_CPU_CONFIG(r3000_config)
	408	MCFG_CPU_ADD("maincpu", R3041, MASTER_CLOCK/2)
	409	MCFG_R3000_ENDIANNESS(ENDIANNESS_BIG)
418	410	MCFG_CPU_PROGRAM_MAP(policetr_map)
419	411	MCFG_CPU_VBLANK_INT_DRIVER("screen", policetr_state, irq4_gen)
420	412

trunk/src/mame/drivers/srmp5.c
r20339	r20340
501	501	&st0016_charram
502	502	};
503	503
504		static const r3000_cpu_core r3000_config =
505		{
506		1, /* 1 if we have an FPU, 0 otherwise */
507		4096, /* code cache size */
508		4096 /* data cache size */
509		};
510
511	504	static const gfx_layout tile_16x8x8_layout =
512	505	{
513	506	16,8,
r20339	r20340
545	538	MCFG_CPU_IO_MAP(st0016_io)
546	539	MCFG_CPU_VBLANK_INT_DRIVER("screen", srmp5_state, irq0_line_hold)
547	540
548		MCFG_CPU_ADD("sub", R3000LE, 25000000)
549		MCFG_CPU_CONFIG(r3000_config)
	541	MCFG_CPU_ADD("sub", R3051, 25000000)
	542	MCFG_R3000_ENDIANNESS(ENDIANNESS_LITTLE)
550	543	MCFG_CPU_PROGRAM_MAP(srmp5_mem)
551	544	MCFG_CPU_VBLANK_INT_DRIVER("screen", srmp5_state, irq4_line_assert)
552	545

199869 Revisions