trunk/src/mame/machine/3do.c
| r20187 | r20188 | |
|---|
| 667 | 667 | logerror( "%08X: CLIO read offset = %08X\n", machine().device("maincpu")->safe_pc(), offset * 4 ); |
| 668 | 668 | } |
| 669 | 669 | |
| 670 | /* TODO: for debug, to be removed once that we write the CPU core */ |
| 671 | if(offset >= 0x3800/4 && offset <= 0x39ff/4) |
| 672 | { |
| 673 | UINT32 res = 0; |
| 674 | offset &= (0xff/4); |
| 675 | res = (m_dspp.EO[(offset<<1)+0] << 16); |
| 676 | res |= (m_dspp.EO[(offset<<1)+1] & 0xffff); |
| 677 | return res; |
| 678 | } |
| 679 | |
| 680 | if(offset >= 0x3c00/4 && offset <= 0x3fff/4) |
| 681 | { |
| 682 | UINT16 res; |
| 683 | offset &= (0x1ff/4); |
| 684 | res = m_dspp.EO[offset] & 0xffff; |
| 685 | return res; |
| 686 | } |
| 687 | |
| 670 | 688 | switch( offset ) |
| 671 | 689 | { |
| 672 | 690 | case 0x0000/4: |
| r20187 | r20188 | |
|---|
| 773 | 791 | offset != 0x118/4 && offset != 0x11c/4) |
| 774 | 792 | logerror( "%08X: CLIO write offset = %08X, data = %08X, mask = %08X\n", machine().device("maincpu")->safe_pc(), offset*4, data, mem_mask ); |
| 775 | 793 | |
| 794 | /* TODO: for debug, to be removed once that we write the CPU core */ |
| 795 | if(offset >= 0x1800/4 && offset <= 0x1fff/4) |
| 796 | { |
| 797 | offset &= (0x3ff/4); |
| 798 | m_dspp.N[(offset<<1)+0] = data >> 16; |
| 799 | m_dspp.N[(offset<<1)+1] = data & 0xffff; |
| 800 | return; |
| 801 | } |
| 802 | |
| 803 | if(offset >= 0x2000/4 && offset <= 0x2fff/4) |
| 804 | { |
| 805 | offset &= (0x7ff/4); |
| 806 | m_dspp.N[offset] = data & 0xffff; |
| 807 | return; |
| 808 | } |
| 809 | |
| 810 | if(offset >= 0x3000/4 && offset <= 0x31ff/4) |
| 811 | { |
| 812 | offset &= (0xff/4); |
| 813 | m_dspp.EI[(offset<<1)+0] = data >> 16; |
| 814 | m_dspp.EI[(offset<<1)+1] = data & 0xffff; |
| 815 | return; |
| 816 | } |
| 817 | |
| 818 | if(offset >= 0x3400/4 && offset <= 0x37ff/4) |
| 819 | { |
| 820 | offset &= (0x1ff/4); |
| 821 | m_dspp.EI[offset] = data & 0xffff; |
| 822 | return; |
| 823 | } |
| 824 | |
| 776 | 825 | switch( offset ) |
| 777 | 826 | { |
| 778 | 827 | case 0x0000/4: |
| r20187 | r20188 | |
|---|
| 983 | 1032 | state->m_clio.cstatbits = 0x01; /* bit 0 = reset of clio caused by power on */ |
| 984 | 1033 | state->m_clio.unclerev = 0x03800000; |
| 985 | 1034 | state->m_clio.expctl = 0x80; /* ARM has the expansion bus */ |
| 1035 | state->m_dspp.N = auto_alloc_array(machine, UINT16, 0x800 ); |
| 1036 | state->m_dspp.EI = auto_alloc_array(machine, UINT16, 0x200 ); |
| 1037 | state->m_dspp.EO = auto_alloc_array(machine, UINT16, 0x200 ); |
| 1038 | |
| 1039 | state_save_register_global_pointer(machine, state->m_dspp.N, 0x800); |
| 1040 | state_save_register_global_pointer(machine, state->m_dspp.EI, 0x200); |
| 1041 | state_save_register_global_pointer(machine, state->m_dspp.EO, 0x200); |
| 986 | 1042 | } |
| 987 | 1043 | |
| 988 | 1044 | |