MAME SVN History

199869 Revisions

r20172 Thursday 10th January, 2013 at 01:50:29 UTC by Angelo Salese
NVRAM hook-up

[src/mame/drivers]	3do.c
[src/mame/includes]	3do.h
[src/mame/machine]	3do.c

trunk/src/mame/machine/3do.c
r20171	r20172
133	133	{
134	134	m_clio.timer_count[i]--;
135	135
136		if(m_clio.timer_count[i] == 0) // timer hit
	136	if(m_clio.timer_count[i] == 0xffffffff) // timer hit
137	137	{
138	138	if(i & 1) // odd timer irq fires
139	139	m_3do_request_fiq(8 << (7-(i >> 1)),0);
r20171	r20172
141	141	if(timer_flag & 2)
142	142	m_clio.timer_count[i] = m_clio.timer_backup[i];
143	143	else
144		m_clio.timer_ctrl &= (~1 << i*4);
	144	m_clio.timer_ctrl &= ~(1 << i*4);
145	145	}
146	146	}
147	147	}
148	148	}
149	149
150		READ32_MEMBER(_3do_state::_3do_nvarea_r){
151		logerror( "%08X: NVRAM read offset = %08X\n", machine().device("maincpu")->safe_pc(), offset );
152		return 0;
153		}
	150	READ8_MEMBER(_3do_state::_3do_nvarea_r) { return m_nvram[offset]; }
	151	WRITE8_MEMBER(_3do_state::_3do_nvarea_w) { m_nvram[offset] = data; }
154	152
155		WRITE32_MEMBER(_3do_state::_3do_nvarea_w){
156		logerror( "%08X: NVRAM write offset = %08X, data = %08X, mask = %08X\n", machine().device("maincpu")->safe_pc(), offset, data, mem_mask );
157		}
158	153
159	154
160
161	155	/*
162	156	I have no idea what piece of hardware this is. Possibly some kind of communication hardware using shift registers.
163	157
r20171	r20172
642	636	READ32_MEMBER(_3do_state::_3do_clio_r)
643	637	{
644	638	if (!space.debugger_access())
645		logerror( "%08X: CLIO read offset = %08X\n", machine().device("maincpu")->safe_pc(), offset * 4 );
	639	if(offset != 0x40/4 && offset != 0x44/4 && offset != 0x48/4 && offset != 0x4c/4)
	640	logerror( "%08X: CLIO read offset = %08X\n", machine().device("maincpu")->safe_pc(), offset * 4 );
646	641
647	642	switch( offset )
648	643	{
r20171	r20172
746	741
747	742	WRITE32_MEMBER(_3do_state::_3do_clio_w)
748	743	{
749		logerror( "%08X: CLIO write offset = %08X, data = %08X, mask = %08X\n", machine().device("maincpu")->safe_pc(), offset*4, data, mem_mask );
	744	if(offset != 0x40/4 && offset != 0x44/4 && offset != 0x48/4 && offset != 0x4c/4)
	745	logerror( "%08X: CLIO write offset = %08X, data = %08X, mask = %08X\n", machine().device("maincpu")->safe_pc(), offset*4, data, mem_mask );
750	746
751	747	switch( offset )
752	748	{
r20171	r20172
844	840	m_clio.adbctl = data;
845	841	break;
846	842
847		/* only lower 16-bits are ~~upload~~ed */
	843	/* only lower 16-bits can be written */
848	844	case 0x0100/4: case 0x0108/4: case 0x0110/4: case 0x0118/4:
849	845	case 0x0120/4: case 0x0128/4: case 0x0130/4: case 0x0138/4:
850	846	case 0x0140/4: case 0x0148/4: case 0x0150/4: case 0x0158/4:

trunk/src/mame/includes/3do.h
r20171	r20172
142	142	MADAM m_madam;
143	143	CLIO m_clio;
144	144	SVF m_svf;
	145	UINT8 m_nvram[0x8000];
145	146	// UINT8 m_video_bits[512];
146		DECLARE_READ32_MEMBER(_3do_nvarea_r);
147		DECLARE_WRITE32_MEMBER(_3do_nvarea_w);
	147	DECLARE_READ8_MEMBER(_3do_nvarea_r);
	148	DECLARE_WRITE8_MEMBER(_3do_nvarea_w);
148	149	DECLARE_READ32_MEMBER(_3do_slow2_r);
149	150	DECLARE_WRITE32_MEMBER(_3do_slow2_w);
150	151	DECLARE_READ32_MEMBER(_3do_svf_r);

trunk/src/mame/drivers/3do.c
r20171	r20172
98	98	#include "cpu/arm7/arm7.h"
99	99
100	100
	101
101	102	#define X2_CLOCK_PAL 59000000
102	103	#define X2_CLOCK_NTSC 49090000
103	104	#define X601_CLOCK XTAL_16_9344MHz
r20171	r20172
108	109	AM_RANGE(0x00200000, 0x003FFFFF) AM_RAM AM_SHARE("vram") /* VRAM */
109	110	AM_RANGE(0x03000000, 0x030FFFFF) AM_ROMBANK("bank2") /* BIOS */
110	111	AM_RANGE(0x03100000, 0x0313FFFF) AM_RAM /* Brooktree? */
111		AM_RANGE(0x03140000, 0x0315FFFF) AM_READWRITE(_3do_nvarea_r, _3do_nvarea_w) /* NVRAM */
	112	AM_RANGE(0x03140000, 0x0315FFFF) AM_READWRITE8(_3do_nvarea_r, _3do_nvarea_w, 0x000000ff) /* NVRAM */
112	113	AM_RANGE(0x03180000, 0x031BFFFF) AM_READWRITE(_3do_slow2_r, _3do_slow2_w) /* Slow bus - additional expansion */
113	114	AM_RANGE(0x03200000, 0x0320FFFF) AM_READWRITE(_3do_svf_r, _3do_svf_w) /* special vram access1 */
114	115	AM_RANGE(0x03300000, 0x033FFFFF) AM_READWRITE(_3do_madam_r, _3do_madam_w) /* address decoder */
r20171	r20172
151	152	NULL
152	153	};
153	154
	155	static NVRAM_HANDLER( _3do )
	156	{
	157	_3do_state *state = machine.driver_data<_3do_state>();
	158	UINT8 *nvram = state->m_nvram;
	159
	160	if (read_or_write)
	161	file->write(nvram,0x8000);
	162	else
	163	{
	164	if (file)
	165	file->read(nvram,0x8000);
	166	else
	167	{
	168	/* fill in the default values */
	169	memset(nvram,0xff,0x8000);
	170	}
	171	}
	172	}
	173
154	174	static MACHINE_CONFIG_START( 3do, _3do_state )
155	175
156	176	/* Basic machine hardware */
157	177	MCFG_CPU_ADD( "maincpu", ARM7_BE, XTAL_50MHz/4 )
158	178	MCFG_CPU_PROGRAM_MAP( 3do_mem)
159	179
	180	MCFG_NVRAM_HANDLER(_3do)
	181
160	182	MCFG_TIMER_DRIVER_ADD_PERIODIC("timer_x16", _3do_state, timer_x16_cb, attotime::from_hz(12000)) // TODO: timing
161	183
162	184	MCFG_VIDEO_START_OVERRIDE(_3do_state, _3do )

199869 Revisions