trunk/src/mame/machine/3do.c
| r20169 | r20170 | |
| 61 | 61 | #define LOG(x) do { if (VERBOSE) printf x; } while (0) |
| 62 | 62 | |
| 63 | 63 | /* |
| 64 | | 0x80000000 Second Priority (?) |
| 64 | 0x80000000 Second Priority |
| 65 | 65 | 0x40000000 SW irq |
| 66 | 66 | 0x20000000 DMA<->EXP |
| 67 | 67 | 0x1fff0000 DMA RAM->DSPP * |
| 68 | 68 | 0x0000f000 DMA DSPP->RAM * |
| 69 | 69 | 0x00000800 DSPP |
| 70 | 70 | 0x00000400 Timer 1 |
| 71 | | 0x00000200 Timer 3 |
| 71 | 0x00000200 Timer 3 <- needed to surpass current hang point |
| 72 | 72 | 0x00000100 Timer 5 |
| 73 | 73 | 0x00000080 Timer 7 |
| 74 | 74 | 0x00000040 Timer 9 |
| r20169 | r20170 | |
| 79 | 79 | 0x00000002 Vertical 1 |
| 80 | 80 | 0x00000001 Vertical 0 |
| 81 | 81 | */ |
| 82 | | void _3do_state::m_3do_request_fiq0(UINT32 irq_req) |
| 82 | void _3do_state::m_3do_request_fiq(UINT32 irq_req, UINT8 type) |
| 83 | 83 | { |
| 84 | | m_clio.irq0 |= irq_req; |
| 84 | if(type) |
| 85 | m_clio.irq1 |= irq_req; |
| 86 | else |
| 87 | m_clio.irq0 |= irq_req; |
| 85 | 88 | |
| 86 | | if(m_clio.irq0 & m_clio.irq0_enable) |
| 87 | | m_maincpu->set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE); |
| 89 | if(m_clio.irq1) |
| 90 | m_clio.irq0 |= 1 << 31; // Second Priority |
| 91 | else |
| 92 | m_clio.irq0 &= ~(1 << 31); |
| 88 | 93 | |
| 89 | | if((m_clio.irq0 & m_clio.irq0_enable) == 0) |
| 90 | | m_maincpu->set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE); |
| 94 | if((m_clio.irq0 & m_clio.irq0_enable) || (m_clio.irq1 & m_clio.irq1_enable)) |
| 95 | { |
| 96 | printf("Go irq %08x & %08x %08x & %08x\n",m_clio.irq0, m_clio.irq0_enable, m_clio.irq1, m_clio.irq1_enable); |
| 97 | generic_pulse_irq_line(m_maincpu, ARM7_FIRQ_LINE, 1); |
| 98 | } |
| 91 | 99 | } |
| 92 | 100 | |
| 93 | 101 | /* |
| r20169 | r20170 | |
| 103 | 111 | 0x00000002 Disk Inserted |
| 104 | 112 | 0x00000001 DMA Player bus |
| 105 | 113 | */ |
| 106 | | void _3do_state::m_3do_request_fiq1(UINT32 irq_req) |
| 107 | | { |
| 108 | | m_clio.irq1 |= irq_req; |
| 109 | 114 | |
| 110 | | if(m_clio.irq1 & m_clio.irq1_enable) |
| 111 | | m_maincpu->set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE); |
| 112 | 115 | |
| 113 | | if((m_clio.irq1 & m_clio.irq1_enable) == 0) |
| 114 | | m_maincpu->set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE); |
| 115 | | } |
| 116 | | |
| 117 | | |
| 118 | 116 | READ32_MEMBER(_3do_state::_3do_nvarea_r){ |
| 119 | 117 | logerror( "%08X: NVRAM read offset = %08X\n", machine().device("maincpu")->safe_pc(), offset ); |
| 120 | 118 | return 0; |
| r20169 | r20170 | |
| 608 | 606 | |
| 609 | 607 | READ32_MEMBER(_3do_state::_3do_clio_r) |
| 610 | 608 | { |
| 611 | | logerror( "%08X: CLIO read offset = %08X\n", machine().device("maincpu")->safe_pc(), offset * 4 ); |
| 609 | if (!space.debugger_access()) |
| 610 | logerror( "%08X: CLIO read offset = %08X\n", machine().device("maincpu")->safe_pc(), offset * 4 ); |
| 612 | 611 | |
| 613 | 612 | switch( offset ) |
| 614 | 613 | { |
| r20169 | r20170 | |
| 759 | 758 | return m_clio.uncle_rom; |
| 760 | 759 | |
| 761 | 760 | default: |
| 761 | if (!space.debugger_access()) |
| 762 | 762 | logerror( "%08X: unhandled CLIO read offset = %08X\n", machine().device("maincpu")->safe_pc(), offset * 4 ); |
| 763 | 763 | break; |
| 764 | 764 | } |
| r20169 | r20170 | |
| 806 | 806 | case 0x0040/4: |
| 807 | 807 | LOG(("%08x PEND0\n",data)); |
| 808 | 808 | m_clio.irq0 |= data; |
| 809 | | m_3do_request_fiq0(0); |
| 809 | m_3do_request_fiq(0,0); |
| 810 | 810 | break; |
| 811 | 811 | case 0x0044/4: |
| 812 | 812 | LOG(("%08x PEND0 CLEAR\n",data)); |
| 813 | 813 | m_clio.irq0 &= ~data; |
| 814 | | m_3do_request_fiq0(0); |
| 814 | m_3do_request_fiq(0,0); |
| 815 | 815 | break; |
| 816 | 816 | case 0x0048/4: |
| 817 | 817 | LOG(("%08x MASK0\n",data)); |
| 818 | 818 | m_clio.irq0_enable |= data; |
| 819 | | m_3do_request_fiq0(0); |
| 819 | m_3do_request_fiq(0,0); |
| 820 | 820 | break; |
| 821 | 821 | case 0x004c/4: |
| 822 | 822 | LOG(("%08x MASK0 CLEAR\n",data)); |
| 823 | 823 | m_clio.irq0_enable &= ~data; |
| 824 | | m_3do_request_fiq0(0); |
| 824 | m_3do_request_fiq(0,0); |
| 825 | 825 | break; |
| 826 | 826 | case 0x0050/4: |
| 827 | 827 | m_clio.mode |= data; |
| r20169 | r20170 | |
| 838 | 838 | case 0x0060/4: |
| 839 | 839 | LOG(("%08x PEND1\n",data)); |
| 840 | 840 | m_clio.irq1 |= data; |
| 841 | | m_3do_request_fiq1(0); |
| 841 | m_3do_request_fiq(0,1); |
| 842 | 842 | break; |
| 843 | 843 | case 0x0064/4: |
| 844 | 844 | LOG(("%08x PEND1 CLEAR\n",data)); |
| 845 | 845 | m_clio.irq1 &= ~data; |
| 846 | | m_3do_request_fiq1(0); |
| 846 | m_3do_request_fiq(0,1); |
| 847 | 847 | break; |
| 848 | 848 | case 0x0068/4: |
| 849 | 849 | LOG(("%08x MASK1\n",data)); |
| 850 | 850 | m_clio.irq1_enable |= data; |
| 851 | | m_3do_request_fiq1(0); |
| 851 | m_3do_request_fiq(0,1); |
| 852 | 852 | break; |
| 853 | 853 | case 0x006c/4: |
| 854 | 854 | LOG(("%08x MASK1 CLEAR\n",data)); |
| 855 | 855 | m_clio.irq1_enable &= ~data; |
| 856 | | m_3do_request_fiq1(0); |
| 856 | m_3do_request_fiq(0,1); |
| 857 | 857 | break; |
| 858 | 858 | case 0x0080/4: |
| 859 | 859 | m_clio.hdelay = data; |