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r20168 Wednesday 9th January, 2013 at 22:39:02 UTC by Angelo Salese
ABC of 3do irq routines

[src/mame/drivers]	3do.c
[src/mame/includes]	3do.h
[src/mame/machine]	3do.c

trunk/src/mame/drivers/3do.c

r20167	r20168
131	131
132	132	void _3do_state::machine_reset()
133	133	{
134
135		m_maincpu = downcast<legacy_cpu_device*>( machine().device<cpu_device>("maincpu") );
136
137	134	membank("bank2")->set_base(memregion("user1")->base());
138	135
139	136	/* configure overlay */

trunk/src/mame/machine/3do.c

r20167	r20168
55	55
56	56	#include "emu.h"
57	57	#include "includes/3do.h"
	58	#include "cpu/arm7/arm7core.h"
58	59
	60	#define   VERBOSE         1
	61	#define LOG(x) do { if (VERBOSE) printf x; } while (0)
59	62
	63	/*
	64	0x80000000 Second Priority (?)
	65	0x40000000 SW irq
	66	0x20000000 DMA<->EXP
	67	0x1fff0000 DMA RAM->DSPP *
	68	0x0000f000 DMA DSPP->RAM *
	69	0x00000800 DSPP
	70	0x00000400 Timer  1
	71	0x00000200 Timer  3
	72	0x00000100 Timer  5
	73	0x00000080 Timer  7
	74	0x00000040 Timer  9
	75	0x00000020 Timer 11
	76	0x00000010 Timer 13
	77	0x00000008 Timer 15
	78	0x00000004 Expansion Bus
	79	0x00000002 Vertical 1
	80	0x00000001 Vertical 0
	81	*/
	82	void _3do_state::m_3do_request_fiq0(UINT32 irq_req)
	83	{
	84	m_clio.irq0 |= irq_req;
60	85
	86	if(m_clio.irq0 & m_clio.irq0_enable)
	87	m_maincpu->set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE);
61	88
	89	if((m_clio.irq0 & m_clio.irq0_enable) == 0)
	90	m_maincpu->set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE);
	91	}
62	92
	93	/*
	94	0x00000400 DSPPOVER (Red rev. only)
	95	0x00000200 DSPPUNDER (Red rev. only)
	96	0x00000100 BadBits
	97	0x00000080 DMA<-External
	98	0x00000040 DMA->External
	99	0x00000020 DMA<-Uncle
	100	0x00000010 DMA->Uncle
	101	0x00000008 DMA RAM->DSPP N
	102	0x00000004 SlowBus
	103	0x00000002 Disk Inserted
	104	0x00000001 DMA Player bus
	105	*/
	106	void _3do_state::m_3do_request_fiq1(UINT32 irq_req)
	107	{
	108	m_clio.irq1 |= irq_req;
63	109
	110	if(m_clio.irq1 & m_clio.irq1_enable)
	111	m_maincpu->set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE);
	112
	113	if((m_clio.irq1 & m_clio.irq1_enable) == 0)
	114	m_maincpu->set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE);
	115	}
	116
	117
64	118	READ32_MEMBER(_3do_state::_3do_nvarea_r){
65	119	logerror( "%08X: NVRAM read offset = %08X\n", machine().device("maincpu")->safe_pc(), offset );
66	120	return 0;
r20167	r20168
585	639	case 0x0048/4:
586	640	case 0x004c/4:
587	641	return m_clio.irq0_enable;
	642	case 0x0060/4:
	643	case 0x0064/4:
	644	return m_clio.irq1;
	645	case 0x0068/4:
	646	case 0x006c/4:
	647	return m_clio.irq1_enable;
588	648	case 0x0080/4:
589	649	return m_clio.hdelay;
590	650	case 0x0084/4:
r20167	r20168
744	804	m_clio.seed = data;
745	805	break;
746	806	case 0x0040/4:
	807	LOG(("%08x PEND0\n",data));
747	808	m_clio.irq0 |= data;
	809	m_3do_request_fiq0(0);
748	810	break;
749	811	case 0x0044/4:
	812	LOG(("%08x PEND0 CLEAR\n",data));
750	813	m_clio.irq0 &= ~data;
	814	m_3do_request_fiq0(0);
751	815	break;
752	816	case 0x0048/4:
	817	LOG(("%08x MASK0\n",data));
753	818	m_clio.irq0_enable |= data;
	819	m_3do_request_fiq0(0);
754	820	break;
755	821	case 0x004c/4:
	822	LOG(("%08x MASK0 CLEAR\n",data));
756	823	m_clio.irq0_enable &= ~data;
	824	m_3do_request_fiq0(0);
757	825	break;
758	826	case 0x0050/4:
759	827	m_clio.mode |= data;
r20167	r20168
768	836	m_clio.spare = data;
769	837	break;
770	838	case 0x0060/4:
	839	LOG(("%08x PEND1\n",data));
771	840	m_clio.irq1 |= data;
	841	m_3do_request_fiq1(0);
772	842	break;
773	843	case 0x0064/4:
	844	LOG(("%08x PEND1 CLEAR\n",data));
774	845	m_clio.irq1 &= ~data;
	846	m_3do_request_fiq1(0);
775	847	break;
776	848	case 0x0068/4:
	849	LOG(("%08x MASK1\n",data));
777	850	m_clio.irq1_enable |= data;
	851	m_3do_request_fiq1(0);
778	852	break;
779	853	case 0x006c/4:
	854	LOG(("%08x MASK1 CLEAR\n",data));
780	855	m_clio.irq1_enable &= ~data;
	856	m_3do_request_fiq1(0);
781	857	break;
782	858	case 0x0080/4:
783	859	m_clio.hdelay = data;
r20167	r20168
981	1057	}
982	1058
983	1059
984		/* This is incorrect! Just testing stuff */
985	1060	UINT32 _3do_state::screen_update__3do(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
986	1061	{
987	1062	UINT32 *source_p = m_vram + 0x1c0000 / 4;
r20167	r20168
993	1068
994	1069	for ( int x = 0; x < 320; x++ )
995	1070	{
996		/* Odd numbered bits go to lower half, even numbered bits to upper half */
	1071	/* Every dword contains two pixels, upper word is top pixel, lower is bottom. */
997	1072	UINT32 lower = *source_p & 0xffff;
998	1073	UINT32 upper = ( *source_p >> 16 ) & 0xffff;
999	1074	int r, g, b;
1000	1075
	1076	/* Format is RGB555 */
1001	1077	r = (upper & 0x7c00) >> 10;
1002	1078	g = (upper & 0x03e0) >> 5;
1003	1079	b = (upper & 0x001f) >> 0;

trunk/src/mame/includes/3do.h

r20167	r20168
164	164	public:
165	165	_3do_state(const machine_config &mconfig, device_type type, const char *tag)
166	166	: driver_device(mconfig, type, tag) ,
	167	m_maincpu(*this, "maincpu"),
167	168	m_dram(*this, "dram"),
168	169	m_vram(*this, "vram"){ }
169	170
170		legacy_cpu_device* m_maincpu;
	171	required_device<cpu_device> m_maincpu;
171	172	required_shared_ptr<UINT32> m_dram;
172	173	required_shared_ptr<UINT32> m_vram;
173	174	SLOW2 m_slow2;
r20167	r20168
188	189	virtual void machine_reset();
189	190	DECLARE_VIDEO_START(_3do);
190	191	UINT32 screen_update__3do(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	192
	193	private:
	194	void m_3do_request_fiq0(UINT32 irq_req);
	195	void m_3do_request_fiq1(UINT32 irq_req);
191	196	};
192	197
193	198	/*----------- defined in machine/3do.c -----------*/

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