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r20073 Saturday 5th January, 2013 at 08:53:11 UTC by Tafoid

8042kbdc.c  [Peter Ferrie] - add support for keyboard enable command - add support for keyboard reset command idectrl.c  [Peter Ferrie] - correct status flags for multi-sector reads - implement more correct controller reset values - fix phantom slave drive detection problem calchase.c  [Peter Ferrie] - corrected memory map to 64kb blocks - corrected access to PAM register - removed execution hack queen.c  [Peter Ferrie] - split BIOS region into 64kb blocks - implement missing PAM registers - remove unused PAM regions savquest.c  [Peter Ferrie] - split BIOS region into 16kb blocks - implement missing PAM registers - correct slave_ack configuration member declaration

[src/emu/machine]	8042kbdc.c idectrl.c
[src/mame/drivers]	calchase.c queen.c savquest.c

trunk/src/mame/drivers/queen.c

r20072	r20073
2	2
3	3	/*
4	4
5		TODO:
6		- goes to la-la-land almost immediately:
7		000F4023: sbb     [42F9h],ah
8		000F4027: loop    0F4003h
9		000F4003: ror     word ptr [si+48B2h],1
10		000F4007: cmp     ax,44B2h
11		000F400A: retf
12		000903D3: add     [bx+si],al
13		000903D5: add     [bx+si],al
14		(Reads stack from BIOS ROM?)
15
16
17	5	Produttore  STG
18	6	N.revisione
19	7	CPU main PCB is a standard EPIA
r20072	r20073
29	17	it's a 2002 era PC at least based on the BIOS,
30	18	almost certainly newer than the standard 'PENTIUM' CPU
31	19
	20	- update by Peter Ferrie:
	21	- split BIOS region into 64kb blocks and implement missing PAM registers
	22	- VIA Apollo VXPro chipset is not compatible with Intel i430.
	23
32	24	*/
33	25
34	26
r20072	r20073
60	52	{ }
61	53
62	54	UINT32 *m_bios_ram;
63		UINT32 *m_bios_ext1_ram;
64		UINT32 *m_bios_ext2_ram;
65		UINT32 *m_bios_ext3_ram;
66		UINT32 *m_bios_ext4_ram;
67		UINT32 *m_isa_ram1;
68		UINT32 *m_isa_ram2;
	55	UINT32 *m_bios_ext_ram;
69	56	int m_dma_channel;
70	57	UINT8 m_dma_offset[2][4];
71	58	UINT8 m_at_pages[0x10];
r20072	r20073
82	69
83	70	DECLARE_READ8_MEMBER( get_slave_ack );
84	71
85		DECLARE_WRITE32_MEMBER( isa_ram1_w );
86		DECLARE_WRITE32_MEMBER( isa_ram2_w );
	72	DECLARE_WRITE32_MEMBER( bios_ext_ram_w );
87	73
88		DECLARE_WRITE32_MEMBER( bios_ext1_ram_w );
89		DECLARE_WRITE32_MEMBER( bios_ext2_ram_w );
90		DECLARE_WRITE32_MEMBER( bios_ext3_ram_w );
91		DECLARE_WRITE32_MEMBER( bios_ext4_ram_w );
92
93	74	DECLARE_WRITE32_MEMBER( bios_ram_w );
94	75	DECLARE_READ8_MEMBER(at_page8_r);
95	76	DECLARE_WRITE8_MEMBER(at_page8_w);
r20072	r20073
129	110
130	111	/*
131	112	memory banking with North Bridge:
132		0x59 (PAM0) xxxx ---- BIOS area 0xf0000-0xfffff
133		---- xxxx Reserved
134		0x5a (PAM1) xxxx ---- ISA add-on BIOS 0xc4000 - 0xc7fff
135		---- xxxx ISA add-on BIOS 0xc0000 - 0xc3fff
136		0x5b (PAM2) xxxx ---- ISA add-on BIOS 0xcc000 - 0xcffff
137		---- xxxx ISA add-on BIOS 0xc8000 - 0xcbfff
138		0x5c (PAM3) xxxx ---- ISA add-on BIOS 0xd4000 - 0xd7fff
139		---- xxxx ISA add-on BIOS 0xd0000 - 0xd3fff
140		0x5d (PAM4) xxxx ---- ISA add-on BIOS 0xdc000 - 0xdffff
141		---- xxxx ISA add-on BIOS 0xd8000 - 0xdbfff
142		0x5e (PAM5) xxxx ---- BIOS extension 0xe4000 - 0xe7fff
143		---- xxxx BIOS extension 0xe0000 - 0xe3fff
144		0x5f (PAM6) xxxx ---- BIOS extension 0xec000 - 0xeffff
145		---- xxxx BIOS extension 0xe8000 - 0xebfff
	113	0x63 (PAM)  xx-- ---- BIOS area 0xf0000-0xfffff
	114	--xx ---- BIOS extension 0xe0000 - 0xeffff
	115	---- xx-- ISA add-on BIOS 0xd0000 - 0xdffff
	116	---- --xx ISA add-on BIOS 0xc0000 - 0xcffff
146	117
147		3210 -> 3 = reserved, 2 = Cache Enable, 1 = Write Enable, 0 = Read Enable
	118	10 -> 1 = Write Enable, 0 = Read Enable
148	119	*/
149	120
150		switch(reg)
	121	if (reg == 0x63)
151	122	{
152		case 0x59: // PAM0
153		{
154		if (data & 0x10)      // enable RAM access to region 0xf0000 - 0xfffff
155		state->membank("bios_bank")->set_base(state->m_bios_ram);
156		else               // disable RAM access (reads go to BIOS ROM)
157		state->membank("bios_bank")->set_base(state->memregion("bios")->base() + 0x10000);
158		break;
159		}
160		case 0x5a: // PAM1
161		{
162		if (data & 0x1)
163		state->membank("video_bank1")->set_base(state->m_isa_ram1);
164		else
165		state->membank("video_bank1")->set_base(state->memregion("video_bios")->base() + 0);
166
167		if (data & 0x10)
168		state->membank("video_bank2")->set_base(state->m_isa_ram2);
169		else
170		state->membank("video_bank2")->set_base(state->memregion("video_bios")->base() + 0x4000);
171
172		break;
173		}
174		case 0x5e: // PAM5
175		{
176		if (data & 0x1)
177		state->membank("bios_ext1")->set_base(state->m_bios_ext1_ram);
178		else
179		state->membank("bios_ext1")->set_base(state->memregion("bios")->base() + 0);
180
181		if (data & 0x10)
182		state->membank("bios_ext2")->set_base(state->m_bios_ext2_ram);
183		else
184		state->membank("bios_ext2")->set_base(state->memregion("bios")->base() + 0x4000);
185
186		break;
187		}
188		case 0x5f: // PAM6
189		{
190		if (data & 0x1)
191		state->membank("bios_ext3")->set_base(state->m_bios_ext3_ram);
192		else
193		state->membank("bios_ext3")->set_base(state->memregion("bios")->base() + 0x8000);
194
195		if (data & 0x10)
196		state->membank("bios_ext4")->set_base(state->m_bios_ext4_ram);
197		else
198		state->membank("bios_ext4")->set_base(state->memregion("bios")->base() + 0xc000);
199
200		break;
201		}
	123	if (data & 0x20)      // enable RAM access to region 0xf0000 - 0xfffff
	124	state->membank("bios_bank")->set_base(state->m_bios_ram);
	125	else               // disable RAM access (reads go to BIOS ROM)
	126	state->membank("bios_bank")->set_base(state->memregion("bios")->base() + 0x30000);
	127	if (data & 0x80)      // enable RAM access to region 0xe0000 - 0xeffff
	128	state->membank("bios_ext")->set_base(state->m_bios_ext_ram);
	129	else
	130	state->membank("bios_ext")->set_base(state->memregion("bios")->base() + 0x20000);
202	131	}
203	132
204	133	state->m_mxtc_config_reg[reg] = data;
r20072	r20073
316	245	}
317	246
318	247
319		WRITE32_MEMBER(queen_state::isa_ram1_w)
	248	WRITE32_MEMBER(queen_state::bios_ext_ram_w)
320	249	{
321		if (m_mxtc_config_reg[0x5a] & 0x2)      // write to RAM if this region is write-enabled
	250	if (m_mxtc_config_reg[0x63] & 0x40)      // write to RAM if this region is write-enabled
322	251	{
323		COMBINE_DATA(m_isa_ram1 + offset);
	252	COMBINE_DATA(m_bios_ext_ram + offset);
324	253	}
325	254	}
326	255
327		WRITE32_MEMBER(queen_state::isa_ram2_w)
328		{
329		if (m_mxtc_config_reg[0x5a] & 0x2)      // write to RAM if this region is write-enabled
330		{
331		COMBINE_DATA(m_isa_ram2 + offset);
332		}
333		}
334	256
335		WRITE32_MEMBER(queen_state::bios_ext1_ram_w)
336		{
337		if (m_mxtc_config_reg[0x5e] & 0x2)      // write to RAM if this region is write-enabled
338		{
339		COMBINE_DATA(m_bios_ext1_ram + offset);
340		}
341		}
342
343
344		WRITE32_MEMBER(queen_state::bios_ext2_ram_w)
345		{
346		if (m_mxtc_config_reg[0x5e] & 0x20)      // write to RAM if this region is write-enabled
347		{
348		COMBINE_DATA(m_bios_ext2_ram + offset);
349		}
350		}
351
352
353		WRITE32_MEMBER(queen_state::bios_ext3_ram_w)
354		{
355		if (m_mxtc_config_reg[0x5f] & 0x2)      // write to RAM if this region is write-enabled
356		{
357		COMBINE_DATA(m_bios_ext3_ram + offset);
358		}
359		}
360
361
362		WRITE32_MEMBER(queen_state::bios_ext4_ram_w)
363		{
364		if (m_mxtc_config_reg[0x5f] & 0x20)      // write to RAM if this region is write-enabled
365		{
366		COMBINE_DATA(m_bios_ext4_ram + offset);
367		}
368		}
369
370
371	257	WRITE32_MEMBER(queen_state::bios_ram_w)
372	258	{
373		if (m_mxtc_config_reg[0x59] & 0x20)      // write to RAM if this region is write-enabled
	259	if (m_mxtc_config_reg[0x63] & 0x10)      // write to RAM if this region is write-enabled
374	260	{
375	261	COMBINE_DATA(m_bios_ram + offset);
376	262	}
r20072	r20073
518	404	static ADDRESS_MAP_START( queen_map, AS_PROGRAM, 32, queen_state )
519	405	AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
520	406	AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff)
521		AM_RANGE(0x000c0000, 0x000c3fff) AM_ROMBANK("video_bank1") AM_WRITE(isa_ram1_w)
522		AM_RANGE(0x000c4000, 0x000c7fff) AM_ROMBANK("video_bank2") AM_WRITE(isa_ram2_w)
523		AM_RANGE(0x000e0000, 0x000e3fff) AM_ROMBANK("bios_ext1") AM_WRITE(bios_ext1_ram_w)
524		AM_RANGE(0x000e4000, 0x000e7fff) AM_ROMBANK("bios_ext2") AM_WRITE(bios_ext2_ram_w)
525		AM_RANGE(0x000e8000, 0x000ebfff) AM_ROMBANK("bios_ext3") AM_WRITE(bios_ext3_ram_w)
526		AM_RANGE(0x000ec000, 0x000effff) AM_ROMBANK("bios_ext4") AM_WRITE(bios_ext4_ram_w)
	407	AM_RANGE(0x000e0000, 0x000effff) AM_ROMBANK("bios_ext") AM_WRITE(bios_ext_ram_w)
527	408	AM_RANGE(0x000f0000, 0x000fffff) AM_ROMBANK("bios_bank") AM_WRITE(bios_ram_w)
528	409	AM_RANGE(0x00100000, 0x01ffffff) AM_RAM
529	410	AM_RANGE(0xfffc0000, 0xffffffff) AM_ROM AM_REGION("bios", 0)   /* System BIOS */
r20072	r20073
635	516	void queen_state::machine_start()
636	517	{
637	518	m_bios_ram = auto_alloc_array(machine(), UINT32, 0x10000/4);
638		m_bios_ext1_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
639		m_bios_ext2_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
640		m_bios_ext3_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
641		m_bios_ext4_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
642		m_isa_ram1 = auto_alloc_array(machine(), UINT32, 0x4000/4);
643		m_isa_ram2 = auto_alloc_array(machine(), UINT32, 0x4000/4);
	519	m_bios_ext_ram = auto_alloc_array(machine(), UINT32, 0x10000/4);
644	520
645	521	init_pc_common(machine(), PCCOMMON_KEYBOARD_AT, queen_set_keyb_int);
646	522
r20072	r20073
653	529	void queen_state::machine_reset()
654	530	{
655	531	machine().root_device().membank("bios_bank")->set_base(machine().root_device().memregion("bios")->base() + 0x30000);
656		machine().root_device().membank("bios_ext1")->set_base(machine().root_device().memregion("bios")->base() + 0x20000);
657		machine().root_device().membank("bios_ext2")->set_base(machine().root_device().memregion("bios")->base() + 0x24000);
658		machine().root_device().membank("bios_ext3")->set_base(machine().root_device().memregion("bios")->base() + 0x28000);
659		machine().root_device().membank("bios_ext4")->set_base(machine().root_device().memregion("bios")->base() + 0x2c000);
660		machine().root_device().membank("video_bank1")->set_base(machine().root_device().memregion("video_bios")->base() + 0);
661		machine().root_device().membank("video_bank2")->set_base(machine().root_device().memregion("video_bios")->base() + 0x4000);
	532	machine().root_device().membank("bios_ext")->set_base(machine().root_device().memregion("bios")->base() + 0x20000);
662	533	}
663	534
664	535

trunk/src/mame/drivers/savquest.c

r20072	r20073
5	5	"Savage Quest" (c) 1999 Interactive Light, developed by Angel Studios.
6	6	Skeleton by R. Belmont
7	7
8		TODO:
9		- BIOS ROM checksum error;
10		- floppy drive error, system halt;
11
12	8	H/W is a white-box PC consisting of:
13	9	Pentium II 450 CPU
14	10	DFI P2XBL motherboard (i440BX chipset)
r20072	r20073
22	18	Copyright Nicola Salmoria and the MAME Team.
23	19	Visit http://mamedev.org for licensing and usage restrictions.
24	20
	21	- update by Peter Ferrie:
	22	- split BIOS region into 16kb blocks and implement missing PAM registers
	23
	24
25	25	***************************************************************************/
26	26
27	27
r20072	r20073
52	52	m_pic8259_2(*this, "pic8259_2")
53	53	{ }
54	54
55		UINT32 *m_bios_ram;
	55	UINT32 *m_bios_f0000_ram;
	56	UINT32 *m_bios_e0000_ram;
	57	UINT32 *m_bios_e4000_ram;
	58	UINT32 *m_bios_e8000_ram;
	59	UINT32 *m_bios_ec000_ram;
56	60	int m_dma_channel;
57	61	UINT8 m_dma_offset[2][4];
58	62	UINT8 m_at_pages[0x10];
59	63	UINT8 m_mxtc_config_reg[256];
60		UINT8 m_piix4_config_reg[4][256];
	64	UINT8 m_piix4_config_reg[8][256];
61	65
62	66	// devices
63	67	required_device<cpu_device> m_maincpu;
r20072	r20073
68	72	required_device<pic8259_device> m_pic8259_2;
69	73
70	74	DECLARE_READ8_MEMBER( get_slave_ack );
71		DECLARE_WRITE32_MEMBER( bios_ram_w );
	75	DECLARE_WRITE32_MEMBER( bios_f0000_ram_w );
	76	DECLARE_WRITE32_MEMBER( bios_e0000_ram_w );
	77	DECLARE_WRITE32_MEMBER( bios_e4000_ram_w );
	78	DECLARE_WRITE32_MEMBER( bios_e8000_ram_w );
	79	DECLARE_WRITE32_MEMBER( bios_ec000_ram_w );
72	80
73	81	protected:
74	82
r20072	r20073
118	126	{
119	127	if (data & 0x10)      // enable RAM access to region 0xf0000 - 0xfffff
120	128	{
121		state->membank("bank1")->set_base(state->m_bios_ram);
	129	state->membank("bios_f0000")->set_base(state->m_bios_f0000_ram);
122	130	}
123	131	else               // disable RAM access (reads go to BIOS ROM)
124	132	{
125		state->membank("bank1")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x20000);
	133	state->membank("bios_f0000")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x30000);
126	134	}
127	135	break;
128	136	}
	137
	138	case 0x5e:      // PAM5
	139	{
	140	if (data & 0x10)      // enable RAM access to region 0xe4000 - 0xe7fff
	141	{
	142	state->membank("bios_e4000")->set_base(state->m_bios_e4000_ram);
	143	}
	144	else               // disable RAM access (reads go to BIOS ROM)
	145	{
	146	state->membank("bios_e4000")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x24000);
	147	}
	148
	149	if (data & 1)      // enable RAM access to region 0xe0000 - 0xe3fff
	150	{
	151	state->membank("bios_e0000")->set_base(state->m_bios_e0000_ram);
	152	}
	153	else               // disable RAM access (reads go to BIOS ROM)
	154	{
	155	state->membank("bios_e0000")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x20000);
	156	}
	157	break;
	158	}
	159
	160	case 0x5f:      // PAM6
	161	{
	162	if (data & 0x10)      // enable RAM access to region 0xec000 - 0xeffff
	163	{
	164	state->membank("bios_ec000")->set_base(state->m_bios_ec000_ram);
	165	}
	166	else               // disable RAM access (reads go to BIOS ROM)
	167	{
	168	state->membank("bios_ec000")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x2c000);
	169	}
	170
	171	if (data & 1)      // enable RAM access to region 0xe8000 - 0xebfff
	172	{
	173	state->membank("bios_e8000")->set_base(state->m_bios_e8000_ram);
	174	}
	175	else               // disable RAM access (reads go to BIOS ROM)
	176	{
	177	state->membank("bios_e8000")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x28000);
	178	}
	179	break;
	180	}
129	181	}
130	182	#endif
131	183
r20072	r20073
243	295	}
244	296	}
245	297
246		WRITE32_MEMBER(savquest_state::bios_ram_w)
	298	WRITE32_MEMBER(savquest_state::bios_f0000_ram_w)
247	299	{
248	300	//if (m_mxtc_config_reg[0x59] & 0x20)       // write to RAM if this region is write-enabled
249	301	#if 1
250	302	if (m_mxtc_config_reg[0x59] & 0x20)      // write to RAM if this region is write-enabled
251	303	{
252		COMBINE_DATA(m_bios_ram + offset);
	304	COMBINE_DATA(m_bios_f0000_ram + offset);
253	305	}
254	306	#endif
255	307	}
256	308
	309	WRITE32_MEMBER(savquest_state::bios_e0000_ram_w)
	310	{
	311	//if (m_mxtc_config_reg[0x5e] & 2)       // write to RAM if this region is write-enabled
	312	#if 1
	313	if (m_mxtc_config_reg[0x5e] & 2)      // write to RAM if this region is write-enabled
	314	{
	315	COMBINE_DATA(m_bios_e0000_ram + offset);
	316	}
	317	#endif
	318	}
	319
	320	WRITE32_MEMBER(savquest_state::bios_e4000_ram_w)
	321	{
	322	//if (m_mxtc_config_reg[0x5e] & 0x20)       // write to RAM if this region is write-enabled
	323	#if 1
	324	if (m_mxtc_config_reg[0x5e] & 0x20)      // write to RAM if this region is write-enabled
	325	{
	326	COMBINE_DATA(m_bios_e4000_ram + offset);
	327	}
	328	#endif
	329	}
	330
	331	WRITE32_MEMBER(savquest_state::bios_e8000_ram_w)
	332	{
	333	//if (m_mxtc_config_reg[0x5f] & 2)       // write to RAM if this region is write-enabled
	334	#if 1
	335	if (m_mxtc_config_reg[0x5f] & 2)      // write to RAM if this region is write-enabled
	336	{
	337	COMBINE_DATA(m_bios_e8000_ram + offset);
	338	}
	339	#endif
	340	}
	341
	342	WRITE32_MEMBER(savquest_state::bios_ec000_ram_w)
	343	{
	344	//if (m_mxtc_config_reg[0x5f] & 0x20)       // write to RAM if this region is write-enabled
	345	#if 1
	346	if (m_mxtc_config_reg[0x5f] & 0x20)      // write to RAM if this region is write-enabled
	347	{
	348	COMBINE_DATA(m_bios_ec000_ram + offset);
	349	}
	350	#endif
	351	}
	352
257	353	READ32_MEMBER(savquest_state::ide_r)
258	354	{
259	355	device_t *device = machine().device("ide");
r20072	r20073
398	494	AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
399	495	AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff)
400	496	AM_RANGE(0x000c0000, 0x000c7fff) AM_ROM AM_REGION("video_bios", 0)
401		AM_RANGE(0x000e0000, 0x000fffff) AM_ROMBANK("bank1")
402		AM_RANGE(0x000e0000, 0x000fffff) AM_WRITE(bios_ram_w)
	497	AM_RANGE(0x000f0000, 0x000fffff) AM_ROMBANK("bios_f0000") AM_WRITE(bios_f0000_ram_w)
	498	AM_RANGE(0x000e0000, 0x000e3fff) AM_ROMBANK("bios_e0000") AM_WRITE(bios_e0000_ram_w)
	499	AM_RANGE(0x000e4000, 0x000e7fff) AM_ROMBANK("bios_e4000") AM_WRITE(bios_e4000_ram_w)
	500	AM_RANGE(0x000e8000, 0x000ebfff) AM_ROMBANK("bios_e8000") AM_WRITE(bios_e8000_ram_w)
	501	AM_RANGE(0x000ec000, 0x000effff) AM_ROMBANK("bios_ec000") AM_WRITE(bios_ec000_ram_w)
403	502	AM_RANGE(0x00100000, 0x01ffffff) AM_RAM
404	503	//  AM_RANGE(0x02000000, 0x02000003) // protection dongle lies there?
405	504	AM_RANGE(0xfffc0000, 0xffffffff) AM_ROM AM_REGION("bios", 0)   /* System BIOS */
r20072	r20073
467	566	{
468	567	DEVCB_DRIVER_LINE_MEMBER(savquest_state,savquest_pic8259_1_set_int_line),
469	568	DEVCB_LINE_VCC,
470		DEVCB_MEMBER(savquest_state,get_slave_ack)
	569	DEVCB_DRIVER_MEMBER(savquest_state,get_slave_ack)
471	570	};
472	571
473	572	static const struct pic8259_interface savquest_pic8259_2_config =
r20072	r20073
515	614
516	615	void savquest_state::machine_start()
517	616	{
518		m_bios_ram = auto_alloc_array(machine(), UINT32, 0x20000/4);
	617	m_bios_f0000_ram = auto_alloc_array(machine(), UINT32, 0x10000/4);
	618	m_bios_e0000_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
	619	m_bios_e4000_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
	620	m_bios_e8000_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
	621	m_bios_ec000_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
519	622
520	623	init_pc_common(machine(), PCCOMMON_KEYBOARD_AT, savquest_set_keyb_int);
521	624
r20072	r20073
527	630
528	631	void savquest_state::machine_reset()
529	632	{
530		machine().root_device().membank("bank1")->set_base(machine().root_device().memregion("bios")->base() + 0x20000);
	633	machine().root_device().membank("bios_f0000")->set_base(machine().root_device().memregion("bios")->base() + 0x30000);
	634	machine().root_device().membank("bios_e0000")->set_base(machine().root_device().memregion("bios")->base() + 0x20000);
	635	machine().root_device().membank("bios_e4000")->set_base(machine().root_device().memregion("bios")->base() + 0x24000);
	636	machine().root_device().membank("bios_e8000")->set_base(machine().root_device().memregion("bios")->base() + 0x28000);
	637	machine().root_device().membank("bios_ec000")->set_base(machine().root_device().memregion("bios")->base() + 0x2c000);
531	638	}
532	639
533	640	static MACHINE_CONFIG_START( savquest, savquest_state )

trunk/src/mame/drivers/calchase.c

r20072	r20073
104	104	255 heads as parameter. Perhaps a bad dump?
105	105
106	106	TODO: A lot of work to do yet!!!
	107
	108	- update by peter ferrie:
	109	- corrected memory map to 64kb blocks
	110	- corrected access to PAM register
107	111	*/
108	112
109	113
r20072	r20073
131	135	{ }
132	136
133	137	UINT32 *m_bios_ram;
	138	UINT32 *m_bios_ext_ram;
134	139	int m_dma_channel;
135	140	UINT8 m_dma_offset[2][4];
136	141	UINT8 m_at_pages[0x10];
r20072	r20073
149	154	DECLARE_WRITE8_MEMBER(at_page8_w);
150	155	DECLARE_READ8_MEMBER(pc_dma_read_byte);
151	156	DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
	157	DECLARE_WRITE32_MEMBER(bios_ext_ram_w);
152	158	DECLARE_WRITE32_MEMBER(bios_ram_w);
153	159	DECLARE_READ16_MEMBER(calchase_iocard1_r);
154	160	DECLARE_READ16_MEMBER(calchase_iocard2_r);
r20072	r20073
336	342	calchase_state *state = busdevice->machine().driver_data<calchase_state>();
337	343	//  mame_printf_debug("%s:MXTC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
338	344
339		switch(reg)
	345	/*
	346	memory banking with North Bridge:
	347	0x63 (PAM)  xx-- ---- BIOS extension 0xe0000 - 0xeffff
	348	--xx ---- BIOS area 0xf0000-0xfffff
	349	---- xx-- ISA add-on BIOS 0xc0000 - 0xcffff
	350	---- --xx ISA add-on BIOS 0xd0000 - 0xdffff
	351
	352	10 -> 1 = Write Enable, 0 = Read Enable
	353	*/
	354
	355	if (reg == 0x63)
340	356	{
341		//case 0x59:
342		case 0x63:   // PAM0
343		{
344		//if (data & 0x10)     // enable RAM access to region 0xf0000 - 0xfffff
345		if ((data & 0x50) | (data & 0xA0))
346		{
347		state->membank("bank1")->set_base(state->m_bios_ram);
348		}
349		else            // disable RAM access (reads go to BIOS ROM)
350		{
351		//Execution Hack to avoid crash when switch back from Shadow RAM to Bios ROM, since i386 emu haven't yet pipelined execution structure.
352		//It happens when exit from BIOS SETUP.
353		#if 0
354		if ((state->m_mxtc_config_reg[0x63] & 0x50) | ( state->m_mxtc_config_reg[0x63] & 0xA0)) // Only DO if comes a change to disable ROM.
355		{
356		if ( busdevice->machine(->safe_pc().device("maincpu"))==0xff74e) busdevice->machine().device("maincpu")->state().set_pc(0xff74d);
357		}
358		#endif
359
360		state->membank("bank1")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x10000);
361		state->membank("bank1")->set_base(busdevice->machine().root_device().memregion("bios")->base());
362		}
363		break;
364		}
	357	if (data & 0x20)      // enable RAM access to region 0xf0000 - 0xfffff
	358	state->membank("bios_bank")->set_base(state->m_bios_ram);
	359	else               // disable RAM access (reads go to BIOS ROM)
	360	state->membank("bios_bank")->set_base(state->memregion("bios")->base() + 0x10000);
	361	if (data & 0x80)      // enable RAM access to region 0xe0000 - 0xeffff
	362	state->membank("bios_ext")->set_base(state->m_bios_ext_ram);
	363	else
	364	state->membank("bios_ext")->set_base(state->memregion("bios")->base() + 0);
365	365	}
366	366
367	367	state->m_mxtc_config_reg[reg] = data;
r20072	r20073
489	489
490	490	WRITE32_MEMBER(calchase_state::bios_ram_w)
491	491	{
492		//if (m_mxtc_config_reg[0x59] & 0x20)       // write to RAM if this region is write-enabled
493		if (m_mxtc_config_reg[0x63] & 0x50)
	492	if (m_mxtc_config_reg[0x63] & 0x10)       // write to RAM if this region is write-enabled
494	493	{
495	494	COMBINE_DATA(m_bios_ram + offset);
496	495	}
497	496	}
498	497
	498	WRITE32_MEMBER(calchase_state::bios_ext_ram_w)
	499	{
	500	if (m_mxtc_config_reg[0x63] & 0x40)       // write to RAM if this region is write-enabled
	501	{
	502	COMBINE_DATA(m_bios_ext_ram + offset);
	503	}
	504	}
	505
499	506	READ16_MEMBER(calchase_state::calchase_iocard1_r)
500	507	{
501	508	return ioport("IOCARD1")->read();
r20072	r20073
555	562	//GRULL AM_RANGE(0x000e0000, 0x000effff) AM_RAM
556	563	//GRULL-AM_RANGE(0x000f0000, 0x000fffff) AM_ROMBANK("bank1")
557	564	//GRULL AM_RANGE(0x000f0000, 0x000fffff) AM_WRITE(bios_ram_w)
558		AM_RANGE(0x000e0000, 0x000fffff) AM_ROMBANK("bank1")
559		AM_RANGE(0x000e0000, 0x000fffff) AM_WRITE(bios_ram_w)
	565	AM_RANGE(0x000e0000, 0x000effff) AM_ROMBANK("bios_ext") AM_WRITE(bios_ext_ram_w)
	566	AM_RANGE(0x000f0000, 0x000fffff) AM_ROMBANK("bios_bank") AM_WRITE(bios_ram_w)
560	567	AM_RANGE(0x00100000, 0x03ffffff) AM_RAM  // 64MB
561	568	AM_RANGE(0x02000000, 0x28ffffff) AM_NOP
562	569	//AM_RANGE(0x04000000, 0x040001ff) AM_RAM
r20072	r20073
804	811
805	812	void calchase_state::machine_start()
806	813	{
	814	m_bios_ram = auto_alloc_array(machine(), UINT32, 0x10000/4);
	815	m_bios_ext_ram = auto_alloc_array(machine(), UINT32, 0x10000/4);
	816
807	817	machine().device("maincpu")->execute().set_irq_acknowledge_callback(irq_callback);
808	818
809	819	m_pit8254 = machine().device( "pit8254" );
r20072	r20073
877	887	void calchase_state::machine_reset()
878	888	{
879	889	//machine().root_device().membank("bank1")->set_base(machine().root_device().memregion("bios")->base() + 0x10000);
880		machine().root_device().membank("bank1")->set_base(machine().root_device().memregion("bios")->base());
	890	machine().root_device().membank("bios_bank")->set_base(machine().root_device().memregion("bios")->base() + 0x10000);
	891	machine().root_device().membank("bios_ext")->set_base(machine().root_device().memregion("bios")->base() + 0);
881	892	}
882	893
883	894	static void set_gate_a20(running_machine &machine, int a20)

trunk/src/emu/machine/8042kbdc.c

r20072	r20073
364	364	switch (offset) {
365	365	case 0:
366	366	data = kbdc8042.data;
367		if (kbdc8042.type != KBDC8042_AT386 || (data != 0x55))
	367	if ((kbdc8042.status_read_mode != 3) || (data != 0xfa))
368	368	{
369		/* at386 self test doesn't like this */
370		at_8042_clear_keyboard_received();
	369	if (kbdc8042.type != KBDC8042_AT386 || (data != 0x55))
	370	{
	371	/* at386 self test doesn't like this */
	372	at_8042_clear_keyboard_received();
	373	}
	374	at_8042_check_keyboard(space.machine());
371	375	}
372		at_8042_check_keyboard(space.machine());
	376	else
	377	{
	378	kbdc8042.status_read_mode = 4;
	379	}
373	380	break;
374	381
375	382	case 1:
r20072	r20073
428	435	case 2:
429	436	data |= kbdc8042.inport<<4;
430	437	break;
	438	case 4:
	439	at_8042_receive(space.machine(), 0xaa);
	440	kbdc8042.status_read_mode = 0;
	441	break;
431	442	}
432	443	break;
433	444	}
r20072	r20073
447	458	kbdc8042.status_read_mode = 0;
448	459	switch (kbdc8042.operation_write_state) {
449	460	case 0:
	461	if ((data == 0xf4) || (data == 0xff)) /* keyboard enable or keyboard reset */
	462	{
	463	at_8042_receive(space.machine(), 0xfa); /* ACK, delivered a bit differently */
	464
	465	if (data == 0xff)
	466	{
	467	kbdc8042.status_read_mode = 3; /* keyboard buffer to be written again after next read */
	468	}
	469
	470	break;
	471	}
	472
450	473	/* normal case */
451	474	kbdc8042.data = data;
452	475	kbdc8042.sending=1;

trunk/src/emu/machine/idectrl.c

r20072	r20073
518	518	/* reset the totals */
519	519	buffer_offset = 0;
520	520
521		/* clear the buffer ready and busy flag */
522		status &= ~IDE_STATUS_BUFFER_READY;
	521	/* clear just the busy flag
	522	the buffer ready flag stays set until all sectors are read
	523	*/
	524	//   status &= ~IDE_STATUS_BUFFER_READY;
523	525	status &= ~IDE_STATUS_BUSY;
524	526
525	527	if (master_password_enable || user_password_enable)
r20072	r20073
540	542	read_next_sector();
541	543	else
542	544	{
	545	status &= ~IDE_STATUS_BUFFER_READY; /* now clear it */
543	546	bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
544	547	dma_active = 0;
545	548	}
r20072	r20073
696	699	void ide_controller_device::read_next_sector()
697	700	{
698	701	/* mark ourselves busy */
699		status |= IDE_STATUS_BUSY;
	702	//   status |= IDE_STATUS_BUSY;
700	703
701	704	if (command == IDE_COMMAND_READ_MULTIPLE_BLOCK)
702	705	{
r20072	r20073
1180	1183	status &= ~IDE_STATUS_DRIVE_READY;
1181	1184	}
1182	1185	}
	1186	else
	1187	{
	1188	return 0;
	1189	}
1183	1190
1184	1191	switch (BANK(bank, offset))
1185	1192	{
r20072	r20073
1432	1439	//if (data == 0x04)
1433	1440	if (data & 0x04)
1434	1441	{
1435		status |= IDE_STATUS_BUSY;
1436		status &= ~IDE_STATUS_DRIVE_READY;
1437		reset_timer->adjust(attotime::from_msec(5));
	1442	//            status |= IDE_STATUS_BUSY;
	1443	//            status &= ~IDE_STATUS_DRIVE_READY;
	1444	//            reset_timer->adjust(attotime::from_msec(5));
	1445	device_reset(); /* deliver instantly to support buggy BIOSes that don't poll properly */
	1446	sector_count = 1;
	1447	drive[0].cur_sector = 1;
	1448	drive[0].cur_head = 0;
	1449	drive[0].cur_cylinder = 0;
	1450	drive[1].cur_sector = 1;
	1451	drive[1].cur_head = 0;
	1452	drive[1].cur_cylinder = 0;
1438	1453	}
1439	1454	break;
1440	1455	}

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