MAME SVN History

199869 Revisions

r19935 Sunday 30th December, 2012 at 01:26:51 UTC by Ryan Holtz
- m6805.c: Modernized M6805 CPU core. [MooglyGuy]

[src/emu/cpu/m6805]	6805ops.c m6805.c m6805.h
[src/emu/cpu/m6809]	m6809.h

trunk/src/emu/cpu/m6805/m6805.c
r19934	r19935
36	36
37	37	#define IRQ_LEVEL_DETECT 0
38	38
39		enum
40		{
41		SUBTYPE_M6805,
42		SUBTYPE_M68705,
43		SUBTYPE_HD63705,
44		SUBTYPE_M68HC05EG
45		};
46
47		/* 6805 Registers */
48		struct m6805_Regs
49		{
50		/* Pre-pointerafied public globals */
51		int iCount;
52		PAIR ea; /* effective address */
53
54		int subtype; /* Which sub-type is being emulated */
55		UINT32 sp_mask; /* Stack pointer address mask */
56		UINT32 sp_low; /* Stack pointer low water mark (or floor) */
57		PAIR pc; /* Program counter */
58		PAIR s; /* Stack pointer */
59		UINT8 a; /* Accumulator */
60		UINT8 x; /* Index register */
61		UINT8 cc; /* Condition codes */
62
63		UINT16 pending_interrupts; /* MB */
64		device_irq_acknowledge_callback irq_callback;
65		legacy_cpu_device *device;
66		address_space *program;
67		direct_read_data *direct;
68		int irq_state[9]; /* KW Additional lines for HD63705 */
69		int nmi_state;
70		};
71
72		INLINE m6805_Regs get_safe_token(device_t device)
73		{
74		assert(device != NULL);
75		assert(device->type() == M6805 \|\|
76		device->type() == M68705 \|\|
77		device->type() == HD63705 \|\|
78		device->type() == M68HC05EG);
79		return (m6805_Regs )downcast<legacy_cpu_device >(device)->token();
80		}
81
82	39	/****************************************************************************/
83	40	/* Read a byte from given memory location */
84	41	/****************************************************************************/
85		#define M6805_RDMEM(Addr) ((unsigned)cp~~ustate->p~~rogram->read_byte(Addr))
	42	#define M6805_RDMEM(addr) ((unsigned)m_program->read_byte(addr))
86	43
87	44	/****************************************************************************/
88	45	/* Write a byte to given memory location */
89	46	/****************************************************************************/
90		#define M6805_WRMEM(Addr,Value) (cp~~ustate->p~~rogram->write_byte(Addr,Value))
	47	#define M6805_WRMEM(addr, value) (m_program->write_byte(addr, value))
91	48
92	49	/****************************************************************************/
93	50	/* M6805_RDOP() is identical to M6805_RDMEM() except it is used for reading */
94	51	/* opcodes. In case of system with memory mapped I/O, this function can be */
95	52	/* used to greatly speed up emulation */
96	53	/****************************************************************************/
97		#define M6805_RDOP(Addr) ((unsigned)~~cpustate->~~direct->read_decrypted_byte(Addr))
	54	#define M6805_RDOP(addr) ((unsigned)m_direct->read_decrypted_byte(addr))
98	55
99	56	/****************************************************************************/
100	57	/* M6805_RDOP_ARG() is identical to M6805_RDOP() but it's used for reading */
101	58	/* opcode arguments. This difference can be used to support systems that */
102	59	/* use different encoding mechanisms for opcodes and opcode arguments */
103	60	/****************************************************************************/
104		#define M6805_RDOP_ARG(Addr) ((unsigned)~~cpustate->~~direct->read_raw_byte(Addr))
	61	#define M6805_RDOP_ARG(addr) ((unsigned)m_direct->read_raw_byte(addr))
105	62
106		#define SUBTYPE cpustate->subtype /* CPU Type */
107		#define SP_MASK cpustate->sp_mask /* stack pointer mask */
108		#define SP_LOW cpustate->sp_low /* stack pointer low water mark */
109		#define pPC cpustate->pc /* program counter PAIR */
110		#define PC cpustate->pc.w.l /* program counter lower word */
111		#define S cpustate->s.w.l /* stack pointer lower word */
112		#define A cpustate->a /* accumulator */
113		#define X cpustate->x /* index register */
114		#define CC cpustate->cc /* condition codes */
	63	#define SP_MASK m_sp_mask /* stack pointer mask */
	64	#define SP_LOW m_sp_low /* stack pointer low water mark */
	65	#define PC m_pc.w.l /* program counter lower word */
	66	#define S m_s.w.l /* stack pointer lower word */
	67	#define A m_a /* accumulator */
	68	#define X m_x /* index register */
	69	#define CC m_cc /* condition codes */
115	70
116		#define EAD cpustate->ea.d
117		#define EA cpustate->ea.w.l
	71	#define EAD m_ea.d
	72	#define EA m_ea.w.l
118	73
119	74
120	75	/* DS -- THESE ARE RE-DEFINED IN m6805.h TO RAM, ROM or FUNCTIONS IN cpuintrf.c */
121		#define RM(Addr) M6805_RDMEM(Addr)
122		#define WM(Addr,Value) M6805_WRMEM(Addr,Value)
123		#define M_RDOP(Addr) M6805_RDOP(Addr)
124		#define M_RDOP_ARG(Addr) M6805_RDOP_ARG(Addr)
	76	#define RM(addr) M6805_RDMEM(addr)
	77	#define WM(addr, value) M6805_WRMEM(addr, value)
	78	#define M_RDOP(addr) M6805_RDOP(addr)
	79	#define M_RDOP_ARG(addr) M6805_RDOP_ARG(addr)
125	80
126	81	/* macros to tweak the PC and SP */
127	82	#define SP_INC if( ++S > SP_MASK) S = SP_LOW
r19934	r19935
132	87	#define IMMBYTE(b) {b = M_RDOP_ARG(PC++);}
133	88	#define IMMWORD(w) {w.d = 0; w.b.h = M_RDOP_ARG(PC); w.b.l = M_RDOP_ARG(PC+1); PC+=2;}
134	89
135		#define PUSHBYTE(b) wr_s_handler_b(cpustate, &b)
136		#define PUSHWORD(w) wr_s_handler_w(cpustate, &w)
137		#define PULLBYTE(b) rd_s_handler_b(cpustate, &b)
138		#define PULLWORD(w) rd_s_handler_w(cpustate, &w)
	90	#define PUSHBYTE(b) wr_s_handler_b(&b)
	91	#define PUSHWORD(w) wr_s_handler_w(&w)
	92	#define PULLBYTE(b) rd_s_handler_b(&b)
	93	#define PULLWORD(w) rd_s_handler_w(&w)
139	94
140	95	/* CC masks H INZC
141	96	7654 3210 */
r19934	r19935
158	113	#define SET_H(a,b,r) CC\|=((a^b^r)&0x10)
159	114	#define SET_C8(a) CC\|=((a&0x100)>>8)
160	115
161		~~stati~~c const UINT8 flags8i[256]= /* increment */
	116	const UINT8 m6805_base_device::m_flags8i[256]= /* increment */
162	117	{
163		0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
164		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
165		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
166		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
167		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
168		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
169		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
170		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
171		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
172		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
173		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
174		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
175		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
176		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
177		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
178		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04
	118	0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	119	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	120	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	121	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	122	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	123	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	124	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	125	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	126	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	127	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	128	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	129	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	130	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	131	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	132	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	133	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04
179	134	};
180		static const UINT8 flags8d[256]= /* decrement */
	135
	136	const UINT8 m6805_base_device::m_flags8d[256]= /* decrement */
181	137	{
182		0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
183		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
184		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
185		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
186		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
187		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
188		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
189		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
190		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
191		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
192		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
193		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
194		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
195		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
196		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
197		0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04
	138	0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	139	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	140	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	141	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	142	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	143	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	144	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	145	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	146	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	147	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	148	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	149	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	150	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	151	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	152	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
	153	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04
198	154	};
199		#define SET_FLAGS8I(a) {CC\|=flags8i[(a)&0xff];}
200		#define SET_FLAGS8D(a) {CC\|=flags8d[(a)&0xff];}
	155	#define SET_FLAGS8I(a) {CC \|= m_flags8i[(a) & 0xff];}
	156	#define SET_FLAGS8D(a) {CC \|= m_flags8d[(a) & 0xff];}
201	157
202	158	/* combos */
203		#define SET_NZ8(a) {SET_N8(a);SET_Z(a);}
204		#define SET_FLAGS8(a,b,r) {SET_N8(r);SET_Z8(r);SET_C8(r);}
	159	#define SET_NZ8(a) {SET_N8(a); SET_Z(a);}
	160	#define SET_FLAGS8(a,b,r) {SET_N8(r); SET_Z8(r); SET_C8(r);}
205	161
206	162	/* for treating an unsigned UINT8 as a signed INT16 */
207		#define SIGNED(b) ((INT16)(b&0x80?b\|0xff00:b))
	163	#define SIGNED(b) ((INT16)(b & 0x80 ? b \| 0xff00 : b))
208	164
209	165	/* Macros for addressing modes */
210		#define DIRECT EAD=0;IMMBYTE(cpustate->ea.b.l)
211		#define IMM8 EA=PC++
212		#define EXTENDED IMMWORD(cpustate->ea)
213		#define INDEXED EA=X
214		#define INDEXED1 {EAD=0; IMMBYTE(cpustate->ea.b.l); EA+=X;}
215		#define INDEXED2 {IMMWORD(cpustate->ea); EA+=X;}
	166	#define DIRECT EAD=0; IMMBYTE(m_ea.b.l)
	167	#define IMM8 EA = PC++
	168	#define EXTENDED IMMWORD(m_ea)
	169	#define INDEXED EA = X
	170	#define INDEXED1 {EAD = 0; IMMBYTE(m_ea.b.l); EA += X;}
	171	#define INDEXED2 {IMMWORD(m_ea); EA += X;}
216	172
217	173	/* macros to set status flags */
218	174	#if defined(SEC)
219	175	#undef SEC
220	176	#endif
221		#define SEC CC\|=CFLAG
222		#define CLC CC&=~CFLAG
223		#define SEZ CC\|=ZFLAG
224		#define CLZ CC&=~ZFLAG
225		#define SEN CC\|=NFLAG
226		#define CLN CC&=~NFLAG
227		#define SEH CC\|=HFLAG
228		#define CLH CC&=~HFLAG
229		#define SEI CC\|=IFLAG
230		#define CLI CC&=~IFLAG
	177	#define SEC CC \|= CFLAG
	178	#define CLC CC &=~ CFLAG
	179	#define SEZ CC \|= ZFLAG
	180	#define CLZ CC &=~ ZFLAG
	181	#define SEN CC \|= NFLAG
	182	#define CLN CC &=~ NFLAG
	183	#define SEH CC \|= HFLAG
	184	#define CLH CC &=~ HFLAG
	185	#define SEI CC \|= IFLAG
	186	#define CLI CC &=~ IFLAG
231	187
232	188	/* macros for convenience */
233		#define DIRBYTE(b) {DIRECT;b=RM(EAD);}
234		#define EXTBYTE(b) {EXTENDED;b=RM(EAD);}
235		#define IDXBYTE(b) {INDEXED;b=RM(EAD);}
236		#define IDX1BYTE(b) {INDEXED1;b=RM(EAD);}
237		#define IDX2BYTE(b) {INDEXED2;b=RM(EAD);}
	189	#define DIRBYTE(b) {DIRECT; b = RM(EAD);}
	190	#define EXTBYTE(b) {EXTENDED; b = RM(EAD);}
	191	#define IDXBYTE(b) {INDEXED; b = RM(EAD);}
	192	#define IDX1BYTE(b) {INDEXED1; b = RM(EAD);}
	193	#define IDX2BYTE(b) {INDEXED2; b = RM(EAD);}
238	194	/* Macros for branch instructions */
239		#define BRANCH(f) { UINT8 t; IMMBYTE(t); if(f) { PC+=SIGNED(t); if (t==0xfe) { /* speed up busy loops */ if(~~cpustate->~~iCount > 0) ~~cpustate->~~iCount = 0; } } }
	195	#define BRANCH(f) { UINT8 t; IMMBYTE(t); if(f) { PC += SIGNED(t); if (t == 0xfe) { /* speed up busy loops */ if(m_icount > 0) m_icount = 0; } } }
240	196
241	197	/* what they say it is ... */
242		~~stati~~c const uns~~ign~~ed c~~har~~ cycles1[] =
	198	const UINT8 m6805_base_device::m_cycles1[] =
243	199	{
244	200	/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
245	201	/0/ 10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,
r19934	r19935
264	220	/* pre-clear a PAIR union; clearing h2 and h3 only might be faster? */
265	221	#define CLEAR_PAIR(p) p->d = 0
266	222
267		~~INLINE~~ void rd_s_handler_b( ~~m6805_Regs cpustate,~~ UINT8 b )
	223	void m6805_base_device::rd_s_handler_b(UINT8 *b)
268	224	{
269	225	SP_INC;
270	226	*b = RM( S );
271	227	}
272	228
273		~~INLINE~~ void rd_s_handler_w( ~~m6805_Regs cpustate,~~ PAIR p )
	229	void m6805_base_device::rd_s_handler_w(PAIR *p)
274	230	{
275	231	CLEAR_PAIR(p);
276	232	SP_INC;
r19934	r19935
279	235	p->b.l = RM( S );
280	236	}
281	237
282		~~INLINE~~ void wr_s_handler_b( ~~m6805_Regs cpustate,~~ UINT8 b )
	238	void m6805_base_device::wr_s_handler_b(UINT8 *b)
283	239	{
284	240	WM( S, *b );
285	241	SP_DEC;
286	242	}
287	243
288		~~INLINE~~ void wr_s_handler_w( ~~m6805_Regs cpustate,~~ PAIR p )
	244	void m6805_base_device::wr_s_handler_w(PAIR *p)
289	245	{
290	246	WM( S, p->b.l );
291	247	SP_DEC;
r19934	r19935
293	249	SP_DEC;
294	250	}
295	251
296		~~INLINE~~ void ~~RM16(~~ m6805_~~Reg~~s c~~pustat~~e, UINT32 Addr, PAIR p )
	252	void m6805_base_device::RM16(UINT32 addr, PAIR *p)
297	253	{
298	254	CLEAR_PAIR(p);
299		p->b.h = RM(Addr);
300		++Addr;
301		// if( ++Addr > AMASK ) Addr = 0;
302		p->b.l = RM(Addr);
	255	p->b.h = RM(addr);
	256	++addr;
	257	// if( ++addr > AMASK ) addr = 0;
	258	p->b.l = RM(addr);
303	259	}
304	260
305		#ifdef UNUSED_FUNCTION
306		INLINE void WM16( m6805_Regs cpustate, UINT32 Addr, PAIR p )
307		{
308		WM( Addr, p->b.h );
309		++Addr;
310		// if( ++Addr > AMASK ) Addr = 0;
311		WM( Addr, p->b.l );
312		}
313		#endif
314
315
316	261	/* Generate interrupt - m68705 version */
317		~~static~~ void m68705_Interrupt( ~~m6805_Regs *cpustate~~ )
	262	void m68705_device::interrupt()
318	263	{
319		if( (cp~~ustat~~e~~->pe~~nding_interrupts & ((1<<M6805_IRQ_LINE)\|M68705_INT_MASK)) != 0 )
	264	if ((m_pending_interrupts & ((1 << M6805_IRQ_LINE) \| M68705_INT_MASK)) != 0 )
320	265	{
321		if ( (CC & IFLAG) == 0 )
	266	if ((CC & IFLAG) == 0)
322	267	{
323		PUSHWORD(cpustate->pc);
324		PUSHBYTE(cpustate->x);
325		PUSHBYTE(cpustate->a);
326		PUSHBYTE(cpustate->cc);
	268	PUSHWORD(m_pc);
	269	PUSHBYTE(m_x);
	270	PUSHBYTE(m_a);
	271	PUSHBYTE(m_cc);
327	272	SEI;
328		if (cpustate->irq_callback)
329		(*cpustate->irq_callback)(cpustate->device, 0);
	273	standard_irq_callback(0);
330	274
331		if ((cp~~ustat~~e~~->pe~~nding_interrupts & (1<<M68705_IRQ_LINE)) != 0 )
	275	if ((m_pending_interrupts & (1 << M68705_IRQ_LINE)) != 0 )
332	276	{
333		cpustate->pending_interrupts &= ~(1<<M68705_IRQ_LINE);
334		RM16( cpustate, 0xfffa, &pPC);
	277	m_pending_interrupts &= ~(1 << M68705_IRQ_LINE);
	278	RM16(0xfffa, &m_pc);
335	279	}
336		else if((cp~~ustat~~e~~->pe~~nding_interrupts&(1<<M68705_INT_TIMER))!=0)
	280	else if ((m_pending_interrupts & (1 << M68705_INT_TIMER)) != 0)
337	281	{
338		cpustate->pending_interrupts &= ~(1<<M68705_INT_TIMER);
339		RM16( cpustate, 0xfff8, &pPC);
	282	m_pending_interrupts &= ~(1 << M68705_INT_TIMER);
	283	RM16(0xfff8, &m_pc);
340	284	}
341	285	}
342		~~cpustate->~~iCount -= 11;
	286	m_icount -= 11;
343	287	}
344	288	}
345	289
	290	void m6805_base_device::interrupt_vector()
	291	{
	292	RM16(0xffff - 5, &m_pc);
	293	}
	294
	295	void m68hc05eg_device::interrupt_vector()
	296	{
	297	if ((m_pending_interrupts & (1 << M68HC05EG_INT_IRQ)) != 0)
	298	{
	299	m_pending_interrupts &= ~(1 << M68HC05EG_INT_IRQ);
	300	RM16(0x1ffa, &m_pc);
	301	}
	302	else if((m_pending_interrupts & (1 << M68HC05EG_INT_TIMER)) != 0)
	303	{
	304	m_pending_interrupts &= ~(1 << M68HC05EG_INT_TIMER);
	305	RM16(0x1ff8, &m_pc);
	306	}
	307	else if((m_pending_interrupts & (1 << M68HC05EG_INT_CPI)) != 0)
	308	{
	309	m_pending_interrupts &= ~(1 << M68HC05EG_INT_CPI);
	310	RM16(0x1ff6, &m_pc);
	311	}
	312	}
	313
	314	void hd63705_device::interrupt_vector()
	315	{
	316	/* Need to add emulation of other interrupt sources here KW-2/4/99 */
	317	/* This is just a quick patch for Namco System 2 operation */
	318
	319	if ((m_pending_interrupts & (1 << HD63705_INT_IRQ1)) != 0)
	320	{
	321	m_pending_interrupts &= ~(1 << HD63705_INT_IRQ1);
	322	RM16(0x1ff8, &m_pc);
	323	}
	324	else if ((m_pending_interrupts & (1 << HD63705_INT_IRQ2)) != 0)
	325	{
	326	m_pending_interrupts &= ~(1 << HD63705_INT_IRQ2);
	327	RM16(0x1fec, &m_pc);
	328	}
	329	else if ((m_pending_interrupts & (1 << HD63705_INT_ADCONV)) != 0)
	330	{
	331	m_pending_interrupts &= ~(1 << HD63705_INT_ADCONV);
	332	RM16(0x1fea, &m_pc);
	333	}
	334	else if ((m_pending_interrupts & (1 << HD63705_INT_TIMER1)) != 0)
	335	{
	336	m_pending_interrupts &= ~(1 << HD63705_INT_TIMER1);
	337	RM16(0x1ff6, &m_pc);
	338	}
	339	else if ((m_pending_interrupts & (1 << HD63705_INT_TIMER2)) != 0)
	340	{
	341	m_pending_interrupts &= ~(1 << HD63705_INT_TIMER2);
	342	RM16(0x1ff4, &m_pc);
	343	}
	344	else if ((m_pending_interrupts & (1 << HD63705_INT_TIMER3)) != 0)
	345	{
	346	m_pending_interrupts &= ~(1<<HD63705_INT_TIMER3);
	347	RM16(0x1ff2, &m_pc);
	348	}
	349	else if ((m_pending_interrupts & (1 << HD63705_INT_PCI)) != 0)
	350	{
	351	m_pending_interrupts &= ~(1 << HD63705_INT_PCI);
	352	RM16(0x1ff0, &m_pc);
	353	}
	354	else if ((m_pending_interrupts & (1 << HD63705_INT_SCI)) != 0)
	355	{
	356	m_pending_interrupts &= ~(1 << HD63705_INT_SCI);
	357	RM16(0x1fee, &m_pc);
	358	}
	359	}
	360
346	361	/* Generate interrupts */
347		~~static~~ void ~~Interrupt(~~ m6805_~~Reg~~s *c~~pus~~tate )
	362	void m6805_base_device::interrupt()
348	363	{
349	364	/* the 6805 latches interrupt requests internally, so we don't clear */
350	365	/* pending_interrupts until the interrupt is taken, no matter what the */
351	366	/* external IRQ pin does. */
352	367
353		if( (cp~~ustat~~e~~->pe~~nding_interrupts & (1<<HD63705_INT_NMI)) != 0)
	368	if ((m_pending_interrupts & (1 << HD63705_INT_NMI)) != 0)
354	369	{
355		PUSHWORD(cpustate->pc);
356		PUSHBYTE(cpustate->x);
357		PUSHBYTE(cpustate->a);
358		PUSHBYTE(cpustate->cc);
	370	PUSHWORD(m_pc);
	371	PUSHBYTE(m_x);
	372	PUSHBYTE(m_a);
	373	PUSHBYTE(m_cc);
359	374	SEI;
360	375	/* no vectors supported, just do the callback to clear irq_state if needed */
361		if (cpustate->irq_callback)
362		(*cpustate->irq_callback)(cpustate->device, 0);
	376	standard_irq_callback(0);
363	377
364		RM16( cpustate, 0x1ffc, &pPC);
365		cpustate->pending_interrupts &= ~(1<<HD63705_INT_NMI);
	378	RM16(0x1ffc, &m_pc);
	379	m_pending_interrupts &= ~(1 << HD63705_INT_NMI);
366	380
367		cpustate->iCount -= 11;
368
	381	m_icount -= 11;
369	382	}
370		else if( (cpustate->pending_interrupts & ((1<<M6805_IRQ_LINE)\|HD63705_INT_MASK)) != 0 ) {
371		if ( (CC & IFLAG) == 0 ) {
	383	else if((m_pending_interrupts & ((1 << M6805_IRQ_LINE) \| HD63705_INT_MASK)) != 0)
372	384	{
373		/* standard IRQ */
374		//#if (HAS_HD63705)
375		// if(SUBTYPE!=SUBTYPE_HD63705)
376		//#endif
377		// PC \|= ~AMASK;
378		PUSHWORD(cpustate->pc);
379		PUSHBYTE(cpustate->x);
380		PUSHBYTE(cpustate->a);
381		PUSHBYTE(cpustate->cc);
382		SEI;
383		/* no vectors supported, just do the callback to clear irq_state if needed */
384		if (cpustate->irq_callback)
385		(*cpustate->irq_callback)(cpustate->device, 0);
386
387
388		if(SUBTYPE==SUBTYPE_HD63705)
	385	if ((CC & IFLAG) == 0)
389	386	{
390		/* Need to add emulation of other interrupt sources here KW-2/4/99 */
391		/* This is just a quick patch for Namco System 2 operation */
	387	/* standard IRQ */
	388	PUSHWORD(m_pc);
	389	PUSHBYTE(m_x);
	390	PUSHBYTE(m_a);
	391	PUSHBYTE(m_cc);
	392	SEI;
	393	/* no vectors supported, just do the callback to clear irq_state if needed */
	394	standard_irq_callback(0);
392	395
393		if((cpustate->pending_interrupts&(1<<HD63705_INT_IRQ1))!=0)
394		{
395		cpustate->pending_interrupts &= ~(1<<HD63705_INT_IRQ1);
396		RM16( cpustate, 0x1ff8, &pPC);
397		}
398		else if((cpustate->pending_interrupts&(1<<HD63705_INT_IRQ2))!=0)
399		{
400		cpustate->pending_interrupts &= ~(1<<HD63705_INT_IRQ2);
401		RM16( cpustate, 0x1fec, &pPC);
402		}
403		else if((cpustate->pending_interrupts&(1<<HD63705_INT_ADCONV))!=0)
404		{
405		cpustate->pending_interrupts &= ~(1<<HD63705_INT_ADCONV);
406		RM16( cpustate, 0x1fea, &pPC);
407		}
408		else if((cpustate->pending_interrupts&(1<<HD63705_INT_TIMER1))!=0)
409		{
410		cpustate->pending_interrupts &= ~(1<<HD63705_INT_TIMER1);
411		RM16( cpustate, 0x1ff6, &pPC);
412		}
413		else if((cpustate->pending_interrupts&(1<<HD63705_INT_TIMER2))!=0)
414		{
415		cpustate->pending_interrupts &= ~(1<<HD63705_INT_TIMER2);
416		RM16( cpustate, 0x1ff4, &pPC);
417		}
418		else if((cpustate->pending_interrupts&(1<<HD63705_INT_TIMER3))!=0)
419		{
420		cpustate->pending_interrupts &= ~(1<<HD63705_INT_TIMER3);
421		RM16( cpustate, 0x1ff2, &pPC);
422		}
423		else if((cpustate->pending_interrupts&(1<<HD63705_INT_PCI))!=0)
424		{
425		cpustate->pending_interrupts &= ~(1<<HD63705_INT_PCI);
426		RM16( cpustate, 0x1ff0, &pPC);
427		}
428		else if((cpustate->pending_interrupts&(1<<HD63705_INT_SCI))!=0)
429		{
430		cpustate->pending_interrupts &= ~(1<<HD63705_INT_SCI);
431		RM16( cpustate, 0x1fee, &pPC);
432		}
433		}
434		else if (SUBTYPE == SUBTYPE_M68HC05EG)
435		{
436		if((cpustate->pending_interrupts&(1<<M68HC05EG_INT_IRQ))!=0)
437		{
438		cpustate->pending_interrupts &= ~(1<<M68HC05EG_INT_IRQ);
439		RM16( cpustate, 0x1ffa, &pPC);
440		}
441		else if((cpustate->pending_interrupts&(1<<M68HC05EG_INT_TIMER))!=0)
442		{
443		cpustate->pending_interrupts &= ~(1<<M68HC05EG_INT_TIMER);
444		RM16( cpustate, 0x1ff8, &pPC);
445		}
446		else if((cpustate->pending_interrupts&(1<<M68HC05EG_INT_CPI))!=0)
447		{
448		cpustate->pending_interrupts &= ~(1<<M68HC05EG_INT_CPI);
449		RM16( cpustate, 0x1ff6, &pPC);
450		}
451		}
452		else
453		{
454		RM16( cpustate, 0xffff - 5, &pPC );
455		}
	396	interrupt_vector();
456	397
457		} // CC & IFLAG
458		cpustate->pending_interrupts &= ~(1<<M6805_IRQ_LINE);
	398	m_pending_interrupts &= ~(1 << M6805_IRQ_LINE);
459	399	}
460		~~cpustate->~~iCount -= 11;
	400	m_icount -= 11;
461	401	}
462	402	}
463	403
464		static void state_register(m6805_Regs cpustate, const char type, legacy_cpu_device *device)
	404
	405	//-------------------------------------------------
	406	// m6809_base_device - constructor
	407	//-------------------------------------------------
	408
	409	m6805_base_device::m6805_base_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock, const device_type type, const char *name, UINT32 addr_width)
	410	: cpu_device(mconfig, type, name, tag, owner, clock),
	411	m_program_config("program", ENDIANNESS_BIG, 8, addr_width)
465	412	{
466		device->save_item(NAME(A));
467		device->save_item(NAME(PC));
468		device->save_item(NAME(S));
469		device->save_item(NAME(X));
470		device->save_item(NAME(CC));
471		device->save_item(NAME(cpustate->pending_interrupts));
472		device->save_item(NAME(cpustate->irq_state));
473	413	}
474	414
475		~~stat~~ic ~~CPU_INIT(~~ m6805 )
	415	void m6805_base_device::device_start()
476	416	{
477		m6805_Regs *cpustate = get_safe_token(device);
	417	// register our state for the debugger
	418	astring tempstr;
	419	state_add(STATE_GENPC, "GENPC", m_pc.w.l).noshow();
	420	state_add(STATE_GENFLAGS, "GENFLAGS", m_cc).callimport().callexport().formatstr("%8s").noshow();
	421	state_add(M6805_A, "A", m_a).mask(0xff);
	422	state_add(M6805_PC, "PC", m_pc.w.l).mask(0xffff);
	423	state_add(M6805_S, "S", m_s.w.l).mask(0xff);
	424	state_add(M6805_X, "X", m_x).mask(0xff);
	425	state_add(M6805_CC, "CC", m_cc).mask(0xff);
478	426
479		state_register(cpustate, "m6805", device);
480		cpustate->irq_callback = irqcallback;
481		cpustate->device = device;
482		cpustate->program = &device->space(AS_PROGRAM);
483		cpustate->direct = &cpustate->program->direct();
	427	save_item(NAME(A));
	428	save_item(NAME(PC));
	429	save_item(NAME(S));
	430	save_item(NAME(X));
	431	save_item(NAME(CC));
	432	save_item(NAME(m_pending_interrupts));
	433	save_item(NAME(m_irq_state));
	434
	435	m_program = &space(AS_PROGRAM);
	436	m_direct = &m_program->direct();
	437
	438	// set our instruction counter
	439	m_icountptr = &m_icount;
	440	m_icount = 50000;
484	441	}
485	442
486		static CPU_RESET( m6805 )
	443
	444	void m6805_base_device::device_reset()
487	445	{
488		m6805_Regs *cpustate = get_safe_token(device);
	446	m_ea.w.l = 0;
	447	m_sp_mask = 0x07f;
	448	m_sp_low = 0x060;
	449	m_pc.w.l = 0;
	450	m_s.w.l = SP_MASK;
	451	m_a = 0;
	452	m_x = 0;
	453	m_cc = 0;
	454	m_pending_interrupts = 0;
489	455
490		device_irq_acknowledge_callback save_irqcallback = cpustate->irq_callback;
491		memset(cpustate, 0, sizeof(*cpustate));
	456	memset(m_irq_state, 0, sizeof(int) * 9);
	457	m_nmi_state = 0;
492	458
493		cpustate->iCount=50000; /* Used to be global */
494		cpustate->irq_callback = save_irqcallback;
495		cpustate->device = device;
496		cpustate->program = &device->space(AS_PROGRAM);
497		cpustate->direct = &cpustate->program->direct();
	459	m_icount = 50000;
498	460
499		/* Force CPU sub-type and relevant masks */
500		cpustate->subtype = SUBTYPE_M6805;
501		SP_MASK = 0x07f;
502		SP_LOW = 0x060;
	461	m_program = &space(AS_PROGRAM);
	462	m_direct = &m_program->direct();
503	463
504		/* Initial stack pointer */
505		S = SP_MASK;
506
507	464	/* IRQ disabled */
508	465	SEI;
509		RM16( cpustate, 0xfffe, &pPC );
510		}
511	466
512		static CPU_EXIT( m6805 )
513		{
514		/* nothing to do */
	467	RM16(0xfffe, &m_pc);
515	468	}
516	469
517	470
518		static void set_irq_line( m6805_Regs *cpustate, int irqline, int state )
519		{
520		/* Basic 6805 only has one IRQ line */
521		/* See HD63705 specific version */
522		if (cpustate->irq_state[0] == state) return;
	471	//-------------------------------------------------
	472	// memory_space_config - return the configuration
	473	// of the specified address space, or NULL if
	474	// the space doesn't exist
	475	//-------------------------------------------------
523	476
524		cpustate->irq_state[0] = state;
525		if (state != CLEAR_LINE)
526		cpustate->pending_interrupts \|= 1<<M6805_IRQ_LINE;
	477	const address_space_config *m6805_base_device::memory_space_config(address_spacenum spacenum) const
	478	{
	479	if (spacenum == AS_PROGRAM)
	480	{
	481	return &m_program_config;
	482	}
	483	return NULL;
527	484	}
528	485
529		#include "6805ops.c"
530	486
	487	//-------------------------------------------------
	488	// state_string_export - export state as a string
	489	// for the debugger
	490	//-------------------------------------------------
531	491
532		/* execute instructions on this CPU until icount expires */
533		static CPU_EXECUTE( m6805 )
	492	void m6805_base_device::state_string_export(const device_state_entry &entry, astring &string)
534	493	{
535		UINT8 ireg;
536		m6805_Regs *cpustate = get_safe_token(device);
537
538		S = SP_ADJUST( S ); /* Taken from CPU_SET_CONTEXT when pointer'afying */
539
540		do
	494	switch (entry.index())
541	495	{
542		if (cpustate->pending_interrupts != 0)
543		{
544		if (SUBTYPE==SUBTYPE_M68705)
545		{
546		m68705_Interrupt(cpustate);
547		}
548		else
549		{
550		Interrupt(cpustate);
551		}
552		}
	496	case STATE_GENFLAGS:
	497	string.printf("%c%c%c%c%c%c%c%c",
	498	(m_cc & 0x80) ? '?' : '.',
	499	(m_cc & 0x40) ? '?' : '.',
	500	(m_cc & 0x20) ? '?' : '.',
	501	(m_cc & 0x10) ? 'H' : '.',
	502	(m_cc & 0x08) ? 'I' : '.',
	503	(m_cc & 0x04) ? 'N' : '.',
	504	(m_cc & 0x02) ? 'Z' : '.',
	505	(m_cc & 0x01) ? 'C' : '.');
	506	break;
	507	}
	508	}
553	509
554		debugger_instruction_hook(device, PC);
555	510
556		ireg=M_RDOP(PC++);
	511	//-------------------------------------------------
	512	// disasm_min_opcode_bytes - return the length
	513	// of the shortest instruction, in bytes
	514	//-------------------------------------------------
557	515
558		switch( ireg )
559		{
560		case 0x00: brset(cpustate, 0x01); break;
561		case 0x01: brclr(cpustate, 0x01); break;
562		case 0x02: brset(cpustate, 0x02); break;
563		case 0x03: brclr(cpustate, 0x02); break;
564		case 0x04: brset(cpustate, 0x04); break;
565		case 0x05: brclr(cpustate, 0x04); break;
566		case 0x06: brset(cpustate, 0x08); break;
567		case 0x07: brclr(cpustate, 0x08); break;
568		case 0x08: brset(cpustate, 0x10); break;
569		case 0x09: brclr(cpustate, 0x10); break;
570		case 0x0A: brset(cpustate, 0x20); break;
571		case 0x0B: brclr(cpustate, 0x20); break;
572		case 0x0C: brset(cpustate, 0x40); break;
573		case 0x0D: brclr(cpustate, 0x40); break;
574		case 0x0E: brset(cpustate, 0x80); break;
575		case 0x0F: brclr(cpustate, 0x80); break;
576		case 0x10: bset(cpustate, 0x01); break;
577		case 0x11: bclr(cpustate, 0x01); break;
578		case 0x12: bset(cpustate, 0x02); break;
579		case 0x13: bclr(cpustate, 0x02); break;
580		case 0x14: bset(cpustate, 0x04); break;
581		case 0x15: bclr(cpustate, 0x04); break;
582		case 0x16: bset(cpustate, 0x08); break;
583		case 0x17: bclr(cpustate, 0x08); break;
584		case 0x18: bset(cpustate, 0x10); break;
585		case 0x19: bclr(cpustate, 0x10); break;
586		case 0x1a: bset(cpustate, 0x20); break;
587		case 0x1b: bclr(cpustate, 0x20); break;
588		case 0x1c: bset(cpustate, 0x40); break;
589		case 0x1d: bclr(cpustate, 0x40); break;
590		case 0x1e: bset(cpustate, 0x80); break;
591		case 0x1f: bclr(cpustate, 0x80); break;
592		case 0x20: bra(cpustate); break;
593		case 0x21: brn(cpustate); break;
594		case 0x22: bhi(cpustate); break;
595		case 0x23: bls(cpustate); break;
596		case 0x24: bcc(cpustate); break;
597		case 0x25: bcs(cpustate); break;
598		case 0x26: bne(cpustate); break;
599		case 0x27: beq(cpustate); break;
600		case 0x28: bhcc(cpustate); break;
601		case 0x29: bhcs(cpustate); break;
602		case 0x2a: bpl(cpustate); break;
603		case 0x2b: bmi(cpustate); break;
604		case 0x2c: bmc(cpustate); break;
605		case 0x2d: bms(cpustate); break;
606		case 0x2e: bil(cpustate); break;
607		case 0x2f: bih(cpustate); break;
608		case 0x30: neg_di(cpustate); break;
609		case 0x31: illegal(cpustate); break;
610		case 0x32: illegal(cpustate); break;
611		case 0x33: com_di(cpustate); break;
612		case 0x34: lsr_di(cpustate); break;
613		case 0x35: illegal(cpustate); break;
614		case 0x36: ror_di(cpustate); break;
615		case 0x37: asr_di(cpustate); break;
616		case 0x38: lsl_di(cpustate); break;
617		case 0x39: rol_di(cpustate); break;
618		case 0x3a: dec_di(cpustate); break;
619		case 0x3b: illegal(cpustate); break;
620		case 0x3c: inc_di(cpustate); break;
621		case 0x3d: tst_di(cpustate); break;
622		case 0x3e: illegal(cpustate); break;
623		case 0x3f: clr_di(cpustate); break;
624		case 0x40: nega(cpustate); break;
625		case 0x41: illegal(cpustate); break;
626		case 0x42: illegal(cpustate); break;
627		case 0x43: coma(cpustate); break;
628		case 0x44: lsra(cpustate); break;
629		case 0x45: illegal(cpustate); break;
630		case 0x46: rora(cpustate); break;
631		case 0x47: asra(cpustate); break;
632		case 0x48: lsla(cpustate); break;
633		case 0x49: rola(cpustate); break;
634		case 0x4a: deca(cpustate); break;
635		case 0x4b: illegal(cpustate); break;
636		case 0x4c: inca(cpustate); break;
637		case 0x4d: tsta(cpustate); break;
638		case 0x4e: illegal(cpustate); break;
639		case 0x4f: clra(cpustate); break;
640		case 0x50: negx(cpustate); break;
641		case 0x51: illegal(cpustate); break;
642		case 0x52: illegal(cpustate); break;
643		case 0x53: comx(cpustate); break;
644		case 0x54: lsrx(cpustate); break;
645		case 0x55: illegal(cpustate); break;
646		case 0x56: rorx(cpustate); break;
647		case 0x57: asrx(cpustate); break;
648		case 0x58: aslx(cpustate); break;
649		case 0x59: rolx(cpustate); break;
650		case 0x5a: decx(cpustate); break;
651		case 0x5b: illegal(cpustate); break;
652		case 0x5c: incx(cpustate); break;
653		case 0x5d: tstx(cpustate); break;
654		case 0x5e: illegal(cpustate); break;
655		case 0x5f: clrx(cpustate); break;
656		case 0x60: neg_ix1(cpustate); break;
657		case 0x61: illegal(cpustate); break;
658		case 0x62: illegal(cpustate); break;
659		case 0x63: com_ix1(cpustate); break;
660		case 0x64: lsr_ix1(cpustate); break;
661		case 0x65: illegal(cpustate); break;
662		case 0x66: ror_ix1(cpustate); break;
663		case 0x67: asr_ix1(cpustate); break;
664		case 0x68: lsl_ix1(cpustate); break;
665		case 0x69: rol_ix1(cpustate); break;
666		case 0x6a: dec_ix1(cpustate); break;
667		case 0x6b: illegal(cpustate); break;
668		case 0x6c: inc_ix1(cpustate); break;
669		case 0x6d: tst_ix1(cpustate); break;
670		case 0x6e: illegal(cpustate); break;
671		case 0x6f: clr_ix1(cpustate); break;
672		case 0x70: neg_ix(cpustate); break;
673		case 0x71: illegal(cpustate); break;
674		case 0x72: illegal(cpustate); break;
675		case 0x73: com_ix(cpustate); break;
676		case 0x74: lsr_ix(cpustate); break;
677		case 0x75: illegal(cpustate); break;
678		case 0x76: ror_ix(cpustate); break;
679		case 0x77: asr_ix(cpustate); break;
680		case 0x78: lsl_ix(cpustate); break;
681		case 0x79: rol_ix(cpustate); break;
682		case 0x7a: dec_ix(cpustate); break;
683		case 0x7b: illegal(cpustate); break;
684		case 0x7c: inc_ix(cpustate); break;
685		case 0x7d: tst_ix(cpustate); break;
686		case 0x7e: illegal(cpustate); break;
687		case 0x7f: clr_ix(cpustate); break;
688		case 0x80: rti(cpustate); break;
689		case 0x81: rts(cpustate); break;
690		case 0x82: illegal(cpustate); break;
691		case 0x83: swi(cpustate); break;
692		case 0x84: illegal(cpustate); break;
693		case 0x85: illegal(cpustate); break;
694		case 0x86: illegal(cpustate); break;
695		case 0x87: illegal(cpustate); break;
696		case 0x88: illegal(cpustate); break;
697		case 0x89: illegal(cpustate); break;
698		case 0x8a: illegal(cpustate); break;
699		case 0x8b: illegal(cpustate); break;
700		case 0x8c: illegal(cpustate); break;
701		case 0x8d: illegal(cpustate); break;
702		case 0x8e: illegal(cpustate); break;
703		case 0x8f: illegal(cpustate); break;
704		case 0x90: illegal(cpustate); break;
705		case 0x91: illegal(cpustate); break;
706		case 0x92: illegal(cpustate); break;
707		case 0x93: illegal(cpustate); break;
708		case 0x94: illegal(cpustate); break;
709		case 0x95: illegal(cpustate); break;
710		case 0x96: illegal(cpustate); break;
711		case 0x97: tax(cpustate); break;
712		case 0x98: CLC; break;
713		case 0x99: SEC; break;
714		#if IRQ_LEVEL_DETECT
715		case 0x9a: CLI; if (m6805.irq_state != CLEAR_LINE) m6805.pending_interrupts \|= 1<<M6805_IRQ_LINE; break;
716		#else
717		case 0x9a: CLI; break;
718		#endif
719		case 0x9b: SEI; break;
720		case 0x9c: rsp(cpustate); break;
721		case 0x9d: nop(cpustate); break;
722		case 0x9e: illegal(cpustate); break;
723		case 0x9f: txa(cpustate); break;
724		case 0xa0: suba_im(cpustate); break;
725		case 0xa1: cmpa_im(cpustate); break;
726		case 0xa2: sbca_im(cpustate); break;
727		case 0xa3: cpx_im(cpustate); break;
728		case 0xa4: anda_im(cpustate); break;
729		case 0xa5: bita_im(cpustate); break;
730		case 0xa6: lda_im(cpustate); break;
731		case 0xa7: illegal(cpustate); break;
732		case 0xa8: eora_im(cpustate); break;
733		case 0xa9: adca_im(cpustate); break;
734		case 0xaa: ora_im(cpustate); break;
735		case 0xab: adda_im(cpustate); break;
736		case 0xac: illegal(cpustate); break;
737		case 0xad: bsr(cpustate); break;
738		case 0xae: ldx_im(cpustate); break;
739		case 0xaf: illegal(cpustate); break;
740		case 0xb0: suba_di(cpustate); break;
741		case 0xb1: cmpa_di(cpustate); break;
742		case 0xb2: sbca_di(cpustate); break;
743		case 0xb3: cpx_di(cpustate); break;
744		case 0xb4: anda_di(cpustate); break;
745		case 0xb5: bita_di(cpustate); break;
746		case 0xb6: lda_di(cpustate); break;
747		case 0xb7: sta_di(cpustate); break;
748		case 0xb8: eora_di(cpustate); break;
749		case 0xb9: adca_di(cpustate); break;
750		case 0xba: ora_di(cpustate); break;
751		case 0xbb: adda_di(cpustate); break;
752		case 0xbc: jmp_di(cpustate); break;
753		case 0xbd: jsr_di(cpustate); break;
754		case 0xbe: ldx_di(cpustate); break;
755		case 0xbf: stx_di(cpustate); break;
756		case 0xc0: suba_ex(cpustate); break;
757		case 0xc1: cmpa_ex(cpustate); break;
758		case 0xc2: sbca_ex(cpustate); break;
759		case 0xc3: cpx_ex(cpustate); break;
760		case 0xc4: anda_ex(cpustate); break;
761		case 0xc5: bita_ex(cpustate); break;
762		case 0xc6: lda_ex(cpustate); break;
763		case 0xc7: sta_ex(cpustate); break;
764		case 0xc8: eora_ex(cpustate); break;
765		case 0xc9: adca_ex(cpustate); break;
766		case 0xca: ora_ex(cpustate); break;
767		case 0xcb: adda_ex(cpustate); break;
768		case 0xcc: jmp_ex(cpustate); break;
769		case 0xcd: jsr_ex(cpustate); break;
770		case 0xce: ldx_ex(cpustate); break;
771		case 0xcf: stx_ex(cpustate); break;
772		case 0xd0: suba_ix2(cpustate); break;
773		case 0xd1: cmpa_ix2(cpustate); break;
774		case 0xd2: sbca_ix2(cpustate); break;
775		case 0xd3: cpx_ix2(cpustate); break;
776		case 0xd4: anda_ix2(cpustate); break;
777		case 0xd5: bita_ix2(cpustate); break;
778		case 0xd6: lda_ix2(cpustate); break;
779		case 0xd7: sta_ix2(cpustate); break;
780		case 0xd8: eora_ix2(cpustate); break;
781		case 0xd9: adca_ix2(cpustate); break;
782		case 0xda: ora_ix2(cpustate); break;
783		case 0xdb: adda_ix2(cpustate); break;
784		case 0xdc: jmp_ix2(cpustate); break;
785		case 0xdd: jsr_ix2(cpustate); break;
786		case 0xde: ldx_ix2(cpustate); break;
787		case 0xdf: stx_ix2(cpustate); break;
788		case 0xe0: suba_ix1(cpustate); break;
789		case 0xe1: cmpa_ix1(cpustate); break;
790		case 0xe2: sbca_ix1(cpustate); break;
791		case 0xe3: cpx_ix1(cpustate); break;
792		case 0xe4: anda_ix1(cpustate); break;
793		case 0xe5: bita_ix1(cpustate); break;
794		case 0xe6: lda_ix1(cpustate); break;
795		case 0xe7: sta_ix1(cpustate); break;
796		case 0xe8: eora_ix1(cpustate); break;
797		case 0xe9: adca_ix1(cpustate); break;
798		case 0xea: ora_ix1(cpustate); break;
799		case 0xeb: adda_ix1(cpustate); break;
800		case 0xec: jmp_ix1(cpustate); break;
801		case 0xed: jsr_ix1(cpustate); break;
802		case 0xee: ldx_ix1(cpustate); break;
803		case 0xef: stx_ix1(cpustate); break;
804		case 0xf0: suba_ix(cpustate); break;
805		case 0xf1: cmpa_ix(cpustate); break;
806		case 0xf2: sbca_ix(cpustate); break;
807		case 0xf3: cpx_ix(cpustate); break;
808		case 0xf4: anda_ix(cpustate); break;
809		case 0xf5: bita_ix(cpustate); break;
810		case 0xf6: lda_ix(cpustate); break;
811		case 0xf7: sta_ix(cpustate); break;
812		case 0xf8: eora_ix(cpustate); break;
813		case 0xf9: adca_ix(cpustate); break;
814		case 0xfa: ora_ix(cpustate); break;
815		case 0xfb: adda_ix(cpustate); break;
816		case 0xfc: jmp_ix(cpustate); break;
817		case 0xfd: jsr_ix(cpustate); break;
818		case 0xfe: ldx_ix(cpustate); break;
819		case 0xff: stx_ix(cpustate); break;
820		}
821		cpustate->iCount -= cycles1[ireg];
822		} while( cpustate->iCount > 0 );
	516	UINT32 m6805_base_device::disasm_min_opcode_bytes() const
	517	{
	518	return 1;
823	519	}
824	520
825		/****************************************************************************
826		* M68HC05EG section
827		****************************************************************************/
828		static CPU_INIT( m68hc05eg )
	521
	522	//-------------------------------------------------
	523	// disasm_max_opcode_bytes - return the length
	524	// of the longest instruction, in bytes
	525	//-------------------------------------------------
	526
	527	UINT32 m6805_base_device::disasm_max_opcode_bytes() const
829	528	{
830		m6805_Regs *cpustate = get_safe_token(device);
831		state_register(cpustate, "m68hc05eg", device);
832		cpustate->irq_callback = irqcallback;
833		cpustate->device = device;
	529	return 3;
834	530	}
835	531
836		static CPU_RESET( m68hc05eg )
837		{
838		m6805_Regs *cpustate = get_safe_token(device);
839		CPU_RESET_CALL(m6805);
840	532
841		/* Overide default 6805 type */
842		cpustate->subtype = SUBTYPE_M68HC05EG;
843		SP_MASK = 0xff;
844		SP_LOW = 0xc0;
845		RM16( cpustate, 0x1ffe, &cpustate->pc );
	533	//-------------------------------------------------
	534	// disasm_disassemble - call the disassembly
	535	// helper function
	536	//-------------------------------------------------
	537
	538	offs_t m6805_base_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
	539	{
	540	extern CPU_DISASSEMBLE( m6805 );
	541	return cpu_disassemble_m6805(NULL, buffer, pc, oprom, opram, options);
846	542	}
847	543
848		static void m68hc05eg_set_irq_line(m6805_Regs *cpustate, int irqline, int state)
	544
	545	void m6805_device::execute_set_input(int inputnum, int state)
849	546	{
850		if (cpustate->irq_state[irqline] != state)
	547	/* Basic 6805 only has one IRQ line */
	548	/* See HD63705 specific version */
	549	if (m_irq_state[0] != state)
851	550	{
852		~~cpustate->~~irq_state[~~irqline~~] = state;
	551	m_irq_state[0] = state;
853	552
854	553	if (state != CLEAR_LINE)
855	554	{
856		cp~~ustat~~e~~->pe~~nding_interrupts \|= 1<<~~irqline~~;
	555	m_pending_interrupts \|= 1 << M6805_IRQ_LINE;
857	556	}
858	557	}
859	558	}
860	559
	560	#include "6805ops.c"
861	561
862		/****************************************************************************
863		* M68705 section
864		****************************************************************************/
865		static CPU_INIT( m68705 )
	562	//-------------------------------------------------
	563	// execute_clocks_to_cycles - convert the raw
	564	// clock into cycles per second
	565	//-------------------------------------------------
	566
	567	UINT64 m6805_base_device::execute_clocks_to_cycles(UINT64 clocks) const
866	568	{
867		m6805_Regs *cpustate = get_safe_token(device);
868		state_register(cpustate, "m68705", device);
869		cpustate->irq_callback = irqcallback;
870		cpustate->device = device;
	569	return (clocks + 3) / 4;
871	570	}
872	571
873		static CPU_RESET( m68705 )
874		{
875		m6805_Regs *cpustate = get_safe_token(device);
876		CPU_RESET_CALL(m6805);
877	572
878		/* Overide default 6805 type */
879		cpustate->subtype = SUBTYPE_M68705;
880		RM16( cpustate, 0xfffe, &cpustate->pc );
881		}
	573	//-------------------------------------------------
	574	// execute_cycles_to_clocks - convert a cycle
	575	// count back to raw clocks
	576	//-------------------------------------------------
882	577
883		~~static~~ ~~void~~ m68705_set_i~~rq_lin~~e~~(m6805_R~~egs *cpustate~~, in~~t ~~irq~~line, int st~~ate)~~
	578	UINT64 m6805_base_device::execute_cycles_to_clocks(UINT64 cycles) const
884	579	{
885		if (cpustate->irq_state[irqline] == state ) return;
886		cpustate->irq_state[irqline] = state;
887		if (state != CLEAR_LINE) cpustate->pending_interrupts \|= 1<<irqline;
	580	return cycles * 4;
888	581	}
889	582
890	583
891		/****************************************************************************
892		* HD63705 section
893		****************************************************************************/
894		static CPU_INIT( hd63705 )
	584	//-------------------------------------------------
	585	// execute_min_cycles - return minimum number of
	586	// cycles it takes for one instruction to execute
	587	//-------------------------------------------------
	588
	589	UINT32 m6805_base_device::execute_min_cycles() const
895	590	{
896		m6805_Regs *cpustate = get_safe_token(device);
897		state_register(cpustate, "hd63705", device);
898		cpustate->irq_callback = irqcallback;
899		cpustate->device = device;
	591	return 2;
900	592	}
901	593
902		static CPU_RESET( hd63705 )
903		{
904		m6805_Regs *cpustate = get_safe_token(device);
905		CPU_RESET_CALL(m6805);
906	594
907		/* Overide default 6805 types */
908		cpustate->subtype = SUBTYPE_HD63705;
909		SP_MASK = 0x17f;
910		SP_LOW = 0x100;
911		RM16( cpustate, 0x1ffe, &cpustate->pc );
912		S = 0x17f;
913		}
	595	//-------------------------------------------------
	596	// execute_max_cycles - return maximum number of
	597	// cycles it takes for one instruction to execute
	598	//-------------------------------------------------
914	599
915		~~static~~ ~~void hd~~63705_set_i~~rq_lin~~e~~(m6805_R~~egs *cpustate~~, int irq~~line, int st~~ate)~~
	600	UINT32 m6805_base_device::execute_max_cycles() const
916	601	{
917		if (irqline == INPUT_LINE_NMI)
918		{
919		if (cpustate->nmi_state == state) return;
920
921		cpustate->nmi_state = state;
922		if (state != CLEAR_LINE)
923		cpustate->pending_interrupts \|= 1<<HD63705_INT_NMI;
924		}
925		else if (irqline <= HD63705_INT_ADCONV)
926		{
927		if (cpustate->irq_state[irqline] == state) return;
928		cpustate->irq_state[irqline] = state;
929		if (state != CLEAR_LINE) cpustate->pending_interrupts \|= 1<<irqline;
930		}
	602	return 10;
931	603	}
932	604
933	605
	606	//-------------------------------------------------
	607	// execute_input_lines - return the number of
	608	// input/interrupt lines
	609	//-------------------------------------------------
934	610
935		/**************************************************************************
936		* Generic set_info
937		**************************************************************************/
938
939		static CPU_SET_INFO( m6805 )
	611	UINT32 m6805_base_device::execute_input_lines() const
940	612	{
941		m6805_Regs *cpustate = get_safe_token(device);
942
943		switch (state)
944		{
945		/* --- the following bits of info are set as 64-bit signed integers --- */
946		case CPUINFO_INT_INPUT_STATE + M6805_IRQ_LINE: set_irq_line(cpustate, M6805_IRQ_LINE, info->i); break;
947
948		case CPUINFO_INT_REGISTER + M6805_A: A = info->i; break;
949		case CPUINFO_INT_PC:
950		case CPUINFO_INT_REGISTER + M6805_PC: PC = info->i; break;
951		case CPUINFO_INT_SP:
952		case CPUINFO_INT_REGISTER + M6805_S: S = SP_ADJUST(info->i); break;
953		case CPUINFO_INT_REGISTER + M6805_X: X = info->i; break;
954		case CPUINFO_INT_REGISTER + M6805_CC: CC = info->i; break;
955		}
	613	return 9;
956	614	}
957	615
958	616
959
960		/**************************************************************************
961		* Generic get_info
962		**************************************************************************/
963
964		CPU_GET_INFO( m6805 )
	617	/* execute instructions on this CPU until icount expires */
	618	void m6805_base_device::execute_run()
965	619	{
966		~~m6805_Regs *cpustate = (device != N~~U~~LL && device->token() !=~~ N~~ULL)~~ ~~? get_safe_token(dev~~ice~~) : NULL~~;
	620	UINT8 ireg;
967	621
968		switch (state)
	622	S = SP_ADJUST( S ); /* Taken from CPU_SET_CONTEXT when pointer'afying */
	623
	624	do
969	625	{
970		/* --- the following bits of info are returned as 64-bit signed integers --- */
971		case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(m6805_Regs); break;
972		case CPUINFO_INT_INPUT_LINES: info->i = 1; break;
973		case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
974		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
975		case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
976		case CPUINFO_INT_CLOCK_DIVIDER: info->i = 4; break;
977		case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
978		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 3; break;
979		case CPUINFO_INT_MIN_CYCLES: info->i = 2; break;
980		case CPUINFO_INT_MAX_CYCLES: info->i = 10; break;
	626	if (m_pending_interrupts != 0)
	627	{
	628	interrupt();
	629	}
981	630
982		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
983		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 12; break;
984		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
985		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
986		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
987		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
988		case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
989		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
990		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
	631	debugger_instruction_hook(this, PC);
991	632
992		~~case CPUINFO_INT_INPUT_STATE + M6805_IRQ_LINE:~~ i~~nfo->i = cpustate->i~~r~~q_stat~~e[M~~6805~~_IR~~Q_LINE]; break~~;
	633	ireg=M_RDOP(PC++);
993	634
994		case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
995
996		case CPUINFO_INT_REGISTER + M6805_A: info->i = A; break;
997		case CPUINFO_INT_PC: info->i = PC; break;
998		case CPUINFO_INT_REGISTER + M6805_PC: info->i = PC; break;
999		case CPUINFO_INT_SP:
1000		case CPUINFO_INT_REGISTER + M6805_S: info->i = SP_ADJUST(S); break;
1001		case CPUINFO_INT_REGISTER + M6805_X: info->i = X; break;
1002		case CPUINFO_INT_REGISTER + M6805_CC: info->i = CC; break;
1003
1004		/* --- the following bits of info are returned as pointers to data or functions --- */
1005		case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m6805); break;
1006		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m6805); break;
1007		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m6805); break;
1008		case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(m6805); break;
1009		case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(m6805); break;
1010		case CPUINFO_FCT_BURN: info->burn = NULL; break;
1011		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(m6805);break;
1012		case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->iCount; break;
1013
1014		/* --- the following bits of info are returned as NULL-terminated strings --- */
1015		case CPUINFO_STR_NAME: strcpy(info->s, "M6805"); break;
1016		case CPUINFO_STR_FAMILY: strcpy(info->s, "Motorola 6805"); break;
1017		case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
1018		case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
1019		case CPUINFO_STR_CREDITS: strcpy(info->s, "The MAME team."); break;
1020
1021		case CPUINFO_STR_FLAGS:
1022		sprintf(info->s, "%c%c%c%c%c%c%c%c",
1023		cpustate->cc & 0x80 ? '?':'.',
1024		cpustate->cc & 0x40 ? '?':'.',
1025		cpustate->cc & 0x20 ? '?':'.',
1026		cpustate->cc & 0x10 ? 'H':'.',
1027		cpustate->cc & 0x08 ? 'I':'.',
1028		cpustate->cc & 0x04 ? 'N':'.',
1029		cpustate->cc & 0x02 ? 'Z':'.',
1030		cpustate->cc & 0x01 ? 'C':'.');
1031		break;
1032
1033		case CPUINFO_STR_REGISTER + M6805_A: sprintf(info->s, "A:%02X", cpustate->a); break;
1034		case CPUINFO_STR_REGISTER + M6805_PC: sprintf(info->s, "PC:%04X", cpustate->pc.w.l); break;
1035		case CPUINFO_STR_REGISTER + M6805_S: sprintf(info->s, "S:%02X", cpustate->s.w.l); break;
1036		case CPUINFO_STR_REGISTER + M6805_X: sprintf(info->s, "X:%02X", cpustate->x); break;
1037		case CPUINFO_STR_REGISTER + M6805_CC: sprintf(info->s, "CC:%02X", cpustate->cc); break;
1038		}
	635	switch( ireg )
	636	{
	637	case 0x00: brset(0x01); break;
	638	case 0x01: brclr(0x01); break;
	639	case 0x02: brset(0x02); break;
	640	case 0x03: brclr(0x02); break;
	641	case 0x04: brset(0x04); break;
	642	case 0x05: brclr(0x04); break;
	643	case 0x06: brset(0x08); break;
	644	case 0x07: brclr(0x08); break;
	645	case 0x08: brset(0x10); break;
	646	case 0x09: brclr(0x10); break;
	647	case 0x0A: brset(0x20); break;
	648	case 0x0B: brclr(0x20); break;
	649	case 0x0C: brset(0x40); break;
	650	case 0x0D: brclr(0x40); break;
	651	case 0x0E: brset(0x80); break;
	652	case 0x0F: brclr(0x80); break;
	653	case 0x10: bset(0x01); break;
	654	case 0x11: bclr(0x01); break;
	655	case 0x12: bset(0x02); break;
	656	case 0x13: bclr(0x02); break;
	657	case 0x14: bset(0x04); break;
	658	case 0x15: bclr(0x04); break;
	659	case 0x16: bset(0x08); break;
	660	case 0x17: bclr(0x08); break;
	661	case 0x18: bset(0x10); break;
	662	case 0x19: bclr(0x10); break;
	663	case 0x1a: bset(0x20); break;
	664	case 0x1b: bclr(0x20); break;
	665	case 0x1c: bset(0x40); break;
	666	case 0x1d: bclr(0x40); break;
	667	case 0x1e: bset(0x80); break;
	668	case 0x1f: bclr(0x80); break;
	669	case 0x20: bra(); break;
	670	case 0x21: brn(); break;
	671	case 0x22: bhi(); break;
	672	case 0x23: bls(); break;
	673	case 0x24: bcc(); break;
	674	case 0x25: bcs(); break;
	675	case 0x26: bne(); break;
	676	case 0x27: beq(); break;
	677	case 0x28: bhcc(); break;
	678	case 0x29: bhcs(); break;
	679	case 0x2a: bpl(); break;
	680	case 0x2b: bmi(); break;
	681	case 0x2c: bmc(); break;
	682	case 0x2d: bms(); break;
	683	case 0x2e: bil(); break;
	684	case 0x2f: bih(); break;
	685	case 0x30: neg_di(); break;
	686	case 0x31: illegal(); break;
	687	case 0x32: illegal(); break;
	688	case 0x33: com_di(); break;
	689	case 0x34: lsr_di(); break;
	690	case 0x35: illegal(); break;
	691	case 0x36: ror_di(); break;
	692	case 0x37: asr_di(); break;
	693	case 0x38: lsl_di(); break;
	694	case 0x39: rol_di(); break;
	695	case 0x3a: dec_di(); break;
	696	case 0x3b: illegal(); break;
	697	case 0x3c: inc_di(); break;
	698	case 0x3d: tst_di(); break;
	699	case 0x3e: illegal(); break;
	700	case 0x3f: clr_di(); break;
	701	case 0x40: nega(); break;
	702	case 0x41: illegal(); break;
	703	case 0x42: illegal(); break;
	704	case 0x43: coma(); break;
	705	case 0x44: lsra(); break;
	706	case 0x45: illegal(); break;
	707	case 0x46: rora(); break;
	708	case 0x47: asra(); break;
	709	case 0x48: lsla(); break;
	710	case 0x49: rola(); break;
	711	case 0x4a: deca(); break;
	712	case 0x4b: illegal(); break;
	713	case 0x4c: inca(); break;
	714	case 0x4d: tsta(); break;
	715	case 0x4e: illegal(); break;
	716	case 0x4f: clra(); break;
	717	case 0x50: negx(); break;
	718	case 0x51: illegal(); break;
	719	case 0x52: illegal(); break;
	720	case 0x53: comx(); break;
	721	case 0x54: lsrx(); break;
	722	case 0x55: illegal(); break;
	723	case 0x56: rorx(); break;
	724	case 0x57: asrx(); break;
	725	case 0x58: aslx(); break;
	726	case 0x59: rolx(); break;
	727	case 0x5a: decx(); break;
	728	case 0x5b: illegal(); break;
	729	case 0x5c: incx(); break;
	730	case 0x5d: tstx(); break;
	731	case 0x5e: illegal(); break;
	732	case 0x5f: clrx(); break;
	733	case 0x60: neg_ix1(); break;
	734	case 0x61: illegal(); break;
	735	case 0x62: illegal(); break;
	736	case 0x63: com_ix1(); break;
	737	case 0x64: lsr_ix1(); break;
	738	case 0x65: illegal(); break;
	739	case 0x66: ror_ix1(); break;
	740	case 0x67: asr_ix1(); break;
	741	case 0x68: lsl_ix1(); break;
	742	case 0x69: rol_ix1(); break;
	743	case 0x6a: dec_ix1(); break;
	744	case 0x6b: illegal(); break;
	745	case 0x6c: inc_ix1(); break;
	746	case 0x6d: tst_ix1(); break;
	747	case 0x6e: illegal(); break;
	748	case 0x6f: clr_ix1(); break;
	749	case 0x70: neg_ix(); break;
	750	case 0x71: illegal(); break;
	751	case 0x72: illegal(); break;
	752	case 0x73: com_ix(); break;
	753	case 0x74: lsr_ix(); break;
	754	case 0x75: illegal(); break;
	755	case 0x76: ror_ix(); break;
	756	case 0x77: asr_ix(); break;
	757	case 0x78: lsl_ix(); break;
	758	case 0x79: rol_ix(); break;
	759	case 0x7a: dec_ix(); break;
	760	case 0x7b: illegal(); break;
	761	case 0x7c: inc_ix(); break;
	762	case 0x7d: tst_ix(); break;
	763	case 0x7e: illegal(); break;
	764	case 0x7f: clr_ix(); break;
	765	case 0x80: rti(); break;
	766	case 0x81: rts(); break;
	767	case 0x82: illegal(); break;
	768	case 0x83: swi(); break;
	769	case 0x84: illegal(); break;
	770	case 0x85: illegal(); break;
	771	case 0x86: illegal(); break;
	772	case 0x87: illegal(); break;
	773	case 0x88: illegal(); break;
	774	case 0x89: illegal(); break;
	775	case 0x8a: illegal(); break;
	776	case 0x8b: illegal(); break;
	777	case 0x8c: illegal(); break;
	778	case 0x8d: illegal(); break;
	779	case 0x8e: illegal(); break;
	780	case 0x8f: illegal(); break;
	781	case 0x90: illegal(); break;
	782	case 0x91: illegal(); break;
	783	case 0x92: illegal(); break;
	784	case 0x93: illegal(); break;
	785	case 0x94: illegal(); break;
	786	case 0x95: illegal(); break;
	787	case 0x96: illegal(); break;
	788	case 0x97: tax(); break;
	789	case 0x98: CLC; break;
	790	case 0x99: SEC; break;
	791	#if IRQ_LEVEL_DETECT
	792	case 0x9a: CLI; if (m_irq_state != CLEAR_LINE) m_pending_interrupts \|= 1 << M6805_IRQ_LINE; break;
	793	#else
	794	case 0x9a: CLI; break;
	795	#endif
	796	case 0x9b: SEI; break;
	797	case 0x9c: rsp(); break;
	798	case 0x9d: nop(); break;
	799	case 0x9e: illegal(); break;
	800	case 0x9f: txa(); break;
	801	case 0xa0: suba_im(); break;
	802	case 0xa1: cmpa_im(); break;
	803	case 0xa2: sbca_im(); break;
	804	case 0xa3: cpx_im(); break;
	805	case 0xa4: anda_im(); break;
	806	case 0xa5: bita_im(); break;
	807	case 0xa6: lda_im(); break;
	808	case 0xa7: illegal(); break;
	809	case 0xa8: eora_im(); break;
	810	case 0xa9: adca_im(); break;
	811	case 0xaa: ora_im(); break;
	812	case 0xab: adda_im(); break;
	813	case 0xac: illegal(); break;
	814	case 0xad: bsr(); break;
	815	case 0xae: ldx_im(); break;
	816	case 0xaf: illegal(); break;
	817	case 0xb0: suba_di(); break;
	818	case 0xb1: cmpa_di(); break;
	819	case 0xb2: sbca_di(); break;
	820	case 0xb3: cpx_di(); break;
	821	case 0xb4: anda_di(); break;
	822	case 0xb5: bita_di(); break;
	823	case 0xb6: lda_di(); break;
	824	case 0xb7: sta_di(); break;
	825	case 0xb8: eora_di(); break;
	826	case 0xb9: adca_di(); break;
	827	case 0xba: ora_di(); break;
	828	case 0xbb: adda_di(); break;
	829	case 0xbc: jmp_di(); break;
	830	case 0xbd: jsr_di(); break;
	831	case 0xbe: ldx_di(); break;
	832	case 0xbf: stx_di(); break;
	833	case 0xc0: suba_ex(); break;
	834	case 0xc1: cmpa_ex(); break;
	835	case 0xc2: sbca_ex(); break;
	836	case 0xc3: cpx_ex(); break;
	837	case 0xc4: anda_ex(); break;
	838	case 0xc5: bita_ex(); break;
	839	case 0xc6: lda_ex(); break;
	840	case 0xc7: sta_ex(); break;
	841	case 0xc8: eora_ex(); break;
	842	case 0xc9: adca_ex(); break;
	843	case 0xca: ora_ex(); break;
	844	case 0xcb: adda_ex(); break;
	845	case 0xcc: jmp_ex(); break;
	846	case 0xcd: jsr_ex(); break;
	847	case 0xce: ldx_ex(); break;
	848	case 0xcf: stx_ex(); break;
	849	case 0xd0: suba_ix2(); break;
	850	case 0xd1: cmpa_ix2(); break;
	851	case 0xd2: sbca_ix2(); break;
	852	case 0xd3: cpx_ix2(); break;
	853	case 0xd4: anda_ix2(); break;
	854	case 0xd5: bita_ix2(); break;
	855	case 0xd6: lda_ix2(); break;
	856	case 0xd7: sta_ix2(); break;
	857	case 0xd8: eora_ix2(); break;
	858	case 0xd9: adca_ix2(); break;
	859	case 0xda: ora_ix2(); break;
	860	case 0xdb: adda_ix2(); break;
	861	case 0xdc: jmp_ix2(); break;
	862	case 0xdd: jsr_ix2(); break;
	863	case 0xde: ldx_ix2(); break;
	864	case 0xdf: stx_ix2(); break;
	865	case 0xe0: suba_ix1(); break;
	866	case 0xe1: cmpa_ix1(); break;
	867	case 0xe2: sbca_ix1(); break;
	868	case 0xe3: cpx_ix1(); break;
	869	case 0xe4: anda_ix1(); break;
	870	case 0xe5: bita_ix1(); break;
	871	case 0xe6: lda_ix1(); break;
	872	case 0xe7: sta_ix1(); break;
	873	case 0xe8: eora_ix1(); break;
	874	case 0xe9: adca_ix1(); break;
	875	case 0xea: ora_ix1(); break;
	876	case 0xeb: adda_ix1(); break;
	877	case 0xec: jmp_ix1(); break;
	878	case 0xed: jsr_ix1(); break;
	879	case 0xee: ldx_ix1(); break;
	880	case 0xef: stx_ix1(); break;
	881	case 0xf0: suba_ix(); break;
	882	case 0xf1: cmpa_ix(); break;
	883	case 0xf2: sbca_ix(); break;
	884	case 0xf3: cpx_ix(); break;
	885	case 0xf4: anda_ix(); break;
	886	case 0xf5: bita_ix(); break;
	887	case 0xf6: lda_ix(); break;
	888	case 0xf7: sta_ix(); break;
	889	case 0xf8: eora_ix(); break;
	890	case 0xf9: adca_ix(); break;
	891	case 0xfa: ora_ix(); break;
	892	case 0xfb: adda_ix(); break;
	893	case 0xfc: jmp_ix(); break;
	894	case 0xfd: jsr_ix(); break;
	895	case 0xfe: ldx_ix(); break;
	896	case 0xff: stx_ix(); break;
	897	}
	898	m_icount -= m_cycles1[ireg];
	899	} while( m_icount > 0 );
1039	900	}
1040	901
1041		/**************************************************************************
1042		* CPU-specific set_info for 68HC05EG
1043		**************************************************************************/
1044		static CPU_SET_INFO( m68hc05eg )
	902	/****************************************************************************
	903	* M68HC05EG section
	904	****************************************************************************/
	905	void m68hc05eg_device::device_reset()
1045	906	{
1046		m6805_~~Regs *cpust~~a~~te = get_~~safe_~~tok~~en(device);
	907	m6805_base_device::device_reset();
1047	908
1048		switch(state)
1049		{
1050		case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_IRQ: m68hc05eg_set_irq_line(cpustate, M68HC05EG_INT_IRQ, info->i); break;
1051		case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_TIMER: m68hc05eg_set_irq_line(cpustate, M68HC05EG_INT_TIMER, info->i); break;
1052		case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_CPI: m68hc05eg_set_irq_line(cpustate, M68HC05EG_INT_CPI, info->i); break;
	909	m_sp_mask = 0xff;
	910	m_sp_low = 0xc0;
1053	911
1054		default: CPU_SET_INFO_CALL(m6805); break;
1055		}
	912	RM16(0x1ffe, &m_pc);
1056	913	}
1057	914
1058		~~CPU_GET_INFO(~~ m68hc05eg )
	915	void m68hc05eg_device::execute_set_input(int inputnum, int state)
1059	916	{
1060		m6805_Regs *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
1061
1062		switch (state)
	917	if (m_irq_state[inputnum] != state)
1063	918	{
1064		/* --- the following bits of info are returned as 64-bit signed integers --- */
1065		case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_IRQ: info->i = cpustate->irq_state[M68HC05EG_INT_IRQ]; break;
1066		case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_TIMER: info->i = cpustate->irq_state[M68HC05EG_INT_TIMER]; break;
1067		case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_CPI: info->i = cpustate->irq_state[M68HC05EG_INT_CPI]; break;
	919	m_irq_state[inputnum] = state;
1068	920
1069		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 13; break;
1070
1071		/* --- the following bits of info are returned as pointers to data or functions --- */
1072		case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m68hc05eg); break;
1073		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68hc05eg); break;
1074		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m68hc05eg); break;
1075
1076		/* --- the following bits of info are returned as NULL-terminated strings --- */
1077		case CPUINFO_STR_NAME: strcpy(info->s, "M68HC05EG"); break;
1078
1079		default: CPU_GET_INFO_CALL(m6805); break;
	921	if (state != CLEAR_LINE)
	922	{
	923	m_pending_interrupts \|= 1 << inputnum;
	924	}
1080	925	}
1081	926	}
1082	927
1083		/**************************************************************************
1084		* CPU-specific set_info
1085		**************************************************************************/
1086		static CPU_SET_INFO( m68705 )
	928
	929	/****************************************************************************
	930	* M68705 section
	931	****************************************************************************/
	932	void m68705_device::device_reset()
1087	933	{
1088		m6805_~~Regs *cpust~~a~~te = get_~~safe_~~tok~~en(device);
	934	m6805_base_device::device_reset();
1089	935
1090		switch(state)
1091		{
1092		/* --- the following bits of info are set as 64-bit signed integers --- */
1093		case CPUINFO_INT_INPUT_STATE + M68705_INT_TIMER: m68705_set_irq_line(cpustate, M68705_INT_TIMER, info->i); break;
1094
1095		default: CPU_SET_INFO_CALL(m6805); break;
1096		}
	936	RM16(0xfffe, &m_pc);
1097	937	}
1098	938
1099		~~CPU_GET_INFO(~~ m68705 )
	939	void m68705_device::execute_set_input(int inputnum, int state)
1100	940	{
1101		m6805_Regs *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
1102
1103		switch (state)
	941	if (m_irq_state[inputnum] != state)
1104	942	{
1105		/* --- the following bits of info are returned as 64-bit signed integers --- */
1106		case CPUINFO_INT_INPUT_STATE + M68705_INT_TIMER: info->i = cpustate->irq_state[M68705_INT_TIMER]; break;
	943	m_irq_state[inputnum] = state;
1107	944
1108		/* --- the following bits of info are returned as pointers to data or functions --- */
1109		case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m68705); break;
1110		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68705); break;
1111		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m68705); break;
1112
1113		/* --- the following bits of info are returned as NULL-terminated strings --- */
1114		case CPUINFO_STR_NAME: strcpy(info->s, "M68705"); break;
1115
1116		default: CPU_GET_INFO_CALL(m6805); break;
	945	if (state != CLEAR_LINE)
	946	{
	947	m_pending_interrupts \|= 1 << inputnum;
	948	}
1117	949	}
1118	950	}
1119	951
1120	952
1121		/**************************************************************************
1122		* CPU-specific set_info
1123		**************************************************************************/
1124
1125		static CPU_SET_INFO( hd63705 )
	953	/****************************************************************************
	954	* HD63705 section
	955	****************************************************************************/
	956	void hd63705_device::device_reset()
1126	957	{
1127		m6805_~~Regs *cpust~~a~~te = get_~~safe_~~tok~~en(device);
	958	m6805_base_device::device_reset();
1128	959
1129		switch (state)
1130		{
1131		/* --- the following bits of info are set as 64-bit signed integers --- */
1132		case CPUINFO_INT_INPUT_STATE + HD63705_INT_IRQ1: hd63705_set_irq_line(cpustate, HD63705_INT_IRQ1, info->i); break;
1133		case CPUINFO_INT_INPUT_STATE + HD63705_INT_IRQ2: hd63705_set_irq_line(cpustate, HD63705_INT_IRQ2, info->i); break;
1134		case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER1: hd63705_set_irq_line(cpustate, HD63705_INT_TIMER1, info->i); break;
1135		case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER2: hd63705_set_irq_line(cpustate, HD63705_INT_TIMER2, info->i); break;
1136		case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER3: hd63705_set_irq_line(cpustate, HD63705_INT_TIMER3, info->i); break;
1137		case CPUINFO_INT_INPUT_STATE + HD63705_INT_PCI: hd63705_set_irq_line(cpustate, HD63705_INT_PCI, info->i); break;
1138		case CPUINFO_INT_INPUT_STATE + HD63705_INT_SCI: hd63705_set_irq_line(cpustate, HD63705_INT_SCI, info->i); break;
1139		case CPUINFO_INT_INPUT_STATE + HD63705_INT_ADCONV: hd63705_set_irq_line(cpustate, HD63705_INT_ADCONV, info->i); break;
1140		case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: hd63705_set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break;
	960	m_sp_mask = 0x17f;
	961	m_sp_low = 0x100;
	962	m_s.w.l = SP_MASK;
1141	963
1142		default: CPU_SET_INFO_CALL(m6805);break;
1143		}
	964	RM16(0x1ffe, &m_pc);
1144	965	}
1145	966
1146		~~CPU_GET_INFO(~~ hd63705 )
	967	void hd63705_device::execute_set_input(int inputnum, int state)
1147	968	{
1148		m6805_Regs *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
	969	if (inputnum == INPUT_LINE_NMI)
	970	{
	971	if (m_nmi_state != state)
	972	{
	973	m_nmi_state = state;
1149	974
1150		switch (state)
	975	if (state != CLEAR_LINE)
	976	{
	977	m_pending_interrupts \|= 1 << HD63705_INT_NMI;
	978	}
	979	}
	980	}
	981	else if (inputnum <= HD63705_INT_ADCONV)
1151	982	{
1152		/* --- the following bits of info are returned as 64-bit signed integers --- */
1153		case CPUINFO_INT_INPUT_STATE + HD63705_INT_IRQ1: info->i = cpustate->irq_state[HD63705_INT_IRQ1]; break;
1154		case CPUINFO_INT_INPUT_STATE + HD63705_INT_IRQ2: info->i = cpustate->irq_state[HD63705_INT_IRQ2]; break;
1155		case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER1: info->i = cpustate->irq_state[HD63705_INT_TIMER1]; break;
1156		case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER2: info->i = cpustate->irq_state[HD63705_INT_TIMER2]; break;
1157		case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER3: info->i = cpustate->irq_state[HD63705_INT_TIMER3]; break;
1158		case CPUINFO_INT_INPUT_STATE + HD63705_INT_PCI: info->i = cpustate->irq_state[HD63705_INT_PCI]; break;
1159		case CPUINFO_INT_INPUT_STATE + HD63705_INT_SCI: info->i = cpustate->irq_state[HD63705_INT_SCI]; break;
1160		case CPUINFO_INT_INPUT_STATE + HD63705_INT_ADCONV: info->i = cpustate->irq_state[HD63705_INT_ADCONV]; break;
1161		case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->irq_state[HD63705_INT_NMI]; break;
	983	if (m_irq_state[inputnum] != state)
	984	{
	985	m_irq_state[inputnum] = state;
1162	986
1163		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break;
1164
1165		/* --- the following bits of info are returned as pointers to data or functions --- */
1166		case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(hd63705); break;
1167		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(hd63705); break;
1168		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(hd63705); break;
1169
1170		/* --- the following bits of info are returned as NULL-terminated strings --- */
1171		case CPUINFO_STR_NAME: strcpy(info->s, "HD63705"); break;
1172		case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
1173		case CPUINFO_STR_CREDITS: strcpy(info->s, "Keith Wilkins, Juergen Buchmueller"); break;
1174
1175		default: CPU_GET_INFO_CALL(m6805); break;
	987	if (state != CLEAR_LINE)
	988	{
	989	m_pending_interrupts \|= 1 << inputnum;
	990	}
	991	}
1176	992	}
1177	993	}
1178	994
1179		DEFINE_LEGACY_CPU_DEVICE(M6805, m6805);
1180		DEFINE_LEGACY_CPU_DEVICE(M68HC05EG, m68hc05eg);
1181		DEFINE_LEGACY_CPU_DEVICE(M68705, m68705);
1182		DEFINE_LEGACY_CPU_DEVICE(HD63705, hd63705);
	995	const device_type M6805 = &device_creator<m6805_device>;
	996	const device_type M68HC05EG = &device_creator<m68hc05eg_device>;
	997	const device_type M68705 = &device_creator<m68705_device>;
	998	const device_type HD63705 = &device_creator<hd63705_device>;

trunk/src/emu/cpu/m6805/6805ops.c
r19934	r19935
13	13
14	14	*/
15	15
16		#define OP_HANDLER(_name) INLINE void _name (m6805_Regs* cpustate)
	16	#define OP_HANDLER(_name) void m6805_base_device::_name()
	17	#define DERIVED_OP_HANDLER(_arch,_name) void _arch##_device::_name()
17	18
18		#define OP_HANDLER_BIT(_name) ~~INLINE~~ void ~~_na~~m~~e (m~~6805_~~Reg~~s* c~~pust~~ate, UINT8 bit)
	19	#define OP_HANDLER_BIT(_name) void m6805_base_device::_name(UINT8 bit)
19	20
20	21	OP_HANDLER( illegal )
21	22	{
r19934	r19935
158	159	/* $2e BIL relative ---- */
159	160	OP_HANDLER( bil )
160	161	{
161		if(SUBTYPE==SUBTYPE_HD63705)
162		{
163		BRANCH( cpustate->nmi_state!=CLEAR_LINE );
164		}
165		else
166		{
167		BRANCH( cpustate->irq_state[0]!=CLEAR_LINE );
168		}
	162	BRANCH(m_irq_state[0] != CLEAR_LINE);
169	163	}
170	164
	165	DERIVED_OP_HANDLER( hd63705, bil )
	166	{
	167	BRANCH(m_nmi_state != CLEAR_LINE);
	168	}
	169
171	170	/* $2f BIH relative ---- */
172	171	OP_HANDLER( bih )
173	172	{
174		if(SUBTYPE==SUBTYPE_HD63705)
175		{
176		BRANCH( cpustate->nmi_state==CLEAR_LINE );
177		}
178		else
179		{
180		BRANCH( cpustate->irq_state[0]==CLEAR_LINE );
181		}
	173	BRANCH(m_irq_state[0] == CLEAR_LINE);
182	174	}
183	175
	176	DERIVED_OP_HANDLER( hd63705, bih )
	177	{
	178	BRANCH(m_nmi_state == CLEAR_LINE);
	179	}
	180
184	181	/* $30 NEG direct -*** */
185	182	OP_HANDLER( neg_di )
186	183	{
r19934	r19935
789	786	PULLBYTE(CC);
790	787	PULLBYTE(A);
791	788	PULLBYTE(X);
792		PULLWORD(pPC);
	789	PULLWORD(m_pc);
793	790	#if IRQ_LEVEL_DETECT
794		if( m6805.irq_state != CLEAR_LINE && (CC & IFLAG) == 0 )
795		m6805.pending_interrupts \|= M6805_INT_IRQ;
	791	if( m_irq_state != CLEAR_LINE && (CC & IFLAG) == 0 )
	792	{
	793	m_pending_interrupts \|= M6805_INT_IRQ;
	794	}
796	795	#endif
797	796	}
798	797
799	798	/* $81 RTS inherent ---- */
800	799	OP_HANDLER( rts )
801	800	{
802		PULLWORD(pPC);
	801	PULLWORD(m_pc);
803	802	}
804	803
805	804	/* $82 ILLEGAL */
r19934	r19935
807	806	/* $83 SWI absolute indirect ---- */
808	807	OP_HANDLER( swi )
809	808	{
810		PUSHWORD(cpustate->pc);
811		PUSHBYTE(cpustate->x);
812		PUSHBYTE(cpustate->a);
813		PUSHBYTE(cpustate->cc);
	809	PUSHWORD(m_pc);
	810	PUSHBYTE(m_x);
	811	PUSHBYTE(m_a);
	812	PUSHBYTE(m_cc);
814	813	SEI;
815		~~if(SUBTYPE==SUBTYPE_HD63705)~~ RM16( ~~cpustate,~~ 0x1ff~~a, &pPC ); else RM16( cpustate, 0x~~fffc, &pPC );
	814	RM16(0xfffc, &m_pc);
816	815	}
817	816
	817	DERIVED_OP_HANDLER( hd63705, swi )
	818	{
	819	PUSHWORD(m_pc);
	820	PUSHBYTE(m_x);
	821	PUSHBYTE(m_a);
	822	PUSHBYTE(m_cc);
	823	SEI;
	824	RM16(0x1ffa, &m_pc);
	825	}
818	826	/* $84 ILLEGAL */
819	827
820	828	/* $85 ILLEGAL */
r19934	r19935
1009	1017	{
1010	1018	UINT8 t;
1011	1019	IMMBYTE(t);
1012		PUSHWORD(~~cpustate->~~pc);
	1020	PUSHWORD(m_pc);
1013	1021	PC += SIGNED(t);
1014	1022	}
1015	1023
r19934	r19935
1157	1165	OP_HANDLER( jsr_di )
1158	1166	{
1159	1167	DIRECT;
1160		PUSHWORD(~~cpustate->~~pc);
	1168	PUSHWORD(m_pc);
1161	1169	PC = EA;
1162	1170	}
1163	1171
r19934	r19935
1312	1320	OP_HANDLER( jsr_ex )
1313	1321	{
1314	1322	EXTENDED;
1315		PUSHWORD(~~cpustate->~~pc);
	1323	PUSHWORD(m_pc);
1316	1324	PC = EA;
1317	1325	}
1318	1326
r19934	r19935
1467	1475	OP_HANDLER( jsr_ix2 )
1468	1476	{
1469	1477	INDEXED2;
1470		PUSHWORD(~~cpustate->~~pc);
	1478	PUSHWORD(m_pc);
1471	1479	PC = EA;
1472	1480	}
1473	1481
r19934	r19935
1622	1630	OP_HANDLER( jsr_ix1 )
1623	1631	{
1624	1632	INDEXED1;
1625		PUSHWORD(~~cpustate->~~pc);
	1633	PUSHWORD(m_pc);
1626	1634	PC = EA;
1627	1635	}
1628	1636
r19934	r19935
1777	1785	OP_HANDLER( jsr_ix )
1778	1786	{
1779	1787	INDEXED;
1780		PUSHWORD(~~cpustate->~~pc);
	1788	PUSHWORD(m_pc);
1781	1789	PC = EA;
1782	1790	}
1783	1791

trunk/src/emu/cpu/m6805/m6805.h
r19934	r19935
5	5	#ifndef __M6805_H__
6	6	#define __M6805_H__
7	7
	8	//**************************************************************************
	9	// TYPE DEFINITIONS
	10	//**************************************************************************
8	11
	12	class m6805_device;
	13
	14	// device type definition
	15	extern const device_type M6805;
	16	extern const device_type M68HC05EG;
	17	extern const device_type M68705;
	18	extern const device_type HD63705;
	19
	20	// ======================> m6805_base_device
	21
	22	// Used by core CPU interface
	23	class m6805_base_device : public cpu_device
	24	{
	25	public:
	26	// construction/destruction
	27	m6805_base_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock, const device_type type, const char *name, UINT32 addr_width);
	28
	29	protected:
	30	// device-level overrides
	31	virtual void device_start();
	32	virtual void device_reset();
	33
	34	// device_execute_interface overrides
	35	virtual UINT32 execute_min_cycles() const;
	36	virtual UINT32 execute_max_cycles() const;
	37	virtual UINT32 execute_input_lines() const;
	38	virtual void execute_run();
	39	virtual void execute_set_input(int inputnum, int state) = 0;
	40	virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const;
	41	virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const;
	42
	43	// device_memory_interface overrides
	44	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
	45
	46	// device_disasm_interface overrides
	47	virtual UINT32 disasm_min_opcode_bytes() const;
	48	virtual UINT32 disasm_max_opcode_bytes() const;
	49	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	50
	51	// device_state_interface overrides
	52	virtual void state_string_export(const device_state_entry &entry, astring &string);
	53
	54	private:
	55	// opcode/condition tables
	56	static const UINT8 m_flags8i[256];
	57	static const UINT8 m_flags8d[256];
	58	static const UINT8 m_cycles1[256];
	59
	60	protected:
	61	void rd_s_handler_b(UINT8 *b);
	62	void rd_s_handler_w(PAIR *p);
	63	void wr_s_handler_b(UINT8 *b);
	64	void wr_s_handler_w(PAIR *p);
	65	void RM16(UINT32 addr, PAIR *p);
	66
	67	void brset(UINT8 bit);
	68	void brclr(UINT8 bit);
	69	void bset(UINT8 bit);
	70	void bclr(UINT8 bit);
	71
	72	void bra();
	73	void brn();
	74	void bhi();
	75	void bls();
	76	void bcc();
	77	void bcs();
	78	void bne();
	79	void beq();
	80	void bhcc();
	81	void bhcs();
	82	void bpl();
	83	void bmi();
	84	void bmc();
	85	void bms();
	86	virtual void bil();
	87	virtual void bih();
	88	void bsr();
	89
	90	void neg_di();
	91	void com_di();
	92	void lsr_di();
	93	void ror_di();
	94	void asr_di();
	95	void lsl_di();
	96	void rol_di();
	97	void dec_di();
	98	void inc_di();
	99	void tst_di();
	100	void clr_di();
	101
	102	void nega();
	103	void coma();
	104	void lsra();
	105	void rora();
	106	void asra();
	107	void lsla();
	108	void rola();
	109	void deca();
	110	void inca();
	111	void tsta();
	112	void clra();
	113
	114	void negx();
	115	void comx();
	116	void lsrx();
	117	void rorx();
	118	void asrx();
	119	void aslx();
	120	void lslx();
	121	void rolx();
	122	void decx();
	123	void incx();
	124	void tstx();
	125	void clrx();
	126
	127	void neg_ix1();
	128	void com_ix1();
	129	void lsr_ix1();
	130	void ror_ix1();
	131	void asr_ix1();
	132	void lsl_ix1();
	133	void rol_ix1();
	134	void dec_ix1();
	135	void inc_ix1();
	136	void tst_ix1();
	137	void clr_ix1();
	138
	139	void neg_ix();
	140	void com_ix();
	141	void lsr_ix();
	142	void ror_ix();
	143	void asr_ix();
	144	void lsl_ix();
	145	void rol_ix();
	146	void dec_ix();
	147	void inc_ix();
	148	void tst_ix();
	149	void clr_ix();
	150
	151	void rti();
	152	void rts();
	153	virtual void swi();
	154
	155	void tax();
	156	void txa();
	157
	158	void rsp();
	159	void nop();
	160
	161	void suba_im();
	162	void cmpa_im();
	163	void sbca_im();
	164	void cpx_im();
	165	void anda_im();
	166	void bita_im();
	167	void lda_im();
	168	void eora_im();
	169	void adca_im();
	170	void ora_im();
	171	void adda_im();
	172
	173	void ldx_im();
	174	void suba_di();
	175	void cmpa_di();
	176	void sbca_di();
	177	void cpx_di();
	178	void anda_di();
	179	void bita_di();
	180	void lda_di();
	181	void sta_di();
	182	void eora_di();
	183	void adca_di();
	184	void ora_di();
	185	void adda_di();
	186	void jmp_di();
	187	void jsr_di();
	188	void ldx_di();
	189	void stx_di();
	190	void suba_ex();
	191	void cmpa_ex();
	192	void sbca_ex();
	193	void cpx_ex();
	194	void anda_ex();
	195	void bita_ex();
	196	void lda_ex();
	197	void sta_ex();
	198	void eora_ex();
	199	void adca_ex();
	200	void ora_ex();
	201	void adda_ex();
	202	void jmp_ex();
	203	void jsr_ex();
	204	void ldx_ex();
	205	void stx_ex();
	206	void suba_ix2();
	207	void cmpa_ix2();
	208	void sbca_ix2();
	209	void cpx_ix2();
	210	void anda_ix2();
	211	void bita_ix2();
	212	void lda_ix2();
	213	void sta_ix2();
	214	void eora_ix2();
	215	void adca_ix2();
	216	void ora_ix2();
	217	void adda_ix2();
	218	void jmp_ix2();
	219	void jsr_ix2();
	220	void ldx_ix2();
	221	void stx_ix2();
	222	void suba_ix1();
	223	void cmpa_ix1();
	224	void sbca_ix1();
	225	void cpx_ix1();
	226	void anda_ix1();
	227	void bita_ix1();
	228	void lda_ix1();
	229	void sta_ix1();
	230	void eora_ix1();
	231	void adca_ix1();
	232	void ora_ix1();
	233	void adda_ix1();
	234	void jmp_ix1();
	235	void jsr_ix1();
	236	void ldx_ix1();
	237	void stx_ix1();
	238	void suba_ix();
	239	void cmpa_ix();
	240	void sbca_ix();
	241	void cpx_ix();
	242	void anda_ix();
	243	void bita_ix();
	244	void lda_ix();
	245	void sta_ix();
	246	void eora_ix();
	247	void adca_ix();
	248	void ora_ix();
	249	void adda_ix();
	250	void jmp_ix();
	251	void jsr_ix();
	252	void ldx_ix();
	253	void stx_ix();
	254
	255	void illegal();
	256
	257	virtual void interrupt();
	258	virtual void interrupt_vector();
	259
	260	const char *m_tag;
	261
	262	// address spaces
	263	const address_space_config m_program_config;
	264
	265	// CPU registers
	266	PAIR m_ea; /* effective address */
	267
	268	UINT32 m_sp_mask; /* Stack pointer address mask */
	269	UINT32 m_sp_low; /* Stack pointer low water mark (or floor) */
	270	PAIR m_pc; /* Program counter */
	271	PAIR m_s; /* Stack pointer */
	272	UINT8 m_a; /* Accumulator */
	273	UINT8 m_x; /* Index register */
	274	UINT8 m_cc; /* Condition codes */
	275
	276	UINT16 m_pending_interrupts; /* MB */
	277
	278	int m_irq_state[9]; /* KW Additional lines for HD63705 */
	279	int m_nmi_state;
	280
	281	// other internal states
	282	int m_icount;
	283
	284	// address spaces
	285	address_space *m_program;
	286	direct_read_data *m_direct;
	287	};
	288
	289	// ======================> m6805_device
	290
	291	class m6805_device : public m6805_base_device
	292	{
	293	public:
	294	// construction/destruction
	295	m6805_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	296	: m6805_base_device(mconfig, tag, owner, clock, M6805, "M6805", 12) { }
	297
	298	protected:
	299	virtual void execute_set_input(int inputnum, int state);
	300	};
	301
	302	// ======================> m68hc05eg_device
	303
	304	class m68hc05eg_device : public m6805_base_device
	305	{
	306	public:
	307	// construction/destruction
	308	m68hc05eg_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	309	: m6805_base_device(mconfig, tag, owner, clock, M68HC05EG, "M68HC05EG", 13) { }
	310
	311	protected:
	312	// device-level overrides
	313	virtual void device_reset();
	314
	315	virtual void execute_set_input(int inputnum, int state);
	316
	317	virtual void interrupt_vector();
	318	};
	319
	320	// ======================> m68705_device
	321
	322	class m68705_device : public m6805_base_device
	323	{
	324	public:
	325	// construction/destruction
	326	m68705_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	327	: m6805_base_device(mconfig, tag, owner, clock, M68705, "M68705", 12) { }
	328
	329	protected:
	330	// device-level overrides
	331	virtual void device_reset();
	332
	333	virtual void execute_set_input(int inputnum, int state);
	334
	335	virtual void interrupt();
	336	};
	337
	338	// ======================> hd63705_device
	339
	340	class hd63705_device : public m6805_base_device
	341	{
	342	public:
	343	// construction/destruction
	344	hd63705_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	345	: m6805_base_device(mconfig, tag, owner, clock, HD63705, "HD63705", 16) { }
	346
	347	protected:
	348	// device-level overrides
	349	virtual void device_reset();
	350
	351	virtual void execute_set_input(int inputnum, int state);
	352
	353	virtual void interrupt_vector();
	354
	355	// opcodes
	356	virtual void bil();
	357	virtual void bih();
	358	virtual void swi();
	359	};
	360
9	361	enum { M6805_PC=1, M6805_S, M6805_CC, M6805_A, M6805_X, M6805_IRQ_STATE };
10	362
11	363	#define M6805_IRQ_LINE 0
12	364
13		DECLARE_LEGACY_CPU_DEVICE(M6805, m6805);
14
15	365	/****************************************************************************
16	366	* 68HC05EG section
17	367	****************************************************************************/
r19934	r19935
20	370	#define M68HC05EG_INT_TIMER (M6805_IRQ_LINE+1)
21	371	#define M68HC05EG_INT_CPI (M6805_IRQ_LINE+2)
22	372
23		DECLARE_LEGACY_CPU_DEVICE(M68HC05EG, m68hc05eg);
24
25	373	/****************************************************************************
26	374	* 68705 section
27	375	****************************************************************************/
	376
28	377	#define M68705_A M6805_A
29	378	#define M68705_PC M6805_PC
30	379	#define M68705_S M6805_S
r19934	r19935
36	385	#define M68705_IRQ_LINE M6805_IRQ_LINE
37	386	#define M68705_INT_TIMER 0x01
38	387
39		DECLARE_LEGACY_CPU_DEVICE(M68705, m68705);
40
41	388	/****************************************************************************
42	389	* HD63705 section
43	390	****************************************************************************/
	391
44	392	#define HD63705_A M6805_A
45	393	#define HD63705_PC M6805_PC
46	394	#define HD63705_S M6805_S
r19934	r19935
63	411	#define HD63705_INT_ADCONV 0x07
64	412	#define HD63705_INT_NMI 0x08
65	413
66		DECLARE_LEGACY_CPU_DEVICE(HD63705, hd63705);
67
68	414	CPU_DISASSEMBLE( m6805 );
69	415
70	416	#endif /* __M6805_H__ */

trunk/src/emu/cpu/m6809/m6809.h
r19934	r19935
30	30	extern const device_type M6809;
31	31	extern const device_type M6809E;
32	32
33		// ======================> m6809_device
	33	// ======================> m6809_base_device
34	34
35	35	// Used by core CPU interface
36	36	class m6809_base_device : public cpu_device,
r19934	r19935
114	114
115	115	int m_extra_cycles; /* cycles used up by interrupts */
116	116
117		device_irq_acknowledge_callback m_irq_callback;
118
119	117	PAIR m_ea; /* effective address */
120	118
121	119	// other internal states

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