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r19876 Friday 28th December, 2012 at 03:37:12 UTC by R. Belmont
Z800x: Fixed some bugs in non-segmented mode [Christian Grössler] (MESS) M20: Added -ramsize support. [Christian Grössler]

[src/emu/cpu/z8000]	z8000.c z8000ops.c
[src/mess/drivers]	m20.c

trunk/src/emu/cpu/z8000/z8000.c

r19875	r19876
108	108
109	109	INLINE int segmented_mode(z8000_state *cpustate)
110	110	{
111		if (cpustate->device->type() == Z8001 && (cpustate->fcw & F_SEG))
112		return 1;
113		return 0;
	111	if (cpustate->device->type() == Z8001 && (cpustate->fcw & F_SEG))
	112	return 1;
	113	return 0;
114	114	}
115	115
116	116	INLINE UINT32 addr_add(z8000_state *cpustate, UINT32 addr, UINT32 addend)
117	117	{
118		if (segmented_mode(cpustate))
119		return (addr & 0xffff0000) | ((addr + addend) & 0xffff);
120		else
121		return (addr + addend) & 0xffff;
	118	return (addr & 0xffff0000) | ((addr + addend) & 0xffff);
122	119	}
123	120
124	121	INLINE UINT32 addr_sub(z8000_state *cpustate, UINT32 addr, UINT32 subtrahend)
125	122	{
126		if (segmented_mode(cpustate))
127		return (addr & 0xffff0000) | ((addr - subtrahend) & 0xffff);
128		else
129		return (addr - subtrahend) & 0xffff;
	123	return (addr & 0xffff0000) | ((addr - subtrahend) & 0xffff);
130	124	}
131	125
132	126	/* conversion table for Z8000 DAB opcode */

trunk/src/emu/cpu/z8000/z8000ops.c

r19875	r19876
4547	4547	CHECK_PRIVILEGED_INSTR();
4548	4548	GET_ADDR(OP1);
4549	4549	UINT16 fcw;
4550		printf("LDPS from 0x%x: old pc: 0x%x\n", addr, cpustate->pc);
4551		if (segmented_mode(cpustate)) {
4552		fcw = RDMEM_W(cpustate, AS_DATA,  addr + 2);
4553		set_pc(cpustate, segmented_addr(RDMEM_L(cpustate, AS_DATA, addr + 4)));
4554		}
4555		else {
4556		fcw = RDMEM_W(cpustate, AS_DATA, addr);
4557		set_pc(cpustate, RDMEM_W(cpustate, AS_DATA, (UINT16)(addr + 2)));
4558		}
4559		if ((fcw ^ cpustate->fcw) & F_SEG) printf("ldps 2 (0x%05x): changing from %ssegmented mode to %ssegmented mode\n", cpustate->pc, (fcw & F_SEG) ? "non-" : "", (fcw & F_SEG) ? "" : "non-");
	4550	if (segmented_mode(cpustate)) {
	4551	fcw = RDMEM_W(cpustate, AS_DATA,  addr + 2);
	4552	set_pc(cpustate, segmented_addr(RDMEM_L(cpustate, AS_DATA, addr + 4)));
	4553	}
	4554	else {
	4555	fcw = RDMEM_W(cpustate, AS_DATA, addr);
	4556	set_pc(cpustate, RDMEM_W(cpustate, AS_DATA, (UINT16)(addr + 2)));
	4557	}
4560	4558	CHANGE_FCW(cpustate, fcw); /* check for user/system mode change */
4561		//printf("LDPS: new pc: 0x%x\n", cpustate->pc);
4562	4559	}
4563	4560
4564	4561	/******************************************

trunk/src/mess/drivers/m20.c

r19875	r19876
17	17	Square      Test ROM
18	18	4 vertical lines    CPU call or trap instructions failed
19	19	Diamond     Test system RAM
20		EC0     8255 parallel interface IC test failed
21		EC1     6845 CRT controller IC test failed
22		EC2     1797 floppy disk controller chip failed
23		EC3     8253 timer IC failed
24		EC4     8251 keyboard interface failed
25		EC5     8251 keyboard test failed
26		EC6     8259 PIC IC test failed
27		EK0     Keyboard did not respond
28		EK1     Keyboard responds, but self test failed
29		ED1     Disk drive 1 test failed
30		ED0     Disk drive 0 test failed
31		EI0     Non-vectored interrupt error
32		EI1     Vectored interrupt error
	20	E C0     8255 parallel interface IC test failed
	21	E C1     6845 CRT controller IC test failed
	22	E C2     1797 floppy disk controller chip failed
	23	E C3     8253 timer IC failed
	24	E C4     8251 keyboard interface failed
	25	E C5     8251 keyboard test failed
	26	E C6     8259 PIC IC test failed
	27	E K0     Keyboard did not respond
	28	E K1     Keyboard responds, but self test failed
	29	E D1     Disk drive 1 test failed
	30	E D0     Disk drive 0 test failed
	31	E I0     Non-vectored interrupt error
	32	E I1     Vectored interrupt error
33	33
34	34	*************************************************************************************************/
35	35
r19875	r19876
38	38	#include "cpu/z8000/z8000.h"
39	39	#include "cpu/i86/i86.h"
40	40	#include "video/mc6845.h"
	41	#include "machine/ram.h"
41	42	#include "machine/wd_fdc.h"
42	43	#include "machine/i8251.h"
43	44	#include "machine/i8255.h"
r19875	r19876
53	54	m20_state(const machine_config &mconfig, device_type type, const char *tag)
54	55	: driver_device(mconfig, type, tag) ,
55	56	m_maincpu(*this, "maincpu"),
	57	m_ram(*this, RAM_TAG),
56	58	m_kbdi8251(*this, "i8251_1"),
57	59	m_ttyi8251(*this, "i8251_2"),
58	60	m_i8255(*this, "ppi8255"),
r19875	r19876
63	65	m_p_videoram(*this, "p_videoram"){ }
64	66
65	67	required_device<z8001_device> m_maincpu;
	68	required_device<ram_device> m_ram;
66	69	required_device<i8251_device> m_kbdi8251;
67	70	required_device<i8251_device> m_ttyi8251;
68	71	required_device<i8255_device> m_i8255;
r19875	r19876
91	94	private:
92	95	bool m_kbrecv_in_progress;
93	96	int m_kbrecv_bitcount;
	97	offs_t m_memsize;
94	98	UINT16 m_kbrecv_data;
95	99	UINT8 m_port21;
	100	void install_memory();
96	101
97	102	public:
98	103	DECLARE_DRIVER_INIT(m20);
r19875	r19876
281	286	m_maincpu->set_input_line(0, state ? HOLD_LINE /*ASSERT_LINE*/ : CLEAR_LINE);
282	287	}
283	288
284		/* from the M20 hardware reference manual:
285		M20 memory is configured according to the following scheme:
286		Segment   Contents
287		0   PCOS kernel
288		1   Basic interpreter and PCOS utilities
289		2   PCOS variables, Basic stock and tables, user memory
290		3   Screen bitmap
291		4   Diagnostics and Bootstrap
	289
	290	/* Memory map description (by courtesy of Dwight Elvey)
	291
	292	DRAM0 = motherboard (128K)
	293	DRAM1 = first slot from keyboard end
	294	DRAM2 = second slot from keyboard end
	295	DRAM3 = third slot from keyboard end
	296	SRAM0 = memory window for expansion slot
	297	ROM0  = ROM
	298
	299	Expansion cards are either 32K or 128K. They cannot be mixed, all installed
	300	cards need to be the same type.
	301
	302	B/W, 32K cards, 3 cards => 224K of memory:
	303	<0>0000 D DRAM0  4000 I DRAM0  4000  <8>0000 D DRAM0 18000 I DRAM0  8000
	304	<0>4000 D DRAM1  4000 I DRAM0  8000  <8>4000 D DRAM0 1C000 I DRAM0  C000
	305	<0>8000 D DRAM2  0000 I DRAM0  C000  <8>8000 D DRAM2  4000 I DRAM1  4000
	306	<0>C000 D DRAM2  4000 I DRAM0 10000  <8>C000 D DRAM3  0000 I DRAM2  0000
	307	<1>0000 D DRAM0 14000 I DRAM0  8000  <9>0000 D DRAM0 18000 I DRAM0 18000
	308	<1>4000 D DRAM0 18000 I DRAM0  C000  <9>4000 D DRAM0 1C000 I DRAM0 1C000
	309	<1>8000 D DRAM0 1C000 I DRAM0 10000  <9>8000 D DRAM2  4000 I DRAM2  4000
	310	<1>C000 D DRAM1  0000 I None         <9>C000 D DRAM3  0000 I DRAM3  0000
	311	<2>0000 D DRAM0 14000 I DRAM0 14000  <A>0000 D DRAM0  8000 I DRAM0  8000
	312	<2>4000 D DRAM0 18000 I DRAM0 18000  <A>4000 D DRAM0  C000 I DRAM0  C000
	313	<2>8000 D DRAM0 1C000 I DRAM0 1C000  <A>8000 D DRAM1  4000 I DRAM1  4000
	314	<2>C000 D DRAM1  0000 I DRAM1  0000  <A>C000 D DRAM2  0000 I DRAM2  0000
	315	<3>0000 D DRAM0  0000 I DRAM0  0000  <B>0000 D DRAM3  4000 I DRAM3  4000
	316	<3>4000 D None        I None         <B>4000 D None        I None
	317	<3>8000 D None        I None         <B>8000 D None        I None
	318	<3>C000 D None        I None         <B>C000 D None        I None
	319	<4>0000 D  ROM0  0000 I  ROM0  0000  <C>0000 D DRAM3  4000 I None
	320	<4>4000 D DRAM3  0000 I  ROM0 10000  <C>4000 D None        I None
	321	<4>8000 D DRAM3  4000 I  ROM0 14000  <C>8000 D None        I None
	322	<4>C000 D None        I  ROM0 18000  <C>C000 D None        I None
	323	<5>0000 D DRAM0  8000 I  ROM0 10000  <D>0000 D None        I None
	324	<5>4000 D DRAM0  C000 I  ROM0 14000  <D>4000 D None        I None
	325	<5>8000 D DRAM0 10000 I  ROM0 18000  <D>8000 D None        I None
	326	<5>C000 D SRAM0  0000 I SRAM0  0000  <D>C000 D None        I None
	327	<6>0000 D DRAM0  8000 I DRAM0  8000  <E>0000 D None        I None
	328	<6>4000 D DRAM0  C000 I DRAM0  C000  <E>4000 D None        I None
	329	<6>8000 D DRAM0 10000 I DRAM0 10000  <E>8000 D None        I None
	330	<6>C000 D None        I None         <E>C000 D None        I None
	331	<7>0000 D  ROM0  0000 I  ROM0  0000  <F>0000 D None        I None
	332	<7>4000 D  ROM0 10000 I  ROM0 10000  <F>4000 D None        I None
	333	<7>8000 D  ROM0 14000 I  ROM0 14000  <F>8000 D None        I None
	334	<7>C000 D  ROM0 18000 I  ROM0 18000  <F>C000 D None        I None
	335
	336	B/W, 128K cards, 3 cards => 512K of memory:
	337	<0>0000 D DRAM0  4000 I DRAM0  4000  <8>0000 D DRAM0 18000 I DRAM0  8000
	338	<0>4000 D DRAM1  4000 I DRAM0  8000  <8>4000 D DRAM0 1C000 I DRAM0  C000
	339	<0>8000 D DRAM2  0000 I DRAM0  C000  <8>8000 D DRAM1  C000 I DRAM1  4000
	340	<0>C000 D DRAM2  4000 I DRAM0 10000  <8>C000 D DRAM1 10000 I DRAM1  8000
	341	<1>0000 D DRAM0 14000 I DRAM0  8000  <9>0000 D DRAM0 18000 I DRAM0 18000
	342	<1>4000 D DRAM0 18000 I DRAM0  C000  <9>4000 D DRAM0 1C000 I DRAM0 1C000
	343	<1>8000 D DRAM0 1C000 I DRAM0 10000  <9>8000 D DRAM1  C000 I DRAM1  C000
	344	<1>C000 D DRAM1  0000 I None         <9>C000 D DRAM1 10000 I DRAM1 10000
	345	<2>0000 D DRAM0 14000 I DRAM0 14000  <A>0000 D DRAM0  8000 I DRAM0  8000
	346	<2>4000 D DRAM0 18000 I DRAM0 18000  <A>4000 D DRAM0  C000 I DRAM0  C000
	347	<2>8000 D DRAM0 1C000 I DRAM0 1C000  <A>8000 D DRAM1  4000 I DRAM1  4000
	348	<2>C000 D DRAM1  0000 I DRAM1  0000  <A>C000 D DRAM1  8000 I DRAM1  8000
	349	<3>0000 D DRAM0  0000 I DRAM0  0000  <B>0000 D DRAM1 14000 I DRAM1 14000
	350	<3>4000 D None        I None         <B>4000 D DRAM1 18000 I DRAM1 18000
	351	<3>8000 D None        I None         <B>8000 D DRAM1 1C000 I DRAM1 1C000
	352	<3>C000 D None        I None         <B>C000 D DRAM2  0000 I DRAM2  0000
	353	<4>0000 D  ROM0  0000 I  ROM0  0000  <C>0000 D DRAM2  4000 I DRAM2  4000
	354	<4>4000 D DRAM3  0000 I None         <C>4000 D DRAM2  8000 I DRAM2  8000
	355	<4>8000 D DRAM3  4000 I None         <C>8000 D DRAM2  C000 I DRAM2  C000
	356	<4>C000 D None        I None         <C>C000 D DRAM2 10000 I DRAM2 10000
	357	<5>0000 D DRAM0  8000 I  ROM0 10000  <D>0000 D DRAM2 14000 I DRAM2 14000
	358	<5>4000 D DRAM0  C000 I  ROM0 14000  <D>4000 D DRAM2 18000 I DRAM2 18000
	359	<5>8000 D DRAM0 10000 I  ROM0 18000  <D>8000 D DRAM2 1C000 I DRAM2 1C000
	360	<5>C000 D SRAM0  0000 I SRAM0  0000  <D>C000 D DRAM3  0000 I DRAM3  0000
	361	<6>0000 D DRAM0  8000 I DRAM0  8000  <E>0000 D DRAM3  4000 I DRAM3  4000
	362	<6>4000 D DRAM0  C000 I DRAM0  C000  <E>4000 D DRAM3  8000 I DRAM3  8000
	363	<6>8000 D DRAM0 10000 I DRAM0 10000  <E>8000 D DRAM3  C000 I DRAM3  C000
	364	<6>C000 D None        I None         <E>C000 D DRAM3 10000 I DRAM3 10000
	365	<7>0000 D  ROM0  0000 I  ROM0  0000  <F>0000 D DRAM3 14000 I DRAM3 14000
	366	<7>4000 D  ROM0 10000 I  ROM0 10000  <F>4000 D DRAM3 18000 I DRAM3 18000
	367	<7>8000 D  ROM0 14000 I  ROM0 14000  <F>8000 D DRAM3 1C000 I DRAM3 1C000
	368	<7>C000 D  ROM0 18000 I  ROM0 18000  <F>C000 D DRAM3  0000 I DRAM3  0000
292	369	*/
293		#if 0
294		static ADDRESS_MAP_START(m20_mem, AS_PROGRAM, 16, m20_state)
	370
	371
	372	static ADDRESS_MAP_START(m20_program_mem, AS_PROGRAM, 16, m20_state)
295	373	ADDRESS_MAP_UNMAP_HIGH
296		AM_RANGE( 0x00000, 0x01fff ) AM_RAM AM_SHARE("mainram")
297		AM_RANGE( 0x02000, 0x0ffff ) AM_RAM
298		AM_RANGE( 0x10000, 0x1ffff ) AM_RAM
299		AM_RANGE( 0x20000, 0x2ffff ) AM_RAM
300		AM_RANGE( 0x30000, 0x33fff ) AM_RAM AM_SHARE("p_videoram")//base vram
301		AM_RANGE( 0x40000, 0x41fff ) AM_ROM AM_REGION("maincpu", 0x10000)
302		AM_RANGE( 0x44000, 0x4bfff ) AM_RAM
303		AM_RANGE( 0x50000, 0x5bfff ) AM_RAM
304		AM_RANGE( 0x60000, 0x6ffff ) AM_RAM
305		AM_RANGE( 0x70000, 0x77fff ) AM_RAM
306		AM_RANGE( 0x80000, 0x8ffff ) AM_RAM
307		AM_RANGE( 0x90000, 0x9ffff ) AM_RAM
308		AM_RANGE( 0xa0000, 0xaffff ) AM_RAM
309		AM_RANGE( 0xb0000, 0xb3fff ) AM_RAM
310		AM_RANGE( 0xc0000, 0xc3fff ) AM_RAM
311		//  AM_RANGE( 0x34000, 0x37fff ) AM_RAM //extra vram for color mode
	374	AM_RANGE( 0x30000, 0x33fff ) AM_RAM AM_SHARE("p_videoram")
	375	AM_RANGE( 0x40000, 0x41fff ) AM_ROM AM_REGION("maincpu", 0x00000)
312	376	ADDRESS_MAP_END
313		#endif
314	377
315		static ADDRESS_MAP_START(m20_program_mem, AS_PROGRAM, 16, m20_state)
	378	static ADDRESS_MAP_START(m20_data_mem, AS_DATA, 16, m20_state)
316	379	ADDRESS_MAP_UNMAP_HIGH
317		AM_RANGE( 0x00000, 0x03fff ) AM_RAM AM_SHARE("dram0_4000") //AM_SHARE("mainram")
318		AM_RANGE( 0x04000, 0x07fff ) AM_RAM AM_SHARE("dram0_8000")
319		AM_RANGE( 0x08000, 0x0bfff ) AM_RAM AM_SHARE("dram0_c000")
320		AM_RANGE( 0x0c000, 0x0ffff ) AM_RAM AM_SHARE("dram0_10000")
	380	AM_RANGE( 0x30000, 0x33fff ) AM_RAM AM_SHARE("p_videoram")
	381	AM_RANGE( 0x40000, 0x41fff ) AM_ROM AM_REGION("maincpu", 0x00000)
	382	ADDRESS_MAP_END
321	383
322		AM_RANGE( 0x10000, 0x13fff ) AM_RAM AM_SHARE("dram0_8000")
323		AM_RANGE( 0x14000, 0x17fff ) AM_RAM AM_SHARE("dram0_c000")
324		AM_RANGE( 0x18000, 0x1bfff ) AM_RAM AM_SHARE("dram0_10000")
325		//AM_RANGE( 0x1c000, 0x1ffff ) AM_RAM AM_SHARE("dram0_10000")
326	384
327		AM_RANGE( 0x20000, 0x23fff ) AM_RAM AM_SHARE("dram0_14000")
328		AM_RANGE( 0x24000, 0x27fff ) AM_RAM AM_SHARE("dram0_18000")
329		AM_RANGE( 0x28000, 0x2bfff ) AM_RAM AM_SHARE("dram0_1c000")
330		AM_RANGE( 0x2c000, 0x2ffff ) AM_RAM AM_SHARE("dram1_0000")
	385	void m20_state::install_memory()
	386	{
	387	m20_state *state = machine().driver_data<m20_state>();
331	388
332		AM_RANGE( 0x30000, 0x33fff ) AM_RAM AM_SHARE("p_videoram")
	389	m_memsize = m_ram->size();
	390	UINT8 *memptr = m_ram->pointer();
	391	address_space& pspace = machine().device("maincpu")->memory().space(AS_PROGRAM);
	392	address_space& dspace = machine().device("maincpu")->memory().space(AS_DATA);
333	393
334		AM_RANGE( 0x40000, 0x41fff ) AM_ROM AM_REGION("maincpu", 0x00000)
335		//AM_RANGE( 0x40000, 0x41fff ) AM_ROM AM_SHARE("maincpu")
	394	/* install mainboard memory (aka DRAM0) */
336	395
337		AM_RANGE( 0x60000, 0x63fff ) AM_RAM AM_SHARE("dram0_8000")
338		AM_RANGE( 0x64000, 0x67fff ) AM_RAM AM_SHARE("dram0_c000")
339		AM_RANGE( 0x68000, 0x6bfff ) AM_RAM AM_SHARE("dram0_10000")
	396	/* <0>0000 */
	397	pspace.install_readwrite_bank(0x0000, 0x3fff, 0x3fff, 0, "dram0_4000");
	398	dspace.install_readwrite_bank(0x0000, 0x3fff, 0x3fff, 0, "dram0_4000");
	399	/* <0>4000 */
	400	pspace.install_readwrite_bank(0x4000, 0x7fff, 0x3fff, 0, "dram0_8000");
	401	/* <0>8000 */
	402	pspace.install_readwrite_bank(0x8000, 0xbfff, 0x3fff, 0, "dram0_c000");
	403	/* <0>C000 */
	404	pspace.install_readwrite_bank(0xc000, 0xcfff, 0x3fff, 0, "dram0_10000");
	405	/* <1>0000 */
	406	pspace.install_readwrite_bank(0x10000, 0x13fff, 0x3fff, 0, "dram0_8000");
	407	dspace.install_readwrite_bank(0x10000, 0x13fff, 0x3fff, 0, "dram0_14000");
	408	/* <1>4000 */
	409	pspace.install_readwrite_bank(0x14000, 0x17fff, 0x3fff, 0, "dram0_c000");
	410	dspace.install_readwrite_bank(0x14000, 0x17fff, 0x3fff, 0, "dram0_18000");
	411	/* <1>8000 */
	412	pspace.install_readwrite_bank(0x18000, 0x1bfff, 0x3fff, 0, "dram0_10000");
	413	dspace.install_readwrite_bank(0x18000, 0x1bfff, 0x3fff, 0, "dram0_1c000");
	414	/* <1>c000 empty*/
	415	/* <2>0000 */
	416	pspace.install_readwrite_bank(0x20000, 0x23fff, 0x3fff, 0, "dram0_14000");
	417	dspace.install_readwrite_bank(0x20000, 0x23fff, 0x3fff, 0, "dram0_14000");
	418	/* <2>4000 */
	419	pspace.install_readwrite_bank(0x24000, 0x27fff, 0x3fff, 0, "dram0_18000");
	420	dspace.install_readwrite_bank(0x24000, 0x27fff, 0x3fff, 0, "dram0_18000");
	421	/* <2>8000 */
	422	pspace.install_readwrite_bank(0x28000, 0x28fff, 0x3fff, 0, "dram0_1c000");
	423	dspace.install_readwrite_bank(0x28000, 0x28fff, 0x3fff, 0, "dram0_1c000");
	424	/* <2>c000 empty*/
	425	/* <3>0000 (video buffer)
	426	pspace.install_readwrite_bank(0x30000, 0x33fff, 0x3fff, 0, "dram0_0000");
	427	dspace.install_readwrite_bank(0x30000, 0x33fff, 0x3fff, 0, "dram0_0000");
	428	*/
340	429
341		AM_RANGE( 0x80000, 0x83fff ) AM_RAM AM_SHARE("dram0_8000")
342		AM_RANGE( 0x84000, 0x87fff ) AM_RAM AM_SHARE("dram0_c000")
343		AM_RANGE( 0x88000, 0x8bfff ) AM_RAM AM_SHARE("dram1_4000")
344		AM_RANGE( 0x8c000, 0x8ffff ) AM_RAM AM_SHARE("dram2_0000")
	430	/* <5>0000 */
	431	dspace.install_readwrite_bank(0x50000, 0x53fff, 0x3fff, 0, "dram0_8000");
	432	/* <5>4000 */
	433	dspace.install_readwrite_bank(0x54000, 0x57fff, 0x3fff, 0, "dram0_c000");
	434	/* <5>8000 */
	435	dspace.install_readwrite_bank(0x58000, 0x5bfff, 0x3fff, 0, "dram0_10000");
	436	/* <5>c000 expansion bus */
	437	/* <6>0000 */
	438	pspace.install_readwrite_bank(0x60000, 0x63fff, 0x3fff, 0, "dram0_8000");
	439	dspace.install_readwrite_bank(0x60000, 0x63fff, 0x3fff, 0, "dram0_8000");
	440	/* <6>4000 */
	441	pspace.install_readwrite_bank(0x64000, 0x67fff, 0x3fff, 0, "dram0_c000");
	442	dspace.install_readwrite_bank(0x64000, 0x67fff, 0x3fff, 0, "dram0_c000");
	443	/* <6>8000 */
	444	pspace.install_readwrite_bank(0x68000, 0x6bfff, 0x3fff, 0, "dram0_10000");
	445	dspace.install_readwrite_bank(0x68000, 0x6bfff, 0x3fff, 0, "dram0_10000");
	446	/* <6>c000 empty*/
	447	/* segment <7> expansion ROM? */
	448	/* <8>0000 */
	449	pspace.install_readwrite_bank(0x80000, 0x83fff, 0x3fff, 0, "dram0_8000");
	450	dspace.install_readwrite_bank(0x80000, 0x83fff, 0x3fff, 0, "dram0_18000");
	451	/* <8>4000 */
	452	pspace.install_readwrite_bank(0x84000, 0x87fff, 0x3fff, 0, "dram0_c000");
	453	dspace.install_readwrite_bank(0x84000, 0x87fff, 0x3fff, 0, "dram0_1c000");
	454	/* <9>0000 */
	455	pspace.install_readwrite_bank(0x90000, 0x93fff, 0x3fff, 0, "dram0_18000");
	456	dspace.install_readwrite_bank(0x90000, 0x93fff, 0x3fff, 0, "dram0_18000");
	457	/* <9>4000 */
	458	pspace.install_readwrite_bank(0x94000, 0x97fff, 0x3fff, 0, "dram0_1c000");
	459	dspace.install_readwrite_bank(0x94000, 0x97fff, 0x3fff, 0, "dram0_1c000");
	460	/* <A>0000 */
	461	pspace.install_readwrite_bank(0xa0000, 0xa3fff, 0x3fff, 0, "dram0_8000");
	462	dspace.install_readwrite_bank(0xa0000, 0xa3fff, 0x3fff, 0, "dram0_8000");
	463	/* <A>4000 */
	464	pspace.install_readwrite_bank(0xa4000, 0xa7fff, 0x3fff, 0, "dram0_c000");
	465	dspace.install_readwrite_bank(0xa4000, 0xa7fff, 0x3fff, 0, "dram0_c000");
345	466
346		AM_RANGE( 0x90000, 0x93fff ) AM_RAM AM_SHARE("dram0_18000")
347		AM_RANGE( 0x94000, 0x97fff ) AM_RAM AM_SHARE("dram0_1c000")
348		AM_RANGE( 0x98000, 0x9bfff ) AM_RAM AM_SHARE("dram2_4000")
349		AM_RANGE( 0x9c000, 0x9ffff ) AM_RAM AM_SHARE("dram3_0000")
	467	//state->membank("dram0_0000")->set_base(memptr);
	468	state->membank("dram0_4000")->set_base(memptr + 0x4000);
	469	state->membank("dram0_8000")->set_base(memptr + 0x8000);
	470	state->membank("dram0_c000")->set_base(memptr + 0xc000);
	471	state->membank("dram0_10000")->set_base(memptr + 0x10000);
	472	state->membank("dram0_14000")->set_base(memptr + 0x14000);
	473	state->membank("dram0_18000")->set_base(memptr + 0x18000);
	474	state->membank("dram0_1c000")->set_base(memptr + 0x1c000);
350	475
351		AM_RANGE( 0xa0000, 0xa3fff ) AM_RAM AM_SHARE("dram0_8000")
352		AM_RANGE( 0xa4000, 0xa7fff ) AM_RAM AM_SHARE("dram0_c000")
353		AM_RANGE( 0xa8000, 0xabfff ) AM_RAM AM_SHARE("dram1_4000")
354		AM_RANGE( 0xac000, 0xaffff ) AM_RAM AM_SHARE("dram2_0000")
	476	if (m_memsize > 128 * 1024) {
355	477
356		AM_RANGE( 0xb0000, 0xb3fff ) AM_RAM AM_SHARE("dram3_4000")
	478	/* install memory expansions (DRAM1..DRAM3) */
357	479
358		ADDRESS_MAP_END
	480	if (m_memsize < 256 * 1024) {
359	481
360		static ADDRESS_MAP_START(m20_data_mem, AS_DATA, 16, m20_state)
361		ADDRESS_MAP_UNMAP_HIGH
	482	/* 32K expansion cards */
362	483
363		AM_RANGE( 0x00000, 0x03fff ) AM_RAM AM_SHARE("dram0_4000")
364		AM_RANGE( 0x04000, 0x07fff ) AM_RAM AM_SHARE("dram1_4000")
365		AM_RANGE( 0x08000, 0x0bfff ) AM_RAM AM_SHARE("dram2_0000")
366		AM_RANGE( 0x0c000, 0x0ffff ) AM_RAM AM_SHARE("dram2_4000")
	484	/* DRAM1, 32K */
367	485
368		AM_RANGE( 0x10000, 0x13fff ) AM_RAM AM_SHARE("dram0_14000")
369		AM_RANGE( 0x14000, 0x17fff ) AM_RAM AM_SHARE("dram0_18000")
370		AM_RANGE( 0x18000, 0x1bfff ) AM_RAM AM_SHARE("dram0_1c000")
371		AM_RANGE( 0x1c000, 0x1ffff ) AM_RAM AM_SHARE("dram1_0000")
	486	/* prog
	487	AM_RANGE( 0x2c000, 0x2ffff ) AM_RAM AM_SHARE("dram1_0000")
	488	AM_RANGE( 0x88000, 0x8bfff ) AM_RAM AM_SHARE("dram1_4000")
	489	AM_RANGE( 0xa8000, 0xabfff ) AM_RAM AM_SHARE("dram1_4000")
	490	*/
	491	pspace.install_readwrite_bank(0x2c000, 0x2ffff, 0x3fff, 0, "dram1_0000");
	492	pspace.install_readwrite_bank(0x88000, 0x8bfff, 0x3fff, 0, "dram1_4000");
	493	pspace.install_readwrite_bank(0xa8000, 0xaffff, 0x3fff, 0, "dram1_4000");
372	494
373		AM_RANGE( 0x20000, 0x23fff ) AM_RAM AM_SHARE("dram0_14000")
374		AM_RANGE( 0x24000, 0x27fff ) AM_RAM AM_SHARE("dram0_18000")
375		AM_RANGE( 0x28000, 0x2bfff ) AM_RAM AM_SHARE("dram0_1c000")
376		AM_RANGE( 0x2c000, 0x2ffff ) AM_RAM AM_SHARE("dram1_0000")
	495	/*
	496	data
	497	AM_RANGE( 0x04000, 0x07fff ) AM_RAM AM_SHARE("dram1_4000")
	498	AM_RANGE( 0x1c000, 0x1ffff ) AM_RAM AM_SHARE("dram1_0000")
	499	AM_RANGE( 0x2c000, 0x2ffff ) AM_RAM AM_SHARE("dram1_0000")
	500	AM_RANGE( 0xa8000, 0xabfff ) AM_RAM AM_SHARE("dram1_4000")
	501	*/
	502	dspace.install_readwrite_bank(0x4000, 0x7fff, 0x3fff, 0, "dram1_4000");
	503	dspace.install_readwrite_bank(0x1c000, 0x1ffff, 0x3fff, 0, "dram1_0000");
	504	dspace.install_readwrite_bank(0x2c000, 0x2ffff, 0x3fff, 0, "dram1_0000");
	505	dspace.install_readwrite_bank(0xa8000, 0xabfff, 0x3fff, 0, "dram1_4000");
377	506
378		AM_RANGE( 0x30000, 0x33fff ) AM_RAM AM_SHARE("p_videoram")
	507	state->membank("dram1_0000")->set_base(memptr + 0x20000);
	508	state->membank("dram1_4000")->set_base(memptr + 0x24000);
379	509
380		//AM_RANGE( 0x40000, 0x41fff ) AM_ROM AM_SHARE("maincpu")
381		AM_RANGE( 0x40000, 0x41fff ) AM_ROM AM_REGION("maincpu", 0x00000)
	510	if (m_memsize > 128 * 1024 + 32768) {
	511	/* DRAM2, 32K */
382	512
383		AM_RANGE( 0x44000, 0x47fff ) AM_RAM AM_SHARE("dram3_0000")
384		AM_RANGE( 0x48000, 0x4bfff ) AM_RAM AM_SHARE("dram3_4000")
	513	/* prog
	514	AM_RANGE( 0x8c000, 0x8ffff ) AM_RAM AM_SHARE("dram2_0000")
	515	AM_RANGE( 0x98000, 0x9bfff ) AM_RAM AM_SHARE("dram2_4000")
	516	AM_RANGE( 0xac000, 0xaffff ) AM_RAM AM_SHARE("dram2_0000")
	517	*/
	518	pspace.install_readwrite_bank(0x8c000, 0x8ffff, 0x3fff, 0, "dram2_0000");
	519	pspace.install_readwrite_bank(0x98000, 0x9bfff, 0x3fff, 0, "dram2_4000");
	520	pspace.install_readwrite_bank(0xac000, 0xaffff, 0x3fff, 0, "dram2_0000");
385	521
386		AM_RANGE( 0x50000, 0x53fff ) AM_RAM AM_SHARE("dram0_8000")
387		AM_RANGE( 0x54000, 0x57fff ) AM_RAM AM_SHARE("dram0_c000")
388		AM_RANGE( 0x58000, 0x5bfff ) AM_RAM AM_SHARE("dram0_10000")
	522	/* data
	523	AM_RANGE( 0x08000, 0x0bfff ) AM_RAM AM_SHARE("dram2_0000")
	524	AM_RANGE( 0x0c000, 0x0ffff ) AM_RAM AM_SHARE("dram2_4000")
	525	AM_RANGE( 0x88000, 0x8bfff ) AM_RAM AM_SHARE("dram2_4000")
	526	AM_RANGE( 0x98000, 0x9bfff ) AM_RAM AM_SHARE("dram2_4000")
	527	AM_RANGE( 0xac000, 0xaffff ) AM_RAM AM_SHARE("dram2_0000")
	528	*/
	529	dspace.install_readwrite_bank(0x8000, 0xbfff, 0x3fff, 0, "dram2_0000");
	530	dspace.install_readwrite_bank(0xc000, 0xffff, 0x3fff, 0, "dram2_4000");
	531	dspace.install_readwrite_bank(0x88000, 0x8bfff, 0x3fff, 0, "dram2_4000");
	532	dspace.install_readwrite_bank(0x98000, 0x9bfff, 0x3fff, 0, "dram2_4000");
	533	dspace.install_readwrite_bank(0xac000, 0xaffff, 0x3fff, 0, "dram2_0000");
389	534
390		AM_RANGE( 0x60000, 0x63fff ) AM_RAM AM_SHARE("dram0_8000")
391		AM_RANGE( 0x64000, 0x67fff ) AM_RAM AM_SHARE("dram0_c000")
392		AM_RANGE( 0x68000, 0x6bfff ) AM_RAM AM_SHARE("dram0_10000")
	535	state->membank("dram2_0000")->set_base(memptr + 0x28000);
	536	state->membank("dram2_4000")->set_base(memptr + 0x2c000);
	537	}
	538	if (m_memsize > 128 * 1024 + 2 * 32768) {
	539	/* DRAM3, 32K */
393	540
394		AM_RANGE( 0x80000, 0x83fff ) AM_RAM AM_SHARE("dram0_18000")
395		AM_RANGE( 0x84000, 0x87fff ) AM_RAM AM_SHARE("dram0_1c000")
396		AM_RANGE( 0x88000, 0x8bfff ) AM_RAM AM_SHARE("dram2_4000")
397		AM_RANGE( 0x8c000, 0x8ffff ) AM_RAM AM_SHARE("dram3_0000")
	541	/* prog
	542	AM_RANGE( 0x9c000, 0x9ffff ) AM_RAM AM_SHARE("dram3_0000")
	543	AM_RANGE( 0xb0000, 0xb3fff ) AM_RAM AM_SHARE("dram3_4000")
	544	*/
	545	pspace.install_readwrite_bank(0x9c000, 0x9ffff, 0x3fff, 0, "dram3_0000");
	546	pspace.install_readwrite_bank(0xb0000, 0xb3fff, 0x3fff, 0, "dram3_4000");
398	547
399		AM_RANGE( 0x90000, 0x93fff ) AM_RAM AM_SHARE("dram0_18000")
400		AM_RANGE( 0x94000, 0x97fff ) AM_RAM AM_SHARE("dram0_1c000")
401		AM_RANGE( 0x98000, 0x9bfff ) AM_RAM AM_SHARE("dram2_4000")
402		AM_RANGE( 0x9c000, 0x9ffff ) AM_RAM AM_SHARE("dram3_0000")
	548	/* data
	549	AM_RANGE( 0x44000, 0x47fff ) AM_RAM AM_SHARE("dram3_0000")
	550	AM_RANGE( 0x48000, 0x4bfff ) AM_RAM AM_SHARE("dram3_4000")
	551	AM_RANGE( 0x8c000, 0x8ffff ) AM_RAM AM_SHARE("dram3_0000")
	552	AM_RANGE( 0x9c000, 0x9ffff ) AM_RAM AM_SHARE("dram3_0000")
	553	AM_RANGE( 0xb0000, 0xb3fff ) AM_RAM AM_SHARE("dram3_4000")
	554	AM_RANGE( 0xc0000, 0xc3fff ) AM_RAM AM_SHARE("dram3_4000")
	555	*/
	556	dspace.install_readwrite_bank(0x44000, 0x47fff, 0x3fff, 0, "dram3_0000");
	557	dspace.install_readwrite_bank(0x48000, 0x4bfff, 0x3fff, 0, "dram3_4000");
	558	dspace.install_readwrite_bank(0x8c000, 0x8ffff, 0x3fff, 0, "dram3_0000");
	559	dspace.install_readwrite_bank(0x9c000, 0x9ffff, 0x3fff, 0, "dram3_0000");
	560	dspace.install_readwrite_bank(0xb0000, 0xb3fff, 0x3fff, 0, "dram3_4000");
	561	dspace.install_readwrite_bank(0xc0000, 0xc3fff, 0x3fff, 0, "dram3_4000");
403	562
404		AM_RANGE( 0xa0000, 0xa3fff ) AM_RAM AM_SHARE("dram0_8000")
405		AM_RANGE( 0xa4000, 0xa7fff ) AM_RAM AM_SHARE("dram0_c000")
406		AM_RANGE( 0xa8000, 0xabfff ) AM_RAM AM_SHARE("dram1_4000")
407		AM_RANGE( 0xac000, 0xaffff ) AM_RAM AM_SHARE("dram2_0000")
	563	state->membank("dram3_0000")->set_base(memptr + 0x30000);
	564	state->membank("dram3_4000")->set_base(memptr + 0x34000);
	565	}
	566	}
	567	else {
408	568
409		AM_RANGE( 0xb0000, 0xb3fff ) AM_RAM AM_SHARE("dram3_4000")
	569	/* 128K expansion cards */
410	570
411		AM_RANGE( 0xc0000, 0xc3fff ) AM_RAM AM_SHARE("dram3_4000")
	571	/* DRAM1, 128K */
412	572
413		ADDRESS_MAP_END
	573	/* prog
	574	AM_RANGE( 0x2c000, 0x2ffff ) AM_RAM AM_SHARE("dram1_0000")
	575	AM_RANGE( 0x88000, 0x8bfff ) AM_RAM AM_SHARE("dram1_4000")
	576	AM_RANGE( 0x8c000, 0x8ffff ) AM_RAM AM_SHARE("dram1_8000")
	577	AM_RANGE( 0x98000, 0x9bfff ) AM_RAM AM_SHARE("dram1_c000")
	578	AM_RANGE( 0x9c000, 0x9ffff ) AM_RAM AM_SHARE("dram1_10000")
	579	AM_RANGE( 0xa8000, 0xabfff ) AM_RAM AM_SHARE("dram1_4000")
	580	AM_RANGE( 0xac000, 0xaffff ) AM_RAM AM_SHARE("dram1_8000")
	581	AM_RANGE( 0xb0000, 0xb3fff ) AM_RAM AM_SHARE("dram1_14000")
	582	AM_RANGE( 0xb4000, 0xb7fff ) AM_RAM AM_SHARE("dram1_18000")
	583	AM_RANGE( 0xb8000, 0xbbfff ) AM_RAM AM_SHARE("dram1_1c000")
	584	*/
	585	pspace.install_readwrite_bank(0x2c000, 0x2ffff, 0x3fff, 0, "dram1_0000");
	586	pspace.install_readwrite_bank(0x88000, 0x8bfff, 0x3fff, 0, "dram1_4000");
	587	pspace.install_readwrite_bank(0x8c000, 0x8ffff, 0x3fff, 0, "dram1_8000");
	588	pspace.install_readwrite_bank(0x98000, 0x9bfff, 0x3fff, 0, "dram1_c000");
	589	pspace.install_readwrite_bank(0x9c000, 0x9ffff, 0x3fff, 0, "dram1_10000");
	590	pspace.install_readwrite_bank(0xa8000, 0xabfff, 0x3fff, 0, "dram1_4000");
	591	pspace.install_readwrite_bank(0xac000, 0xaffff, 0x3fff, 0, "dram1_8000");
	592	pspace.install_readwrite_bank(0xb0000, 0xb3fff, 0x3fff, 0, "dram1_14000");
	593	pspace.install_readwrite_bank(0xb4000, 0xb7fff, 0x3fff, 0, "dram1_18000");
	594	pspace.install_readwrite_bank(0xb8000, 0xbbfff, 0x3fff, 0, "dram1_1c000");
414	595
	596	/* data
	597	AM_RANGE( 0x04000, 0x07fff ) AM_RAM AM_SHARE("dram1_4000")
	598	AM_RANGE( 0x1c000, 0x1ffff ) AM_RAM AM_SHARE("dram1_0000")
	599	AM_RANGE( 0x2c000, 0x2ffff ) AM_RAM AM_SHARE("dram1_0000")
	600	AM_RANGE( 0x88000, 0x8bfff ) AM_RAM AM_SHARE("dram1_c000")
	601	AM_RANGE( 0x8c000, 0x8ffff ) AM_RAM AM_SHARE("dram1_10000")
	602	AM_RANGE( 0x98000, 0x9bfff ) AM_RAM AM_SHARE("dram1_c000")
	603	AM_RANGE( 0x9c000, 0x9ffff ) AM_RAM AM_SHARE("dram1_10000")
	604	AM_RANGE( 0xa8000, 0xabfff ) AM_RAM AM_SHARE("dram1_4000")
	605	AM_RANGE( 0xac000, 0xaffff ) AM_RAM AM_SHARE("dram1_8000")
	606	AM_RANGE( 0xb0000, 0xb3fff ) AM_RAM AM_SHARE("dram1_14000")
	607	AM_RANGE( 0xb4000, 0xb7fff ) AM_RAM AM_SHARE("dram1_18000")
	608	AM_RANGE( 0xb8000, 0xbbfff ) AM_RAM AM_SHARE("dram1_1c000")
	609	*/
	610	dspace.install_readwrite_bank(0x4000, 0x7fff, 0x3fff, 0, "dram1_4000");
	611	dspace.install_readwrite_bank(0x1c000, 0x1ffff, 0x3fff, 0, "dram1_0000");
	612	dspace.install_readwrite_bank(0x2c000, 0x2ffff, 0x3fff, 0, "dram1_0000");
	613	dspace.install_readwrite_bank(0x88000, 0x8bfff, 0x3fff, 0, "dram1_c000");
	614	dspace.install_readwrite_bank(0x8c000, 0x8ffff, 0x3fff, 0, "dram1_10000");
	615	dspace.install_readwrite_bank(0x98000, 0x9bfff, 0x3fff, 0, "dram1_c000");
	616	dspace.install_readwrite_bank(0x9c000, 0x9ffff, 0x3fff, 0, "dram1_10000");
	617	dspace.install_readwrite_bank(0xa8000, 0xabfff, 0x3fff, 0, "dram1_4000");
	618	dspace.install_readwrite_bank(0xac000, 0xaffff, 0x3fff, 0, "dram1_8000");
	619	dspace.install_readwrite_bank(0xb0000, 0xb3fff, 0x3fff, 0, "dram1_14000");
	620	dspace.install_readwrite_bank(0xb4000, 0xb7fff, 0x3fff, 0, "dram1_18000");
	621	dspace.install_readwrite_bank(0xb8000, 0xbbfff, 0x3fff, 0, "dram1_1c000");
	622
	623	state->membank("dram1_0000")->set_base(memptr + 0x20000);
	624	state->membank("dram1_4000")->set_base(memptr + 0x24000);
	625	state->membank("dram1_8000")->set_base(memptr + 0x28000);
	626	state->membank("dram1_c000")->set_base(memptr + 0x2c000);
	627	state->membank("dram1_10000")->set_base(memptr + 0x30000);
	628	state->membank("dram1_14000")->set_base(memptr + 0x34000);
	629	state->membank("dram1_18000")->set_base(memptr + 0x38000);
	630	state->membank("dram1_1c000")->set_base(memptr + 0x3c000);
	631
	632	if (m_memsize > 256 * 1024) {
	633	/* DRAM2, 128K */
	634
	635	/* prog
	636	AM_RANGE( 0xbc000, 0xbffff ) AM_RAM AM_SHARE("dram2_0000")
	637
	638	AM_RANGE( 0xc0000, 0xc3fff ) AM_RAM AM_SHARE("dram2_4000")
	639	AM_RANGE( 0xc4000, 0xc7fff ) AM_RAM AM_SHARE("dram2_8000")
	640	AM_RANGE( 0xc8000, 0xcbfff ) AM_RAM AM_SHARE("dram2_c000")
	641	AM_RANGE( 0xcc000, 0xcffff ) AM_RAM AM_SHARE("dram2_10000")
	642
	643	AM_RANGE( 0xd0000, 0xd3fff ) AM_RAM AM_SHARE("dram2_14000")
	644	AM_RANGE( 0xd4000, 0xd7fff ) AM_RAM AM_SHARE("dram2_18000")
	645	AM_RANGE( 0xd8000, 0xdbfff ) AM_RAM AM_SHARE("dram2_1c000")
	646	*/
	647	pspace.install_readwrite_bank(0xbc000, 0xbffff, 0x3fff, 0, "dram2_0000");
	648	pspace.install_readwrite_bank(0xc0000, 0xc3fff, 0x3fff, 0, "dram2_4000");
	649	pspace.install_readwrite_bank(0xc4000, 0xc7fff, 0x3fff, 0, "dram2_8000");
	650	pspace.install_readwrite_bank(0xc8000, 0xcbfff, 0x3fff, 0, "dram2_c000");
	651	pspace.install_readwrite_bank(0xcc000, 0xcffff, 0x3fff, 0, "dram2_10000");
	652	pspace.install_readwrite_bank(0xd0000, 0xd3fff, 0x3fff, 0, "dram2_14000");
	653	pspace.install_readwrite_bank(0xd4000, 0xd7fff, 0x3fff, 0, "dram2_18000");
	654	pspace.install_readwrite_bank(0xd8000, 0xdbfff, 0x3fff, 0, "dram2_1c000");
	655
	656	/* data
	657	AM_RANGE( 0x08000, 0x0bfff ) AM_RAM AM_SHARE("dram2_0000")
	658	AM_RANGE( 0x0c000, 0x0ffff ) AM_RAM AM_SHARE("dram2_4000")
	659
	660	AM_RANGE( 0xbc000, 0xbffff ) AM_RAM AM_SHARE("dram2_0000")
	661
	662	AM_RANGE( 0xc0000, 0xc3fff ) AM_RAM AM_SHARE("dram2_4000")
	663	AM_RANGE( 0xc4000, 0xc7fff ) AM_RAM AM_SHARE("dram2_8000")
	664	AM_RANGE( 0xc8000, 0xcbfff ) AM_RAM AM_SHARE("dram2_c000")
	665	AM_RANGE( 0xcc000, 0xcffff ) AM_RAM AM_SHARE("dram2_10000")
	666
	667	AM_RANGE( 0xd0000, 0xd3fff ) AM_RAM AM_SHARE("dram2_14000")
	668	AM_RANGE( 0xd4000, 0xd7fff ) AM_RAM AM_SHARE("dram2_18000")
	669	AM_RANGE( 0xd8000, 0xdbfff ) AM_RAM AM_SHARE("dram2_1c000")
	670	*/
	671	dspace.install_readwrite_bank(0x8000, 0xbfff, 0x3fff, 0, "dram2_0000");
	672	dspace.install_readwrite_bank(0xc000, 0xffff, 0x3fff, 0, "dram2_4000");
	673	dspace.install_readwrite_bank(0xbc000, 0xbffff, 0x3fff, 0, "dram2_0000");
	674	dspace.install_readwrite_bank(0xc0000, 0xc3fff, 0x3fff, 0, "dram2_4000");
	675	dspace.install_readwrite_bank(0xc4000, 0xc7fff, 0x3fff, 0, "dram2_8000");
	676	dspace.install_readwrite_bank(0xc8000, 0xcbfff, 0x3fff, 0, "dram2_c000");
	677	dspace.install_readwrite_bank(0xcc000, 0xcffff, 0x3fff, 0, "dram2_10000");
	678	dspace.install_readwrite_bank(0xd0000, 0xd3fff, 0x3fff, 0, "dram2_14000");
	679	dspace.install_readwrite_bank(0xd4000, 0xd7fff, 0x3fff, 0, "dram2_18000");
	680	dspace.install_readwrite_bank(0xd8000, 0xdbfff, 0x3fff, 0, "dram2_1c000");
	681
	682	state->membank("dram2_0000")->set_base(memptr + 0x40000);
	683	state->membank("dram2_4000")->set_base(memptr + 0x44000);
	684	state->membank("dram2_8000")->set_base(memptr + 0x48000);
	685	state->membank("dram2_c000")->set_base(memptr + 0x4c000);
	686	state->membank("dram2_10000")->set_base(memptr + 0x50000);
	687	state->membank("dram2_14000")->set_base(memptr + 0x54000);
	688	state->membank("dram2_18000")->set_base(memptr + 0x58000);
	689	state->membank("dram2_1c000")->set_base(memptr + 0x5c000);
	690	}
	691	if (m_memsize > 384 * 1024) {
	692	/* DRAM3, 128K */
	693
	694	/* prog
	695	AM_RANGE( 0xdc000, 0xdffff ) AM_RAM AM_SHARE("dram3_0000")
	696
	697	AM_RANGE( 0xe0000, 0xe3fff ) AM_RAM AM_SHARE("dram3_4000")
	698	AM_RANGE( 0xe4000, 0xe7fff ) AM_RAM AM_SHARE("dram3_8000")
	699	AM_RANGE( 0xe8000, 0xebfff ) AM_RAM AM_SHARE("dram3_c000")
	700	AM_RANGE( 0xec000, 0xeffff ) AM_RAM AM_SHARE("dram3_10000")
	701
	702	AM_RANGE( 0xf0000, 0xf3fff ) AM_RAM AM_SHARE("dram3_14000")
	703	AM_RANGE( 0xf4000, 0xf7fff ) AM_RAM AM_SHARE("dram3_18000")
	704	AM_RANGE( 0xf8000, 0xfbfff ) AM_RAM AM_SHARE("dram3_1c000")
	705	AM_RANGE( 0xfc000, 0xfffff ) AM_RAM AM_SHARE("dram3_0000")
	706	*/
	707	pspace.install_readwrite_bank(0xdc000, 0xdffff, 0x3fff, 0, "dram3_0000");
	708	pspace.install_readwrite_bank(0xe0000, 0xe3fff, 0x3fff, 0, "dram3_4000");
	709	pspace.install_readwrite_bank(0xe4000, 0xe7fff, 0x3fff, 0, "dram3_8000");
	710	pspace.install_readwrite_bank(0xe8000, 0xebfff, 0x3fff, 0, "dram3_c000");
	711	pspace.install_readwrite_bank(0xec000, 0xeffff, 0x3fff, 0, "dram3_10000");
	712	pspace.install_readwrite_bank(0xf0000, 0xf3fff, 0x3fff, 0, "dram3_14000");
	713	pspace.install_readwrite_bank(0xf4000, 0xf7fff, 0x3fff, 0, "dram3_18000");
	714	pspace.install_readwrite_bank(0xf8000, 0xfbfff, 0x3fff, 0, "dram3_1c000");
	715	pspace.install_readwrite_bank(0xfc000, 0xfffff, 0x3fff, 0, "dram3_0000");
	716
	717	/* data
	718	AM_RANGE( 0x44000, 0x47fff ) AM_RAM AM_SHARE("dram3_0000")
	719	AM_RANGE( 0x48000, 0x4bfff ) AM_RAM AM_SHARE("dram3_4000")
	720	AM_RANGE( 0xdc000, 0xdffff ) AM_RAM AM_SHARE("dram3_0000")
	721
	722	AM_RANGE( 0xe0000, 0xe3fff ) AM_RAM AM_SHARE("dram3_4000")
	723	AM_RANGE( 0xe4000, 0xe7fff ) AM_RAM AM_SHARE("dram3_8000")
	724	AM_RANGE( 0xe8000, 0xebfff ) AM_RAM AM_SHARE("dram3_c000")
	725	AM_RANGE( 0xec000, 0xeffff ) AM_RAM AM_SHARE("dram3_10000")
	726
	727	AM_RANGE( 0xf0000, 0xf3fff ) AM_RAM AM_SHARE("dram3_14000")
	728	AM_RANGE( 0xf4000, 0xf7fff ) AM_RAM AM_SHARE("dram3_18000")
	729	AM_RANGE( 0xf8000, 0xfbfff ) AM_RAM AM_SHARE("dram3_1c000")
	730	AM_RANGE( 0xfc000, 0xfffff ) AM_RAM AM_SHARE("dram3_0000")
	731	*/
	732	dspace.install_readwrite_bank(0x44000, 0x47fff, 0x3fff, 0, "dram3_0000");
	733	dspace.install_readwrite_bank(0x48000, 0x4bfff, 0x3fff, 0, "dram3_4000");
	734	dspace.install_readwrite_bank(0xdc000, 0xdffff, 0x3fff, 0, "dram3_0000");
	735	dspace.install_readwrite_bank(0xe0000, 0xe3fff, 0x3fff, 0, "dram3_4000");
	736	dspace.install_readwrite_bank(0xe4000, 0xe7fff, 0x3fff, 0, "dram3_8000");
	737	dspace.install_readwrite_bank(0xe8000, 0xebfff, 0x3fff, 0, "dram3_c000");
	738	dspace.install_readwrite_bank(0xec000, 0xeffff, 0x3fff, 0, "dram3_10000");
	739	dspace.install_readwrite_bank(0xf0000, 0xf3fff, 0x3fff, 0, "dram3_14000");
	740	dspace.install_readwrite_bank(0xf4000, 0xf7fff, 0x3fff, 0, "dram3_18000");
	741	dspace.install_readwrite_bank(0xf8000, 0xfbfff, 0x3fff, 0, "dram3_1c000");
	742	dspace.install_readwrite_bank(0xfc000, 0xfffff, 0x3fff, 0, "dram3_0000");
	743
	744	state->membank("dram3_0000")->set_base(memptr + 0x60000);
	745	state->membank("dram3_4000")->set_base(memptr + 0x64000);
	746	state->membank("dram3_8000")->set_base(memptr + 0x68000);
	747	state->membank("dram3_c000")->set_base(memptr + 0x6c000);
	748	state->membank("dram3_10000")->set_base(memptr + 0x70000);
	749	state->membank("dram3_14000")->set_base(memptr + 0x74000);
	750	state->membank("dram3_18000")->set_base(memptr + 0x78000);
	751	state->membank("dram3_1c000")->set_base(memptr + 0x7c000);
	752	}
	753	}
	754	}
	755	}
	756
415	757	static ADDRESS_MAP_START(m20_io, AS_IO, 16, m20_state)
416	758	ADDRESS_MAP_UNMAP_HIGH
417	759
r19875	r19876
470	812	void m20_state::machine_start()
471	813	{
472	814	m_fd1797->setup_intrq_cb(fd1797_t::line_cb(FUNC(m20_state::fdc_intrq_w), this));
	815
	816	install_memory();
473	817	}
474	818
475	819	void m20_state::machine_reset()
476	820	{
477	821	UINT8 *ROM = machine().root_device().memregion("maincpu")->base();
478		//  UINT8 *RAM = (UINT8 *)machine().root_device().memshare("mainram")->ptr();
479		UINT8 *RAM = (UINT8 *)machine().root_device().memshare("dram0_4000")->ptr();
	822	UINT8 *RAM = (UINT8 *)(m_ram->pointer() + 0x4000);
480	823
481		//ROM += 0x10000; // don't know why they load at an offset, but let's go with it
	824	if (m_memsize >= 256 * 1024)
	825	m_port21 = 0xdf;
	826	else
	827	m_port21 = 0xff;
482	828
483		m_port21 = 0xff;
484
485	829	m_maincpu->set_irq_acknowledge_callback(m20_irq_callback);
486	830
487	831	m_fd1797->reset();
r19875	r19876
562	906	WRITE8_MEMBER( m20_state::kbd_put )
563	907	{
564	908	if (data) {
565		if (data == 0xd) data = 0xc1;
566		else if (data == 0x20) data = 0xc0;
567		else if (data == 8) data = 0x69; /* ^H */
568		else if (data == 3) data = 0x64; /* ^C */
569		else if (data >= '0' && data <= '9') data += 0x4c - '0';
	909	if (data == 0xd) data = 0xc1;
	910	else if (data == 0x20) data = 0xc0;
	911	else if (data == 8) data = 0x69; /* ^H */
	912	else if (data == 3) data = 0x64; /* ^C */
	913	else if (data >= '0' && data <= '9') data += 0x1c - '0';
570	914	else {
571	915	int i;
572	916	for (i = 0; i < sizeof(kbxlat); i++)
r19875	r19876
628	972	MCFG_CPU_DATA_MAP(m20_data_mem)
629	973	MCFG_CPU_IO_MAP(m20_io)
630	974
	975	MCFG_RAM_ADD(RAM_TAG)
	976	MCFG_RAM_DEFAULT_SIZE("160K")
	977	MCFG_RAM_EXTRA_OPTIONS("128K,192K,224K,256K,384K,512K")
	978
631	979	#if 0
632	980	MCFG_CPU_ADD("apb", I8086, MAIN_CLOCK)
633	981	MCFG_CPU_PROGRAM_MAP(m20_apb_mem)
r19875	r19876
661	1009
662	1010	ROM_START(m20)
663	1011	ROM_REGION(0x2000,"maincpu", 0)
664		//ROM_REGION(0x12000,"maincpu", 0)
665	1012	ROM_SYSTEM_BIOS( 0, "m20", "M20 1.0" )
666	1013	ROMX_LOAD("m20.bin", 0x0000, 0x2000, CRC(5c93d931) SHA1(d51025e087a94c55529d7ee8fd18ff4c46d93230), ROM_BIOS(1))
667	1014	ROM_SYSTEM_BIOS( 1, "m20-20d", "M20 2.0d" )
668	1015	ROMX_LOAD("m20-20d.bin", 0x0000, 0x2000, CRC(cbe265a6) SHA1(c7cb9d9900b7b5014fcf1ceb2e45a66a91c564d0), ROM_BIOS(2))
669	1016	ROM_SYSTEM_BIOS( 2, "m20-20f", "M20 2.0f" )
670	1017	ROMX_LOAD("m20-20f.bin", 0x0000, 0x2000, CRC(db7198d8) SHA1(149d8513867081d31c73c2965dabb36d5f308041), ROM_BIOS(3))
671
672	1018	ROM_END
673	1019
674		#if 0
675		ROM_START(m20)
676		ROM_REGION(0x2000,"maincpu", 0)
677		//ROM_REGION(0x12000,"maincpu", 0)
678		ROM_SYSTEM_BIOS( 0, "m20", "M20 1.0" )
679		ROMX_LOAD("m20.bin", 0x10000, 0x2000, CRC(5c93d931) SHA1(d51025e087a94c55529d7ee8fd18ff4c46d93230), ROM_BIOS(1))
680		ROM_SYSTEM_BIOS( 1, "m20-20d", "M20 2.0d" )
681		ROMX_LOAD("m20-20d.bin", 0x10000, 0x2000, CRC(cbe265a6) SHA1(c7cb9d9900b7b5014fcf1ceb2e45a66a91c564d0), ROM_BIOS(2))
682		ROM_SYSTEM_BIOS( 2, "m20-20f", "M20 2.0f" )
683		ROMX_LOAD("m20-20f.bin", 0x10000, 0x2000, CRC(db7198d8) SHA1(149d8513867081d31c73c2965dabb36d5f308041), ROM_BIOS(3))
684
685		ROM_REGION(0x4000,"apb_bios", 0) // Processor board with 8086
686		ROM_LOAD( "apb-1086-2.0.bin", 0x0000, 0x4000, CRC(8c05be93) SHA1(2bb424afd874cc6562e9642780eaac2391308053))
687		ROM_END
688		#endif
689
690	1020	ROM_START(m40)
691	1021	ROM_REGION(0x14000,"maincpu", 0)
692	1022	ROM_SYSTEM_BIOS( 0, "m40-81", "M40 15.dec.81" )

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