Previous

199869 Revisions

Next

r19874 Friday 28th December, 2012 at 02:27:46 UTC by Ryan Holtz
Re-modernized Hyperstone device, Korean bootlegs all work now, tested with: (nw) mosaicf2, vamphalf, dynabomb, gstream, pasha2, mrdig, boonggab (nw)

[src/emu/cpu/e132xs]

e132xs.c e132xs.h e132xsop.c

trunk/src/emu/cpu/e132xs/e132xsop.c

r19873	r19874
18	18	decode->same_srcf_dst = 0; \
19	19
20	20
21		static void hyperstone_op00(hyperstone_state *cpustate)
	21	void hyperstone_device::op00()
22	22	{
23	23	LOCAL_DECODE_INIT;
24	24	RRdecode(decode, 0, 0);
25		hyperstone_chk(cpustate, decode);
	25	hyperstone_chk(decode);
26	26	}
27	27
28		static void hyperstone_op01(hyperstone_state *cpustate)
	28	void hyperstone_device::op01()
29	29	{
30	30	LOCAL_DECODE_INIT;
31	31	RRdecode(decode, 0, 1);
32		hyperstone_chk(cpustate, decode);
	32	hyperstone_chk(decode);
33	33	}
34	34
35		static void hyperstone_op02(hyperstone_state *cpustate)
	35	void hyperstone_device::op02()
36	36	{
37	37	LOCAL_DECODE_INIT;
38	38	RRdecode(decode, 1, 0);
39		hyperstone_chk(cpustate, decode);
	39	hyperstone_chk(decode);
40	40	}
41	41
42		static void hyperstone_op03(hyperstone_state *cpustate)
	42	void hyperstone_device::op03()
43	43	{
44	44	LOCAL_DECODE_INIT;
45	45	RRdecode(decode, 1, 1);
46		hyperstone_chk(cpustate, decode);
	46	hyperstone_chk(decode);
47	47	}
48	48
49		static void hyperstone_op04(hyperstone_state *cpustate)
	49	void hyperstone_device::op04()
50	50	{
51	51	LOCAL_DECODE_INIT;
52	52	RRdecode(decode, 0, 0);
53		hyperstone_movd(cpustate, decode);
	53	hyperstone_movd(decode);
54	54	}
55	55
56		static void hyperstone_op05(hyperstone_state *cpustate)
	56	void hyperstone_device::op05()
57	57	{
58	58	LOCAL_DECODE_INIT;
59	59	RRdecode(decode, 0, 1);
60		hyperstone_movd(cpustate, decode);
	60	hyperstone_movd(decode);
61	61	}
62	62
63		static void hyperstone_op06(hyperstone_state *cpustate)
	63	void hyperstone_device::op06()
64	64	{
65	65	LOCAL_DECODE_INIT;
66	66	RRdecode(decode, 1, 0);
67		hyperstone_movd(cpustate, decode);
	67	hyperstone_movd(decode);
68	68	}
69	69
70		static void hyperstone_op07(hyperstone_state *cpustate)
	70	void hyperstone_device::op07()
71	71	{
72	72	LOCAL_DECODE_INIT;
73	73	RRdecode(decode, 1, 1);
74		hyperstone_movd(cpustate, decode);
	74	hyperstone_movd(decode);
75	75	}
76	76
77		static void hyperstone_op08(hyperstone_state *cpustate)
	77	void hyperstone_device::op08()
78	78	{
79	79	LOCAL_DECODE_INIT;
80	80	RRdecode(decode, 0, 0);
81		hyperstone_divu(cpustate, decode);
	81	hyperstone_divu(decode);
82	82	}
83	83
84		static void hyperstone_op09(hyperstone_state *cpustate)
	84	void hyperstone_device::op09()
85	85	{
86	86	LOCAL_DECODE_INIT;
87	87	RRdecode(decode, 0, 1);
88		hyperstone_divu(cpustate, decode);
	88	hyperstone_divu(decode);
89	89	}
90	90
91		static void hyperstone_op0a(hyperstone_state *cpustate)
	91	void hyperstone_device::op0a()
92	92	{
93	93	LOCAL_DECODE_INIT;
94	94	RRdecode(decode, 1, 0);
95		hyperstone_divu(cpustate, decode);
	95	hyperstone_divu(decode);
96	96	}
97	97
98		static void hyperstone_op0b(hyperstone_state *cpustate)
	98	void hyperstone_device::op0b()
99	99	{
100	100	LOCAL_DECODE_INIT;
101	101	RRdecode(decode, 1, 1);
102		hyperstone_divu(cpustate, decode);
	102	hyperstone_divu(decode);
103	103	}
104	104
105		static void hyperstone_op0c(hyperstone_state *cpustate)
	105	void hyperstone_device::op0c()
106	106	{
107	107	LOCAL_DECODE_INIT;
108	108	RRdecode(decode, 0, 0);
109		hyperstone_divs(cpustate, decode);
	109	hyperstone_divs(decode);
110	110	}
111	111
112		static void hyperstone_op0d(hyperstone_state *cpustate)
	112	void hyperstone_device::op0d()
113	113	{
114	114	LOCAL_DECODE_INIT;
115	115	RRdecode(decode, 0, 1);
116		hyperstone_divs(cpustate, decode);
	116	hyperstone_divs(decode);
117	117	}
118	118
119		static void hyperstone_op0e(hyperstone_state *cpustate)
	119	void hyperstone_device::op0e()
120	120	{
121	121	LOCAL_DECODE_INIT;
122	122	RRdecode(decode, 1, 0);
123		hyperstone_divs(cpustate, decode);
	123	hyperstone_divs(decode);
124	124	}
125	125
126		static void hyperstone_op0f(hyperstone_state *cpustate)
	126	void hyperstone_device::op0f()
127	127	{
128	128	LOCAL_DECODE_INIT;
129	129	RRdecode(decode, 1, 1);
130		hyperstone_divs(cpustate, decode);
	130	hyperstone_divs(decode);
131	131	}
132	132
133	133
134	134
135		static void hyperstone_op10(hyperstone_state *cpustate)
	135	void hyperstone_device::op10()
136	136	{
137	137	LOCAL_DECODE_INIT;
138	138	RRlimdecode(decode, 0, 0);
139		hyperstone_xm(cpustate, decode);
	139	hyperstone_xm(decode);
140	140	}
141	141
142		static void hyperstone_op11(hyperstone_state *cpustate)
	142	void hyperstone_device::op11()
143	143	{
144	144	LOCAL_DECODE_INIT;
145	145	RRlimdecode(decode, 0, 1);
146		hyperstone_xm(cpustate, decode);
	146	hyperstone_xm(decode);
147	147	}
148	148
149		static void hyperstone_op12(hyperstone_state *cpustate)
	149	void hyperstone_device::op12()
150	150	{
151	151	LOCAL_DECODE_INIT;
152	152	RRlimdecode(decode, 1, 0);
153		hyperstone_xm(cpustate, decode);
	153	hyperstone_xm(decode);
154	154	}
155	155
156		static void hyperstone_op13(hyperstone_state *cpustate)
	156	void hyperstone_device::op13()
157	157	{
158	158	LOCAL_DECODE_INIT;
159	159	RRlimdecode(decode, 1, 1);
160		hyperstone_xm(cpustate, decode);
	160	hyperstone_xm(decode);
161	161	}
162	162
163		static void hyperstone_op14(hyperstone_state *cpustate)
	163	void hyperstone_device::op14()
164	164	{
165	165	LOCAL_DECODE_INIT;
166	166	RRconstdecode(decode, 0, 0);
167		hyperstone_mask(cpustate, decode);
	167	hyperstone_mask(decode);
168	168	}
169	169
170		static void hyperstone_op15(hyperstone_state *cpustate)
	170	void hyperstone_device::op15()
171	171	{
172	172	LOCAL_DECODE_INIT;
173	173	RRconstdecode(decode, 0, 1);
174		hyperstone_mask(cpustate, decode);
	174	hyperstone_mask(decode);
175	175	}
176	176
177		static void hyperstone_op16(hyperstone_state *cpustate)
	177	void hyperstone_device::op16()
178	178	{
179	179	LOCAL_DECODE_INIT;
180	180	RRconstdecode(decode, 1, 0);
181		hyperstone_mask(cpustate, decode);
	181	hyperstone_mask(decode);
182	182	}
183	183
184		static void hyperstone_op17(hyperstone_state *cpustate)
	184	void hyperstone_device::op17()
185	185	{
186	186	LOCAL_DECODE_INIT;
187	187	RRconstdecode(decode, 1, 1);
188		hyperstone_mask(cpustate, decode);
	188	hyperstone_mask(decode);
189	189	}
190	190
191		static void hyperstone_op18(hyperstone_state *cpustate)
	191	void hyperstone_device::op18()
192	192	{
193	193	LOCAL_DECODE_INIT;
194	194	RRconstdecode(decode, 0, 0);
195		hyperstone_sum(cpustate, decode);
	195	hyperstone_sum(decode);
196	196	}
197	197
198		static void hyperstone_op19(hyperstone_state *cpustate)
	198	void hyperstone_device::op19()
199	199	{
200	200	LOCAL_DECODE_INIT;
201	201	RRconstdecode(decode, 0, 1);
202		hyperstone_sum(cpustate, decode);
	202	hyperstone_sum(decode);
203	203	}
204	204
205		static void hyperstone_op1a(hyperstone_state *cpustate)
	205	void hyperstone_device::op1a()
206	206	{
207	207	LOCAL_DECODE_INIT;
208	208	RRconstdecode(decode, 1, 0);
209		hyperstone_sum(cpustate, decode);
	209	hyperstone_sum(decode);
210	210	}
211	211
212		static void hyperstone_op1b(hyperstone_state *cpustate)
	212	void hyperstone_device::op1b()
213	213	{
214	214	LOCAL_DECODE_INIT;
215	215	RRconstdecode(decode, 1, 1);
216		hyperstone_sum(cpustate, decode);
	216	hyperstone_sum(decode);
217	217	}
218	218
219		static void hyperstone_op1c(hyperstone_state *cpustate)
	219	void hyperstone_device::op1c()
220	220	{
221	221	LOCAL_DECODE_INIT;
222	222	RRconstdecode(decode, 0, 0);
223		hyperstone_sums(cpustate, decode);
	223	hyperstone_sums(decode);
224	224	}
225	225
226		static void hyperstone_op1d(hyperstone_state *cpustate)
	226	void hyperstone_device::op1d()
227	227	{
228	228	LOCAL_DECODE_INIT;
229	229	RRconstdecode(decode, 0, 1);
230		hyperstone_sums(cpustate, decode);
	230	hyperstone_sums(decode);
231	231	}
232	232
233		static void hyperstone_op1e(hyperstone_state *cpustate)
	233	void hyperstone_device::op1e()
234	234	{
235	235	LOCAL_DECODE_INIT;
236	236	RRconstdecode(decode, 1, 0);
237		hyperstone_sums(cpustate, decode);
	237	hyperstone_sums(decode);
238	238	}
239	239
240		static void hyperstone_op1f(hyperstone_state *cpustate)
	240	void hyperstone_device::op1f()
241	241	{
242	242	LOCAL_DECODE_INIT;
243	243	RRconstdecode(decode, 1, 1);
244		hyperstone_sums(cpustate, decode);
	244	hyperstone_sums(decode);
245	245	}
246	246
247	247
248	248
249		static void hyperstone_op20(hyperstone_state *cpustate)
	249	void hyperstone_device::op20()
250	250	{
251	251	LOCAL_DECODE_INIT;
252	252	RRdecode(decode, 0, 0);
253		hyperstone_cmp(cpustate, decode);
	253	hyperstone_cmp(decode);
254	254	}
255	255
256		static void hyperstone_op21(hyperstone_state *cpustate)
	256	void hyperstone_device::op21()
257	257	{
258	258	LOCAL_DECODE_INIT;
259	259	RRdecode(decode, 0, 1);
260		hyperstone_cmp(cpustate, decode);
	260	hyperstone_cmp(decode);
261	261	}
262	262
263		static void hyperstone_op22(hyperstone_state *cpustate)
	263	void hyperstone_device::op22()
264	264	{
265	265	LOCAL_DECODE_INIT;
266	266	RRdecode(decode, 1, 0);
267		hyperstone_cmp(cpustate, decode);
	267	hyperstone_cmp(decode);
268	268	}
269	269
270		static void hyperstone_op23(hyperstone_state *cpustate)
	270	void hyperstone_device::op23()
271	271	{
272	272	LOCAL_DECODE_INIT;
273	273	RRdecode(decode, 1, 1);
274		hyperstone_cmp(cpustate, decode);
	274	hyperstone_cmp(decode);
275	275	}
276	276
277		static void hyperstone_op24(hyperstone_state *cpustate)
	277	void hyperstone_device::op24()
278	278	{
279	279	LOCAL_DECODE_INIT;
280	280	RRdecodewithHflag(decode, 0, 0);
281		hyperstone_mov(cpustate, decode);
	281	hyperstone_mov(decode);
282	282	}
283	283
284		static void hyperstone_op25(hyperstone_state *cpustate)
	284	void hyperstone_device::op25()
285	285	{
286	286	LOCAL_DECODE_INIT;
287	287	RRdecodewithHflag(decode, 0, 1);
288		hyperstone_mov(cpustate, decode);
	288	hyperstone_mov(decode);
289	289	}
290	290
291		static void hyperstone_op26(hyperstone_state *cpustate)
	291	void hyperstone_device::op26()
292	292	{
293	293	LOCAL_DECODE_INIT;
294	294	RRdecodewithHflag(decode, 1, 0);
295		hyperstone_mov(cpustate, decode);
	295	hyperstone_mov(decode);
296	296	}
297	297
298		static void hyperstone_op27(hyperstone_state *cpustate)
	298	void hyperstone_device::op27()
299	299	{
300	300	LOCAL_DECODE_INIT;
301	301	RRdecodewithHflag(decode, 1, 1);
302		hyperstone_mov(cpustate, decode);
	302	hyperstone_mov(decode);
303	303	}
304	304
305		static void hyperstone_op28(hyperstone_state *cpustate)
	305	void hyperstone_device::op28()
306	306	{
307	307	LOCAL_DECODE_INIT;
308	308	RRdecode(decode, 0, 0);
309		hyperstone_add(cpustate, decode);
	309	hyperstone_add(decode);
310	310	}
311	311
312		static void hyperstone_op29(hyperstone_state *cpustate)
	312	void hyperstone_device::op29()
313	313	{
314	314	LOCAL_DECODE_INIT;
315	315	RRdecode(decode, 0, 1);
316		hyperstone_add(cpustate, decode);
	316	hyperstone_add(decode);
317	317	}
318	318
319		static void hyperstone_op2a(hyperstone_state *cpustate)
	319	void hyperstone_device::op2a()
320	320	{
321	321	LOCAL_DECODE_INIT;
322	322	RRdecode(decode, 1, 0);
323		hyperstone_add(cpustate, decode);
	323	hyperstone_add(decode);
324	324	}
325	325
326		static void hyperstone_op2b(hyperstone_state *cpustate)
	326	void hyperstone_device::op2b()
327	327	{
328	328	LOCAL_DECODE_INIT;
329	329	RRdecode(decode, 1, 1);
330		hyperstone_add(cpustate, decode);
	330	hyperstone_add(decode);
331	331	}
332	332
333		static void hyperstone_op2c(hyperstone_state *cpustate)
	333	void hyperstone_device::op2c()
334	334	{
335	335	LOCAL_DECODE_INIT;
336	336	RRdecode(decode, 0, 0);
337		hyperstone_adds(cpustate, decode);
	337	hyperstone_adds(decode);
338	338	}
339	339
340		static void hyperstone_op2d(hyperstone_state *cpustate)
	340	void hyperstone_device::op2d()
341	341	{
342	342	LOCAL_DECODE_INIT;
343	343	RRdecode(decode, 0, 1);
344		hyperstone_adds(cpustate, decode);
	344	hyperstone_adds(decode);
345	345	}
346	346
347		static void hyperstone_op2e(hyperstone_state *cpustate)
	347	void hyperstone_device::op2e()
348	348	{
349	349	LOCAL_DECODE_INIT;
350	350	RRdecode(decode, 1, 0);
351		hyperstone_adds(cpustate, decode);
	351	hyperstone_adds(decode);
352	352	}
353	353
354		static void hyperstone_op2f(hyperstone_state *cpustate)
	354	void hyperstone_device::op2f()
355	355	{
356	356	LOCAL_DECODE_INIT;
357	357	RRdecode(decode, 1, 1);
358		hyperstone_adds(cpustate, decode);
	358	hyperstone_adds(decode);
359	359	}
360	360
361	361
362	362
363		static void hyperstone_op30(hyperstone_state *cpustate)
	363	void hyperstone_device::op30()
364	364	{
365	365	LOCAL_DECODE_INIT;
366	366	RRdecode(decode, 0, 0);
367		hyperstone_cmpb(cpustate, decode);
	367	hyperstone_cmpb(decode);
368	368	}
369	369
370		static void hyperstone_op31(hyperstone_state *cpustate)
	370	void hyperstone_device::op31()
371	371	{
372	372	LOCAL_DECODE_INIT;
373	373	RRdecode(decode, 0, 1);
374		hyperstone_cmpb(cpustate, decode);
	374	hyperstone_cmpb(decode);
375	375	}
376	376
377		static void hyperstone_op32(hyperstone_state *cpustate)
	377	void hyperstone_device::op32()
378	378	{
379	379	LOCAL_DECODE_INIT;
380	380	RRdecode(decode, 1, 0);
381		hyperstone_cmpb(cpustate, decode);
	381	hyperstone_cmpb(decode);
382	382	}
383	383
384		static void hyperstone_op33(hyperstone_state *cpustate)
	384	void hyperstone_device::op33()
385	385	{
386	386	LOCAL_DECODE_INIT;
387	387	RRdecode(decode, 1, 1);
388		hyperstone_cmpb(cpustate, decode);
	388	hyperstone_cmpb(decode);
389	389	}
390	390
391		static void hyperstone_op34(hyperstone_state *cpustate)
	391	void hyperstone_device::op34()
392	392	{
393	393	LOCAL_DECODE_INIT;
394	394	RRdecode(decode, 0, 0);
395		hyperstone_andn(cpustate, decode);
	395	hyperstone_andn(decode);
396	396	}
397	397
398		static void hyperstone_op35(hyperstone_state *cpustate)
	398	void hyperstone_device::op35()
399	399	{
400	400	LOCAL_DECODE_INIT;
401	401	RRdecode(decode, 0, 1);
402		hyperstone_andn(cpustate, decode);
	402	hyperstone_andn(decode);
403	403	}
404	404
405		static void hyperstone_op36(hyperstone_state *cpustate)
	405	void hyperstone_device::op36()
406	406	{
407	407	LOCAL_DECODE_INIT;
408	408	RRdecode(decode, 1, 0);
409		hyperstone_andn(cpustate, decode);
	409	hyperstone_andn(decode);
410	410	}
411	411
412		static void hyperstone_op37(hyperstone_state *cpustate)
	412	void hyperstone_device::op37()
413	413	{
414	414	LOCAL_DECODE_INIT;
415	415	RRdecode(decode, 1, 1);
416		hyperstone_andn(cpustate, decode);
	416	hyperstone_andn(decode);
417	417	}
418	418
419		static void hyperstone_op38(hyperstone_state *cpustate)
	419	void hyperstone_device::op38()
420	420	{
421	421	LOCAL_DECODE_INIT;
422	422	RRdecode(decode, 0, 0);
423		hyperstone_or(cpustate, decode);
	423	hyperstone_or(decode);
424	424	}
425	425
426		static void hyperstone_op39(hyperstone_state *cpustate)
	426	void hyperstone_device::op39()
427	427	{
428	428	LOCAL_DECODE_INIT;
429	429	RRdecode(decode, 0, 1);
430		hyperstone_or(cpustate, decode);
	430	hyperstone_or(decode);
431	431	}
432	432
433		static void hyperstone_op3a(hyperstone_state *cpustate)
	433	void hyperstone_device::op3a()
434	434	{
435	435	LOCAL_DECODE_INIT;
436	436	RRdecode(decode, 1, 0);
437		hyperstone_or(cpustate, decode);
	437	hyperstone_or(decode);
438	438	}
439	439
440		static void hyperstone_op3b(hyperstone_state *cpustate)
	440	void hyperstone_device::op3b()
441	441	{
442	442	LOCAL_DECODE_INIT;
443	443	RRdecode(decode, 1, 1);
444		hyperstone_or(cpustate, decode);
	444	hyperstone_or(decode);
445	445	}
446	446
447		static void hyperstone_op3c(hyperstone_state *cpustate)
	447	void hyperstone_device::op3c()
448	448	{
449	449	LOCAL_DECODE_INIT;
450	450	RRdecode(decode, 0, 0);
451		hyperstone_xor(cpustate, decode);
	451	hyperstone_xor(decode);
452	452	}
453	453
454		static void hyperstone_op3d(hyperstone_state *cpustate)
	454	void hyperstone_device::op3d()
455	455	{
456	456	LOCAL_DECODE_INIT;
457	457	RRdecode(decode, 0, 1);
458		hyperstone_xor(cpustate, decode);
	458	hyperstone_xor(decode);
459	459	}
460	460
461		static void hyperstone_op3e(hyperstone_state *cpustate)
	461	void hyperstone_device::op3e()
462	462	{
463	463	LOCAL_DECODE_INIT;
464	464	RRdecode(decode, 1, 0);
465		hyperstone_xor(cpustate, decode);
	465	hyperstone_xor(decode);
466	466	}
467	467
468		static void hyperstone_op3f(hyperstone_state *cpustate)
	468	void hyperstone_device::op3f()
469	469	{
470	470	LOCAL_DECODE_INIT;
471	471	RRdecode(decode, 1, 1);
472		hyperstone_xor(cpustate, decode);
	472	hyperstone_xor(decode);
473	473	}
474	474
475	475
476	476
477		static void hyperstone_op40(hyperstone_state *cpustate)
	477	void hyperstone_device::op40()
478	478	{
479	479	LOCAL_DECODE_INIT;
480	480	RRdecode(decode, 0, 0);
481		hyperstone_subc(cpustate, decode);
	481	hyperstone_subc(decode);
482	482	}
483	483
484		static void hyperstone_op41(hyperstone_state *cpustate)
	484	void hyperstone_device::op41()
485	485	{
486	486	LOCAL_DECODE_INIT;
487	487	RRdecode(decode, 0, 1);
488		hyperstone_subc(cpustate, decode);
	488	hyperstone_subc(decode);
489	489	}
490	490
491		static void hyperstone_op42(hyperstone_state *cpustate)
	491	void hyperstone_device::op42()
492	492	{
493	493	LOCAL_DECODE_INIT;
494	494	RRdecode(decode, 1, 0);
495		hyperstone_subc(cpustate, decode);
	495	hyperstone_subc(decode);
496	496	}
497	497
498		static void hyperstone_op43(hyperstone_state *cpustate)
	498	void hyperstone_device::op43()
499	499	{
500	500	LOCAL_DECODE_INIT;
501	501	RRdecode(decode, 1, 1);
502		hyperstone_subc(cpustate, decode);
	502	hyperstone_subc(decode);
503	503	}
504	504
505		static void hyperstone_op44(hyperstone_state *cpustate)
	505	void hyperstone_device::op44()
506	506	{
507	507	LOCAL_DECODE_INIT;
508	508	RRdecode(decode, 0, 0);
509		hyperstone_not(cpustate, decode);
	509	hyperstone_not(decode);
510	510	}
511	511
512		static void hyperstone_op45(hyperstone_state *cpustate)
	512	void hyperstone_device::op45()
513	513	{
514	514	LOCAL_DECODE_INIT;
515	515	RRdecode(decode, 0, 1);
516		hyperstone_not(cpustate, decode);
	516	hyperstone_not(decode);
517	517	}
518	518
519		static void hyperstone_op46(hyperstone_state *cpustate)
	519	void hyperstone_device::op46()
520	520	{
521	521	LOCAL_DECODE_INIT;
522	522	RRdecode(decode, 1, 0);
523		hyperstone_not(cpustate, decode);
	523	hyperstone_not(decode);
524	524	}
525	525
526		static void hyperstone_op47(hyperstone_state *cpustate)
	526	void hyperstone_device::op47()
527	527	{
528	528	LOCAL_DECODE_INIT;
529	529	RRdecode(decode, 1, 1);
530		hyperstone_not(cpustate, decode);
	530	hyperstone_not(decode);
531	531	}
532	532
533		static void hyperstone_op48(hyperstone_state *cpustate)
	533	void hyperstone_device::op48()
534	534	{
535	535	LOCAL_DECODE_INIT;
536	536	RRdecode(decode, 0, 0);
537		hyperstone_sub(cpustate, decode);
	537	hyperstone_sub(decode);
538	538	}
539	539
540		static void hyperstone_op49(hyperstone_state *cpustate)
	540	void hyperstone_device::op49()
541	541	{
542	542	LOCAL_DECODE_INIT;
543	543	RRdecode(decode, 0, 1);
544		hyperstone_sub(cpustate, decode);
	544	hyperstone_sub(decode);
545	545	}
546	546
547		static void hyperstone_op4a(hyperstone_state *cpustate)
	547	void hyperstone_device::op4a()
548	548	{
549	549	LOCAL_DECODE_INIT;
550	550	RRdecode(decode, 1, 0);
551		hyperstone_sub(cpustate, decode);
	551	hyperstone_sub(decode);
552	552	}
553	553
554		static void hyperstone_op4b(hyperstone_state *cpustate)
	554	void hyperstone_device::op4b()
555	555	{
556	556	LOCAL_DECODE_INIT;
557	557	RRdecode(decode, 1, 1);
558		hyperstone_sub(cpustate, decode);
	558	hyperstone_sub(decode);
559	559	}
560	560
561		static void hyperstone_op4c(hyperstone_state *cpustate)
	561	void hyperstone_device::op4c()
562	562	{
563	563	LOCAL_DECODE_INIT;
564	564	RRdecode(decode, 0, 0);
565		hyperstone_subs(cpustate, decode);
	565	hyperstone_subs(decode);
566	566	}
567	567
568		static void hyperstone_op4d(hyperstone_state *cpustate)
	568	void hyperstone_device::op4d()
569	569	{
570	570	LOCAL_DECODE_INIT;
571	571	RRdecode(decode, 0, 1);
572		hyperstone_subs(cpustate, decode);
	572	hyperstone_subs(decode);
573	573	}
574	574
575		static void hyperstone_op4e(hyperstone_state *cpustate)
	575	void hyperstone_device::op4e()
576	576	{
577	577	LOCAL_DECODE_INIT;
578	578	RRdecode(decode, 1, 0);
579		hyperstone_subs(cpustate, decode);
	579	hyperstone_subs(decode);
580	580	}
581	581
582		static void hyperstone_op4f(hyperstone_state *cpustate)
	582	void hyperstone_device::op4f()
583	583	{
584	584	LOCAL_DECODE_INIT;
585	585	RRdecode(decode, 1, 1);
586		hyperstone_subs(cpustate, decode);
	586	hyperstone_subs(decode);
587	587	}
588	588
589	589
590	590
591		static void hyperstone_op50(hyperstone_state *cpustate)
	591	void hyperstone_device::op50()
592	592	{
593	593	LOCAL_DECODE_INIT;
594	594	RRdecode(decode, 0, 0);
595		hyperstone_addc(cpustate, decode);
	595	hyperstone_addc(decode);
596	596	}
597	597
598		static void hyperstone_op51(hyperstone_state *cpustate)
	598	void hyperstone_device::op51()
599	599	{
600	600	LOCAL_DECODE_INIT;
601	601	RRdecode(decode, 0, 1);
602		hyperstone_addc(cpustate, decode);
	602	hyperstone_addc(decode);
603	603	}
604	604
605		static void hyperstone_op52(hyperstone_state *cpustate)
	605	void hyperstone_device::op52()
606	606	{
607	607	LOCAL_DECODE_INIT;
608	608	RRdecode(decode, 1, 0);
609		hyperstone_addc(cpustate, decode);
	609	hyperstone_addc(decode);
610	610	}
611	611
612		static void hyperstone_op53(hyperstone_state *cpustate)
	612	void hyperstone_device::op53()
613	613	{
614	614	LOCAL_DECODE_INIT;
615	615	RRdecode(decode, 1, 1);
616		hyperstone_addc(cpustate, decode);
	616	hyperstone_addc(decode);
617	617	}
618	618
619		static void hyperstone_op54(hyperstone_state *cpustate)
	619	void hyperstone_device::op54()
620	620	{
621	621	LOCAL_DECODE_INIT;
622	622	RRdecode(decode, 0, 0);
623		hyperstone_and(cpustate, decode);
	623	hyperstone_and(decode);
624	624	}
625	625
626		static void hyperstone_op55(hyperstone_state *cpustate)
	626	void hyperstone_device::op55()
627	627	{
628	628	LOCAL_DECODE_INIT;
629	629	RRdecode(decode, 0, 1);
630		hyperstone_and(cpustate, decode);
	630	hyperstone_and(decode);
631	631	}
632	632
633		static void hyperstone_op56(hyperstone_state *cpustate)
	633	void hyperstone_device::op56()
634	634	{
635	635	LOCAL_DECODE_INIT;
636	636	RRdecode(decode, 1, 0);
637		hyperstone_and(cpustate, decode);
	637	hyperstone_and(decode);
638	638	}
639	639
640		static void hyperstone_op57(hyperstone_state *cpustate)
	640	void hyperstone_device::op57()
641	641	{
642	642	LOCAL_DECODE_INIT;
643	643	RRdecode(decode, 1, 1);
644		hyperstone_and(cpustate, decode);
	644	hyperstone_and(decode);
645	645	}
646	646
647		static void hyperstone_op58(hyperstone_state *cpustate)
	647	void hyperstone_device::op58()
648	648	{
649	649	LOCAL_DECODE_INIT;
650	650	RRdecode(decode, 0, 0);
651		hyperstone_neg(cpustate, decode);
	651	hyperstone_neg(decode);
652	652	}
653	653
654		static void hyperstone_op59(hyperstone_state *cpustate)
	654	void hyperstone_device::op59()
655	655	{
656	656	LOCAL_DECODE_INIT;
657	657	RRdecode(decode, 0, 1);
658		hyperstone_neg(cpustate, decode);
	658	hyperstone_neg(decode);
659	659	}
660	660
661		static void hyperstone_op5a(hyperstone_state *cpustate)
	661	void hyperstone_device::op5a()
662	662	{
663	663	LOCAL_DECODE_INIT;
664	664	RRdecode(decode, 1, 0);
665		hyperstone_neg(cpustate, decode);
	665	hyperstone_neg(decode);
666	666	}
667	667
668		static void hyperstone_op5b(hyperstone_state *cpustate)
	668	void hyperstone_device::op5b()
669	669	{
670	670	LOCAL_DECODE_INIT;
671	671	RRdecode(decode, 1, 1);
672		hyperstone_neg(cpustate, decode);
	672	hyperstone_neg(decode);
673	673	}
674	674
675		static void hyperstone_op5c(hyperstone_state *cpustate)
	675	void hyperstone_device::op5c()
676	676	{
677	677	LOCAL_DECODE_INIT;
678	678	RRdecode(decode, 0, 0);
679		hyperstone_negs(cpustate, decode);
	679	hyperstone_negs(decode);
680	680	}
681	681
682		static void hyperstone_op5d(hyperstone_state *cpustate)
	682	void hyperstone_device::op5d()
683	683	{
684	684	LOCAL_DECODE_INIT;
685	685	RRdecode(decode, 0, 1);
686		hyperstone_negs(cpustate, decode);
	686	hyperstone_negs(decode);
687	687	}
688	688
689		static void hyperstone_op5e(hyperstone_state *cpustate)
	689	void hyperstone_device::op5e()
690	690	{
691	691	LOCAL_DECODE_INIT;
692	692	RRdecode(decode, 1, 0);
693		hyperstone_negs(cpustate, decode);
	693	hyperstone_negs(decode);
694	694	}
695	695
696		static void hyperstone_op5f(hyperstone_state *cpustate)
	696	void hyperstone_device::op5f()
697	697	{
698	698	LOCAL_DECODE_INIT;
699	699	RRdecode(decode, 1, 1);
700		hyperstone_negs(cpustate, decode);
	700	hyperstone_negs(decode);
701	701	}
702	702
703	703
704	704
705		static void hyperstone_op60(hyperstone_state *cpustate)
	705	void hyperstone_device::op60()
706	706	{
707	707	LOCAL_DECODE_INIT;
708	708	Rimmdecode(decode, 0, 0);
709		hyperstone_cmpi(cpustate, decode);
	709	hyperstone_cmpi(decode);
710	710	}
711	711
712		static void hyperstone_op61(hyperstone_state *cpustate)
	712	void hyperstone_device::op61()
713	713	{
714	714	LOCAL_DECODE_INIT;
715	715	Rimmdecode(decode, 0, 1);
716		hyperstone_cmpi(cpustate, decode);
	716	hyperstone_cmpi(decode);
717	717	}
718	718
719		static void hyperstone_op62(hyperstone_state *cpustate)
	719	void hyperstone_device::op62()
720	720	{
721	721	LOCAL_DECODE_INIT;
722	722	Rimmdecode(decode, 1, 0);
723		hyperstone_cmpi(cpustate, decode);
	723	hyperstone_cmpi(decode);
724	724	}
725	725
726		static void hyperstone_op63(hyperstone_state *cpustate)
	726	void hyperstone_device::op63()
727	727	{
728	728	LOCAL_DECODE_INIT;
729	729	Rimmdecode(decode, 1, 1);
730		hyperstone_cmpi(cpustate, decode);
	730	hyperstone_cmpi(decode);
731	731	}
732	732
733		static void hyperstone_op64(hyperstone_state *cpustate)
	733	void hyperstone_device::op64()
734	734	{
735	735	LOCAL_DECODE_INIT;
736	736	RimmdecodewithHflag(decode, 0, 0);
737		hyperstone_movi(cpustate, decode);
	737	hyperstone_movi(decode);
738	738	}
739	739
740		static void hyperstone_op65(hyperstone_state *cpustate)
	740	void hyperstone_device::op65()
741	741	{
742	742	LOCAL_DECODE_INIT;
743	743	RimmdecodewithHflag(decode, 0, 1);
744		hyperstone_movi(cpustate, decode);
	744	hyperstone_movi(decode);
745	745	}
746	746
747		static void hyperstone_op66(hyperstone_state *cpustate)
	747	void hyperstone_device::op66()
748	748	{
749	749	LOCAL_DECODE_INIT;
750	750	RimmdecodewithHflag(decode, 1, 0);
751		hyperstone_movi(cpustate, decode);
	751	hyperstone_movi(decode);
752	752	}
753	753
754		static void hyperstone_op67(hyperstone_state *cpustate)
	754	void hyperstone_device::op67()
755	755	{
756	756	LOCAL_DECODE_INIT;
757	757	RimmdecodewithHflag(decode, 1, 1);
758		hyperstone_movi(cpustate, decode);
	758	hyperstone_movi(decode);
759	759	}
760	760
761		static void hyperstone_op68(hyperstone_state *cpustate)
	761	void hyperstone_device::op68()
762	762	{
763	763	LOCAL_DECODE_INIT;
764	764	Rimmdecode(decode, 0, 0);
765		hyperstone_addi(cpustate, decode);
	765	hyperstone_addi(decode);
766	766	}
767	767
768		static void hyperstone_op69(hyperstone_state *cpustate)
	768	void hyperstone_device::op69()
769	769	{
770	770	LOCAL_DECODE_INIT;
771	771	Rimmdecode(decode, 0, 1);
772		hyperstone_addi(cpustate, decode);
	772	hyperstone_addi(decode);
773	773	}
774	774
775		static void hyperstone_op6a(hyperstone_state *cpustate)
	775	void hyperstone_device::op6a()
776	776	{
777	777	LOCAL_DECODE_INIT;
778	778	Rimmdecode(decode, 1, 0);
779		hyperstone_addi(cpustate, decode);
	779	hyperstone_addi(decode);
780	780	}
781	781
782		static void hyperstone_op6b(hyperstone_state *cpustate)
	782	void hyperstone_device::op6b()
783	783	{
784	784	LOCAL_DECODE_INIT;
785	785	Rimmdecode(decode, 1, 1);
786		hyperstone_addi(cpustate, decode);
	786	hyperstone_addi(decode);
787	787	}
788	788
789		static void hyperstone_op6c(hyperstone_state *cpustate)
	789	void hyperstone_device::op6c()
790	790	{
791	791	LOCAL_DECODE_INIT;
792	792	Rimmdecode(decode, 0, 0);
793		hyperstone_addsi(cpustate, decode);
	793	hyperstone_addsi(decode);
794	794	}
795	795
796		static void hyperstone_op6d(hyperstone_state *cpustate)
	796	void hyperstone_device::op6d()
797	797	{
798	798	LOCAL_DECODE_INIT;
799	799	Rimmdecode(decode, 0, 1);
800		hyperstone_addsi(cpustate, decode);
	800	hyperstone_addsi(decode);
801	801	}
802	802
803		static void hyperstone_op6e(hyperstone_state *cpustate)
	803	void hyperstone_device::op6e()
804	804	{
805	805	LOCAL_DECODE_INIT;
806	806	Rimmdecode(decode, 1, 0);
807		hyperstone_addsi(cpustate, decode);
	807	hyperstone_addsi(decode);
808	808	}
809	809
810		static void hyperstone_op6f(hyperstone_state *cpustate)
	810	void hyperstone_device::op6f()
811	811	{
812	812	LOCAL_DECODE_INIT;
813	813	Rimmdecode(decode, 1, 1);
814		hyperstone_addsi(cpustate, decode);
	814	hyperstone_addsi(decode);
815	815	}
816	816
817	817
818	818
819		static void hyperstone_op70(hyperstone_state *cpustate)
	819	void hyperstone_device::op70()
820	820	{
821	821	LOCAL_DECODE_INIT;
822	822	Rimmdecode(decode, 0, 0);
823		hyperstone_cmpbi(cpustate, decode);
	823	hyperstone_cmpbi(decode);
824	824	}
825	825
826		static void hyperstone_op71(hyperstone_state *cpustate)
	826	void hyperstone_device::op71()
827	827	{
828	828	LOCAL_DECODE_INIT;
829	829	Rimmdecode(decode, 0, 1);
830		hyperstone_cmpbi(cpustate, decode);
	830	hyperstone_cmpbi(decode);
831	831	}
832	832
833		static void hyperstone_op72(hyperstone_state *cpustate)
	833	void hyperstone_device::op72()
834	834	{
835	835	LOCAL_DECODE_INIT;
836	836	Rimmdecode(decode, 1, 0);
837		hyperstone_cmpbi(cpustate, decode);
	837	hyperstone_cmpbi(decode);
838	838	}
839	839
840		static void hyperstone_op73(hyperstone_state *cpustate)
	840	void hyperstone_device::op73()
841	841	{
842	842	LOCAL_DECODE_INIT;
843	843	Rimmdecode(decode, 1, 1);
844		hyperstone_cmpbi(cpustate, decode);
	844	hyperstone_cmpbi(decode);
845	845	}
846	846
847		static void hyperstone_op74(hyperstone_state *cpustate)
	847	void hyperstone_device::op74()
848	848	{
849	849	LOCAL_DECODE_INIT;
850	850	Rimmdecode(decode, 0, 0);
851		hyperstone_andni(cpustate, decode);
	851	hyperstone_andni(decode);
852	852	}
853	853
854		static void hyperstone_op75(hyperstone_state *cpustate)
	854	void hyperstone_device::op75()
855	855	{
856	856	LOCAL_DECODE_INIT;
857	857	Rimmdecode(decode, 0, 1);
858		hyperstone_andni(cpustate, decode);
	858	hyperstone_andni(decode);
859	859	}
860	860
861		static void hyperstone_op76(hyperstone_state *cpustate)
	861	void hyperstone_device::op76()
862	862	{
863	863	LOCAL_DECODE_INIT;
864	864	Rimmdecode(decode, 1, 0);
865		hyperstone_andni(cpustate, decode);
	865	hyperstone_andni(decode);
866	866	}
867	867
868		static void hyperstone_op77(hyperstone_state *cpustate)
	868	void hyperstone_device::op77()
869	869	{
870	870	LOCAL_DECODE_INIT;
871	871	Rimmdecode(decode, 1, 1);
872		hyperstone_andni(cpustate, decode);
	872	hyperstone_andni(decode);
873	873	}
874	874
875		static void hyperstone_op78(hyperstone_state *cpustate)
	875	void hyperstone_device::op78()
876	876	{
877	877	LOCAL_DECODE_INIT;
878	878	Rimmdecode(decode, 0, 0);
879		hyperstone_ori(cpustate, decode);
	879	hyperstone_ori(decode);
880	880	}
881	881
882		static void hyperstone_op79(hyperstone_state *cpustate)
	882	void hyperstone_device::op79()
883	883	{
884	884	LOCAL_DECODE_INIT;
885	885	Rimmdecode(decode, 0, 1);
886		hyperstone_ori(cpustate, decode);
	886	hyperstone_ori(decode);
887	887	}
888	888
889		static void hyperstone_op7a(hyperstone_state *cpustate)
	889	void hyperstone_device::op7a()
890	890	{
891	891	LOCAL_DECODE_INIT;
892	892	Rimmdecode(decode, 1, 0);
893		hyperstone_ori(cpustate, decode);
	893	hyperstone_ori(decode);
894	894	}
895	895
896		static void hyperstone_op7b(hyperstone_state *cpustate)
	896	void hyperstone_device::op7b()
897	897	{
898	898	LOCAL_DECODE_INIT;
899	899	Rimmdecode(decode, 1, 1);
900		hyperstone_ori(cpustate, decode);
	900	hyperstone_ori(decode);
901	901	}
902	902
903		static void hyperstone_op7c(hyperstone_state *cpustate)
	903	void hyperstone_device::op7c()
904	904	{
905	905	LOCAL_DECODE_INIT;
906	906	Rimmdecode(decode, 0, 0);
907		hyperstone_xori(cpustate, decode);
	907	hyperstone_xori(decode);
908	908	}
909	909
910		static void hyperstone_op7d(hyperstone_state *cpustate)
	910	void hyperstone_device::op7d()
911	911	{
912	912	LOCAL_DECODE_INIT;
913	913	Rimmdecode(decode, 0, 1);
914		hyperstone_xori(cpustate, decode);
	914	hyperstone_xori(decode);
915	915	}
916	916
917		static void hyperstone_op7e(hyperstone_state *cpustate)
	917	void hyperstone_device::op7e()
918	918	{
919	919	LOCAL_DECODE_INIT;
920	920	Rimmdecode(decode, 1, 0);
921		hyperstone_xori(cpustate, decode);
	921	hyperstone_xori(decode);
922	922	}
923	923
924		static void hyperstone_op7f(hyperstone_state *cpustate)
	924	void hyperstone_device::op7f()
925	925	{
926	926	LOCAL_DECODE_INIT;
927	927	Rimmdecode(decode, 1, 1);
928		hyperstone_xori(cpustate, decode);
	928	hyperstone_xori(decode);
929	929	}
930	930
931	931
932	932
933		static void hyperstone_op80(hyperstone_state *cpustate)
	933	void hyperstone_device::op80()
934	934	{
935	935	LOCAL_DECODE_INIT;
936	936	Lndecode(decode);
937		hyperstone_shrdi(cpustate, decode);
	937	hyperstone_shrdi(decode);
938	938	}
939	939
940		static void hyperstone_op81(hyperstone_state *cpustate)
	940	void hyperstone_device::op81()
941	941	{
942	942	LOCAL_DECODE_INIT;
943	943	Lndecode(decode);
944		hyperstone_shrdi(cpustate, decode);
	944	hyperstone_shrdi(decode);
945	945	}
946	946
947		static void hyperstone_op82(hyperstone_state *cpustate)
	947	void hyperstone_device::op82()
948	948	{
949	949	LOCAL_DECODE_INIT;
950	950	LLdecode(decode);
951		hyperstone_shrd(cpustate, decode);
	951	hyperstone_shrd(decode);
952	952	}
953	953
954		static void hyperstone_op83(hyperstone_state *cpustate)
	954	void hyperstone_device::op83()
955	955	{
956	956	LOCAL_DECODE_INIT;
957	957	LLdecode(decode);
958		hyperstone_shr(cpustate, decode);
	958	hyperstone_shr(decode);
959	959	}
960	960
961		static void hyperstone_op84(hyperstone_state *cpustate)
	961	void hyperstone_device::op84()
962	962	{
963	963	LOCAL_DECODE_INIT;
964	964	Lndecode(decode);
965		hyperstone_sardi(cpustate, decode);
	965	hyperstone_sardi(decode);
966	966	}
967	967
968		static void hyperstone_op85(hyperstone_state *cpustate)
	968	void hyperstone_device::op85()
969	969	{
970	970	LOCAL_DECODE_INIT;
971	971	Lndecode(decode);
972		hyperstone_sardi(cpustate, decode);
	972	hyperstone_sardi(decode);
973	973	}
974	974
975		static void hyperstone_op86(hyperstone_state *cpustate)
	975	void hyperstone_device::op86()
976	976	{
977	977	LOCAL_DECODE_INIT;
978	978	LLdecode(decode);
979		hyperstone_sard(cpustate, decode);
	979	hyperstone_sard(decode);
980	980	}
981	981
982		static void hyperstone_op87(hyperstone_state *cpustate)
	982	void hyperstone_device::op87()
983	983	{
984	984	LOCAL_DECODE_INIT;
985	985	LLdecode(decode);
986		hyperstone_sar(cpustate, decode);
	986	hyperstone_sar(decode);
987	987	}
988	988
989		static void hyperstone_op88(hyperstone_state *cpustate)
	989	void hyperstone_device::op88()
990	990	{
991	991	LOCAL_DECODE_INIT;
992	992	Lndecode(decode);
993		hyperstone_shldi(cpustate, decode);
	993	hyperstone_shldi(decode);
994	994	}
995	995
996		static void hyperstone_op89(hyperstone_state *cpustate)
	996	void hyperstone_device::op89()
997	997	{
998	998	LOCAL_DECODE_INIT;
999	999	Lndecode(decode);
1000		hyperstone_shldi(cpustate, decode);
	1000	hyperstone_shldi(decode);
1001	1001	}
1002	1002
1003		static void hyperstone_op8a(hyperstone_state *cpustate)
	1003	void hyperstone_device::op8a()
1004	1004	{
1005	1005	LOCAL_DECODE_INIT;
1006	1006	LLdecode(decode);
1007		hyperstone_shld(cpustate, decode);
	1007	hyperstone_shld(decode);
1008	1008	}
1009	1009
1010		static void hyperstone_op8b(hyperstone_state *cpustate)
	1010	void hyperstone_device::op8b()
1011	1011	{
1012	1012	LOCAL_DECODE_INIT;
1013	1013	LLdecode(decode);
1014		hyperstone_shl(cpustate, decode);
	1014	hyperstone_shl(decode);
1015	1015	}
1016	1016
1017		static void hyperstone_op8c(hyperstone_state *cpustate)
	1017	void hyperstone_device::op8c()
1018	1018	{
1019	1019	LOCAL_DECODE_INIT;
1020	1020	no_decode(decode);
1021		reserved(cpustate, decode);
	1021	reserved(decode);
1022	1022	}
1023	1023
1024		static void hyperstone_op8d(hyperstone_state *cpustate)
	1024	void hyperstone_device::op8d()
1025	1025	{
1026	1026	LOCAL_DECODE_INIT;
1027	1027	no_decode(decode);
1028		reserved(cpustate, decode);
	1028	reserved(decode);
1029	1029	}
1030	1030
1031		static void hyperstone_op8e(hyperstone_state *cpustate)
	1031	void hyperstone_device::op8e()
1032	1032	{
1033	1033	LOCAL_DECODE_INIT;
1034	1034	LLdecode(decode);
1035		hyperstone_testlz(cpustate, decode);
	1035	hyperstone_testlz(decode);
1036	1036	}
1037	1037
1038		static void hyperstone_op8f(hyperstone_state *cpustate)
	1038	void hyperstone_device::op8f()
1039	1039	{
1040	1040	LOCAL_DECODE_INIT;
1041	1041	LLdecode(decode);
1042		hyperstone_rol(cpustate, decode);
	1042	hyperstone_rol(decode);
1043	1043	}
1044	1044
1045	1045
1046	1046
1047		static void hyperstone_op90(hyperstone_state *cpustate)
	1047	void hyperstone_device::op90()
1048	1048	{
1049	1049	LOCAL_DECODE_INIT;
1050	1050	RRdisdecode(decode, 0, 0);
1051		hyperstone_ldxx1(cpustate, decode);
	1051	hyperstone_ldxx1(decode);
1052	1052	}
1053	1053
1054		static void hyperstone_op91(hyperstone_state *cpustate)
	1054	void hyperstone_device::op91()
1055	1055	{
1056	1056	LOCAL_DECODE_INIT;
1057	1057	RRdisdecode(decode, 0, 1);
1058		hyperstone_ldxx1(cpustate, decode);
	1058	hyperstone_ldxx1(decode);
1059	1059	}
1060	1060
1061		static void hyperstone_op92(hyperstone_state *cpustate)
	1061	void hyperstone_device::op92()
1062	1062	{
1063	1063	LOCAL_DECODE_INIT;
1064	1064	RRdisdecode(decode, 1, 0);
1065		hyperstone_ldxx1(cpustate, decode);
	1065	hyperstone_ldxx1(decode);
1066	1066	}
1067	1067
1068		static void hyperstone_op93(hyperstone_state *cpustate)
	1068	void hyperstone_device::op93()
1069	1069	{
1070	1070	LOCAL_DECODE_INIT;
1071	1071	RRdisdecode(decode, 1, 1);
1072		hyperstone_ldxx1(cpustate, decode);
	1072	hyperstone_ldxx1(decode);
1073	1073	}
1074	1074
1075		static void hyperstone_op94(hyperstone_state *cpustate)
	1075	void hyperstone_device::op94()
1076	1076	{
1077	1077	LOCAL_DECODE_INIT;
1078	1078	RRdisdecode(decode, 0, 0);
1079		hyperstone_ldxx2(cpustate, decode);
	1079	hyperstone_ldxx2(decode);
1080	1080	}
1081	1081
1082		static void hyperstone_op95(hyperstone_state *cpustate)
	1082	void hyperstone_device::op95()
1083	1083	{
1084	1084	LOCAL_DECODE_INIT;
1085	1085	RRdisdecode(decode, 0, 1);
1086		hyperstone_ldxx2(cpustate, decode);
	1086	hyperstone_ldxx2(decode);
1087	1087	}
1088	1088
1089		static void hyperstone_op96(hyperstone_state *cpustate)
	1089	void hyperstone_device::op96()
1090	1090	{
1091	1091	LOCAL_DECODE_INIT;
1092	1092	RRdisdecode(decode, 1, 0);
1093		hyperstone_ldxx2(cpustate, decode);
	1093	hyperstone_ldxx2(decode);
1094	1094	}
1095	1095
1096		static void hyperstone_op97(hyperstone_state *cpustate)
	1096	void hyperstone_device::op97()
1097	1097	{
1098	1098	LOCAL_DECODE_INIT;
1099	1099	RRdisdecode(decode, 1, 1);
1100		hyperstone_ldxx2(cpustate, decode);
	1100	hyperstone_ldxx2(decode);
1101	1101	}
1102	1102
1103		static void hyperstone_op98(hyperstone_state *cpustate)
	1103	void hyperstone_device::op98()
1104	1104	{
1105	1105	LOCAL_DECODE_INIT;
1106	1106	RRdisdecode(decode, 0, 0);
1107		hyperstone_stxx1(cpustate, decode);
	1107	hyperstone_stxx1(decode);
1108	1108	}
1109	1109
1110		static void hyperstone_op99(hyperstone_state *cpustate)
	1110	void hyperstone_device::op99()
1111	1111	{
1112	1112	LOCAL_DECODE_INIT;
1113	1113	RRdisdecode(decode, 0, 1);
1114		hyperstone_stxx1(cpustate, decode);
	1114	hyperstone_stxx1(decode);
1115	1115	}
1116	1116
1117		static void hyperstone_op9a(hyperstone_state *cpustate)
	1117	void hyperstone_device::op9a()
1118	1118	{
1119	1119	LOCAL_DECODE_INIT;
1120	1120	RRdisdecode(decode, 1, 0);
1121		hyperstone_stxx1(cpustate, decode);
	1121	hyperstone_stxx1(decode);
1122	1122	}
1123	1123
1124		static void hyperstone_op9b(hyperstone_state *cpustate)
	1124	void hyperstone_device::op9b()
1125	1125	{
1126	1126	LOCAL_DECODE_INIT;
1127	1127	RRdisdecode(decode, 1, 1);
1128		hyperstone_stxx1(cpustate, decode);
	1128	hyperstone_stxx1(decode);
1129	1129	}
1130	1130
1131		static void hyperstone_op9c(hyperstone_state *cpustate)
	1131	void hyperstone_device::op9c()
1132	1132	{
1133	1133	LOCAL_DECODE_INIT;
1134	1134	RRdisdecode(decode, 0, 0);
1135		hyperstone_stxx2(cpustate, decode);
	1135	hyperstone_stxx2(decode);
1136	1136	}
1137	1137
1138		static void hyperstone_op9d(hyperstone_state *cpustate)
	1138	void hyperstone_device::op9d()
1139	1139	{
1140	1140	LOCAL_DECODE_INIT;
1141	1141	RRdisdecode(decode, 0, 1);
1142		hyperstone_stxx2(cpustate, decode);
	1142	hyperstone_stxx2(decode);
1143	1143	}
1144	1144
1145		static void hyperstone_op9e(hyperstone_state *cpustate)
	1145	void hyperstone_device::op9e()
1146	1146	{
1147	1147	LOCAL_DECODE_INIT;
1148	1148	RRdisdecode(decode, 1, 0);
1149		hyperstone_stxx2(cpustate, decode);
	1149	hyperstone_stxx2(decode);
1150	1150	}
1151	1151
1152		static void hyperstone_op9f(hyperstone_state *cpustate)
	1152	void hyperstone_device::op9f()
1153	1153	{
1154	1154	LOCAL_DECODE_INIT;
1155	1155	RRdisdecode(decode, 1, 1);
1156		hyperstone_stxx2(cpustate, decode);
	1156	hyperstone_stxx2(decode);
1157	1157	}
1158	1158
1159	1159
1160	1160
1161		static void hyperstone_opa0(hyperstone_state *cpustate)
	1161	void hyperstone_device::opa0()
1162	1162	{
1163	1163	LOCAL_DECODE_INIT;
1164	1164	Rndecode(decode, 0);
1165		hyperstone_shri(cpustate, decode);
	1165	hyperstone_shri(decode);
1166	1166	}
1167	1167
1168		static void hyperstone_opa1(hyperstone_state *cpustate)
	1168	void hyperstone_device::opa1()
1169	1169	{
1170	1170	LOCAL_DECODE_INIT;
1171	1171	Rndecode(decode, 0);
1172		hyperstone_shri(cpustate, decode);
	1172	hyperstone_shri(decode);
1173	1173	}
1174	1174
1175		static void hyperstone_opa2(hyperstone_state *cpustate)
	1175	void hyperstone_device::opa2()
1176	1176	{
1177	1177	LOCAL_DECODE_INIT;
1178	1178	Rndecode(decode, 1);
1179		hyperstone_shri(cpustate, decode);
	1179	hyperstone_shri(decode);
1180	1180	}
1181	1181
1182		static void hyperstone_opa3(hyperstone_state *cpustate)
	1182	void hyperstone_device::opa3()
1183	1183	{
1184	1184	LOCAL_DECODE_INIT;
1185	1185	Rndecode(decode, 1);
1186		hyperstone_shri(cpustate, decode);
	1186	hyperstone_shri(decode);
1187	1187	}
1188	1188
1189		static void hyperstone_opa4(hyperstone_state *cpustate)
	1189	void hyperstone_device::opa4()
1190	1190	{
1191	1191	LOCAL_DECODE_INIT;
1192	1192	Rndecode(decode, 0);
1193		hyperstone_sari(cpustate, decode);
	1193	hyperstone_sari(decode);
1194	1194	}
1195	1195
1196		static void hyperstone_opa5(hyperstone_state *cpustate)
	1196	void hyperstone_device::opa5()
1197	1197	{
1198	1198	LOCAL_DECODE_INIT;
1199	1199	Rndecode(decode, 0);
1200		hyperstone_sari(cpustate, decode);
	1200	hyperstone_sari(decode);
1201	1201	}
1202	1202
1203		static void hyperstone_opa6(hyperstone_state *cpustate)
	1203	void hyperstone_device::opa6()
1204	1204	{
1205	1205	LOCAL_DECODE_INIT;
1206	1206	Rndecode(decode, 1);
1207		hyperstone_sari(cpustate, decode);
	1207	hyperstone_sari(decode);
1208	1208	}
1209	1209
1210		static void hyperstone_opa7(hyperstone_state *cpustate)
	1210	void hyperstone_device::opa7()
1211	1211	{
1212	1212	LOCAL_DECODE_INIT;
1213	1213	Rndecode(decode, 1);
1214		hyperstone_sari(cpustate, decode);
	1214	hyperstone_sari(decode);
1215	1215	}
1216	1216
1217		static void hyperstone_opa8(hyperstone_state *cpustate)
	1217	void hyperstone_device::opa8()
1218	1218	{
1219	1219	LOCAL_DECODE_INIT;
1220	1220	Rndecode(decode, 0);
1221		hyperstone_shli(cpustate, decode);
	1221	hyperstone_shli(decode);
1222	1222	}
1223	1223
1224		static void hyperstone_opa9(hyperstone_state *cpustate)
	1224	void hyperstone_device::opa9()
1225	1225	{
1226	1226	LOCAL_DECODE_INIT;
1227	1227	Rndecode(decode, 0);
1228		hyperstone_shli(cpustate, decode);
	1228	hyperstone_shli(decode);
1229	1229	}
1230	1230
1231		static void hyperstone_opaa(hyperstone_state *cpustate)
	1231	void hyperstone_device::opaa()
1232	1232	{
1233	1233	LOCAL_DECODE_INIT;
1234	1234	Rndecode(decode, 1);
1235		hyperstone_shli(cpustate, decode);
	1235	hyperstone_shli(decode);
1236	1236	}
1237	1237
1238		static void hyperstone_opab(hyperstone_state *cpustate)
	1238	void hyperstone_device::opab()
1239	1239	{
1240	1240	LOCAL_DECODE_INIT;
1241	1241	Rndecode(decode, 1);
1242		hyperstone_shli(cpustate, decode);
	1242	hyperstone_shli(decode);
1243	1243	}
1244	1244
1245		static void hyperstone_opac(hyperstone_state *cpustate)
	1245	void hyperstone_device::opac()
1246	1246	{
1247	1247	LOCAL_DECODE_INIT;
1248	1248	no_decode(decode);
1249		reserved(cpustate, decode);
	1249	reserved(decode);
1250	1250	}
1251	1251
1252		static void hyperstone_opad(hyperstone_state *cpustate)
	1252	void hyperstone_device::opad()
1253	1253	{
1254	1254	LOCAL_DECODE_INIT;
1255	1255	no_decode(decode);
1256		reserved(cpustate, decode);
	1256	reserved(decode);
1257	1257	}
1258	1258
1259		static void hyperstone_opae(hyperstone_state *cpustate)
	1259	void hyperstone_device::opae()
1260	1260	{
1261	1261	LOCAL_DECODE_INIT;
1262	1262	no_decode(decode);
1263		reserved(cpustate, decode);
	1263	reserved(decode);
1264	1264	}
1265	1265
1266		static void hyperstone_opaf(hyperstone_state *cpustate)
	1266	void hyperstone_device::opaf()
1267	1267	{
1268	1268	LOCAL_DECODE_INIT;
1269	1269	no_decode(decode);
1270		reserved(cpustate, decode);
	1270	reserved(decode);
1271	1271	}
1272	1272
1273	1273
1274	1274
1275		static void hyperstone_opb0(hyperstone_state *cpustate)
	1275	void hyperstone_device::opb0()
1276	1276	{
1277	1277	LOCAL_DECODE_INIT;
1278	1278	RRdecode(decode, 0, 0);
1279		hyperstone_mulu(cpustate, decode);
	1279	hyperstone_mulu(decode);
1280	1280	}
1281	1281
1282		static void hyperstone_opb1(hyperstone_state *cpustate)
	1282	void hyperstone_device::opb1()
1283	1283	{
1284	1284	LOCAL_DECODE_INIT;
1285	1285	RRdecode(decode, 0, 1);
1286		hyperstone_mulu(cpustate, decode);
	1286	hyperstone_mulu(decode);
1287	1287	}
1288	1288
1289		static void hyperstone_opb2(hyperstone_state *cpustate)
	1289	void hyperstone_device::opb2()
1290	1290	{
1291	1291	LOCAL_DECODE_INIT;
1292	1292	RRdecode(decode, 1, 0);
1293		hyperstone_mulu(cpustate, decode);
	1293	hyperstone_mulu(decode);
1294	1294	}
1295	1295
1296		static void hyperstone_opb3(hyperstone_state *cpustate)
	1296	void hyperstone_device::opb3()
1297	1297	{
1298	1298	LOCAL_DECODE_INIT;
1299	1299	RRdecode(decode, 1, 1);
1300		hyperstone_mulu(cpustate, decode);
	1300	hyperstone_mulu(decode);
1301	1301	}
1302	1302
1303		static void hyperstone_opb4(hyperstone_state *cpustate)
	1303	void hyperstone_device::opb4()
1304	1304	{
1305	1305	LOCAL_DECODE_INIT;
1306	1306	RRdecode(decode, 0, 0);
1307		hyperstone_muls(cpustate, decode);
	1307	hyperstone_muls(decode);
1308	1308	}
1309	1309
1310		static void hyperstone_opb5(hyperstone_state *cpustate)
	1310	void hyperstone_device::opb5()
1311	1311	{
1312	1312	LOCAL_DECODE_INIT;
1313	1313	RRdecode(decode, 0, 1);
1314		hyperstone_muls(cpustate, decode);
	1314	hyperstone_muls(decode);
1315	1315	}
1316	1316
1317		static void hyperstone_opb6(hyperstone_state *cpustate)
	1317	void hyperstone_device::opb6()
1318	1318	{
1319	1319	LOCAL_DECODE_INIT;
1320	1320	RRdecode(decode, 1, 0);
1321		hyperstone_muls(cpustate, decode);
	1321	hyperstone_muls(decode);
1322	1322	}
1323	1323
1324		static void hyperstone_opb7(hyperstone_state *cpustate)
	1324	void hyperstone_device::opb7()
1325	1325	{
1326	1326	LOCAL_DECODE_INIT;
1327	1327	RRdecode(decode, 1, 1);
1328		hyperstone_muls(cpustate, decode);
	1328	hyperstone_muls(decode);
1329	1329	}
1330	1330
1331		static void hyperstone_opb8(hyperstone_state *cpustate)
	1331	void hyperstone_device::opb8()
1332	1332	{
1333	1333	LOCAL_DECODE_INIT;
1334	1334	Rndecode(decode, 0);
1335		hyperstone_set(cpustate, decode);
	1335	hyperstone_set(decode);
1336	1336	}
1337	1337
1338		static void hyperstone_opb9(hyperstone_state *cpustate)
	1338	void hyperstone_device::opb9()
1339	1339	{
1340	1340	LOCAL_DECODE_INIT;
1341	1341	Rndecode(decode, 0);
1342		hyperstone_set(cpustate, decode);
	1342	hyperstone_set(decode);
1343	1343	}
1344	1344
1345		static void hyperstone_opba(hyperstone_state *cpustate)
	1345	void hyperstone_device::opba()
1346	1346	{
1347	1347	LOCAL_DECODE_INIT;
1348	1348	Rndecode(decode, 1);
1349		hyperstone_set(cpustate, decode);
	1349	hyperstone_set(decode);
1350	1350	}
1351	1351
1352		static void hyperstone_opbb(hyperstone_state *cpustate)
	1352	void hyperstone_device::opbb()
1353	1353	{
1354	1354	LOCAL_DECODE_INIT;
1355	1355	Rndecode(decode, 1);
1356		hyperstone_set(cpustate, decode);
	1356	hyperstone_set(decode);
1357	1357	}
1358	1358
1359		static void hyperstone_opbc(hyperstone_state *cpustate)
	1359	void hyperstone_device::opbc()
1360	1360	{
1361	1361	LOCAL_DECODE_INIT;
1362	1362	RRdecode(decode, 0, 0);
1363		hyperstone_mul(cpustate, decode);
	1363	hyperstone_mul(decode);
1364	1364	}
1365	1365
1366		static void hyperstone_opbd(hyperstone_state *cpustate)
	1366	void hyperstone_device::opbd()
1367	1367	{
1368	1368	LOCAL_DECODE_INIT;
1369	1369	RRdecode(decode, 0, 1);
1370		hyperstone_mul(cpustate, decode);
	1370	hyperstone_mul(decode);
1371	1371	}
1372	1372
1373		static void hyperstone_opbe(hyperstone_state *cpustate)
	1373	void hyperstone_device::opbe()
1374	1374	{
1375	1375	LOCAL_DECODE_INIT;
1376	1376	RRdecode(decode, 1, 0);
1377		hyperstone_mul(cpustate, decode);
	1377	hyperstone_mul(decode);
1378	1378	}
1379	1379
1380		static void hyperstone_opbf(hyperstone_state *cpustate)
	1380	void hyperstone_device::opbf()
1381	1381	{
1382	1382	LOCAL_DECODE_INIT;
1383	1383	RRdecode(decode, 1, 1);
1384		hyperstone_mul(cpustate, decode);
	1384	hyperstone_mul(decode);
1385	1385	}
1386	1386
1387	1387
1388	1388
1389		static void hyperstone_opc0(hyperstone_state *cpustate)
	1389	void hyperstone_device::opc0()
1390	1390	{
1391	1391	LOCAL_DECODE_INIT;
1392	1392	LLdecode(decode);
1393		hyperstone_fadd(cpustate, decode);
	1393	hyperstone_fadd(decode);
1394	1394	}
1395	1395
1396		static void hyperstone_opc1(hyperstone_state *cpustate)
	1396	void hyperstone_device::opc1()
1397	1397	{
1398	1398	LOCAL_DECODE_INIT;
1399	1399	LLdecode(decode);
1400		hyperstone_faddd(cpustate, decode);
	1400	hyperstone_faddd(decode);
1401	1401	}
1402	1402
1403		static void hyperstone_opc2(hyperstone_state *cpustate)
	1403	void hyperstone_device::opc2()
1404	1404	{
1405	1405	LOCAL_DECODE_INIT;
1406	1406	LLdecode(decode);
1407		hyperstone_fsub(cpustate, decode);
	1407	hyperstone_fsub(decode);
1408	1408	}
1409	1409
1410		static void hyperstone_opc3(hyperstone_state *cpustate)
	1410	void hyperstone_device::opc3()
1411	1411	{
1412	1412	LOCAL_DECODE_INIT;
1413	1413	LLdecode(decode);
1414		hyperstone_fsubd(cpustate, decode);
	1414	hyperstone_fsubd(decode);
1415	1415	}
1416	1416
1417		static void hyperstone_opc4(hyperstone_state *cpustate)
	1417	void hyperstone_device::opc4()
1418	1418	{
1419	1419	LOCAL_DECODE_INIT;
1420	1420	LLdecode(decode);
1421		hyperstone_fmul(cpustate, decode);
	1421	hyperstone_fmul(decode);
1422	1422	}
1423	1423
1424		static void hyperstone_opc5(hyperstone_state *cpustate)
	1424	void hyperstone_device::opc5()
1425	1425	{
1426	1426	LOCAL_DECODE_INIT;
1427	1427	LLdecode(decode);
1428		hyperstone_fmuld(cpustate, decode);
	1428	hyperstone_fmuld(decode);
1429	1429	}
1430	1430
1431		static void hyperstone_opc6(hyperstone_state *cpustate)
	1431	void hyperstone_device::opc6()
1432	1432	{
1433	1433	LOCAL_DECODE_INIT;
1434	1434	LLdecode(decode);
1435		hyperstone_fdiv(cpustate, decode);
	1435	hyperstone_fdiv(decode);
1436	1436	}
1437	1437
1438		static void hyperstone_opc7(hyperstone_state *cpustate)
	1438	void hyperstone_device::opc7()
1439	1439	{
1440	1440	LOCAL_DECODE_INIT;
1441	1441	LLdecode(decode);
1442		hyperstone_fdivd(cpustate, decode);
	1442	hyperstone_fdivd(decode);
1443	1443	}
1444	1444
1445		static void hyperstone_opc8(hyperstone_state *cpustate)
	1445	void hyperstone_device::opc8()
1446	1446	{
1447	1447	LOCAL_DECODE_INIT;
1448	1448	LLdecode(decode);
1449		hyperstone_fcmp(cpustate, decode);
	1449	hyperstone_fcmp(decode);
1450	1450	}
1451	1451
1452		static void hyperstone_opc9(hyperstone_state *cpustate)
	1452	void hyperstone_device::opc9()
1453	1453	{
1454	1454	LOCAL_DECODE_INIT;
1455	1455	LLdecode(decode);
1456		hyperstone_fcmpd(cpustate, decode);
	1456	hyperstone_fcmpd(decode);
1457	1457	}
1458	1458
1459		static void hyperstone_opca(hyperstone_state *cpustate)
	1459	void hyperstone_device::opca()
1460	1460	{
1461	1461	LOCAL_DECODE_INIT;
1462	1462	LLdecode(decode);
1463		hyperstone_fcmpu(cpustate, decode);
	1463	hyperstone_fcmpu(decode);
1464	1464	}
1465	1465
1466		static void hyperstone_opcb(hyperstone_state *cpustate)
	1466	void hyperstone_device::opcb()
1467	1467	{
1468	1468	LOCAL_DECODE_INIT;
1469	1469	LLdecode(decode);
1470		hyperstone_fcmpud(cpustate, decode);
	1470	hyperstone_fcmpud(decode);
1471	1471	}
1472	1472
1473		static void hyperstone_opcc(hyperstone_state *cpustate)
	1473	void hyperstone_device::opcc()
1474	1474	{
1475	1475	LOCAL_DECODE_INIT;
1476	1476	LLdecode(decode);
1477		hyperstone_fcvt(cpustate, decode);
	1477	hyperstone_fcvt(decode);
1478	1478	}
1479	1479
1480		static void hyperstone_opcd(hyperstone_state *cpustate)
	1480	void hyperstone_device::opcd()
1481	1481	{
1482	1482	LOCAL_DECODE_INIT;
1483	1483	LLdecode(decode);
1484		hyperstone_fcvtd(cpustate, decode);
	1484	hyperstone_fcvtd(decode);
1485	1485	}
1486	1486
1487		static void hyperstone_opce(hyperstone_state *cpustate)
	1487	void hyperstone_device::opce()
1488	1488	{
1489	1489	LOCAL_DECODE_INIT;
1490	1490	LLextdecode(decode);
1491		hyperstone_extend(cpustate, decode);
	1491	hyperstone_extend(decode);
1492	1492	}
1493	1493
1494		static void hyperstone_opcf(hyperstone_state *cpustate)
	1494	void hyperstone_device::opcf()
1495	1495	{
1496	1496	LOCAL_DECODE_INIT;
1497	1497	LLdecode(decode);
1498		hyperstone_do(cpustate, decode);
	1498	hyperstone_do(decode);
1499	1499	}
1500	1500
1501	1501
1502	1502
1503		static void hyperstone_opd0(hyperstone_state *cpustate)
	1503	void hyperstone_device::opd0()
1504	1504	{
1505	1505	LOCAL_DECODE_INIT;
1506	1506	LRdecode(decode, 0);
1507		hyperstone_ldwr(cpustate, decode);
	1507	hyperstone_ldwr(decode);
1508	1508	}
1509	1509
1510		static void hyperstone_opd1(hyperstone_state *cpustate)
	1510	void hyperstone_device::opd1()
1511	1511	{
1512	1512	LOCAL_DECODE_INIT;
1513	1513	LRdecode(decode, 1);
1514		hyperstone_ldwr(cpustate, decode);
	1514	hyperstone_ldwr(decode);
1515	1515	}
1516	1516
1517		static void hyperstone_opd2(hyperstone_state *cpustate)
	1517	void hyperstone_device::opd2()
1518	1518	{
1519	1519	LOCAL_DECODE_INIT;
1520	1520	LRdecode(decode, 0);
1521		hyperstone_lddr(cpustate, decode);
	1521	hyperstone_lddr(decode);
1522	1522	}
1523	1523
1524		static void hyperstone_opd3(hyperstone_state *cpustate)
	1524	void hyperstone_device::opd3()
1525	1525	{
1526	1526	LOCAL_DECODE_INIT;
1527	1527	LRdecode(decode, 1);
1528		hyperstone_lddr(cpustate, decode);
	1528	hyperstone_lddr(decode);
1529	1529	}
1530	1530
1531		static void hyperstone_opd4(hyperstone_state *cpustate)
	1531	void hyperstone_device::opd4()
1532	1532	{
1533	1533	LOCAL_DECODE_INIT;
1534	1534	LRdecode(decode, 0);
1535		hyperstone_ldwp(cpustate, decode);
	1535	hyperstone_ldwp(decode);
1536	1536	}
1537	1537
1538		static void hyperstone_opd5(hyperstone_state *cpustate)
	1538	void hyperstone_device::opd5()
1539	1539	{
1540	1540	LOCAL_DECODE_INIT;
1541	1541	LRdecode(decode, 1);
1542		hyperstone_ldwp(cpustate, decode);
	1542	hyperstone_ldwp(decode);
1543	1543	}
1544	1544
1545		static void hyperstone_opd6(hyperstone_state *cpustate)
	1545	void hyperstone_device::opd6()
1546	1546	{
1547	1547	LOCAL_DECODE_INIT;
1548	1548	LRdecode(decode, 0);
1549		hyperstone_lddp(cpustate, decode);
	1549	hyperstone_lddp(decode);
1550	1550	}
1551	1551
1552		static void hyperstone_opd7(hyperstone_state *cpustate)
	1552	void hyperstone_device::opd7()
1553	1553	{
1554	1554	LOCAL_DECODE_INIT;
1555	1555	LRdecode(decode, 1);
1556		hyperstone_lddp(cpustate, decode);
	1556	hyperstone_lddp(decode);
1557	1557	}
1558	1558
1559		static void hyperstone_opd8(hyperstone_state *cpustate)
	1559	void hyperstone_device::opd8()
1560	1560	{
1561	1561	LOCAL_DECODE_INIT;
1562	1562	LRdecode(decode, 0);
1563		hyperstone_stwr(cpustate, decode);
	1563	hyperstone_stwr(decode);
1564	1564	}
1565	1565
1566		static void hyperstone_opd9(hyperstone_state *cpustate)
	1566	void hyperstone_device::opd9()
1567	1567	{
1568	1568	LOCAL_DECODE_INIT;
1569	1569	LRdecode(decode, 1);
1570		hyperstone_stwr(cpustate, decode);
	1570	hyperstone_stwr(decode);
1571	1571	}
1572	1572
1573		static void hyperstone_opda(hyperstone_state *cpustate)
	1573	void hyperstone_device::opda()
1574	1574	{
1575	1575	LOCAL_DECODE_INIT;
1576	1576	LRdecode(decode, 0);
1577		hyperstone_stdr(cpustate, decode);
	1577	hyperstone_stdr(decode);
1578	1578	}
1579	1579
1580		static void hyperstone_opdb(hyperstone_state *cpustate)
	1580	void hyperstone_device::opdb()
1581	1581	{
1582	1582	LOCAL_DECODE_INIT;
1583	1583	LRdecode(decode, 1);
1584		hyperstone_stdr(cpustate, decode);
	1584	hyperstone_stdr(decode);
1585	1585	}
1586	1586
1587		static void hyperstone_opdc(hyperstone_state *cpustate)
	1587	void hyperstone_device::opdc()
1588	1588	{
1589	1589	LOCAL_DECODE_INIT;
1590	1590	LRdecode(decode, 0);
1591		hyperstone_stwp(cpustate, decode);
	1591	hyperstone_stwp(decode);
1592	1592	}
1593	1593
1594		static void hyperstone_opdd(hyperstone_state *cpustate)
	1594	void hyperstone_device::opdd()
1595	1595	{
1596	1596	LOCAL_DECODE_INIT;
1597	1597	LRdecode(decode, 1);
1598		hyperstone_stwp(cpustate, decode);
	1598	hyperstone_stwp(decode);
1599	1599	}
1600	1600
1601		static void hyperstone_opde(hyperstone_state *cpustate)
	1601	void hyperstone_device::opde()
1602	1602	{
1603	1603	LOCAL_DECODE_INIT;
1604	1604	LRdecode(decode, 0);
1605		hyperstone_stdp(cpustate, decode);
	1605	hyperstone_stdp(decode);
1606	1606	}
1607	1607
1608		static void hyperstone_opdf(hyperstone_state *cpustate)
	1608	void hyperstone_device::opdf()
1609	1609	{
1610	1610	LOCAL_DECODE_INIT;
1611	1611	LRdecode(decode, 1);
1612		hyperstone_stdp(cpustate, decode);
	1612	hyperstone_stdp(decode);
1613	1613	}
1614	1614
1615	1615
1616	1616
1617		static void hyperstone_ope0(hyperstone_state *cpustate)
	1617	void hyperstone_device::ope0()
1618	1618	{
1619	1619	LOCAL_DECODE_INIT;
1620	1620	PCreldecode(decode);
1621		hyperstone_dbv(cpustate, decode);
	1621	hyperstone_dbv(decode);
1622	1622	}
1623	1623
1624		static void hyperstone_ope1(hyperstone_state *cpustate)
	1624	void hyperstone_device::ope1()
1625	1625	{
1626	1626	LOCAL_DECODE_INIT;
1627	1627	PCreldecode(decode);
1628		hyperstone_dbnv(cpustate, decode);
	1628	hyperstone_dbnv(decode);
1629	1629	}
1630	1630
1631		static void hyperstone_ope2(hyperstone_state *cpustate)
	1631	void hyperstone_device::ope2()
1632	1632	{
1633	1633	LOCAL_DECODE_INIT;
1634	1634	PCreldecode(decode);
1635		hyperstone_dbe(cpustate, decode);
	1635	hyperstone_dbe(decode);
1636	1636	}
1637	1637
1638		static void hyperstone_ope3(hyperstone_state *cpustate)
	1638	void hyperstone_device::ope3()
1639	1639	{
1640	1640	LOCAL_DECODE_INIT;
1641	1641	PCreldecode(decode);
1642		hyperstone_dbne(cpustate, decode);
	1642	hyperstone_dbne(decode);
1643	1643	}
1644	1644
1645		static void hyperstone_ope4(hyperstone_state *cpustate)
	1645	void hyperstone_device::ope4()
1646	1646	{
1647	1647	LOCAL_DECODE_INIT;
1648	1648	PCreldecode(decode);
1649		hyperstone_dbc(cpustate, decode);
	1649	hyperstone_dbc(decode);
1650	1650	}
1651	1651
1652		static void hyperstone_ope5(hyperstone_state *cpustate)
	1652	void hyperstone_device::ope5()
1653	1653	{
1654	1654	LOCAL_DECODE_INIT;
1655	1655	PCreldecode(decode);
1656		hyperstone_dbnc(cpustate, decode);
	1656	hyperstone_dbnc(decode);
1657	1657	}
1658	1658
1659		static void hyperstone_ope6(hyperstone_state *cpustate)
	1659	void hyperstone_device::ope6()
1660	1660	{
1661	1661	LOCAL_DECODE_INIT;
1662	1662	PCreldecode(decode);
1663		hyperstone_dbse(cpustate, decode);
	1663	hyperstone_dbse(decode);
1664	1664	}
1665	1665
1666		static void hyperstone_ope7(hyperstone_state *cpustate)
	1666	void hyperstone_device::ope7()
1667	1667	{
1668	1668	LOCAL_DECODE_INIT;
1669	1669	PCreldecode(decode);
1670		hyperstone_dbht(cpustate, decode);
	1670	hyperstone_dbht(decode);
1671	1671	}
1672	1672
1673		static void hyperstone_ope8(hyperstone_state *cpustate)
	1673	void hyperstone_device::ope8()
1674	1674	{
1675	1675	LOCAL_DECODE_INIT;
1676	1676	PCreldecode(decode);
1677		hyperstone_dbn(cpustate, decode);
	1677	hyperstone_dbn(decode);
1678	1678	}
1679	1679
1680		static void hyperstone_ope9(hyperstone_state *cpustate)
	1680	void hyperstone_device::ope9()
1681	1681	{
1682	1682	LOCAL_DECODE_INIT;
1683	1683	PCreldecode(decode);
1684		hyperstone_dbnn(cpustate, decode);
	1684	hyperstone_dbnn(decode);
1685	1685	}
1686	1686
1687		static void hyperstone_opea(hyperstone_state *cpustate)
	1687	void hyperstone_device::opea()
1688	1688	{
1689	1689	LOCAL_DECODE_INIT;
1690	1690	PCreldecode(decode);
1691		hyperstone_dble(cpustate, decode);
	1691	hyperstone_dble(decode);
1692	1692	}
1693	1693
1694		static void hyperstone_opeb(hyperstone_state *cpustate)
	1694	void hyperstone_device::opeb()
1695	1695	{
1696	1696	LOCAL_DECODE_INIT;
1697	1697	PCreldecode(decode);
1698		hyperstone_dbgt(cpustate, decode);
	1698	hyperstone_dbgt(decode);
1699	1699	}
1700	1700
1701		static void hyperstone_opec(hyperstone_state *cpustate)
	1701	void hyperstone_device::opec()
1702	1702	{
1703	1703	LOCAL_DECODE_INIT;
1704	1704	PCreldecode(decode);
1705		hyperstone_dbr(cpustate, decode);
	1705	hyperstone_dbr(decode);
1706	1706	}
1707	1707
1708		static void hyperstone_oped(hyperstone_state *cpustate)
	1708	void hyperstone_device::oped()
1709	1709	{
1710	1710	LOCAL_DECODE_INIT;
1711	1711	LLdecode(decode);
1712		hyperstone_frame(cpustate, decode);
	1712	hyperstone_frame(decode);
1713	1713	}
1714	1714
1715		static void hyperstone_opee(hyperstone_state *cpustate)
	1715	void hyperstone_device::opee()
1716	1716	{
1717	1717	LOCAL_DECODE_INIT;
1718	1718	LRconstdecode(decode, 0);
1719		hyperstone_call(cpustate, decode);
	1719	hyperstone_call(decode);
1720	1720	}
1721	1721
1722		static void hyperstone_opef(hyperstone_state *cpustate)
	1722	void hyperstone_device::opef()
1723	1723	{
1724	1724	LOCAL_DECODE_INIT;
1725	1725	LRconstdecode(decode, 1);
1726		hyperstone_call(cpustate, decode);
	1726	hyperstone_call(decode);
1727	1727	}
1728	1728
1729	1729
1730	1730
1731		static void hyperstone_opf0(hyperstone_state *cpustate)
	1731	void hyperstone_device::opf0()
1732	1732	{
1733	1733	LOCAL_DECODE_INIT;
1734	1734	PCreldecode(decode);
1735		hyperstone_bv(cpustate, decode);
	1735	hyperstone_bv(decode);
1736	1736	}
1737	1737
1738		static void hyperstone_opf1(hyperstone_state *cpustate)
	1738	void hyperstone_device::opf1()
1739	1739	{
1740	1740	LOCAL_DECODE_INIT;
1741	1741	PCreldecode(decode);
1742		hyperstone_bnv(cpustate, decode);
	1742	hyperstone_bnv(decode);
1743	1743	}
1744	1744
1745		static void hyperstone_opf2(hyperstone_state *cpustate)
	1745	void hyperstone_device::opf2()
1746	1746	{
1747	1747	LOCAL_DECODE_INIT;
1748	1748	PCreldecode(decode);
1749		hyperstone_be(cpustate, decode);
	1749	hyperstone_be(decode);
1750	1750	}
1751	1751
1752		static void hyperstone_opf3(hyperstone_state *cpustate)
	1752	void hyperstone_device::opf3()
1753	1753	{
1754	1754	LOCAL_DECODE_INIT;
1755	1755	PCreldecode(decode);
1756		hyperstone_bne(cpustate, decode);
	1756	hyperstone_bne(decode);
1757	1757	}
1758	1758
1759		static void hyperstone_opf4(hyperstone_state *cpustate)
	1759	void hyperstone_device::opf4()
1760	1760	{
1761	1761	LOCAL_DECODE_INIT;
1762	1762	PCreldecode(decode);
1763		hyperstone_bc(cpustate, decode);
	1763	hyperstone_bc(decode);
1764	1764	}
1765	1765
1766		static void hyperstone_opf5(hyperstone_state *cpustate)
	1766	void hyperstone_device::opf5()
1767	1767	{
1768	1768	LOCAL_DECODE_INIT;
1769	1769	PCreldecode(decode);
1770		hyperstone_bnc(cpustate, decode);
	1770	hyperstone_bnc(decode);
1771	1771	}
1772	1772
1773		static void hyperstone_opf6(hyperstone_state *cpustate)
	1773	void hyperstone_device::opf6()
1774	1774	{
1775	1775	LOCAL_DECODE_INIT;
1776	1776	PCreldecode(decode);
1777		hyperstone_bse(cpustate, decode);
	1777	hyperstone_bse(decode);
1778	1778	}
1779	1779
1780		static void hyperstone_opf7(hyperstone_state *cpustate)
	1780	void hyperstone_device::opf7()
1781	1781	{
1782	1782	LOCAL_DECODE_INIT;
1783	1783	PCreldecode(decode);
1784		hyperstone_bht(cpustate, decode);
	1784	hyperstone_bht(decode);
1785	1785	}
1786	1786
1787		static void hyperstone_opf8(hyperstone_state *cpustate)
	1787	void hyperstone_device::opf8()
1788	1788	{
1789	1789	LOCAL_DECODE_INIT;
1790	1790	PCreldecode(decode);
1791		hyperstone_bn(cpustate, decode);
	1791	hyperstone_bn(decode);
1792	1792	}
1793	1793
1794		static void hyperstone_opf9(hyperstone_state *cpustate)
	1794	void hyperstone_device::opf9()
1795	1795	{
1796	1796	LOCAL_DECODE_INIT;
1797	1797	PCreldecode(decode);
1798		hyperstone_bnn(cpustate, decode);
	1798	hyperstone_bnn(decode);
1799	1799	}
1800	1800
1801		static void hyperstone_opfa(hyperstone_state *cpustate)
	1801	void hyperstone_device::opfa()
1802	1802	{
1803	1803	LOCAL_DECODE_INIT;
1804	1804	PCreldecode(decode);
1805		hyperstone_ble(cpustate, decode);
	1805	hyperstone_ble(decode);
1806	1806	}
1807	1807
1808		static void hyperstone_opfb(hyperstone_state *cpustate)
	1808	void hyperstone_device::opfb()
1809	1809	{
1810	1810	LOCAL_DECODE_INIT;
1811	1811	PCreldecode(decode);
1812		hyperstone_bgt(cpustate, decode);
	1812	hyperstone_bgt(decode);
1813	1813	}
1814	1814
1815		static void hyperstone_opfc(hyperstone_state *cpustate)
	1815	void hyperstone_device::opfc()
1816	1816	{
1817	1817	LOCAL_DECODE_INIT;
1818	1818	PCreldecode(decode);
1819		hyperstone_br(cpustate, decode);
	1819	hyperstone_br(decode);
1820	1820	}
1821	1821
1822		static void hyperstone_opfd(hyperstone_state *cpustate)
	1822	void hyperstone_device::opfd()
1823	1823	{
1824	1824	LOCAL_DECODE_INIT;
1825	1825	PCadrdecode(decode);
1826		hyperstone_trap(cpustate, decode);
	1826	hyperstone_trap(decode);
1827	1827	}
1828	1828
1829		static void hyperstone_opfe(hyperstone_state *cpustate)
	1829	void hyperstone_device::opfe()
1830	1830	{
1831	1831	LOCAL_DECODE_INIT;
1832	1832	PCadrdecode(decode);
1833		hyperstone_trap(cpustate, decode);
	1833	hyperstone_trap(decode);
1834	1834	}
1835	1835
1836		static void hyperstone_opff(hyperstone_state *cpustate)
	1836	void hyperstone_device::opff()
1837	1837	{
1838	1838	LOCAL_DECODE_INIT;
1839	1839	PCadrdecode(decode);
1840		hyperstone_trap(cpustate, decode);
	1840	hyperstone_trap(decode);
1841	1841	}
1842	1842
1843
1844		static void (*const hyperstone_op[0x100])(hyperstone_state *cpustate) =
	1843	const hyperstone_device::ophandler hyperstone_device::s_opcodetable[256] =
1845	1844	{
1846		hyperstone_op00, hyperstone_op01, hyperstone_op02, hyperstone_op03,
1847		hyperstone_op04, hyperstone_op05, hyperstone_op06, hyperstone_op07,
1848		hyperstone_op08, hyperstone_op09, hyperstone_op0a, hyperstone_op0b,
1849		hyperstone_op0c, hyperstone_op0d, hyperstone_op0e, hyperstone_op0f,
	1845	&hyperstone_device::op00, &hyperstone_device::op01, &hyperstone_device::op02, &hyperstone_device::op03,
	1846	&hyperstone_device::op04, &hyperstone_device::op05, &hyperstone_device::op06, &hyperstone_device::op07,
	1847	&hyperstone_device::op08, &hyperstone_device::op09, &hyperstone_device::op0a, &hyperstone_device::op0b,
	1848	&hyperstone_device::op0c, &hyperstone_device::op0d, &hyperstone_device::op0e, &hyperstone_device::op0f,
1850	1849
1851		hyperstone_op10, hyperstone_op11, hyperstone_op12, hyperstone_op13,
1852		hyperstone_op14, hyperstone_op15, hyperstone_op16, hyperstone_op17,
1853		hyperstone_op18, hyperstone_op19, hyperstone_op1a, hyperstone_op1b,
1854		hyperstone_op1c, hyperstone_op1d, hyperstone_op1e, hyperstone_op1f,
	1850	&hyperstone_device::op10, &hyperstone_device::op11, &hyperstone_device::op12, &hyperstone_device::op13,
	1851	&hyperstone_device::op14, &hyperstone_device::op15, &hyperstone_device::op16, &hyperstone_device::op17,
	1852	&hyperstone_device::op18, &hyperstone_device::op19, &hyperstone_device::op1a, &hyperstone_device::op1b,
	1853	&hyperstone_device::op1c, &hyperstone_device::op1d, &hyperstone_device::op1e, &hyperstone_device::op1f,
1855	1854
1856		hyperstone_op20, hyperstone_op21, hyperstone_op22, hyperstone_op23,
1857		hyperstone_op24, hyperstone_op25, hyperstone_op26, hyperstone_op27,
1858		hyperstone_op28, hyperstone_op29, hyperstone_op2a, hyperstone_op2b,
1859		hyperstone_op2c, hyperstone_op2d, hyperstone_op2e, hyperstone_op2f,
	1855	&hyperstone_device::op20, &hyperstone_device::op21, &hyperstone_device::op22, &hyperstone_device::op23,
	1856	&hyperstone_device::op24, &hyperstone_device::op25, &hyperstone_device::op26, &hyperstone_device::op27,
	1857	&hyperstone_device::op28, &hyperstone_device::op29, &hyperstone_device::op2a, &hyperstone_device::op2b,
	1858	&hyperstone_device::op2c, &hyperstone_device::op2d, &hyperstone_device::op2e, &hyperstone_device::op2f,
1860	1859
1861		hyperstone_op30, hyperstone_op31, hyperstone_op32, hyperstone_op33,
1862		hyperstone_op34, hyperstone_op35, hyperstone_op36, hyperstone_op37,
1863		hyperstone_op38, hyperstone_op39, hyperstone_op3a, hyperstone_op3b,
1864		hyperstone_op3c, hyperstone_op3d, hyperstone_op3e, hyperstone_op3f,
	1860	&hyperstone_device::op30, &hyperstone_device::op31, &hyperstone_device::op32, &hyperstone_device::op33,
	1861	&hyperstone_device::op34, &hyperstone_device::op35, &hyperstone_device::op36, &hyperstone_device::op37,
	1862	&hyperstone_device::op38, &hyperstone_device::op39, &hyperstone_device::op3a, &hyperstone_device::op3b,
	1863	&hyperstone_device::op3c, &hyperstone_device::op3d, &hyperstone_device::op3e, &hyperstone_device::op3f,
1865	1864
1866		hyperstone_op40, hyperstone_op41, hyperstone_op42, hyperstone_op43,
1867		hyperstone_op44, hyperstone_op45, hyperstone_op46, hyperstone_op47,
1868		hyperstone_op48, hyperstone_op49, hyperstone_op4a, hyperstone_op4b,
1869		hyperstone_op4c, hyperstone_op4d, hyperstone_op4e, hyperstone_op4f,
	1865	&hyperstone_device::op40, &hyperstone_device::op41, &hyperstone_device::op42, &hyperstone_device::op43,
	1866	&hyperstone_device::op44, &hyperstone_device::op45, &hyperstone_device::op46, &hyperstone_device::op47,
	1867	&hyperstone_device::op48, &hyperstone_device::op49, &hyperstone_device::op4a, &hyperstone_device::op4b,
	1868	&hyperstone_device::op4c, &hyperstone_device::op4d, &hyperstone_device::op4e, &hyperstone_device::op4f,
1870	1869
1871		hyperstone_op50, hyperstone_op51, hyperstone_op52, hyperstone_op53,
1872		hyperstone_op54, hyperstone_op55, hyperstone_op56, hyperstone_op57,
1873		hyperstone_op58, hyperstone_op59, hyperstone_op5a, hyperstone_op5b,
1874		hyperstone_op5c, hyperstone_op5d, hyperstone_op5e, hyperstone_op5f,
	1870	&hyperstone_device::op50, &hyperstone_device::op51, &hyperstone_device::op52, &hyperstone_device::op53,
	1871	&hyperstone_device::op54, &hyperstone_device::op55, &hyperstone_device::op56, &hyperstone_device::op57,
	1872	&hyperstone_device::op58, &hyperstone_device::op59, &hyperstone_device::op5a, &hyperstone_device::op5b,
	1873	&hyperstone_device::op5c, &hyperstone_device::op5d, &hyperstone_device::op5e, &hyperstone_device::op5f,
1875	1874
1876		hyperstone_op60, hyperstone_op61, hyperstone_op62, hyperstone_op63,
1877		hyperstone_op64, hyperstone_op65, hyperstone_op66, hyperstone_op67,
1878		hyperstone_op68, hyperstone_op69, hyperstone_op6a, hyperstone_op6b,
1879		hyperstone_op6c, hyperstone_op6d, hyperstone_op6e, hyperstone_op6f,
	1875	&hyperstone_device::op60, &hyperstone_device::op61, &hyperstone_device::op62, &hyperstone_device::op63,
	1876	&hyperstone_device::op64, &hyperstone_device::op65, &hyperstone_device::op66, &hyperstone_device::op67,
	1877	&hyperstone_device::op68, &hyperstone_device::op69, &hyperstone_device::op6a, &hyperstone_device::op6b,
	1878	&hyperstone_device::op6c, &hyperstone_device::op6d, &hyperstone_device::op6e, &hyperstone_device::op6f,
1880	1879
1881		hyperstone_op70, hyperstone_op71, hyperstone_op72, hyperstone_op73,
1882		hyperstone_op74, hyperstone_op75, hyperstone_op76, hyperstone_op77,
1883		hyperstone_op78, hyperstone_op79, hyperstone_op7a, hyperstone_op7b,
1884		hyperstone_op7c, hyperstone_op7d, hyperstone_op7e, hyperstone_op7f,
	1880	&hyperstone_device::op70, &hyperstone_device::op71, &hyperstone_device::op72, &hyperstone_device::op73,
	1881	&hyperstone_device::op74, &hyperstone_device::op75, &hyperstone_device::op76, &hyperstone_device::op77,
	1882	&hyperstone_device::op78, &hyperstone_device::op79, &hyperstone_device::op7a, &hyperstone_device::op7b,
	1883	&hyperstone_device::op7c, &hyperstone_device::op7d, &hyperstone_device::op7e, &hyperstone_device::op7f,
1885	1884
1886		hyperstone_op80, hyperstone_op81, hyperstone_op82, hyperstone_op83,
1887		hyperstone_op84, hyperstone_op85, hyperstone_op86, hyperstone_op87,
1888		hyperstone_op88, hyperstone_op89, hyperstone_op8a, hyperstone_op8b,
1889		hyperstone_op8c, hyperstone_op8d, hyperstone_op8e, hyperstone_op8f,
	1885	&hyperstone_device::op80, &hyperstone_device::op81, &hyperstone_device::op82, &hyperstone_device::op83,
	1886	&hyperstone_device::op84, &hyperstone_device::op85, &hyperstone_device::op86, &hyperstone_device::op87,
	1887	&hyperstone_device::op88, &hyperstone_device::op89, &hyperstone_device::op8a, &hyperstone_device::op8b,
	1888	&hyperstone_device::op8c, &hyperstone_device::op8d, &hyperstone_device::op8e, &hyperstone_device::op8f,
1890	1889
1891		hyperstone_op90, hyperstone_op91, hyperstone_op92, hyperstone_op93,
1892		hyperstone_op94, hyperstone_op95, hyperstone_op96, hyperstone_op97,
1893		hyperstone_op98, hyperstone_op99, hyperstone_op9a, hyperstone_op9b,
1894		hyperstone_op9c, hyperstone_op9d, hyperstone_op9e, hyperstone_op9f,
	1890	&hyperstone_device::op90, &hyperstone_device::op91, &hyperstone_device::op92, &hyperstone_device::op93,
	1891	&hyperstone_device::op94, &hyperstone_device::op95, &hyperstone_device::op96, &hyperstone_device::op97,
	1892	&hyperstone_device::op98, &hyperstone_device::op99, &hyperstone_device::op9a, &hyperstone_device::op9b,
	1893	&hyperstone_device::op9c, &hyperstone_device::op9d, &hyperstone_device::op9e, &hyperstone_device::op9f,
1895	1894
1896		hyperstone_opa0, hyperstone_opa1, hyperstone_opa2, hyperstone_opa3,
1897		hyperstone_opa4, hyperstone_opa5, hyperstone_opa6, hyperstone_opa7,
1898		hyperstone_opa8, hyperstone_opa9, hyperstone_opaa, hyperstone_opab,
1899		hyperstone_opac, hyperstone_opad, hyperstone_opae, hyperstone_opaf,
	1895	&hyperstone_device::opa0, &hyperstone_device::opa1, &hyperstone_device::opa2, &hyperstone_device::opa3,
	1896	&hyperstone_device::opa4, &hyperstone_device::opa5, &hyperstone_device::opa6, &hyperstone_device::opa7,
	1897	&hyperstone_device::opa8, &hyperstone_device::opa9, &hyperstone_device::opaa, &hyperstone_device::opab,
	1898	&hyperstone_device::opac, &hyperstone_device::opad, &hyperstone_device::opae, &hyperstone_device::opaf,
1900	1899
1901		hyperstone_opb0, hyperstone_opb1, hyperstone_opb2, hyperstone_opb3,
1902		hyperstone_opb4, hyperstone_opb5, hyperstone_opb6, hyperstone_opb7,
1903		hyperstone_opb8, hyperstone_opb9, hyperstone_opba, hyperstone_opbb,
1904		hyperstone_opbc, hyperstone_opbd, hyperstone_opbe, hyperstone_opbf,
	1900	&hyperstone_device::opb0, &hyperstone_device::opb1, &hyperstone_device::opb2, &hyperstone_device::opb3,
	1901	&hyperstone_device::opb4, &hyperstone_device::opb5, &hyperstone_device::opb6, &hyperstone_device::opb7,
	1902	&hyperstone_device::opb8, &hyperstone_device::opb9, &hyperstone_device::opba, &hyperstone_device::opbb,
	1903	&hyperstone_device::opbc, &hyperstone_device::opbd, &hyperstone_device::opbe, &hyperstone_device::opbf,
1905	1904
1906		hyperstone_opc0, hyperstone_opc1, hyperstone_opc2, hyperstone_opc3,
1907		hyperstone_opc4, hyperstone_opc5, hyperstone_opc6, hyperstone_opc7,
1908		hyperstone_opc8, hyperstone_opc9, hyperstone_opca, hyperstone_opcb,
1909		hyperstone_opcc, hyperstone_opcd, hyperstone_opce, hyperstone_opcf,
	1905	&hyperstone_device::opc0, &hyperstone_device::opc1, &hyperstone_device::opc2, &hyperstone_device::opc3,
	1906	&hyperstone_device::opc4, &hyperstone_device::opc5, &hyperstone_device::opc6, &hyperstone_device::opc7,
	1907	&hyperstone_device::opc8, &hyperstone_device::opc9, &hyperstone_device::opca, &hyperstone_device::opcb,
	1908	&hyperstone_device::opcc, &hyperstone_device::opcd, &hyperstone_device::opce, &hyperstone_device::opcf,
1910	1909
1911		hyperstone_opd0, hyperstone_opd1, hyperstone_opd2, hyperstone_opd3,
1912		hyperstone_opd4, hyperstone_opd5, hyperstone_opd6, hyperstone_opd7,
1913		hyperstone_opd8, hyperstone_opd9, hyperstone_opda, hyperstone_opdb,
1914		hyperstone_opdc, hyperstone_opdd, hyperstone_opde, hyperstone_opdf,
	1910	&hyperstone_device::opd0, &hyperstone_device::opd1, &hyperstone_device::opd2, &hyperstone_device::opd3,
	1911	&hyperstone_device::opd4, &hyperstone_device::opd5, &hyperstone_device::opd6, &hyperstone_device::opd7,
	1912	&hyperstone_device::opd8, &hyperstone_device::opd9, &hyperstone_device::opda, &hyperstone_device::opdb,
	1913	&hyperstone_device::opdc, &hyperstone_device::opdd, &hyperstone_device::opde, &hyperstone_device::opdf,
1915	1914
1916		hyperstone_ope0, hyperstone_ope1, hyperstone_ope2, hyperstone_ope3,
1917		hyperstone_ope4, hyperstone_ope5, hyperstone_ope6, hyperstone_ope7,
1918		hyperstone_ope8, hyperstone_ope9, hyperstone_opea, hyperstone_opeb,
1919		hyperstone_opec, hyperstone_oped, hyperstone_opee, hyperstone_opef,
	1915	&hyperstone_device::ope0, &hyperstone_device::ope1, &hyperstone_device::ope2, &hyperstone_device::ope3,
	1916	&hyperstone_device::ope4, &hyperstone_device::ope5, &hyperstone_device::ope6, &hyperstone_device::ope7,
	1917	&hyperstone_device::ope8, &hyperstone_device::ope9, &hyperstone_device::opea, &hyperstone_device::opeb,
	1918	&hyperstone_device::opec, &hyperstone_device::oped, &hyperstone_device::opee, &hyperstone_device::opef,
1920	1919
1921		hyperstone_opf0, hyperstone_opf1, hyperstone_opf2, hyperstone_opf3,
1922		hyperstone_opf4, hyperstone_opf5, hyperstone_opf6, hyperstone_opf7,
1923		hyperstone_opf8, hyperstone_opf9, hyperstone_opfa, hyperstone_opfb,
1924		hyperstone_opfc, hyperstone_opfd, hyperstone_opfe, hyperstone_opff
	1920	&hyperstone_device::opf0, &hyperstone_device::opf1, &hyperstone_device::opf2, &hyperstone_device::opf3,
	1921	&hyperstone_device::opf4, &hyperstone_device::opf5, &hyperstone_device::opf6, &hyperstone_device::opf7,
	1922	&hyperstone_device::opf8, &hyperstone_device::opf9, &hyperstone_device::opfa, &hyperstone_device::opfb,
	1923	&hyperstone_device::opfc, &hyperstone_device::opfd, &hyperstone_device::opfe, &hyperstone_device::opff
1925	1924	};

trunk/src/emu/cpu/e132xs/e132xs.c

r19873	r19874
227	227
228	228	/* Registers */
229	229
230		enum
231		{
232		E132XS_PC = 1,
233		E132XS_SR,
234		E132XS_FER,
235		E132XS_G3,
236		E132XS_G4,
237		E132XS_G5,
238		E132XS_G6,
239		E132XS_G7,
240		E132XS_G8,
241		E132XS_G9,
242		E132XS_G10,
243		E132XS_G11,
244		E132XS_G12,
245		E132XS_G13,
246		E132XS_G14,
247		E132XS_G15,
248		E132XS_G16,
249		E132XS_G17,
250		E132XS_SP,
251		E132XS_UB,
252		E132XS_BCR,
253		E132XS_TPR,
254		E132XS_TCR,
255		E132XS_TR,
256		E132XS_WCR,
257		E132XS_ISR,
258		E132XS_FCR,
259		E132XS_MCR,
260		E132XS_G28,
261		E132XS_G29,
262		E132XS_G30,
263		E132XS_G31,
264		E132XS_CL0, E132XS_CL1, E132XS_CL2, E132XS_CL3,
265		E132XS_CL4, E132XS_CL5, E132XS_CL6, E132XS_CL7,
266		E132XS_CL8, E132XS_CL9, E132XS_CL10,E132XS_CL11,
267		E132XS_CL12,E132XS_CL13,E132XS_CL14,E132XS_CL15,
268		E132XS_L0,  E132XS_L1,  E132XS_L2,  E132XS_L3,
269		E132XS_L4,  E132XS_L5,  E132XS_L6,  E132XS_L7,
270		E132XS_L8,  E132XS_L9,  E132XS_L10, E132XS_L11,
271		E132XS_L12, E132XS_L13, E132XS_L14, E132XS_L15,
272		E132XS_L16, E132XS_L17, E132XS_L18, E132XS_L19,
273		E132XS_L20, E132XS_L21, E132XS_L22, E132XS_L23,
274		E132XS_L24, E132XS_L25, E132XS_L26, E132XS_L27,
275		E132XS_L28, E132XS_L29, E132XS_L30, E132XS_L31,
276		E132XS_L32, E132XS_L33, E132XS_L34, E132XS_L35,
277		E132XS_L36, E132XS_L37, E132XS_L38, E132XS_L39,
278		E132XS_L40, E132XS_L41, E132XS_L42, E132XS_L43,
279		E132XS_L44, E132XS_L45, E132XS_L46, E132XS_L47,
280		E132XS_L48, E132XS_L49, E132XS_L50, E132XS_L51,
281		E132XS_L52, E132XS_L53, E132XS_L54, E132XS_L55,
282		E132XS_L56, E132XS_L57, E132XS_L58, E132XS_L59,
283		E132XS_L60, E132XS_L61, E132XS_L62, E132XS_L63
284		};
285
286
287		/* Delay information */
288		struct delay_info
289		{
290		INT32   delay_cmd;
291		UINT32   delay_pc;
292		};
293
294	230	/* Internal registers */
295		struct hyperstone_state
296		{
297		UINT32   global_regs[32];
298		UINT32   local_regs[64];
299	231
300		/* internal stuff */
301		UINT32   ppc;   // previous pc
302		UINT16   op;      // opcode
303		UINT32   trap_entry; // entry point to get trap address
304
305		UINT8   clock_scale_mask;
306		UINT8   clock_scale;
307		UINT8   clock_cycles_1;
308		UINT8   clock_cycles_2;
309		UINT8   clock_cycles_4;
310		UINT8   clock_cycles_6;
311
312		UINT64   tr_base_cycles;
313		UINT32   tr_base_value;
314		UINT32   tr_clocks_per_tick;
315		UINT8   timer_int_pending;
316		emu_timer *timer;
317
318		delay_info delay;
319
320		device_irq_acknowledge_callback irq_callback;
321		legacy_cpu_device *device;
322		address_space *program;
323		direct_read_data *direct;
324		address_space *io;
325		UINT32 opcodexor;
326
327		INT32 instruction_length;
328		INT32 intblock;
329
330		int icount;
331		};
332
333		struct regs_decode
334		{
335		UINT8   src, dst;       // destination and source register code
336		UINT32   src_value;      // current source register value
337		UINT32   next_src_value; // current next source register value
338		UINT32   dst_value;      // current destination register value
339		UINT32   next_dst_value; // current next destination register value
340		UINT8   sub_type;      // sub type opcode (for DD and X_CODE bits)
341		union
342		{
343		UINT32 u;
344		INT32  s;
345		} extra;            // extra value such as immediate value, const, pcrel, ...
346		UINT8   src_is_local;
347		UINT8   dst_is_local;
348		UINT8   same_src_dst;
349		UINT8   same_src_dstf;
350		UINT8   same_srcf_dst;
351		};
352
353		static void check_interrupts(hyperstone_state *cpustate);
354
355	232	#define SREG  (decode)->src_value
356	233	#define SREGF (decode)->next_src_value
357	234	#define DREG  (decode)->dst_value
r19873	r19874
359	236	#define EXTRA_U (decode)->extra.u
360	237	#define EXTRA_S (decode)->extra.s
361	238
362		#define SET_SREG( _data_ )  ((decode)->src_is_local ? set_local_register(cpustate, (decode)->src, (UINT32)_data_) : set_global_register(cpustate, (decode)->src, (UINT32)_data_))
363		#define SET_SREGF( _data_ ) ((decode)->src_is_local ? set_local_register(cpustate, (decode)->src + 1, (UINT32)_data_) : set_global_register(cpustate, (decode)->src + 1, (UINT32)_data_))
364		#define SET_DREG( _data_ )  ((decode)->dst_is_local ? set_local_register(cpustate, (decode)->dst, (UINT32)_data_) : set_global_register(cpustate, (decode)->dst, (UINT32)_data_))
365		#define SET_DREGF( _data_ ) ((decode)->dst_is_local ? set_local_register(cpustate, (decode)->dst + 1, (UINT32)_data_) : set_global_register(cpustate, (decode)->dst + 1, (UINT32)_data_))
	239	#define SET_SREG( _data_ )  ((decode)->src_is_local ? set_local_register((decode)->src, (UINT32)_data_) : set_global_register((decode)->src, (UINT32)_data_))
	240	#define SET_SREGF( _data_ ) ((decode)->src_is_local ? set_local_register((decode)->src + 1, (UINT32)_data_) : set_global_register((decode)->src + 1, (UINT32)_data_))
	241	#define SET_DREG( _data_ )  ((decode)->dst_is_local ? set_local_register((decode)->dst, (UINT32)_data_) : set_global_register((decode)->dst, (UINT32)_data_))
	242	#define SET_DREGF( _data_ ) ((decode)->dst_is_local ? set_local_register((decode)->dst + 1, (UINT32)_data_) : set_global_register((decode)->dst + 1, (UINT32)_data_))
366	243
367	244	#define SRC_IS_PC      (!(decode)->src_is_local && (decode)->src == PC_REGISTER)
368	245	#define DST_IS_PC      (!(decode)->dst_is_local && (decode)->dst == PC_REGISTER)
r19873	r19874
372	249	#define SAME_SRC_DSTF  (decode)->same_src_dstf
373	250	#define SAME_SRCF_DST  (decode)->same_srcf_dst
374	251
	252	//**************************************************************************
	253	//  INTERNAL ADDRESS MAP
	254	//**************************************************************************
	255
375	256	// 4Kb IRAM (On-Chip Memory)
376	257
377		static ADDRESS_MAP_START( e116_4k_iram_map, AS_PROGRAM, 16, legacy_cpu_device )
	258	static ADDRESS_MAP_START( e116_4k_iram_map, AS_PROGRAM, 16, hyperstone_device )
378	259	AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM AM_MIRROR(0x1ffff000)
379	260	ADDRESS_MAP_END
380	261
381
382
383		static ADDRESS_MAP_START( e132_4k_iram_map, AS_PROGRAM, 32, legacy_cpu_device )
	262	static ADDRESS_MAP_START( e132_4k_iram_map, AS_PROGRAM, 32, hyperstone_device )
384	263	AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM AM_MIRROR(0x1ffff000)
385	264	ADDRESS_MAP_END
386	265
387	266
388	267	// 8Kb IRAM (On-Chip Memory)
389	268
390		static ADDRESS_MAP_START( e116_8k_iram_map, AS_PROGRAM, 16, legacy_cpu_device )
391
	269	static ADDRESS_MAP_START( e116_8k_iram_map, AS_PROGRAM, 16, hyperstone_device )
392	270	AM_RANGE(0xc0000000, 0xc0001fff) AM_RAM AM_MIRROR(0x1fffe000)
393	271	ADDRESS_MAP_END
394	272
395
396
397		static ADDRESS_MAP_START( e132_8k_iram_map, AS_PROGRAM, 32, legacy_cpu_device )
	273	static ADDRESS_MAP_START( e132_8k_iram_map, AS_PROGRAM, 32, hyperstone_device )
398	274	AM_RANGE(0xc0000000, 0xc0001fff) AM_RAM AM_MIRROR(0x1fffe000)
399	275	ADDRESS_MAP_END
400	276
401	277
402	278	// 16Kb IRAM (On-Chip Memory)
403	279
	280	static ADDRESS_MAP_START( e116_16k_iram_map, AS_PROGRAM, 16, hyperstone_device )
	281	AM_RANGE(0xc0000000, 0xc0003fff) AM_RAM AM_MIRROR(0x1fffc000)
	282	ADDRESS_MAP_END
404	283
405		static ADDRESS_MAP_START( e116_16k_iram_map, AS_PROGRAM, 16, legacy_cpu_device )
	284	static ADDRESS_MAP_START( e132_16k_iram_map, AS_PROGRAM, 32, hyperstone_device )
406	285	AM_RANGE(0xc0000000, 0xc0003fff) AM_RAM AM_MIRROR(0x1fffc000)
407	286	ADDRESS_MAP_END
408	287
409	288
	289	//-------------------------------------------------
	290	//  hyperstone_device - constructor
	291	//-------------------------------------------------
410	292
411		static ADDRESS_MAP_START( e132_16k_iram_map, AS_PROGRAM, 32, legacy_cpu_device )
412		AM_RANGE(0xc0000000, 0xc0003fff) AM_RAM AM_MIRROR(0x1fffc000)
413		ADDRESS_MAP_END
	293	hyperstone_device::hyperstone_device(const machine_config &mconfig, const char *name, const char *tag, device_t *owner, UINT32 clock,
	294	const device_type type, UINT32 prg_data_width, UINT32 io_data_width, address_map_constructor internal_map)
	295	: cpu_device(mconfig, type, name, tag, owner, clock),
	296	m_program_config("program", ENDIANNESS_BIG, prg_data_width, 32, 0, internal_map),
	297	m_io_config("io", ENDIANNESS_BIG, io_data_width, 15),
	298	m_icount(0)
	299	{
	300	// build the opcode table
	301	for (int op = 0; op < 256; op++)
	302	m_opcode[op] = s_opcodetable[op];
	303	}
414	304
415	305
416		INLINE hyperstone_state *get_safe_token(device_t *device)
	306	//-------------------------------------------------
	307	//  e116t_device - constructor
	308	//-------------------------------------------------
	309
	310	e116t_device::e116t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	311	: hyperstone_device(mconfig, "E1-16T", tag, owner, clock, E116T, 16, 16, ADDRESS_MAP_NAME(e116_4k_iram_map))
417	312	{
418		assert(device != NULL);
419		assert(device->type() == E116T ||
420		device->type() == E116XT ||
421		device->type() == E116XS ||
422		device->type() == E116XSR ||
423		device->type() == E132N ||
424		device->type() == E132T ||
425		device->type() == E132XN ||
426		device->type() == E132XT ||
427		device->type() == E132XS ||
428		device->type() == E132XSR ||
429		device->type() == GMS30C2116 ||
430		device->type() == GMS30C2132 ||
431		device->type() == GMS30C2216 ||
432		device->type() == GMS30C2232);
433		return (hyperstone_state *)downcast<legacy_cpu_device *>(device)->token();
434	313	}
435	314
	315
	316	//-------------------------------------------------
	317	//  e116xt_device - constructor
	318	//-------------------------------------------------
	319
	320	e116xt_device::e116xt_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	321	: hyperstone_device(mconfig, "E1-16XT", tag, owner, clock, E116XT, 16, 16, ADDRESS_MAP_NAME(e116_8k_iram_map))
	322	{
	323	}
	324
	325
	326	//-------------------------------------------------
	327	//  e116xs_device - constructor
	328	//-------------------------------------------------
	329
	330	e116xs_device::e116xs_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	331	: hyperstone_device(mconfig, "E1-16XS", tag, owner, clock, E116XS, 16, 16, ADDRESS_MAP_NAME(e116_16k_iram_map))
	332	{
	333	}
	334
	335
	336	//-------------------------------------------------
	337	//  e116xsr_device - constructor
	338	//-------------------------------------------------
	339
	340	e116xsr_device::e116xsr_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	341	: hyperstone_device(mconfig, "E1-16XSR", tag, owner, clock, E116XT, 16, 16, ADDRESS_MAP_NAME(e116_16k_iram_map))
	342	{
	343	}
	344
	345
	346	//-------------------------------------------------
	347	//  e132n_device - constructor
	348	//-------------------------------------------------
	349
	350	e132n_device::e132n_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	351	: hyperstone_device(mconfig, "E1-32N", tag, owner, clock, E132N, 32, 32, ADDRESS_MAP_NAME(e132_4k_iram_map))
	352	{
	353	}
	354
	355
	356	//-------------------------------------------------
	357	//  e132t_device - constructor
	358	//-------------------------------------------------
	359
	360	e132t_device::e132t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	361	: hyperstone_device(mconfig, "E1-32T", tag, owner, clock, E132T, 32, 32, ADDRESS_MAP_NAME(e132_4k_iram_map))
	362	{
	363	}
	364
	365
	366	//-------------------------------------------------
	367	//  e132xn_device - constructor
	368	//-------------------------------------------------
	369
	370	e132xn_device::e132xn_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	371	: hyperstone_device(mconfig, "E1-32XN", tag, owner, clock, E132XN, 32, 32, ADDRESS_MAP_NAME(e132_8k_iram_map))
	372	{
	373	}
	374
	375
	376	//-------------------------------------------------
	377	//  e132xt_device - constructor
	378	//-------------------------------------------------
	379
	380	e132xt_device::e132xt_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	381	: hyperstone_device(mconfig, "E1-32XT", tag, owner, clock, E132XT, 32, 32, ADDRESS_MAP_NAME(e132_8k_iram_map))
	382	{
	383	}
	384
	385
	386	//-------------------------------------------------
	387	//  e132xs_device - constructor
	388	//-------------------------------------------------
	389
	390	e132xs_device::e132xs_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	391	: hyperstone_device(mconfig, "E1-32XS", tag, owner, clock, E132XS, 32, 32, ADDRESS_MAP_NAME(e132_16k_iram_map))
	392	{
	393	}
	394
	395
	396	//-------------------------------------------------
	397	//  e132xsr_device - constructor
	398	//-------------------------------------------------
	399
	400	e132xsr_device::e132xsr_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	401	: hyperstone_device(mconfig, "E1-32XSR", tag, owner, clock, E132XSR, 32, 32, ADDRESS_MAP_NAME(e132_16k_iram_map))
	402	{
	403	}
	404
	405
	406	//-------------------------------------------------
	407	//  gms30c2116_device - constructor
	408	//-------------------------------------------------
	409
	410	gms30c2116_device::gms30c2116_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	411	: hyperstone_device(mconfig, "GMS30C2116", tag, owner, clock, GMS30C2116, 16, 16, ADDRESS_MAP_NAME(e116_4k_iram_map))
	412	{
	413	}
	414
	415
	416	//-------------------------------------------------
	417	//  gms30c2132_device - constructor
	418	//-------------------------------------------------
	419
	420	gms30c2132_device::gms30c2132_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	421	: hyperstone_device(mconfig, "GMS30C2132", tag, owner, clock, GMS30C2132, 32, 32, ADDRESS_MAP_NAME(e132_4k_iram_map))
	422	{
	423	}
	424
	425
	426	//-------------------------------------------------
	427	//  gms30c2216_device - constructor
	428	//-------------------------------------------------
	429
	430	gms30c2216_device::gms30c2216_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	431	: hyperstone_device(mconfig, "GMS30C2216", tag, owner, clock, GMS30C2216, 16, 16, ADDRESS_MAP_NAME(e116_8k_iram_map))
	432	{
	433	}
	434
	435
	436	//-------------------------------------------------
	437	//  gms30c2232_device - constructor
	438	//-------------------------------------------------
	439
	440	gms30c2232_device::gms30c2232_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	441	: hyperstone_device(mconfig, "GMS30C2232", tag, owner, clock, GMS30C2232, 32, 32, ADDRESS_MAP_NAME(e132_8k_iram_map))
	442	{
	443	}
	444
436	445	/* Return the entry point for a determinated trap */
437		static UINT32 get_trap_addr(hyperstone_state *cpustate, UINT8 trapno)
	446	UINT32 hyperstone_device::get_trap_addr(UINT8 trapno)
438	447	{
439	448	UINT32 addr;
440		if( cpustate->trap_entry == 0xffffff00 ) /* @ MEM3 */
	449	if( m_trap_entry == 0xffffff00 ) /* @ MEM3 */
441	450	{
442	451	addr = trapno * 4;
443	452	}
r19873	r19874
445	454	{
446	455	addr = (63 - trapno) * 4;
447	456	}
448		addr |= cpustate->trap_entry;
	457	addr |= m_trap_entry;
449	458
450	459	return addr;
451	460	}
452	461
453	462	/* Return the entry point for a determinated emulated code (the one for "extend" opcode is reserved) */
454		static UINT32 get_emu_code_addr(hyperstone_state *cpustate, UINT8 num) /* num is OP */
	463	UINT32 hyperstone_device::get_emu_code_addr(UINT8 num) /* num is OP */
455	464	{
456	465	UINT32 addr;
457		if( cpustate->trap_entry == 0xffffff00 ) /* @ MEM3 */
	466	if( m_trap_entry == 0xffffff00 ) /* @ MEM3 */
458	467	{
459		addr = (cpustate->trap_entry - 0x100) | ((num & 0xf) << 4);
	468	addr = (m_trap_entry - 0x100) | ((num & 0xf) << 4);
460	469	}
461	470	else
462	471	{
463		addr = cpustate->trap_entry | (0x10c | ((0xcf - num) << 4));
	472	addr = m_trap_entry | (0x10c | ((0xcf - num) << 4));
464	473	}
465	474	return addr;
466	475	}
467	476
468		static void hyperstone_set_trap_entry(hyperstone_state *cpustate, int which)
	477	void hyperstone_device::hyperstone_set_trap_entry(int which)
469	478	{
470	479	switch( which )
471	480	{
472	481	case E132XS_ENTRY_MEM0:
473		cpustate->trap_entry = 0x00000000;
	482	m_trap_entry = 0x00000000;
474	483	break;
475	484
476	485	case E132XS_ENTRY_MEM1:
477		cpustate->trap_entry = 0x40000000;
	486	m_trap_entry = 0x40000000;
478	487	break;
479	488
480	489	case E132XS_ENTRY_MEM2:
481		cpustate->trap_entry = 0x80000000;
	490	m_trap_entry = 0x80000000;
482	491	break;
483	492
484	493	case E132XS_ENTRY_MEM3:
485		cpustate->trap_entry = 0xffffff00;
	494	m_trap_entry = 0xffffff00;
486	495	break;
487	496
488	497	case E132XS_ENTRY_IRAM:
489		cpustate->trap_entry = 0xc0000000;
	498	m_trap_entry = 0xc0000000;
490	499	break;
491	500
492	501	default:
r19873	r19874
495	504	}
496	505	}
497	506
498		#define OP           cpustate->op
499		#define PPC            cpustate->ppc //previous pc
500		#define PC            cpustate->global_regs[0] //Program Counter
501		#define SR            cpustate->global_regs[1] //Status Register
502		#define FER            cpustate->global_regs[2] //Floating-Point Exception Register
	507	#define OP           m_op
	508	#define PPC            m_ppc //previous pc
	509	#define PC            m_global_regs[0] //Program Counter
	510	#define SR            m_global_regs[1] //Status Register
	511	#define FER            m_global_regs[2] //Floating-Point Exception Register
503	512	// 03 - 15  General Purpose Registers
504	513	// 16 - 17  Reserved
505		#define SP            cpustate->global_regs[18] //Stack Pointer
506		#define UB            cpustate->global_regs[19] //Upper Stack Bound
507		#define BCR            cpustate->global_regs[20] //Bus Control Register
508		#define TPR            cpustate->global_regs[21] //Timer Prescaler Register
509		#define TCR            cpustate->global_regs[22] //Timer Compare Register
510		#define TR            compute_tr(cpustate) //Timer Register
511		#define WCR            cpustate->global_regs[24] //Watchdog Compare Register
512		#define ISR            cpustate->global_regs[25] //Input Status Register
513		#define FCR            cpustate->global_regs[26] //Function Control Register
514		#define MCR            cpustate->global_regs[27] //Memory Control Register
	514	#define SP            m_global_regs[18] //Stack Pointer
	515	#define UB            m_global_regs[19] //Upper Stack Bound
	516	#define BCR            m_global_regs[20] //Bus Control Register
	517	#define TPR            m_global_regs[21] //Timer Prescaler Register
	518	#define TCR            m_global_regs[22] //Timer Compare Register
	519	#define TR            compute_tr() //Timer Register
	520	#define WCR            m_global_regs[24] //Watchdog Compare Register
	521	#define ISR            m_global_regs[25] //Input Status Register
	522	#define FCR            m_global_regs[26] //Function Control Register
	523	#define MCR            m_global_regs[27] //Memory Control Register
515	524	// 28 - 31  Reserved
516	525
517	526	/* SR flags */
r19873	r19874
571	580	//the user program can only changes the above 2 flags
572	581
573	582
574
575
576		static UINT32 compute_tr(hyperstone_state *cpustate)
	583	UINT32 hyperstone_device::compute_tr()
577	584	{
578		UINT64 cycles_since_base = cpustate->device->total_cycles() - cpustate->tr_base_cycles;
579		UINT64 clocks_since_base = cycles_since_base >> cpustate->clock_scale;
580		return cpustate->tr_base_value + (clocks_since_base / cpustate->tr_clocks_per_tick);
	585	UINT64 cycles_since_base = total_cycles() - m_tr_base_cycles;
	586	UINT64 clocks_since_base = cycles_since_base >> m_clock_scale;
	587	return m_tr_base_value + (clocks_since_base / m_tr_clocks_per_tick);
581	588	}
582	589
583		static void update_timer_prescale(hyperstone_state *cpustate)
	590	void hyperstone_device::update_timer_prescale()
584	591	{
585		UINT32 prevtr = compute_tr(cpustate);
	592	UINT32 prevtr = compute_tr();
586	593	TPR &= ~0x80000000;
587		cpustate->clock_scale = (TPR >> 26) & cpustate->clock_scale_mask;
588		cpustate->clock_cycles_1 = 1 << cpustate->clock_scale;
589		cpustate->clock_cycles_2 = 2 << cpustate->clock_scale;
590		cpustate->clock_cycles_4 = 4 << cpustate->clock_scale;
591		cpustate->clock_cycles_6 = 6 << cpustate->clock_scale;
592		cpustate->tr_clocks_per_tick = ((TPR >> 16) & 0xff) + 2;
593		cpustate->tr_base_value = prevtr;
594		cpustate->tr_base_cycles = cpustate->device->total_cycles();
	594	m_clock_scale = (TPR >> 26) & m_clock_scale_mask;
	595	m_clock_cycles_1 = 1 << m_clock_scale;
	596	m_clock_cycles_2 = 2 << m_clock_scale;
	597	m_clock_cycles_4 = 4 << m_clock_scale;
	598	m_clock_cycles_6 = 6 << m_clock_scale;
	599	m_tr_clocks_per_tick = ((TPR >> 16) & 0xff) + 2;
	600	m_tr_base_value = prevtr;
	601	m_tr_base_cycles = total_cycles();
595	602	}
596	603
597		static void adjust_timer_interrupt(hyperstone_state *cpustate)
	604	void hyperstone_device::adjust_timer_interrupt()
598	605	{
599		UINT64 cycles_since_base = cpustate->device->total_cycles() - cpustate->tr_base_cycles;
600		UINT64 clocks_since_base = cycles_since_base >> cpustate->clock_scale;
601		UINT64 cycles_until_next_clock = cycles_since_base - (clocks_since_base << cpustate->clock_scale);
	606	UINT64 cycles_since_base = total_cycles() - m_tr_base_cycles;
	607	UINT64 clocks_since_base = cycles_since_base >> m_clock_scale;
	608	UINT64 cycles_until_next_clock = cycles_since_base - (clocks_since_base << m_clock_scale);
602	609
603	610	if (cycles_until_next_clock == 0)
604		cycles_until_next_clock = (UINT64)(1 << cpustate->clock_scale);
	611	cycles_until_next_clock = (UINT64)(1 << m_clock_scale);
605	612
606	613	/* special case: if we have a change pending, set a timer to fire then */
607	614	if (TPR & 0x80000000)
608	615	{
609		UINT64 clocks_until_int = cpustate->tr_clocks_per_tick - (clocks_since_base % cpustate->tr_clocks_per_tick);
610		UINT64 cycles_until_int = (clocks_until_int << cpustate->clock_scale) + cycles_until_next_clock;
611		cpustate->timer->adjust(cpustate->device->cycles_to_attotime(cycles_until_int + 1), 1);
	616	UINT64 clocks_until_int = m_tr_clocks_per_tick - (clocks_since_base % m_tr_clocks_per_tick);
	617	UINT64 cycles_until_int = (clocks_until_int << m_clock_scale) + cycles_until_next_clock;
	618	m_timer->adjust(cycles_to_attotime(cycles_until_int + 1), 1);
612	619	}
613	620
614	621	/* else if the timer interrupt is enabled, configure it to fire at the appropriate time */
615	622	else if (!(FCR & 0x00800000))
616	623	{
617		UINT32 curtr = cpustate->tr_base_value + (clocks_since_base / cpustate->tr_clocks_per_tick);
	624	UINT32 curtr = m_tr_base_value + (clocks_since_base / m_tr_clocks_per_tick);
618	625	UINT32 delta = TCR - curtr;
619	626	if (delta > 0x80000000)
620	627	{
621		if (!cpustate->timer_int_pending)
622		cpustate->timer->adjust(attotime::zero);
	628	if (!m_timer_int_pending)
	629	m_timer->adjust(attotime::zero);
623	630	}
624	631	else
625	632	{
626		UINT64 clocks_until_int = mulu_32x32(delta, cpustate->tr_clocks_per_tick);
627		UINT64 cycles_until_int = (clocks_until_int << cpustate->clock_scale) + cycles_until_next_clock;
628		cpustate->timer->adjust(cpustate->device->cycles_to_attotime(cycles_until_int));
	633	UINT64 clocks_until_int = mulu_32x32(delta, m_tr_clocks_per_tick);
	634	UINT64 cycles_until_int = (clocks_until_int << m_clock_scale) + cycles_until_next_clock;
	635	m_timer->adjust(cycles_to_attotime(cycles_until_int));
629	636	}
630	637	}
631	638
632	639	/* otherwise, disable the timer */
633	640	else
634		cpustate->timer->adjust(attotime::never);
	641	m_timer->adjust(attotime::never);
635	642	}
636	643
637		static TIMER_CALLBACK( e132xs_timer_callback )
	644	TIMER_CALLBACK_MEMBER( hyperstone_device::timer_callback )
638	645	{
639		legacy_cpu_device *device = (legacy_cpu_device *)ptr;
640		hyperstone_state *cpustate = get_safe_token(device);
641	646	int update = param;
642	647
643	648	/* update the values if necessary */
644	649	if (update)
645		update_timer_prescale(cpustate);
	650	update_timer_prescale();
646	651
647	652	/* see if the timer is right for firing */
648		if (!((compute_tr(cpustate) - TCR) & 0x80000000))
649		cpustate->timer_int_pending = 1;
	653	if (!((compute_tr() - TCR) & 0x80000000))
	654	m_timer_int_pending = 1;
650	655
651	656	/* adjust ourselves for the next time */
652	657	else
653		adjust_timer_interrupt(cpustate);
	658	adjust_timer_interrupt();
654	659	}
655	660
656	661
657	662
658	663
659		static UINT32 get_global_register(hyperstone_state *cpustate, UINT8 code)
	664	UINT32 hyperstone_device::get_global_register(UINT8 code)
660	665	{
661	666	/*
662	667	if( code >= 16 )
r19873	r19874
693	698	if (code == TR_REGISTER)
694	699	{
695	700	/* it is common to poll this in a loop */
696		if (cpustate->icount > cpustate->tr_clocks_per_tick / 2)
697		cpustate->icount -= cpustate->tr_clocks_per_tick / 2;
698		return compute_tr(cpustate);
	701	if (m_icount > m_tr_clocks_per_tick / 2)
	702	m_icount -= m_tr_clocks_per_tick / 2;
	703	return compute_tr();
699	704	}
700		return cpustate->global_regs[code];
	705	return m_global_regs[code];
701	706	}
702	707
703		INLINE void set_global_register(hyperstone_state *cpustate, UINT8 code, UINT32 val)
	708	void hyperstone_device::set_local_register(UINT8 code, UINT32 val)
704	709	{
	710	UINT8 new_code = (code + GET_FP) % 64;
	711
	712	m_local_regs[new_code] = val;
	713	}
	714
	715	void hyperstone_device::set_global_register(UINT8 code, UINT32 val)
	716	{
705	717	//TODO: add correct FER set instruction
706	718
707	719	if( code == PC_REGISTER )
r19873	r19874
712	724	{
713	725	SET_LOW_SR(val); // only a RET instruction can change the full content of SR
714	726	SR &= ~0x40; //reserved bit 6 always zero
715		if (cpustate->intblock < 1)
716		cpustate->intblock = 1;
	727	if (m_intblock < 1)
	728	m_intblock = 1;
717	729	}
718	730	else
719	731	{
720		UINT32 oldval = cpustate->global_regs[code];
	732	UINT32 oldval = m_global_regs[code];
721	733	if( code != ISR_REGISTER )
722		cpustate->global_regs[code] = val;
	734	m_global_regs[code] = val;
723	735	else
724	736	DEBUG_PRINTF(("Written to ISR register. PC = %08X\n", PC));
725	737
r19873	r19874
765	777	break;
766	778	*/
767	779	case TR_REGISTER:
768		cpustate->tr_base_value = val;
769		cpustate->tr_base_cycles = cpustate->device->total_cycles();
770		adjust_timer_interrupt(cpustate);
	780	m_tr_base_value = val;
	781	m_tr_base_cycles = total_cycles();
	782	adjust_timer_interrupt();
771	783	break;
772	784
773	785	case TPR_REGISTER:
774	786	if (!(val & 0x80000000)) /* change immediately */
775		update_timer_prescale(cpustate);
776		adjust_timer_interrupt(cpustate);
	787	update_timer_prescale();
	788	adjust_timer_interrupt();
777	789	break;
778	790
779	791	case TCR_REGISTER:
780	792	if (oldval != val)
781	793	{
782		adjust_timer_interrupt(cpustate);
783		if (cpustate->intblock < 1)
784		cpustate->intblock = 1;
	794	adjust_timer_interrupt();
	795	if (m_intblock < 1)
	796	m_intblock = 1;
785	797	}
786	798	break;
787	799
788	800	case FCR_REGISTER:
789	801	if ((oldval ^ val) & 0x00800000)
790		adjust_timer_interrupt(cpustate);
791		if (cpustate->intblock < 1)
792		cpustate->intblock = 1;
	802	adjust_timer_interrupt();
	803	if (m_intblock < 1)
	804	m_intblock = 1;
793	805	break;
794	806
795	807	case MCR_REGISTER:
796	808	// bits 14..12 EntryTableMap
797		hyperstone_set_trap_entry(cpustate, (val & 0x7000) >> 12);
	809	hyperstone_set_trap_entry((val & 0x7000) >> 12);
798	810	break;
799	811	}
800	812	}
801	813	}
802	814	}
803	815
804		INLINE void set_local_register(hyperstone_state *cpustate, UINT8 code, UINT32 val)
805		{
806		UINT8 new_code = (code + GET_FP) % 64;
	816	#define GET_ABS_L_REG(code)         m_local_regs[code]
	817	#define SET_L_REG(code, val)       set_local_register(code, val)
	818	#define SET_ABS_L_REG(code, val)   m_local_regs[code] = val
	819	#define GET_G_REG(code)            get_global_register(code)
	820	#define SET_G_REG(code, val)       set_global_register(code, val)
807	821
808		cpustate->local_regs[new_code] = val;
809		}
810
811		#define GET_ABS_L_REG(code)         cpustate->local_regs[code]
812		#define SET_L_REG(code, val)       set_local_register(cpustate, code, val)
813		#define SET_ABS_L_REG(code, val)   cpustate->local_regs[code] = val
814		#define GET_G_REG(code)            get_global_register(cpustate, code)
815		#define SET_G_REG(code, val)       set_global_register(cpustate, code, val)
816
817	822	#define S_BIT               ((OP & 0x100) >> 8)
818	823	#define N_BIT               S_BIT
819	824	#define D_BIT               ((OP & 0x200) >> 9)
r19873	r19874
842	847	UINT8 code = (decode)->src;                                       \
843	848	(decode)->src_is_local = 1;                                       \
844	849	code = ((decode)->src + GET_FP) % 64; /* registers offset by frame pointer  */\
845		SREG = cpustate->local_regs[code];                                 \
	850	SREG = m_local_regs[code];                                       \
846	851	code = ((decode)->src + 1 + GET_FP) % 64;                           \
847		SREGF = cpustate->local_regs[code];                              \
	852	SREGF = m_local_regs[code];                                       \
848	853	}                                                            \
849	854	else                                                         \
850	855	{                                                            \
r19873	r19874
852	857	\
853	858	if (!hflag)                                                   \
854	859	{                                                         \
855		SREG = get_global_register(cpustate, (decode)->src);                        \
	860	SREG = get_global_register((decode)->src);                        \
856	861	\
857	862	/* bound safe */                                          \
858	863	if ((decode)->src != 15)                                    \
859		SREGF = get_global_register(cpustate, (decode)->src + 1);                  \
	864	SREGF = get_global_register((decode)->src + 1);                  \
860	865	}                                                         \
861	866	else                                                      \
862	867	{                                                         \
863	868	(decode)->src += 16;                                       \
864	869	\
865		SREG = get_global_register(cpustate, (decode)->src);                        \
	870	SREG = get_global_register((decode)->src);                        \
866	871	if ((WRITE_ONLY_REGMASK >> (decode)->src) & 1)                     \
867	872	SREG = 0; /* write-only registers */                        \
868	873	else if ((decode)->src == ISR_REGISTER)                           \
r19873	r19874
870	875	\
871	876	/* bound safe */                                          \
872	877	if ((decode)->src != 31)                                    \
873		SREGF = get_global_register(cpustate, (decode)->src + 1);                  \
	878	SREGF = get_global_register((decode)->src + 1);                  \
874	879	}                                                         \
875	880	}                                                            \
876	881	} while (0)
r19873	r19874
883	888	UINT8 code = (decode)->dst;                                       \
884	889	(decode)->dst_is_local = 1;                                       \
885	890	code = ((decode)->dst + GET_FP) % 64; /* registers offset by frame pointer */\
886		DREG = cpustate->local_regs[code];                                 \
	891	DREG = m_local_regs[code];                                       \
887	892	code = ((decode)->dst + 1 + GET_FP) % 64;                           \
888		DREGF = cpustate->local_regs[code];                              \
	893	DREGF = m_local_regs[code];                                       \
889	894	}                                                            \
890	895	else                                                         \
891	896	{                                                            \
r19873	r19874
893	898	\
894	899	if (!hflag)                                                   \
895	900	{                                                         \
896		DREG = get_global_register(cpustate, (decode)->dst);                        \
	901	DREG = get_global_register((decode)->dst);                        \
897	902	\
898	903	/* bound safe */                                          \
899	904	if ((decode)->dst != 15)                                    \
900		DREGF = get_global_register(cpustate, (decode)->dst + 1);                  \
	905	DREGF = get_global_register((decode)->dst + 1);                  \
901	906	}                                                         \
902	907	else                                                      \
903	908	{                                                         \
904	909	(decode)->dst += 16;                                       \
905	910	\
906		DREG = get_global_register(cpustate, (decode)->dst);                        \
	911	DREG = get_global_register((decode)->dst);                        \
907	912	if( (decode)->dst == ISR_REGISTER )                              \
908	913	DEBUG_PRINTF(("read dst ISR. PC = %08X\n",PPC));               \
909	914	\
910	915	/* bound safe */                                          \
911	916	if ((decode)->dst != 31)                                    \
912		DREGF = get_global_register(cpustate, (decode)->dst + 1);                  \
	917	DREGF = get_global_register((decode)->dst + 1);                  \
913	918	}                                                         \
914	919	}                                                            \
915	920	} while (0)
r19873	r19874
974	979	do                                                               \
975	980	{                                                               \
976	981	/* if PC is used in a delay instruction, the delayed PC should be used */      \
977		if( cpustate->delay.delay_cmd == DELAY_EXECUTE )                        \
	982	if( m_delay.delay_cmd == DELAY_EXECUTE )                              \
978	983	{                                                            \
979		PC = cpustate->delay.delay_pc;                                    \
980		cpustate->delay.delay_cmd = NO_DELAY;                              \
	984	PC = m_delay.delay_pc;                                          \
	985	m_delay.delay_cmd = NO_DELAY;                                    \
981	986	}                                                            \
982	987	} while (0)
983	988
r19873	r19874
994	999	break;                                                \
995	1000	\
996	1001	case 1:                                                   \
997		cpustate->instruction_length = 3;                           \
998		EXTRA_U = (READ_OP(cpustate, PC) << 16) | READ_OP(cpustate, PC + 2);\
	1002	m_instruction_length = 3;                                 \
	1003	EXTRA_U = (READ_OP(PC) << 16) | READ_OP(PC + 2);               \
999	1004	PC += 4;                                             \
1000	1005	break;                                                \
1001	1006	\
1002	1007	case 2:                                                   \
1003		cpustate->instruction_length = 2;                           \
1004		EXTRA_U = READ_OP(cpustate, PC);                           \
	1008	m_instruction_length = 2;                                 \
	1009	EXTRA_U = READ_OP(PC);                                    \
1005	1010	PC += 2;                                             \
1006	1011	break;                                                \
1007	1012	\
1008	1013	case 3:                                                   \
1009		cpustate->instruction_length = 2;                           \
1010		EXTRA_U = 0xffff0000 | READ_OP(cpustate, PC);                  \
	1014	m_instruction_length = 2;                                 \
	1015	EXTRA_U = 0xffff0000 | READ_OP(PC);                           \
1011	1016	PC += 2;                                             \
1012	1017	break;                                                \
1013	1018	}                                                         \
r19873	r19874
1016	1021	#define decode_const(decode)                                          \
1017	1022	do                                                               \
1018	1023	{                                                               \
1019		UINT16 imm_1 = READ_OP(cpustate, PC);                                 \
	1024	UINT16 imm_1 = READ_OP(PC);                                          \
1020	1025	\
1021	1026	PC += 2;                                                      \
1022		cpustate->instruction_length = 2;                                    \
	1027	m_instruction_length = 2;                                          \
1023	1028	\
1024	1029	if( E_BIT(imm_1) )                                                \
1025	1030	{                                                            \
1026		UINT16 imm_2 = READ_OP(cpustate, PC);                              \
	1031	UINT16 imm_2 = READ_OP(PC);                                       \
1027	1032	\
1028	1033	PC += 2;                                                   \
1029		cpustate->instruction_length = 3;                                 \
	1034	m_instruction_length = 3;                                       \
1030	1035	\
1031	1036	EXTRA_S = imm_2;                                             \
1032	1037	EXTRA_S |= ((imm_1 & 0x3fff) << 16);                              \
r19873	r19874
1052	1057	{                                                               \
1053	1058	if( OP & 0x80 )                                                   \
1054	1059	{                                                            \
1055		UINT16 next = READ_OP(cpustate, PC);                              \
	1060	UINT16 next = READ_OP(PC);                                       \
1056	1061	\
1057	1062	PC += 2;                                                   \
1058		cpustate->instruction_length = 2;                                 \
	1063	m_instruction_length = 2;                                       \
1059	1064	\
1060	1065	EXTRA_S = (OP & 0x7f) << 16;                                    \
1061	1066	EXTRA_S |= (next & 0xfffe);                                       \
r19873	r19874
1075	1080	#define decode_dis(decode)                                             \
1076	1081	do                                                               \
1077	1082	{                                                               \
1078		UINT16 next_1 = READ_OP(cpustate, PC);                                 \
	1083	UINT16 next_1 = READ_OP(PC);                                       \
1079	1084	\
1080	1085	PC += 2;                                                      \
1081		cpustate->instruction_length = 2;                                    \
	1086	m_instruction_length = 2;                                          \
1082	1087	\
1083	1088	(decode)->sub_type = DD(next_1);                                    \
1084	1089	\
1085	1090	if( E_BIT(next_1) )                                                \
1086	1091	{                                                            \
1087		UINT16 next_2 = READ_OP(cpustate, PC);                              \
	1092	UINT16 next_2 = READ_OP(PC);                                    \
1088	1093	\
1089	1094	PC += 2;                                                   \
1090		cpustate->instruction_length = 3;                                 \
	1095	m_instruction_length = 3;                                       \
1091	1096	\
1092	1097	EXTRA_S = next_2;                                             \
1093	1098	EXTRA_S |= ((next_1 & 0xfff) << 16);                              \
r19873	r19874
1111	1116	#define decode_lim(decode)                                             \
1112	1117	do                                                               \
1113	1118	{                                                               \
1114		UINT32 next = READ_OP(cpustate, PC);                                 \
	1119	UINT32 next = READ_OP(PC);                                          \
1115	1120	PC += 2;                                                      \
1116		cpustate->instruction_length = 2;                                    \
	1121	m_instruction_length = 2;                                          \
1117	1122	\
1118	1123	(decode)->sub_type = X_CODE(next);                                    \
1119	1124	\
1120	1125	if( E_BIT(next) )                                                \
1121	1126	{                                                            \
1122		EXTRA_U = ((next & 0xfff) << 16) | READ_OP(cpustate, PC);               \
	1127	EXTRA_U = ((next & 0xfff) << 16) | READ_OP(PC);                        \
1123	1128	PC += 2;                                                   \
1124		cpustate->instruction_length = 3;                                 \
	1129	m_instruction_length = 3;                                       \
1125	1130	}                                                            \
1126	1131	else                                                         \
1127	1132	{                                                            \
r19873	r19874
1218	1223	#define LLextdecode(decode)                                             \
1219	1224	do                                                               \
1220	1225	{                                                               \
1221		cpustate->instruction_length = 2;                                    \
1222		EXTRA_U = READ_OP(cpustate, PC);                                    \
	1226	m_instruction_length = 2;                                          \
	1227	EXTRA_U = READ_OP(PC);                                             \
1223	1228	PC += 2;                                                      \
1224	1229	check_delay_PC();                                                \
1225	1230	decode_LL(decode);                                                \
r19873	r19874
1259	1264	} while (0)
1260	1265
1261	1266
1262		INLINE void execute_br(hyperstone_state *cpustate, struct regs_decode *decode)
	1267	void hyperstone_device::execute_br(struct hyperstone_device::regs_decode *decode)
1263	1268	{
1264	1269	PPC = PC;
1265	1270	PC += EXTRA_S;
1266	1271	SET_M(0);
1267	1272
1268		cpustate->icount -= cpustate->clock_cycles_2;
	1273	m_icount -= m_clock_cycles_2;
1269	1274	}
1270	1275
1271		INLINE void execute_dbr(hyperstone_state *cpustate, struct regs_decode *decode)
	1276	void hyperstone_device::execute_dbr(struct hyperstone_device::regs_decode *decode)
1272	1277	{
1273		cpustate->delay.delay_cmd = DELAY_EXECUTE;
1274		cpustate->delay.delay_pc  = PC + EXTRA_S;
	1278	m_delay.delay_cmd = DELAY_EXECUTE;
	1279	m_delay.delay_pc  = PC + EXTRA_S;
1275	1280
1276		cpustate->intblock = 3;
	1281	m_intblock = 3;
1277	1282	}
1278	1283
1279	1284
1280		static void execute_trap(hyperstone_state *cpustate, UINT32 addr)
	1285	void hyperstone_device::execute_trap(UINT32 addr)
1281	1286	{
1282	1287	UINT8 reg;
1283	1288	UINT32 oldSR;
1284	1289	reg = GET_FP + GET_FL;
1285	1290
1286		SET_ILC(cpustate->instruction_length & 3);
	1291	SET_ILC(m_instruction_length & 3);
1287	1292
1288	1293	oldSR = SR;
1289	1294
r19873	r19874
1301	1306	PPC = PC;
1302	1307	PC = addr;
1303	1308
1304		cpustate->icount -= cpustate->clock_cycles_2;
	1309	m_icount -= m_clock_cycles_2;
1305	1310	}
1306	1311
1307	1312
1308		static void execute_int(hyperstone_state *cpustate, UINT32 addr)
	1313	void hyperstone_device::execute_int(UINT32 addr)
1309	1314	{
1310	1315	UINT8 reg;
1311	1316	UINT32 oldSR;
1312	1317	reg = GET_FP + GET_FL;
1313	1318
1314		SET_ILC(cpustate->instruction_length & 3);
	1319	SET_ILC(m_instruction_length & 3);
1315	1320
1316	1321	oldSR = SR;
1317	1322
r19873	r19874
1330	1335	PPC = PC;
1331	1336	PC = addr;
1332	1337
1333		cpustate->icount -= cpustate->clock_cycles_2;
	1338	m_icount -= m_clock_cycles_2;
1334	1339	}
1335	1340
1336	1341	/* TODO: mask Parity Error and Extended Overflow exceptions */
1337		static void execute_exception(hyperstone_state *cpustate, UINT32 addr)
	1342	void hyperstone_device::execute_exception(UINT32 addr)
1338	1343	{
1339	1344	UINT8 reg;
1340	1345	UINT32 oldSR;
1341	1346	reg = GET_FP + GET_FL;
1342	1347
1343		SET_ILC(cpustate->instruction_length & 3);
	1348	SET_ILC(m_instruction_length & 3);
1344	1349
1345	1350	oldSR = SR;
1346	1351
r19873	r19874
1359	1364	PC = addr;
1360	1365
1361	1366	DEBUG_PRINTF(("EXCEPTION! PPC = %08X PC = %08X\n",PPC-2,PC-2));
1362		cpustate->icount -= cpustate->clock_cycles_2;
	1367	m_icount -= m_clock_cycles_2;
1363	1368	}
1364	1369
1365		static void execute_software(hyperstone_state *cpustate, struct regs_decode *decode)
	1370	void hyperstone_device::execute_software(struct hyperstone_device::regs_decode *decode)
1366	1371	{
1367	1372	UINT8 reg;
1368	1373	UINT32 oldSR;
r19873	r19874
1371	1376
1372	1377	SET_ILC(1);
1373	1378
1374		addr = get_emu_code_addr(cpustate, (OP & 0xff00) >> 8);
	1379	addr = get_emu_code_addr((OP & 0xff00) >> 8);
1375	1380	reg = GET_FP + GET_FL;
1376	1381
1377	1382	//since it's sure the register is in the register part of the stack,
r19873	r19874
1419	1424	#define IO2_LINE_STATE      ((ISR >> 5) & 1)
1420	1425	#define IO3_LINE_STATE      ((ISR >> 6) & 1)
1421	1426
1422		static void check_interrupts(hyperstone_state *cpustate)
	1427	void hyperstone_device::check_interrupts()
1423	1428	{
1424	1429	/* Interrupt-Lock flag isn't set */
1425		if (GET_L || cpustate->intblock > 0)
	1430	if (GET_L || m_intblock > 0)
1426	1431	return;
1427	1432
1428	1433	/* quick exit if nothing */
1429		if (!cpustate->timer_int_pending && (ISR & 0x7f) == 0)
	1434	if (!m_timer_int_pending && (ISR & 0x7f) == 0)
1430	1435	return;
1431	1436
1432	1437	/* IO3 is priority 5; state is in bit 6 of ISR; FCR bit 10 enables input and FCR bit 8 inhibits interrupt */
1433	1438	if (IO3_LINE_STATE && (FCR & 0x00000500) == 0x00000400)
1434	1439	{
1435		execute_int(cpustate, get_trap_addr(cpustate, TRAPNO_IO3));
1436		(*cpustate->irq_callback)(cpustate->device, IRQ_IO3);
	1440	execute_int(get_trap_addr(TRAPNO_IO3));
	1441	standard_irq_callback(IRQ_IO3);
1437	1442	return;
1438	1443	}
1439	1444
1440	1445	/* timer int might be priority 6 if FCR bits 20-21 == 3; FCR bit 23 inhibits interrupt */
1441		if (cpustate->timer_int_pending && (FCR & 0x00b00000) == 0x00300000)
	1446	if (m_timer_int_pending && (FCR & 0x00b00000) == 0x00300000)
1442	1447	{
1443		cpustate->timer_int_pending = 0;
1444		execute_int(cpustate, get_trap_addr(cpustate, TRAPNO_TIMER));
	1448	m_timer_int_pending = 0;
	1449	execute_int(get_trap_addr(TRAPNO_TIMER));
1445	1450	return;
1446	1451	}
1447	1452
1448	1453	/* INT1 is priority 7; state is in bit 0 of ISR; FCR bit 28 inhibits interrupt */
1449	1454	if (INT1_LINE_STATE && (FCR & 0x10000000) == 0x00000000)
1450	1455	{
1451		execute_int(cpustate, get_trap_addr(cpustate, TRAPNO_INT1));
1452		(*cpustate->irq_callback)(cpustate->device, IRQ_INT1);
	1456	execute_int(get_trap_addr(TRAPNO_INT1));
	1457	standard_irq_callback(IRQ_INT1);
1453	1458	return;
1454	1459	}
1455	1460
1456	1461	/* timer int might be priority 8 if FCR bits 20-21 == 2; FCR bit 23 inhibits interrupt */
1457		if (cpustate->timer_int_pending && (FCR & 0x00b00000) == 0x00200000)
	1462	if (m_timer_int_pending && (FCR & 0x00b00000) == 0x00200000)
1458	1463	{
1459		cpustate->timer_int_pending = 0;
1460		execute_int(cpustate, get_trap_addr(cpustate, TRAPNO_TIMER));
	1464	m_timer_int_pending = 0;
	1465	execute_int(get_trap_addr(TRAPNO_TIMER));
1461	1466	return;
1462	1467	}
1463	1468
1464	1469	/* INT2 is priority 9; state is in bit 1 of ISR; FCR bit 29 inhibits interrupt */
1465	1470	if (INT2_LINE_STATE && (FCR & 0x20000000) == 0x00000000)
1466	1471	{
1467		execute_int(cpustate, get_trap_addr(cpustate, TRAPNO_INT2));
1468		(*cpustate->irq_callback)(cpustate->device, IRQ_INT2);
	1472	execute_int(get_trap_addr(TRAPNO_INT2));
	1473	standard_irq_callback(IRQ_INT2);
1469	1474	return;
1470	1475	}
1471	1476
1472	1477	/* timer int might be priority 10 if FCR bits 20-21 == 1; FCR bit 23 inhibits interrupt */
1473		if (cpustate->timer_int_pending && (FCR & 0x00b00000) == 0x00100000)
	1478	if (m_timer_int_pending && (FCR & 0x00b00000) == 0x00100000)
1474	1479	{
1475		cpustate->timer_int_pending = 0;
1476		execute_int(cpustate, get_trap_addr(cpustate, TRAPNO_TIMER));
	1480	m_timer_int_pending = 0;
	1481	execute_int(get_trap_addr(TRAPNO_TIMER));
1477	1482	return;
1478	1483	}
1479	1484
1480	1485	/* INT3 is priority 11; state is in bit 2 of ISR; FCR bit 30 inhibits interrupt */
1481	1486	if (INT3_LINE_STATE && (FCR & 0x40000000) == 0x00000000)
1482	1487	{
1483		execute_int(cpustate, get_trap_addr(cpustate, TRAPNO_INT3));
1484		(*cpustate->irq_callback)(cpustate->device, IRQ_INT3);
	1488	execute_int(get_trap_addr(TRAPNO_INT3));
	1489	standard_irq_callback(IRQ_INT3);
1485	1490	return;
1486	1491	}
1487	1492
1488	1493	/* timer int might be priority 12 if FCR bits 20-21 == 0; FCR bit 23 inhibits interrupt */
1489		if (cpustate->timer_int_pending && (FCR & 0x00b00000) == 0x00000000)
	1494	if (m_timer_int_pending && (FCR & 0x00b00000) == 0x00000000)
1490	1495	{
1491		cpustate->timer_int_pending = 0;
1492		execute_int(cpustate, get_trap_addr(cpustate, TRAPNO_TIMER));
	1496	m_timer_int_pending = 0;
	1497	execute_int(get_trap_addr(TRAPNO_TIMER));
1493	1498	return;
1494	1499	}
1495	1500
1496	1501	/* INT4 is priority 13; state is in bit 3 of ISR; FCR bit 31 inhibits interrupt */
1497	1502	if (INT4_LINE_STATE && (FCR & 0x80000000) == 0x00000000)
1498	1503	{
1499		execute_int(cpustate, get_trap_addr(cpustate, TRAPNO_INT4));
1500		(*cpustate->irq_callback)(cpustate->device, IRQ_INT4);
	1504	execute_int(get_trap_addr(TRAPNO_INT4));
	1505	standard_irq_callback(IRQ_INT4);
1501	1506	return;
1502	1507	}
1503	1508
1504	1509	/* IO1 is priority 14; state is in bit 4 of ISR; FCR bit 2 enables input and FCR bit 0 inhibits interrupt */
1505	1510	if (IO1_LINE_STATE && (FCR & 0x00000005) == 0x00000004)
1506	1511	{
1507		execute_int(cpustate, get_trap_addr(cpustate, TRAPNO_IO1));
1508		(*cpustate->irq_callback)(cpustate->device, IRQ_IO1);
	1512	execute_int(get_trap_addr(TRAPNO_IO1));
	1513	standard_irq_callback(IRQ_IO1);
1509	1514	return;
1510	1515	}
1511	1516
1512	1517	/* IO2 is priority 15; state is in bit 5 of ISR; FCR bit 6 enables input and FCR bit 4 inhibits interrupt */
1513	1518	if (IO2_LINE_STATE && (FCR & 0x00000050) == 0x00000040)
1514	1519	{
1515		execute_int(cpustate, get_trap_addr(cpustate, TRAPNO_IO2));
1516		(*cpustate->irq_callback)(cpustate->device, IRQ_IO2);
	1520	execute_int(get_trap_addr(TRAPNO_IO2));
	1521	standard_irq_callback(IRQ_IO2);
1517	1522	return;
1518	1523	}
1519	1524	}
1520	1525
1521		static void set_irq_line(hyperstone_state *cpustate, int irqline, int state)
	1526	void hyperstone_device::device_start()
1522	1527	{
1523		if (state)
1524		ISR |= 1 << irqline;
1525		else
1526		ISR &= ~(1 << irqline);
	1528	// Handled entirely by init() and derived classes
1527	1529	}
1528	1530
1529		static void hyperstone_init(legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback, int scale_mask)
	1531	void hyperstone_device::init(int scale_mask)
1530	1532	{
1531		hyperstone_state *cpustate = get_safe_token(device);
	1533	memset(m_global_regs, 0, sizeof(UINT32) * 32);
	1534	memset(m_local_regs, 0, sizeof(UINT32) * 64);
	1535	m_ppc = 0;
	1536	m_op = 0;
	1537	m_trap_entry = 0;
	1538	m_clock_scale_mask = 0;
	1539	m_clock_scale = 0;
	1540	m_clock_cycles_1 = 0;
	1541	m_clock_cycles_2 = 0;
	1542	m_clock_cycles_4 = 0;
	1543	m_clock_cycles_6 = 0;
1532	1544
1533		device->save_item(NAME(cpustate->global_regs));
1534		device->save_item(NAME(cpustate->local_regs));
1535		device->save_item(NAME(cpustate->ppc));
1536		device->save_item(NAME(cpustate->trap_entry));
1537		device->save_item(NAME(cpustate->delay.delay_pc));
1538		device->save_item(NAME(cpustate->instruction_length));
1539		device->save_item(NAME(cpustate->intblock));
1540		device->save_item(NAME(cpustate->delay.delay_cmd));
1541		device->save_item(NAME(cpustate->tr_clocks_per_tick));
	1545	m_tr_base_cycles = 0;
	1546	m_tr_base_value = 0;
	1547	m_tr_clocks_per_tick = 0;
	1548	m_timer_int_pending = 0;
1542	1549
1543		cpustate->irq_callback = irqcallback;
1544		cpustate->device = device;
1545		cpustate->program = &device->space(AS_PROGRAM);
1546		cpustate->direct = &cpustate->program->direct();
1547		cpustate->io = &device->space(AS_IO);
1548		cpustate->timer = device->machine().scheduler().timer_alloc(FUNC(e132xs_timer_callback), (void *)device);
1549		cpustate->clock_scale_mask = scale_mask;
1550		}
	1550	m_instruction_length = 0;
	1551	m_intblock = 0;
1551	1552
1552		static void e116_init(legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback, int scale_mask)
1553		{
1554		hyperstone_state *cpustate = get_safe_token(device);
1555		hyperstone_init(device, irqcallback, scale_mask);
1556		cpustate->opcodexor = 0;
1557		}
	1553	m_icount = 0;
1558	1554
1559		static CPU_INIT( e116t )
1560		{
1561		e116_init(device, irqcallback, 0);
	1555	m_program = &space(AS_PROGRAM);
	1556	m_direct = &m_program->direct();
	1557	m_io = &space(AS_IO);
	1558
	1559	m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(hyperstone_device::timer_callback), this));
	1560	m_clock_scale_mask = scale_mask;
	1561
	1562	// register our state for the debugger
	1563	astring tempstr;
	1564	state_add(STATE_GENPC,     "GENPC",     m_global_regs[0]).noshow();
	1565	state_add(STATE_GENFLAGS,  "GENFLAGS",  m_global_regs[1]).callimport().callexport().formatstr("%40s").noshow();
	1566	state_add(E132XS_PC,       "PC  :%08X", m_global_regs[0]).mask(0xffffffff);
	1567	state_add(E132XS_SR,       "SR  :%08X", m_global_regs[1]).mask(0xffffffff);
	1568	state_add(E132XS_FER,      "FER :%08X", m_global_regs[2]).mask(0xffffffff);
	1569	state_add(E132XS_G3,       "G3  :%08X", m_global_regs[3]).mask(0xffffffff);
	1570	state_add(E132XS_G4,       "G4  :%08X", m_global_regs[4]).mask(0xffffffff);
	1571	state_add(E132XS_G5,       "G5  :%08X", m_global_regs[5]).mask(0xffffffff);
	1572	state_add(E132XS_G6,       "G6  :%08X", m_global_regs[6]).mask(0xffffffff);
	1573	state_add(E132XS_G7,       "G7  :%08X", m_global_regs[7]).mask(0xffffffff);
	1574	state_add(E132XS_G8,       "G8  :%08X", m_global_regs[8]).mask(0xffffffff);
	1575	state_add(E132XS_G9,       "G9  :%08X", m_global_regs[9]).mask(0xffffffff);
	1576	state_add(E132XS_G10,      "G10 :%08X", m_global_regs[10]).mask(0xffffffff);
	1577	state_add(E132XS_G11,      "G11 :%08X", m_global_regs[11]).mask(0xffffffff);
	1578	state_add(E132XS_G12,      "G12 :%08X", m_global_regs[12]).mask(0xffffffff);
	1579	state_add(E132XS_G13,      "G13 :%08X", m_global_regs[13]).mask(0xffffffff);
	1580	state_add(E132XS_G14,      "G14 :%08X", m_global_regs[14]).mask(0xffffffff);
	1581	state_add(E132XS_G15,      "G15 :%08X", m_global_regs[15]).mask(0xffffffff);
	1582	state_add(E132XS_G16,      "G16 :%08X", m_global_regs[16]).mask(0xffffffff);
	1583	state_add(E132XS_G17,      "G17 :%08X", m_global_regs[17]).mask(0xffffffff);
	1584	state_add(E132XS_SP,       "SP  :%08X", m_global_regs[18]).mask(0xffffffff);
	1585	state_add(E132XS_UB,       "UB  :%08X", m_global_regs[19]).mask(0xffffffff);
	1586	state_add(E132XS_BCR,      "BCR :%08X", m_global_regs[20]).mask(0xffffffff);
	1587	state_add(E132XS_TPR,      "TPR :%08X", m_global_regs[21]).mask(0xffffffff);
	1588	state_add(E132XS_TCR,      "TCR :%08X", m_global_regs[22]).mask(0xffffffff);
	1589	state_add(E132XS_TR,       "TR  :%08X", m_global_regs[23]).mask(0xffffffff);
	1590	state_add(E132XS_WCR,      "WCR :%08X", m_global_regs[24]).mask(0xffffffff);
	1591	state_add(E132XS_ISR,      "ISR :%08X", m_global_regs[25]).mask(0xffffffff);
	1592	state_add(E132XS_FCR,      "FCR :%08X", m_global_regs[26]).mask(0xffffffff);
	1593	state_add(E132XS_MCR,      "MCR :%08X", m_global_regs[27]).mask(0xffffffff);
	1594	state_add(E132XS_G28,      "G28 :%08X", m_global_regs[28]).mask(0xffffffff);
	1595	state_add(E132XS_G29,      "G29 :%08X", m_global_regs[29]).mask(0xffffffff);
	1596	state_add(E132XS_G30,      "G30 :%08X", m_global_regs[30]).mask(0xffffffff);
	1597	state_add(E132XS_G31,      "G31 :%08X", m_global_regs[31]).mask(0xffffffff);
	1598	state_add(E132XS_CL0,      "CL0 :%08X", m_local_regs[(0 + GET_FP) % 64]).mask(0xffffffff);
	1599	state_add(E132XS_CL1,      "CL1 :%08X", m_local_regs[(1 + GET_FP) % 64]).mask(0xffffffff);
	1600	state_add(E132XS_CL2,      "CL2 :%08X", m_local_regs[(2 + GET_FP) % 64]).mask(0xffffffff);
	1601	state_add(E132XS_CL3,      "CL3 :%08X", m_local_regs[(3 + GET_FP) % 64]).mask(0xffffffff);
	1602	state_add(E132XS_CL4,      "CL4 :%08X", m_local_regs[(4 + GET_FP) % 64]).mask(0xffffffff);
	1603	state_add(E132XS_CL5,      "CL5 :%08X", m_local_regs[(5 + GET_FP) % 64]).mask(0xffffffff);
	1604	state_add(E132XS_CL6,      "CL6 :%08X", m_local_regs[(6 + GET_FP) % 64]).mask(0xffffffff);
	1605	state_add(E132XS_CL7,      "CL7 :%08X", m_local_regs[(7 + GET_FP) % 64]).mask(0xffffffff);
	1606	state_add(E132XS_CL8,      "CL8 :%08X", m_local_regs[(8 + GET_FP) % 64]).mask(0xffffffff);
	1607	state_add(E132XS_CL9,      "CL9 :%08X", m_local_regs[(9 + GET_FP) % 64]).mask(0xffffffff);
	1608	state_add(E132XS_CL10,      "CL10:%08X", m_local_regs[(10 + GET_FP) % 64]).mask(0xffffffff);
	1609	state_add(E132XS_CL11,      "CL11:%08X", m_local_regs[(11 + GET_FP) % 64]).mask(0xffffffff);
	1610	state_add(E132XS_CL12,      "CL12:%08X", m_local_regs[(12 + GET_FP) % 64]).mask(0xffffffff);
	1611	state_add(E132XS_CL13,      "CL13:%08X", m_local_regs[(13 + GET_FP) % 64]).mask(0xffffffff);
	1612	state_add(E132XS_CL14,      "CL14:%08X", m_local_regs[(14 + GET_FP) % 64]).mask(0xffffffff);
	1613	state_add(E132XS_CL15,      "CL15:%08X", m_local_regs[(15 + GET_FP) % 64]).mask(0xffffffff);
	1614	state_add(E132XS_L0,       "L0  :%08X", m_local_regs[0]).mask(0xffffffff);
	1615	state_add(E132XS_L1,       "L1  :%08X", m_local_regs[1]).mask(0xffffffff);
	1616	state_add(E132XS_L2,       "L2  :%08X", m_local_regs[2]).mask(0xffffffff);
	1617	state_add(E132XS_L3,       "L3  :%08X", m_local_regs[3]).mask(0xffffffff);
	1618	state_add(E132XS_L4,       "L4  :%08X", m_local_regs[4]).mask(0xffffffff);
	1619	state_add(E132XS_L5,       "L5  :%08X", m_local_regs[5]).mask(0xffffffff);
	1620	state_add(E132XS_L6,       "L6  :%08X", m_local_regs[6]).mask(0xffffffff);
	1621	state_add(E132XS_L7,       "L7  :%08X", m_local_regs[7]).mask(0xffffffff);
	1622	state_add(E132XS_L8,       "L8  :%08X", m_local_regs[8]).mask(0xffffffff);
	1623	state_add(E132XS_L9,       "L9  :%08X", m_local_regs[9]).mask(0xffffffff);
	1624	state_add(E132XS_L10,      "L10 :%08X", m_local_regs[10]).mask(0xffffffff);
	1625	state_add(E132XS_L11,      "L11 :%08X", m_local_regs[11]).mask(0xffffffff);
	1626	state_add(E132XS_L12,      "L12 :%08X", m_local_regs[12]).mask(0xffffffff);
	1627	state_add(E132XS_L13,      "L13 :%08X", m_local_regs[13]).mask(0xffffffff);
	1628	state_add(E132XS_L14,      "L14 :%08X", m_local_regs[14]).mask(0xffffffff);
	1629	state_add(E132XS_L15,      "L15 :%08X", m_local_regs[15]).mask(0xffffffff);
	1630	state_add(E132XS_L16,      "L16 :%08X", m_local_regs[16]).mask(0xffffffff);
	1631	state_add(E132XS_L17,      "L17 :%08X", m_local_regs[17]).mask(0xffffffff);
	1632	state_add(E132XS_L18,      "L18 :%08X", m_local_regs[18]).mask(0xffffffff);
	1633	state_add(E132XS_L19,      "L19 :%08X", m_local_regs[19]).mask(0xffffffff);
	1634	state_add(E132XS_L20,      "L20 :%08X", m_local_regs[20]).mask(0xffffffff);
	1635	state_add(E132XS_L21,      "L21 :%08X", m_local_regs[21]).mask(0xffffffff);
	1636	state_add(E132XS_L22,      "L22 :%08X", m_local_regs[22]).mask(0xffffffff);
	1637	state_add(E132XS_L23,      "L23 :%08X", m_local_regs[23]).mask(0xffffffff);
	1638	state_add(E132XS_L24,      "L24 :%08X", m_local_regs[24]).mask(0xffffffff);
	1639	state_add(E132XS_L25,      "L25 :%08X", m_local_regs[25]).mask(0xffffffff);
	1640	state_add(E132XS_L26,      "L26 :%08X", m_local_regs[26]).mask(0xffffffff);
	1641	state_add(E132XS_L27,      "L27 :%08X", m_local_regs[27]).mask(0xffffffff);
	1642	state_add(E132XS_L28,      "L28 :%08X", m_local_regs[28]).mask(0xffffffff);
	1643	state_add(E132XS_L29,      "L29 :%08X", m_local_regs[29]).mask(0xffffffff);
	1644	state_add(E132XS_L30,      "L30 :%08X", m_local_regs[30]).mask(0xffffffff);
	1645	state_add(E132XS_L31,      "L31 :%08X", m_local_regs[31]).mask(0xffffffff);
	1646	state_add(E132XS_L32,      "L32 :%08X", m_local_regs[32]).mask(0xffffffff);
	1647	state_add(E132XS_L33,      "L33 :%08X", m_local_regs[33]).mask(0xffffffff);
	1648	state_add(E132XS_L34,      "L34 :%08X", m_local_regs[34]).mask(0xffffffff);
	1649	state_add(E132XS_L35,      "L35 :%08X", m_local_regs[35]).mask(0xffffffff);
	1650	state_add(E132XS_L36,      "L36 :%08X", m_local_regs[36]).mask(0xffffffff);
	1651	state_add(E132XS_L37,      "L37 :%08X", m_local_regs[37]).mask(0xffffffff);
	1652	state_add(E132XS_L38,      "L38 :%08X", m_local_regs[38]).mask(0xffffffff);
	1653	state_add(E132XS_L39,      "L39 :%08X", m_local_regs[39]).mask(0xffffffff);
	1654	state_add(E132XS_L40,      "L40 :%08X", m_local_regs[40]).mask(0xffffffff);
	1655	state_add(E132XS_L41,      "L41 :%08X", m_local_regs[41]).mask(0xffffffff);
	1656	state_add(E132XS_L42,      "L42 :%08X", m_local_regs[42]).mask(0xffffffff);
	1657	state_add(E132XS_L43,      "L43 :%08X", m_local_regs[43]).mask(0xffffffff);
	1658	state_add(E132XS_L44,      "L44 :%08X", m_local_regs[44]).mask(0xffffffff);
	1659	state_add(E132XS_L45,      "L45 :%08X", m_local_regs[45]).mask(0xffffffff);
	1660	state_add(E132XS_L46,      "L46 :%08X", m_local_regs[46]).mask(0xffffffff);
	1661	state_add(E132XS_L47,      "L47 :%08X", m_local_regs[47]).mask(0xffffffff);
	1662	state_add(E132XS_L48,      "L48 :%08X", m_local_regs[48]).mask(0xffffffff);
	1663	state_add(E132XS_L49,      "L49 :%08X", m_local_regs[49]).mask(0xffffffff);
	1664	state_add(E132XS_L50,      "L50 :%08X", m_local_regs[50]).mask(0xffffffff);
	1665	state_add(E132XS_L51,      "L51 :%08X", m_local_regs[51]).mask(0xffffffff);
	1666	state_add(E132XS_L52,      "L52 :%08X", m_local_regs[52]).mask(0xffffffff);
	1667	state_add(E132XS_L53,      "L53 :%08X", m_local_regs[53]).mask(0xffffffff);
	1668	state_add(E132XS_L54,      "L54 :%08X", m_local_regs[54]).mask(0xffffffff);
	1669	state_add(E132XS_L55,      "L55 :%08X", m_local_regs[55]).mask(0xffffffff);
	1670	state_add(E132XS_L56,      "L56 :%08X", m_local_regs[56]).mask(0xffffffff);
	1671	state_add(E132XS_L57,      "L57 :%08X", m_local_regs[57]).mask(0xffffffff);
	1672	state_add(E132XS_L58,      "L58 :%08X", m_local_regs[58]).mask(0xffffffff);
	1673	state_add(E132XS_L59,      "L59 :%08X", m_local_regs[59]).mask(0xffffffff);
	1674	state_add(E132XS_L60,      "L60 :%08X", m_local_regs[60]).mask(0xffffffff);
	1675	state_add(E132XS_L61,      "L61 :%08X", m_local_regs[61]).mask(0xffffffff);
	1676	state_add(E132XS_L62,      "L62 :%08X", m_local_regs[62]).mask(0xffffffff);
	1677	state_add(E132XS_L63,      "L63 :%08X", m_local_regs[63]).mask(0xffffffff);
	1678
	1679	save_item(NAME(m_global_regs));
	1680	save_item(NAME(m_local_regs));
	1681	save_item(NAME(m_ppc));
	1682	save_item(NAME(m_trap_entry));
	1683	save_item(NAME(m_delay.delay_pc));
	1684	save_item(NAME(m_instruction_length));
	1685	save_item(NAME(m_intblock));
	1686	save_item(NAME(m_delay.delay_cmd));
	1687	save_item(NAME(m_tr_clocks_per_tick));
	1688
	1689	// set our instruction counter
	1690	m_icountptr = &m_icount;
1562	1691	}
1563	1692
1564		static CPU_INIT( e116xt )
	1693	void e116t_device::device_start()
1565	1694	{
1566		e116_init(device, irqcallback, 3);
	1695	init(0);
	1696	m_opcodexor = 0;
1567	1697	}
1568	1698
1569		static CPU_INIT( e116xs )
	1699	void e116xt_device::device_start()
1570	1700	{
1571		e116_init(device, irqcallback, 7);
	1701	init(3);
	1702	m_opcodexor = 0;
1572	1703	}
1573	1704
1574		static CPU_INIT( e116xsr )
	1705	void e116xs_device::device_start()
1575	1706	{
1576		e116_init(device, irqcallback, 7);
	1707	init(7);
	1708	m_opcodexor = 0;
1577	1709	}
1578	1710
1579		static CPU_INIT( gms30c2116 )
	1711	void e116xsr_device::device_start()
1580	1712	{
1581		e116_init(device, irqcallback, 0);
	1713	init(7);
	1714	m_opcodexor = 0;
1582	1715	}
1583	1716
1584		static CPU_INIT( gms30c2216 )
	1717	void gms30c2116_device::device_start()
1585	1718	{
1586		e116_init(device, irqcallback, 0);
	1719	init(0);
	1720	m_opcodexor = 0;
1587	1721	}
1588	1722
1589		static void e132_init(legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback, int scale_mask)
	1723	void gms30c2216_device::device_start()
1590	1724	{
1591		hyperstone_state *cpustate = get_safe_token(device);
1592		hyperstone_init(device, irqcallback, scale_mask);
1593		cpustate->opcodexor = WORD_XOR_BE(0);
	1725	init(0);
	1726	m_opcodexor = 0;
1594	1727	}
1595	1728
1596		static CPU_INIT( e132n )
	1729	void e132n_device::device_start()
1597	1730	{
1598		e132_init(device, irqcallback, 0);
	1731	init(0);
	1732	m_opcodexor = WORD_XOR_BE(0);
1599	1733	}
1600	1734
1601		static CPU_INIT( e132t )
	1735	void e132t_device::device_start()
1602	1736	{
1603		e132_init(device, irqcallback, 0);
	1737	init(0);
	1738	m_opcodexor = WORD_XOR_BE(0);
1604	1739	}
1605	1740
1606		static CPU_INIT( e132xn )
	1741	void e132xn_device::device_start()
1607	1742	{
1608		e132_init(device, irqcallback, 3);
	1743	init(3);
	1744	m_opcodexor = WORD_XOR_BE(0);
1609	1745	}
1610	1746
1611		static CPU_INIT( e132xt )
	1747	void e132xt_device::device_start()
1612	1748	{
1613		e132_init(device, irqcallback, 3);
	1749	init(3);
	1750	m_opcodexor = WORD_XOR_BE(0);
1614	1751	}
1615	1752
1616		static CPU_INIT( e132xs )
	1753	void e132xs_device::device_start()
1617	1754	{
1618		e132_init(device, irqcallback, 7);
	1755	init(7);
	1756	m_opcodexor = WORD_XOR_BE(0);
1619	1757	}
1620	1758
1621		static CPU_INIT( e132xsr )
	1759	void e132xsr_device::device_start()
1622	1760	{
1623		e132_init(device, irqcallback, 7);
	1761	init(7);
	1762	m_opcodexor = WORD_XOR_BE(0);
1624	1763	}
1625	1764
1626		static CPU_INIT( gms30c2132 )
	1765	void gms30c2132_device::device_start()
1627	1766	{
1628		e132_init(device, irqcallback, 0);
	1767	init(0);
	1768	m_opcodexor = WORD_XOR_BE(0);
1629	1769	}
1630	1770
1631		static CPU_INIT( gms30c2232 )
	1771	void gms30c2232_device::device_start()
1632	1772	{
1633		e132_init(device, irqcallback, 0);
	1773	init(0);
	1774	m_opcodexor = WORD_XOR_BE(0);
1634	1775	}
1635	1776
1636		static CPU_RESET( hyperstone )
	1777	void hyperstone_device::device_reset()
1637	1778	{
1638		hyperstone_state *cpustate = get_safe_token(device);
1639
1640	1779	//TODO: Add different reset initializations for BCR, MCR, FCR, TPR
1641	1780
1642		emu_timer *save_timer;
1643		device_irq_acknowledge_callback save_irqcallback;
1644		UINT32 save_opcodexor;
	1781	m_program = &space(AS_PROGRAM);
	1782	m_direct = &m_program->direct();
	1783	m_io = &space(AS_IO);
1645	1784
1646		save_timer = cpustate->timer;
1647		save_irqcallback = cpustate->irq_callback;
1648		save_opcodexor = cpustate->opcodexor;
1649		memset(cpustate, 0, sizeof(*cpustate));
1650		cpustate->irq_callback = save_irqcallback;
1651		cpustate->opcodexor = save_opcodexor;
1652		cpustate->device = device;
1653		cpustate->program = &device->space(AS_PROGRAM);
1654		cpustate->direct = &cpustate->program->direct();
1655		cpustate->io = &device->space(AS_IO);
1656		cpustate->timer = save_timer;
	1785	m_tr_clocks_per_tick = 2;
1657	1786
1658		cpustate->tr_clocks_per_tick = 2;
	1787	hyperstone_set_trap_entry(E132XS_ENTRY_MEM3); /* default entry point @ MEM3 */
1659	1788
1660		hyperstone_set_trap_entry(cpustate, E132XS_ENTRY_MEM3); /* default entry point @ MEM3 */
	1789	set_global_register(BCR_REGISTER, ~0);
	1790	set_global_register(MCR_REGISTER, ~0);
	1791	set_global_register(FCR_REGISTER, ~0);
	1792	set_global_register(TPR_REGISTER, 0xc000000);
1661	1793
1662		set_global_register(cpustate, BCR_REGISTER, ~0);
1663		set_global_register(cpustate, MCR_REGISTER, ~0);
1664		set_global_register(cpustate, FCR_REGISTER, ~0);
1665		set_global_register(cpustate, TPR_REGISTER, 0xc000000);
	1794	PC = get_trap_addr(TRAPNO_RESET);
1666	1795
1667		PC = get_trap_addr(cpustate, TRAPNO_RESET);
1668
1669	1796	SET_FP(0);
1670	1797	SET_FL(2);
1671	1798
r19873	r19874
1677	1804	SET_L_REG(0, (PC & 0xfffffffe) | GET_S);
1678	1805	SET_L_REG(1, SR);
1679	1806
1680		cpustate->icount -= cpustate->clock_cycles_2;
	1807	m_icount -= m_clock_cycles_2;
1681	1808	}
1682	1809
1683		static CPU_EXIT( hyperstone )
	1810	void hyperstone_device::device_stop()
1684	1811	{
1685	1812	// nothing to do
1686	1813	}
1687	1814
1688		static CPU_DISASSEMBLE( hyperstone )
	1815
	1816	//-------------------------------------------------
	1817	//  memory_space_config - return the configuration
	1818	//  of the specified address space, or NULL if
	1819	//  the space doesn't exist
	1820	//-------------------------------------------------
	1821
	1822	const address_space_config *hyperstone_device::memory_space_config(address_spacenum spacenum) const
1689	1823	{
1690		hyperstone_state *cpustate = get_safe_token(device);
	1824	if (spacenum == AS_PROGRAM)
	1825	{
	1826	return &m_program_config;
	1827	}
	1828	else if (spacenum == AS_IO)
	1829	{
	1830	return &m_io_config;
	1831	}
	1832	return NULL;
	1833	}
	1834
	1835
	1836	//-------------------------------------------------
	1837	//  state_string_export - export state as a string
	1838	//  for the debugger
	1839	//-------------------------------------------------
	1840
	1841	void hyperstone_device::state_string_export(const device_state_entry &entry, astring &string)
	1842	{
	1843	switch (entry.index())
	1844	{
	1845	case STATE_GENFLAGS:
	1846	string.printf("%c%c%c%c%c%c%c%c%c%c%c%c FTE:%X FRM:%X ILC:%d FL:%d FP:%d",
	1847	GET_S ? 'S':'.',
	1848	GET_P ? 'P':'.',
	1849	GET_T ? 'T':'.',
	1850	GET_L ? 'L':'.',
	1851	GET_I ? 'I':'.',
	1852	m_global_regs[1] & 0x00040 ? '?':'.',
	1853	GET_H ? 'H':'.',
	1854	GET_M ? 'M':'.',
	1855	GET_V ? 'V':'.',
	1856	GET_N ? 'N':'.',
	1857	GET_Z ? 'Z':'.',
	1858	GET_C ? 'C':'.',
	1859	GET_FTE,
	1860	GET_FRM,
	1861	GET_ILC,
	1862	GET_FL,
	1863	GET_FP);
	1864	break;
	1865	}
	1866	}
	1867
	1868
	1869	//-------------------------------------------------
	1870	//  disasm_min_opcode_bytes - return the length
	1871	//  of the shortest instruction, in bytes
	1872	//-------------------------------------------------
	1873
	1874	UINT32 hyperstone_device::disasm_min_opcode_bytes() const
	1875	{
	1876	return 2;
	1877	}
	1878
	1879
	1880	//-------------------------------------------------
	1881	//  disasm_max_opcode_bytes - return the length
	1882	//  of the longest instruction, in bytes
	1883	//-------------------------------------------------
	1884
	1885	UINT32 hyperstone_device::disasm_max_opcode_bytes() const
	1886	{
	1887	return 6;
	1888	}
	1889
	1890
	1891	//-------------------------------------------------
	1892	//  disasm_disassemble - call the disassembly
	1893	//  helper function
	1894	//-------------------------------------------------
	1895
	1896	offs_t hyperstone_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
	1897	{
	1898	extern CPU_DISASSEMBLE( hyperstone );
1691	1899	return dasm_hyperstone( buffer, pc, oprom, GET_H, GET_FP );
1692	1900	}
1693	1901
1694	1902	/* Opcodes */
1695	1903
1696		INLINE void hyperstone_chk(hyperstone_state *cpustate, struct regs_decode *decode)
	1904	void hyperstone_device::hyperstone_chk(struct hyperstone_device::regs_decode *decode)
1697	1905	{
1698		UINT32 addr = get_trap_addr(cpustate, TRAPNO_RANGE_ERROR);
	1906	UINT32 addr = get_trap_addr(TRAPNO_RANGE_ERROR);
1699	1907
1700	1908	if( SRC_IS_SR )
1701	1909	{
1702	1910	if( DREG == 0 )
1703		execute_exception(cpustate, addr);
	1911	execute_exception(addr);
1704	1912	}
1705	1913	else
1706	1914	{
1707	1915	if( SRC_IS_PC )
1708	1916	{
1709	1917	if( DREG >= SREG )
1710		execute_exception(cpustate, addr);
	1918	execute_exception(addr);
1711	1919	}
1712	1920	else
1713	1921	{
1714	1922	if( DREG > SREG )
1715		execute_exception(cpustate, addr);
	1923	execute_exception(addr);
1716	1924	}
1717	1925	}
1718	1926
1719		cpustate->icount -= cpustate->clock_cycles_1;
	1927	m_icount -= m_clock_cycles_1;
1720	1928	}
1721	1929
1722		INLINE void hyperstone_movd(hyperstone_state *cpustate, struct regs_decode *decode)
	1930	void hyperstone_device::hyperstone_movd(struct hyperstone_device::regs_decode *decode)
1723	1931	{
1724	1932	if( DST_IS_PC ) // Rd denotes PC
1725	1933	{
r19873	r19874
1740	1948
1741	1949	SET_PC(SREG);
1742	1950	SR = (SREGF & 0xffe00000) | ((SREG & 0x01) << 18 ) | (SREGF & 0x3ffff);
1743		if (cpustate->intblock < 1)
1744		cpustate->intblock = 1;
	1951	if (m_intblock < 1)
	1952	m_intblock = 1;
1745	1953
1746		cpustate->instruction_length = 0; // undefined
	1954	m_instruction_length = 0; // undefined
1747	1955
1748	1956	if( (!old_s && GET_S) || (!GET_S && !old_l && GET_L))
1749	1957	{
1750		UINT32 addr = get_trap_addr(cpustate, TRAPNO_PRIVILEGE_ERROR);
1751		execute_exception(cpustate, addr);
	1958	UINT32 addr = get_trap_addr(TRAPNO_PRIVILEGE_ERROR);
	1959	execute_exception(addr);
1752	1960	}
1753	1961
1754	1962	difference = GET_FP - ((SP & 0x1fc) >> 2);
r19873	r19874
1764	1972	do
1765	1973	{
1766	1974	SP -= 4;
1767		SET_ABS_L_REG(((SP & 0xfc) >> 2), READ_W(cpustate, SP));
	1975	SET_ABS_L_REG(((SP & 0xfc) >> 2), READ_W(SP));
1768	1976	difference++;
1769	1977
1770	1978	} while(difference != 0);
r19873	r19874
1772	1980	}
1773	1981
1774	1982	//TODO: no 1!
1775		cpustate->icount -= cpustate->clock_cycles_1;
	1983	m_icount -= m_clock_cycles_1;
1776	1984	}
1777	1985	else if( SRC_IS_SR ) // Rd doesn't denote PC and Rs denotes SR
1778	1986	{
r19873	r19874
1781	1989	SET_Z(1);
1782	1990	SET_N(0);
1783	1991
1784		cpustate->icount -= cpustate->clock_cycles_2;
	1992	m_icount -= m_clock_cycles_2;
1785	1993	}
1786	1994	else // Rd doesn't denote PC and Rs doesn't denote SR
1787	1995	{
r19873	r19874
1794	2002	SET_Z( tmp == 0 ? 1 : 0 );
1795	2003	SET_N( SIGN_BIT(SREG) );
1796	2004
1797		cpustate->icount -= cpustate->clock_cycles_2;
	2005	m_icount -= m_clock_cycles_2;
1798	2006	}
1799	2007	}
1800	2008
1801		INLINE void hyperstone_divu(hyperstone_state *cpustate, struct regs_decode *decode)
	2009	void hyperstone_device::hyperstone_divu(struct hyperstone_device::regs_decode *decode)
1802	2010	{
1803	2011	if( SAME_SRC_DST || SAME_SRC_DSTF )
1804	2012	{
r19873	r19874
1823	2031	//N -> undefined
1824	2032	UINT32 addr;
1825	2033	SET_V(1);
1826		addr = get_trap_addr(cpustate, TRAPNO_RANGE_ERROR);
1827		execute_exception(cpustate, addr);
	2034	addr = get_trap_addr(TRAPNO_RANGE_ERROR);
	2035	execute_exception(addr);
1828	2036	}
1829	2037	else
1830	2038	{
r19873	r19874
1844	2052	}
1845	2053	}
1846	2054
1847		cpustate->icount -= 36 << cpustate->clock_scale;
	2055	m_icount -= 36 << m_clock_scale;
1848	2056	}
1849	2057
1850		INLINE void hyperstone_divs(hyperstone_state *cpustate, struct regs_decode *decode)
	2058	void hyperstone_device::hyperstone_divs(struct hyperstone_device::regs_decode *decode)
1851	2059	{
1852	2060	if( SAME_SRC_DST || SAME_SRC_DSTF )
1853	2061	{
r19873	r19874
1872	2080	//N -> undefined
1873	2081	UINT32 addr;
1874	2082	SET_V(1);
1875		addr = get_trap_addr(cpustate, TRAPNO_RANGE_ERROR);
1876		execute_exception(cpustate, addr);
	2083	addr = get_trap_addr(TRAPNO_RANGE_ERROR);
	2084	execute_exception(addr);
1877	2085	}
1878	2086	else
1879	2087	{
r19873	r19874
1893	2101	}
1894	2102	}
1895	2103
1896		cpustate->icount -= 36 << cpustate->clock_scale;
	2104	m_icount -= 36 << m_clock_scale;
1897	2105	}
1898	2106
1899		INLINE void hyperstone_xm(hyperstone_state *cpustate, struct regs_decode *decode)
	2107	void hyperstone_device::hyperstone_xm(struct hyperstone_device::regs_decode *decode)
1900	2108	{
1901	2109	if( SRC_IS_SR || DST_IS_SR || DST_IS_PC )
1902	2110	{
r19873	r19874
1912	2120	case 3:
1913	2121	if( !SRC_IS_PC && (SREG > EXTRA_U) )
1914	2122	{
1915		UINT32 addr = get_trap_addr(cpustate, TRAPNO_RANGE_ERROR);
1916		execute_exception(cpustate, addr);
	2123	UINT32 addr = get_trap_addr(TRAPNO_RANGE_ERROR);
	2124	execute_exception(addr);
1917	2125	}
1918	2126	else if( SRC_IS_PC && (SREG >= EXTRA_U) )
1919	2127	{
1920		UINT32 addr = get_trap_addr(cpustate, TRAPNO_RANGE_ERROR);
1921		execute_exception(cpustate, addr);
	2128	UINT32 addr = get_trap_addr(TRAPNO_RANGE_ERROR);
	2129	execute_exception(addr);
1922	2130	}
1923	2131	else
1924	2132	{
r19873	r19874
1940	2148	SET_DREG(SREG);
1941	2149	}
1942	2150
1943		cpustate->icount -= cpustate->clock_cycles_1;
	2151	m_icount -= m_clock_cycles_1;
1944	2152	}
1945	2153
1946		INLINE void hyperstone_mask(hyperstone_state *cpustate, struct regs_decode *decode)
	2154	void hyperstone_device::hyperstone_mask(struct hyperstone_device::regs_decode *decode)
1947	2155	{
1948	2156	DREG = SREG & EXTRA_U;
1949	2157
1950	2158	SET_DREG(DREG);
1951	2159	SET_Z( DREG == 0 ? 1 : 0 );
1952	2160
1953		cpustate->icount -= cpustate->clock_cycles_1;
	2161	m_icount -= m_clock_cycles_1;
1954	2162	}
1955	2163
1956		INLINE void hyperstone_sum(hyperstone_state *cpustate, struct regs_decode *decode)
	2164	void hyperstone_device::hyperstone_sum(struct hyperstone_device::regs_decode *decode)
1957	2165	{
1958	2166	UINT64 tmp;
1959	2167
r19873	r19874
1974	2182	SET_Z( DREG == 0 ? 1 : 0 );
1975	2183	SET_N( SIGN_BIT(DREG) );
1976	2184
1977		cpustate->icount -= cpustate->clock_cycles_1;
	2185	m_icount -= m_clock_cycles_1;
1978	2186	}
1979	2187
1980		INLINE void hyperstone_sums(hyperstone_state *cpustate, struct regs_decode *decode)
	2188	void hyperstone_device::hyperstone_sums(struct hyperstone_device::regs_decode *decode)
1981	2189	{
1982	2190	INT32 res;
1983	2191	INT64 tmp;
r19873	r19874
1999	2207	SET_Z( res == 0 ? 1 : 0 );
2000	2208	SET_N( SIGN_BIT(res) );
2001	2209
2002		cpustate->icount -= cpustate->clock_cycles_1;
	2210	m_icount -= m_clock_cycles_1;
2003	2211
2004	2212	if( GET_V && !SRC_IS_SR )
2005	2213	{
2006		UINT32 addr = get_trap_addr(cpustate, TRAPNO_RANGE_ERROR);
2007		execute_exception(cpustate, addr);
	2214	UINT32 addr = get_trap_addr(TRAPNO_RANGE_ERROR);
	2215	execute_exception(addr);
2008	2216	}
2009	2217	}
2010	2218
2011		INLINE void hyperstone_cmp(hyperstone_state *cpustate, struct regs_decode *decode)
	2219	void hyperstone_device::hyperstone_cmp(struct hyperstone_device::regs_decode *decode)
2012	2220	{
2013	2221	UINT64 tmp;
2014	2222
r19873	r19874
2033	2241	else
2034	2242	SET_C(0);
2035	2243
2036		cpustate->icount -= cpustate->clock_cycles_1;
	2244	m_icount -= m_clock_cycles_1;
2037	2245	}
2038	2246
2039		INLINE void hyperstone_mov(hyperstone_state *cpustate, struct regs_decode *decode)
	2247	void hyperstone_device::hyperstone_mov(struct hyperstone_device::regs_decode *decode)
2040	2248	{
2041	2249	if( !GET_S && decode->dst >= 16 )
2042	2250	{
2043		UINT32 addr = get_trap_addr(cpustate, TRAPNO_PRIVILEGE_ERROR);
2044		execute_exception(cpustate, addr);
	2251	UINT32 addr = get_trap_addr(TRAPNO_PRIVILEGE_ERROR);
	2252	execute_exception(addr);
2045	2253	}
2046	2254
2047	2255	SET_DREG(SREG);
r19873	r19874
2052	2260	SET_Z( SREG == 0 ? 1 : 0 );
2053	2261	SET_N( SIGN_BIT(SREG) );
2054	2262
2055		cpustate->icount -= cpustate->clock_cycles_1;
	2263	m_icount -= m_clock_cycles_1;
2056	2264	}
2057	2265
2058	2266
2059		INLINE void hyperstone_add(hyperstone_state *cpustate, struct regs_decode *decode)
	2267	void hyperstone_device::hyperstone_add(struct hyperstone_device::regs_decode *decode)
2060	2268	{
2061	2269	UINT64 tmp;
2062	2270
r19873	r19874
2076	2284	SET_Z( DREG == 0 ? 1 : 0 );
2077	2285	SET_N( SIGN_BIT(DREG) );
2078	2286
2079		cpustate->icount -= cpustate->clock_cycles_1;
	2287	m_icount -= m_clock_cycles_1;
2080	2288	}
2081	2289
2082		INLINE void hyperstone_adds(hyperstone_state *cpustate, struct regs_decode *decode)
	2290	void hyperstone_device::hyperstone_adds(struct hyperstone_device::regs_decode *decode)
2083	2291	{
2084	2292	INT32 res;
2085	2293	INT64 tmp;
r19873	r19874
2101	2309	SET_Z( res == 0 ? 1 : 0 );
2102	2310	SET_N( SIGN_BIT(res) );
2103	2311
2104		cpustate->icount -= cpustate->clock_cycles_1;
	2312	m_icount -= m_clock_cycles_1;
2105	2313
2106	2314	if( GET_V )
2107	2315	{
2108		UINT32 addr = get_trap_addr(cpustate, TRAPNO_RANGE_ERROR);
2109		execute_exception(cpustate, addr);
	2316	UINT32 addr = get_trap_addr(TRAPNO_RANGE_ERROR);
	2317	execute_exception(addr);
2110	2318	}
2111	2319	}
2112	2320
2113		INLINE void hyperstone_cmpb(hyperstone_state *cpustate, struct regs_decode *decode)
	2321	void hyperstone_device::hyperstone_cmpb(struct hyperstone_device::regs_decode *decode)
2114	2322	{
2115	2323	SET_Z( (DREG & SREG) == 0 ? 1 : 0 );
2116	2324
2117		cpustate->icount -= cpustate->clock_cycles_1;
	2325	m_icount -= m_clock_cycles_1;
2118	2326	}
2119	2327
2120		INLINE void hyperstone_andn(hyperstone_state *cpustate, struct regs_decode *decode)
	2328	void hyperstone_device::hyperstone_andn(struct hyperstone_device::regs_decode *decode)
2121	2329	{
2122	2330	DREG = DREG & ~SREG;
2123	2331
2124	2332	SET_DREG(DREG);
2125	2333	SET_Z( DREG == 0 ? 1 : 0 );
2126	2334
2127		cpustate->icount -= cpustate->clock_cycles_1;
	2335	m_icount -= m_clock_cycles_1;
2128	2336	}
2129	2337
2130		INLINE void hyperstone_or(hyperstone_state *cpustate, struct regs_decode *decode)
	2338	void hyperstone_device::hyperstone_or(struct hyperstone_device::regs_decode *decode)
2131	2339	{
2132	2340	DREG = DREG | SREG;
2133	2341
2134	2342	SET_DREG(DREG);
2135	2343	SET_Z( DREG == 0 ? 1 : 0 );
2136	2344
2137		cpustate->icount -= cpustate->clock_cycles_1;
	2345	m_icount -= m_clock_cycles_1;
2138	2346	}
2139	2347
2140		INLINE void hyperstone_xor(hyperstone_state *cpustate, struct regs_decode *decode)
	2348	void hyperstone_device::hyperstone_xor(struct hyperstone_device::regs_decode *decode)
2141	2349	{
2142	2350	DREG = DREG ^ SREG;
2143	2351
2144	2352	SET_DREG(DREG);
2145	2353	SET_Z( DREG == 0 ? 1 : 0 );
2146	2354
2147		cpustate->icount -= cpustate->clock_cycles_1;
	2355	m_icount -= m_clock_cycles_1;
2148	2356	}
2149	2357
2150		INLINE void hyperstone_subc(hyperstone_state *cpustate, struct regs_decode *decode)
	2358	void hyperstone_device::hyperstone_subc(struct hyperstone_device::regs_decode *decode)
2151	2359	{
2152	2360	UINT64 tmp;
2153	2361
r19873	r19874
2180	2388	SET_Z( GET_Z & (DREG == 0 ? 1 : 0) );
2181	2389	SET_N( SIGN_BIT(DREG) );
2182	2390
2183		cpustate->icount -= cpustate->clock_cycles_1;
	2391	m_icount -= m_clock_cycles_1;
2184	2392	}
2185	2393
2186		INLINE void hyperstone_not(hyperstone_state *cpustate, struct regs_decode *decode)
	2394	void hyperstone_device::hyperstone_not(struct hyperstone_device::regs_decode *decode)
2187	2395	{
2188	2396	SET_DREG(~SREG);
2189	2397	SET_Z( ~SREG == 0 ? 1 : 0 );
2190	2398
2191		cpustate->icount -= cpustate->clock_cycles_1;
	2399	m_icount -= m_clock_cycles_1;
2192	2400	}
2193	2401
2194		INLINE void hyperstone_sub(hyperstone_state *cpustate, struct regs_decode *decode)
	2402	void hyperstone_device::hyperstone_sub(struct hyperstone_device::regs_decode *decode)
2195	2403	{
2196	2404	UINT64 tmp;
2197	2405
r19873	r19874
2211	2419	SET_Z( DREG == 0 ? 1 : 0 );
2212	2420	SET_N( SIGN_BIT(DREG) );
2213	2421
2214		cpustate->icount -= cpustate->clock_cycles_1;
	2422	m_icount -= m_clock_cycles_1;
2215	2423	}
2216	2424
2217		INLINE void hyperstone_subs(hyperstone_state *cpustate, struct regs_decode *decode)
	2425	void hyperstone_device::hyperstone_subs(struct hyperstone_device::regs_decode *decode)
2218	2426	{
2219	2427	INT32 res;
2220	2428	INT64 tmp;
r19873	r19874
2237	2445	SET_Z( res == 0 ? 1 : 0 );
2238	2446	SET_N( SIGN_BIT(res) );
2239	2447
2240		cpustate->icount -= cpustate->clock_cycles_1;
	2448	m_icount -= m_clock_cycles_1;
2241	2449
2242	2450	if( GET_V )
2243	2451	{
2244		UINT32 addr = get_trap_addr(cpustate, TRAPNO_RANGE_ERROR);
2245		execute_exception(cpustate, addr);
	2452	UINT32 addr = get_trap_addr(TRAPNO_RANGE_ERROR);
	2453	execute_exception(addr);
2246	2454	}
2247	2455	}
2248	2456
2249		INLINE void hyperstone_addc(hyperstone_state *cpustate, struct regs_decode *decode)
	2457	void hyperstone_device::hyperstone_addc(struct hyperstone_device::regs_decode *decode)
2250	2458	{
2251	2459	UINT64 tmp;
2252	2460
r19873	r19874
2284	2492	SET_Z( GET_Z & (DREG == 0 ? 1 : 0) );
2285	2493	SET_N( SIGN_BIT(DREG) );
2286	2494
2287		cpustate->icount -= cpustate->clock_cycles_1;
	2495	m_icount -= m_clock_cycles_1;
2288	2496	}
2289	2497
2290		INLINE void hyperstone_and(hyperstone_state *cpustate, struct regs_decode *decode)
	2498	void hyperstone_device::hyperstone_and(struct hyperstone_device::regs_decode *decode)
2291	2499	{
2292	2500	DREG = DREG & SREG;
2293	2501
2294	2502	SET_DREG(DREG);
2295	2503	SET_Z( DREG == 0 ? 1 : 0 );
2296	2504
2297		cpustate->icount -= cpustate->clock_cycles_1;
	2505	m_icount -= m_clock_cycles_1;
2298	2506	}
2299	2507
2300		INLINE void hyperstone_neg(hyperstone_state *cpustate, struct regs_decode *decode)
	2508	void hyperstone_device::hyperstone_neg(struct hyperstone_device::regs_decode *decode)
2301	2509	{
2302	2510	UINT64 tmp;
2303	2511
r19873	r19874
2315	2523	SET_Z( DREG == 0 ? 1 : 0 );
2316	2524	SET_N( SIGN_BIT(DREG) );
2317	2525
2318		cpustate->icount -= cpustate->clock_cycles_1;
	2526	m_icount -= m_clock_cycles_1;
2319	2527	}
2320	2528
2321		INLINE void hyperstone_negs(hyperstone_state *cpustate, struct regs_decode *decode)
	2529	void hyperstone_device::hyperstone_negs(struct hyperstone_device::regs_decode *decode)
2322	2530	{
2323	2531	INT32 res;
2324	2532	INT64 tmp;
r19873	r19874
2341	2549	SET_N( SIGN_BIT(res) );
2342	2550
2343	2551
2344		cpustate->icount -= cpustate->clock_cycles_1;
	2552	m_icount -= m_clock_cycles_1;
2345	2553
2346	2554	if( GET_V && !SRC_IS_SR ) //trap doesn't occur when source is SR
2347	2555	{
2348		UINT32 addr = get_trap_addr(cpustate, TRAPNO_RANGE_ERROR);
2349		execute_exception(cpustate, addr);
	2556	UINT32 addr = get_trap_addr(TRAPNO_RANGE_ERROR);
	2557	execute_exception(addr);
2350	2558	}
2351	2559	}
2352	2560
2353		INLINE void hyperstone_cmpi(hyperstone_state *cpustate, struct regs_decode *decode)
	2561	void hyperstone_device::hyperstone_cmpi(struct hyperstone_device::regs_decode *decode)
2354	2562	{
2355	2563	UINT64 tmp;
2356	2564
r19873	r19874
2372	2580	else
2373	2581	SET_C(0);
2374	2582
2375		cpustate->icount -= cpustate->clock_cycles_1;
	2583	m_icount -= m_clock_cycles_1;
2376	2584	}
2377	2585
2378		INLINE void hyperstone_movi(hyperstone_state *cpustate, struct regs_decode *decode)
	2586	void hyperstone_device::hyperstone_movi(struct hyperstone_device::regs_decode *decode)
2379	2587	{
2380	2588	if( !GET_S && decode->dst >= 16 )
2381	2589	{
2382		UINT32 addr = get_trap_addr(cpustate, TRAPNO_PRIVILEGE_ERROR);
2383		execute_exception(cpustate, addr);
	2590	UINT32 addr = get_trap_addr(TRAPNO_PRIVILEGE_ERROR);
	2591	execute_exception(addr);
2384	2592	}
2385	2593
2386	2594	SET_DREG(EXTRA_U);
r19873	r19874
2395	2603	SET_V(0); // or V undefined ?
2396	2604	#endif
2397	2605
2398		cpustate->icount -= cpustate->clock_cycles_1;
	2606	m_icount -= m_clock_cycles_1;
2399	2607	}
2400	2608
2401		INLINE void hyperstone_addi(hyperstone_state *cpustate, struct regs_decode *decode)
	2609	void hyperstone_device::hyperstone_addi(struct hyperstone_device::regs_decode *decode)
2402	2610	{
2403	2611	UINT32 imm;
2404	2612	UINT64 tmp;
r19873	r19874
2422	2630	SET_Z( DREG == 0 ? 1 : 0 );
2423	2631	SET_N( SIGN_BIT(DREG) );
2424	2632
2425		cpustate->icount -= cpustate->clock_cycles_1;
	2633	m_icount -= m_clock_cycles_1;
2426	2634	}
2427	2635
2428		INLINE void hyperstone_addsi(hyperstone_state *cpustate, struct regs_decode *decode)
	2636	void hyperstone_device::hyperstone_addsi(struct hyperstone_device::regs_decode *decode)
2429	2637	{
2430	2638	INT32 imm, res;
2431	2639	INT64 tmp;
r19873	r19874
2449	2657	SET_Z( res == 0 ? 1 : 0 );
2450	2658	SET_N( SIGN_BIT(res) );
2451	2659
2452		cpustate->icount -= cpustate->clock_cycles_1;
	2660	m_icount -= m_clock_cycles_1;
2453	2661
2454	2662	if( GET_V )
2455	2663	{
2456		UINT32 addr = get_trap_addr(cpustate, TRAPNO_RANGE_ERROR);
2457		execute_exception(cpustate, addr);
	2664	UINT32 addr = get_trap_addr(TRAPNO_RANGE_ERROR);
	2665	execute_exception(addr);
2458	2666	}
2459	2667	}
2460	2668
2461		INLINE void hyperstone_cmpbi(hyperstone_state *cpustate, struct regs_decode *decode)
	2669	void hyperstone_device::hyperstone_cmpbi(struct hyperstone_device::regs_decode *decode)
2462	2670	{
2463	2671	UINT32 imm;
2464	2672
r19873	r19874
2484	2692	SET_Z(0);
2485	2693	}
2486	2694
2487		cpustate->icount -= cpustate->clock_cycles_1;
	2695	m_icount -= m_clock_cycles_1;
2488	2696	}
2489	2697
2490		INLINE void hyperstone_andni(hyperstone_state *cpustate, struct regs_decode *decode)
	2698	void hyperstone_device::hyperstone_andni(struct hyperstone_device::regs_decode *decode)
2491	2699	{
2492	2700	UINT32 imm;
2493	2701
r19873	r19874
2501	2709	SET_DREG(DREG);
2502	2710	SET_Z( DREG == 0 ? 1 : 0 );
2503	2711
2504		cpustate->icount -= cpustate->clock_cycles_1;
	2712	m_icount -= m_clock_cycles_1;
2505	2713	}
2506	2714
2507		INLINE void hyperstone_ori(hyperstone_state *cpustate, struct regs_decode *decode)
	2715	void hyperstone_device::hyperstone_ori(struct hyperstone_device::regs_decode *decode)
2508	2716	{
2509	2717	DREG = DREG | EXTRA_U;
2510	2718
2511	2719	SET_DREG(DREG);
2512	2720	SET_Z( DREG == 0 ? 1 : 0 );
2513	2721
2514		cpustate->icount -= cpustate->clock_cycles_1;
	2722	m_icount -= m_clock_cycles_1;
2515	2723	}
2516	2724
2517		INLINE void hyperstone_xori(hyperstone_state *cpustate, struct regs_decode *decode)
	2725	void hyperstone_device::hyperstone_xori(struct hyperstone_device::regs_decode *decode)
2518	2726	{
2519	2727	DREG = DREG ^ EXTRA_U;
2520	2728
2521	2729	SET_DREG(DREG);
2522	2730	SET_Z( DREG == 0 ? 1 : 0 );
2523	2731
2524		cpustate->icount -= cpustate->clock_cycles_1;
	2732	m_icount -= m_clock_cycles_1;
2525	2733	}
2526	2734
2527		INLINE void hyperstone_shrdi(hyperstone_state *cpustate, struct regs_decode *decode)
	2735	void hyperstone_device::hyperstone_shrdi(struct hyperstone_device::regs_decode *decode)
2528	2736	{
2529	2737	UINT32 low_order, high_order;
2530	2738	UINT64 val;
r19873	r19874
2549	2757	SET_Z( val == 0 ? 1 : 0 );
2550	2758	SET_N( SIGN_BIT(high_order) );
2551	2759
2552		cpustate->icount -= cpustate->clock_cycles_2;
	2760	m_icount -= m_clock_cycles_2;
2553	2761	}
2554	2762
2555		INLINE void hyperstone_shrd(hyperstone_state *cpustate, struct regs_decode *decode)
	2763	void hyperstone_device::hyperstone_shrd(struct hyperstone_device::regs_decode *decode)
2556	2764	{
2557	2765	UINT32 low_order, high_order;
2558	2766	UINT64 val;
r19873	r19874
2587	2795	SET_N( SIGN_BIT(high_order) );
2588	2796	}
2589	2797
2590		cpustate->icount -= cpustate->clock_cycles_2;
	2798	m_icount -= m_clock_cycles_2;
2591	2799	}
2592	2800
2593		INLINE void hyperstone_shr(hyperstone_state *cpustate, struct regs_decode *decode)
	2801	void hyperstone_device::hyperstone_shr(struct hyperstone_device::regs_decode *decode)
2594	2802	{
2595	2803	UINT32 ret;
2596	2804	UINT8 n;
r19873	r19874
2609	2817	SET_Z( ret == 0 ? 1 : 0 );
2610	2818	SET_N( SIGN_BIT(ret) );
2611	2819
2612		cpustate->icount -= cpustate->clock_cycles_1;
	2820	m_icount -= m_clock_cycles_1;
2613	2821	}
2614	2822
2615		INLINE void hyperstone_sardi(hyperstone_state *cpustate, struct regs_decode *decode)
	2823	void hyperstone_device::hyperstone_sardi(struct hyperstone_device::regs_decode *decode)
2616	2824	{
2617	2825	UINT32 low_order, high_order;
2618	2826	UINT64 val;
r19873	r19874
2649	2857	SET_Z( val == 0 ? 1 : 0 );
2650	2858	SET_N( SIGN_BIT(high_order) );
2651	2859
2652		cpustate->icount -= cpustate->clock_cycles_2;
	2860	m_icount -= m_clock_cycles_2;
2653	2861	}
2654	2862
2655		INLINE void hyperstone_sard(hyperstone_state *cpustate, struct regs_decode *decode)
	2863	void hyperstone_device::hyperstone_sard(struct hyperstone_device::regs_decode *decode)
2656	2864	{
2657	2865	UINT32 low_order, high_order;
2658	2866	UINT64 val;
r19873	r19874
2699	2907	SET_N( SIGN_BIT(high_order) );
2700	2908	}
2701	2909
2702		cpustate->icount -= cpustate->clock_cycles_2;
	2910	m_icount -= m_clock_cycles_2;
2703	2911	}
2704	2912
2705		INLINE void hyperstone_sar(hyperstone_state *cpustate, struct regs_decode *decode)
	2913	void hyperstone_device::hyperstone_sar(struct hyperstone_device::regs_decode *decode)
2706	2914	{
2707	2915	UINT32 ret;
2708	2916	UINT8 n, sign_bit;
r19873	r19874
2731	2939	SET_Z( ret == 0 ? 1 : 0 );
2732	2940	SET_N( SIGN_BIT(ret) );
2733	2941
2734		cpustate->icount -= cpustate->clock_cycles_1;
	2942	m_icount -= m_clock_cycles_1;
2735	2943	}
2736	2944
2737		INLINE void hyperstone_shldi(hyperstone_state *cpustate, struct regs_decode *decode)
	2945	void hyperstone_device::hyperstone_shldi(struct hyperstone_device::regs_decode *decode)
2738	2946	{
2739	2947	UINT32 low_order, high_order, tmp;
2740	2948	UINT64 val, mask;
r19873	r19874
2764	2972	SET_Z( val == 0 ? 1 : 0 );
2765	2973	SET_N( SIGN_BIT(high_order) );
2766	2974
2767		cpustate->icount -= cpustate->clock_cycles_2;
	2975	m_icount -= m_clock_cycles_2;
2768	2976	}
2769	2977
2770		INLINE void hyperstone_shld(hyperstone_state *cpustate, struct regs_decode *decode)
	2978	void hyperstone_device::hyperstone_shld(struct hyperstone_device::regs_decode *decode)
2771	2979	{
2772	2980	UINT32 low_order, high_order, tmp, n;
2773	2981	UINT64 val, mask;
r19873	r19874
2808	3016	SET_N( SIGN_BIT(high_order) );
2809	3017	}
2810	3018
2811		cpustate->icount -= cpustate->clock_cycles_2;
	3019	m_icount -= m_clock_cycles_2;
2812	3020	}
2813	3021
2814		INLINE void hyperstone_shl(hyperstone_state *cpustate, struct regs_decode *decode)
	3022	void hyperstone_device::hyperstone_shl(struct hyperstone_device::regs_decode *decode)
2815	3023	{
2816	3024	UINT32 base, ret, n;
2817	3025	UINT64 mask;
r19873	r19874
2832	3040	SET_Z( ret == 0 ? 1 : 0 );
2833	3041	SET_N( SIGN_BIT(ret) );
2834	3042
2835		cpustate->icount -= cpustate->clock_cycles_1;
	3043	m_icount -= m_clock_cycles_1;
2836	3044	}
2837	3045
2838		static void reserved(hyperstone_state *cpustate, struct regs_decode *decode)
	3046	void hyperstone_device::reserved(struct hyperstone_device::regs_decode *decode)
2839	3047	{
2840	3048	DEBUG_PRINTF(("Executed Reserved opcode. PC = %08X OP = %04X\n", PC, OP));
2841	3049	}
2842	3050
2843		INLINE void hyperstone_testlz(hyperstone_state *cpustate, struct regs_decode *decode)
	3051	void hyperstone_device::hyperstone_testlz(struct hyperstone_device::regs_decode *decode)
2844	3052	{
2845	3053	UINT8 zeros = 0;
2846	3054	UINT32 mask;
r19873	r19874
2858	3066
2859	3067	SET_DREG(zeros);
2860	3068
2861		cpustate->icount -= cpustate->clock_cycles_2;
	3069	m_icount -= m_clock_cycles_2;
2862	3070	}
2863	3071
2864		INLINE void hyperstone_rol(hyperstone_state *cpustate, struct regs_decode *decode)
	3072	void hyperstone_device::hyperstone_rol(struct hyperstone_device::regs_decode *decode)
2865	3073	{
2866	3074	UINT32 val, base;
2867	3075	UINT8 n;
r19873	r19874
2894	3102	SET_Z( val == 0 ? 1 : 0 );
2895	3103	SET_N( SIGN_BIT(val) );
2896	3104
2897		cpustate->icount -= cpustate->clock_cycles_1;
	3105	m_icount -= m_clock_cycles_1;
2898	3106	}
2899	3107
2900	3108	//TODO: add trap error
2901		INLINE void hyperstone_ldxx1(hyperstone_state *cpustate, struct regs_decode *decode)
	3109	void hyperstone_device::hyperstone_ldxx1(struct hyperstone_device::regs_decode *decode)
2902	3110	{
2903	3111	UINT32 load;
2904	3112
r19873	r19874
2908	3116	{
2909	3117	case 0: // LDBS.A
2910	3118
2911		load = READ_B(cpustate, EXTRA_S);
	3119	load = READ_B(EXTRA_S);
2912	3120	load |= (load & 0x80) ? 0xffffff00 : 0;
2913	3121	SET_SREG(load);
2914	3122
r19873	r19874
2916	3124
2917	3125	case 1: // LDBU.A
2918	3126
2919		load = READ_B(cpustate, EXTRA_S);
	3127	load = READ_B(EXTRA_S);
2920	3128	SET_SREG(load);
2921	3129
2922	3130	break;
2923	3131
2924	3132	case 2:
2925	3133
2926		load = READ_HW(cpustate, EXTRA_S & ~1);
	3134	load = READ_HW(EXTRA_S & ~1);
2927	3135
2928	3136	if( EXTRA_S & 1 ) // LDHS.A
2929	3137	{
r19873	r19874
2944	3152
2945	3153	if( (EXTRA_S & 3) == 3 )      // LDD.IOA
2946	3154	{
2947		load = IO_READ_W(cpustate, EXTRA_S & ~3);
	3155	load = IO_READ_W(EXTRA_S & ~3);
2948	3156	SET_SREG(load);
2949	3157
2950		load = IO_READ_W(cpustate, (EXTRA_S & ~3) + 4);
	3158	load = IO_READ_W((EXTRA_S & ~3) + 4);
2951	3159	SET_SREGF(load);
2952	3160
2953		cpustate->icount -= cpustate->clock_cycles_1; // extra cycle
	3161	m_icount -= m_clock_cycles_1; // extra cycle
2954	3162	}
2955	3163	else if( (EXTRA_S & 3) == 2 ) // LDW.IOA
2956	3164	{
2957		load = IO_READ_W(cpustate, EXTRA_S & ~3);
	3165	load = IO_READ_W(EXTRA_S & ~3);
2958	3166	SET_SREG(load);
2959	3167	}
2960	3168	else if( (EXTRA_S & 3) == 1 ) // LDD.A
2961	3169	{
2962		load = READ_W(cpustate, EXTRA_S & ~1);
	3170	load = READ_W(EXTRA_S & ~1);
2963	3171	SET_SREG(load);
2964	3172
2965		load = READ_W(cpustate, (EXTRA_S & ~1) + 4);
	3173	load = READ_W((EXTRA_S & ~1) + 4);
2966	3174	SET_SREGF(load);
2967	3175
2968		cpustate->icount -= cpustate->clock_cycles_1; // extra cycle
	3176	m_icount -= m_clock_cycles_1; // extra cycle
2969	3177	}
2970	3178	else                      // LDW.A
2971	3179	{
2972		load = READ_W(cpustate, EXTRA_S & ~1);
	3180	load = READ_W(EXTRA_S & ~1);
2973	3181	SET_SREG(load);
2974	3182	}
2975	3183
r19873	r19874
2982	3190	{
2983	3191	case 0: // LDBS.D
2984	3192
2985		load = READ_B(cpustate, DREG + EXTRA_S);
	3193	load = READ_B(DREG + EXTRA_S);
2986	3194	load |= (load & 0x80) ? 0xffffff00 : 0;
2987	3195	SET_SREG(load);
2988	3196
r19873	r19874
2990	3198
2991	3199	case 1: // LDBU.D
2992	3200
2993		load = READ_B(cpustate, DREG + EXTRA_S);
	3201	load = READ_B(DREG + EXTRA_S);
2994	3202	SET_SREG(load);
2995	3203
2996	3204	break;
2997	3205
2998	3206	case 2:
2999	3207
3000		load = READ_HW(cpustate, DREG + (EXTRA_S & ~1));
	3208	load = READ_HW(DREG + (EXTRA_S & ~1));
3001	3209
3002	3210	if( EXTRA_S & 1 ) // LDHS.D
3003	3211	{
r19873	r19874
3018	3226
3019	3227	if( (EXTRA_S & 3) == 3 )      // LDD.IOD
3020	3228	{
3021		load = IO_READ_W(cpustate, DREG + (EXTRA_S & ~3));
	3229	load = IO_READ_W(DREG + (EXTRA_S & ~3));
3022	3230	SET_SREG(load);
3023	3231
3024		load = IO_READ_W(cpustate, DREG + (EXTRA_S & ~3) + 4);
	3232	load = IO_READ_W(DREG + (EXTRA_S & ~3) + 4);
3025	3233	SET_SREGF(load);
3026	3234
3027		cpustate->icount -= cpustate->clock_cycles_1; // extra cycle
	3235	m_icount -= m_clock_cycles_1; // extra cycle
3028	3236	}
3029	3237	else if( (EXTRA_S & 3) == 2 ) // LDW.IOD
3030	3238	{
3031		load = IO_READ_W(cpustate, DREG + (EXTRA_S & ~3));
	3239	load = IO_READ_W(DREG + (EXTRA_S & ~3));
3032	3240	SET_SREG(load);
3033	3241	}
3034	3242	else if( (EXTRA_S & 3) == 1 ) // LDD.D
3035	3243	{
3036		load = READ_W(cpustate, DREG + (EXTRA_S & ~1));
	3244	load = READ_W(DREG + (EXTRA_S & ~1));
3037	3245	SET_SREG(load);
3038	3246
3039		load = READ_W(cpustate, DREG + (EXTRA_S & ~1) + 4);
	3247	load = READ_W(DREG + (EXTRA_S & ~1) + 4);
3040	3248	SET_SREGF(load);
3041	3249
3042		cpustate->icount -= cpustate->clock_cycles_1; // extra cycle
	3250	m_icount -= m_clock_cycles_1; // extra cycle
3043	3251	}
3044	3252	else                      // LDW.D
3045	3253	{
3046		load = READ_W(cpustate, DREG + (EXTRA_S & ~1));
	3254	load = READ_W(DREG + (EXTRA_S & ~1));
3047	3255	SET_SREG(load);
3048	3256	}
3049	3257
r19873	r19874
3051	3259	}
3052	3260	}
3053	3261
3054		cpustate->icount -= cpustate->clock_cycles_1;
	3262	m_icount -= m_clock_cycles_1;
3055	3263	}
3056	3264
3057		INLINE void hyperstone_ldxx2(hyperstone_state *cpustate, struct regs_decode *decode)
	3265	void hyperstone_device::hyperstone_ldxx2(struct hyperstone_device::regs_decode *decode)
3058	3266	{
3059	3267	UINT32 load;
3060	3268
r19873	r19874
3071	3279	if(SAME_SRC_DST)
3072	3280	DEBUG_PRINTF(("LDBS.N denoted same regs @ %08X",PPC));
3073	3281
3074		load = READ_B(cpustate, DREG);
	3282	load = READ_B(DREG);
3075	3283	load |= (load & 0x80) ? 0xffffff00 : 0;
3076	3284	SET_SREG(load);
3077	3285
r19873	r19874
3085	3293	if(SAME_SRC_DST)
3086	3294	DEBUG_PRINTF(("LDBU.N denoted same regs @ %08X",PPC));
3087	3295
3088		load = READ_B(cpustate, DREG);
	3296	load = READ_B(DREG);
3089	3297	SET_SREG(load);
3090	3298
3091	3299	if(!SAME_SRC_DST)
r19873	r19874
3095	3303
3096	3304	case 2:
3097	3305
3098		load = READ_HW(cpustate, DREG);
	3306	load = READ_HW(DREG);
3099	3307
3100	3308	if( EXTRA_S & 1 ) // LDHS.N
3101	3309	{
r19873	r19874
3126	3334	DEBUG_PRINTF(("LDW.S denoted same regs @ %08X",PPC));
3127	3335
3128	3336	if(DREG < SP)
3129		SET_SREG(READ_W(cpustate, DREG));
	3337	SET_SREG(READ_W(DREG));
3130	3338	else
3131	3339	SET_SREG(GET_ABS_L_REG((DREG & 0xfc) >> 2));
3132	3340
3133	3341	if(!SAME_SRC_DST)
3134	3342	SET_DREG(DREG + (EXTRA_S & ~3));
3135	3343
3136		cpustate->icount -= cpustate->clock_cycles_2; // extra cycles
	3344	m_icount -= m_clock_cycles_2; // extra cycles
3137	3345	}
3138	3346	else if( (EXTRA_S & 3) == 2 ) // Reserved
3139	3347	{
r19873	r19874
3144	3352	if(SAME_SRC_DST || SAME_SRCF_DST)
3145	3353	DEBUG_PRINTF(("LDD.N denoted same regs @ %08X",PPC));
3146	3354
3147		load = READ_W(cpustate, DREG);
	3355	load = READ_W(DREG);
3148	3356	SET_SREG(load);
3149	3357
3150		load = READ_W(cpustate, DREG + 4);
	3358	load = READ_W(DREG + 4);
3151	3359	SET_SREGF(load);
3152	3360
3153	3361	if(!SAME_SRC_DST && !SAME_SRCF_DST)
3154	3362	SET_DREG(DREG + (EXTRA_S & ~1));
3155	3363
3156		cpustate->icount -= cpustate->clock_cycles_1; // extra cycle
	3364	m_icount -= m_clock_cycles_1; // extra cycle
3157	3365	}
3158	3366	else                      // LDW.N
3159	3367	{
3160	3368	if(SAME_SRC_DST)
3161	3369	DEBUG_PRINTF(("LDW.N denoted same regs @ %08X",PPC));
3162	3370
3163		load = READ_W(cpustate, DREG);
	3371	load = READ_W(DREG);
3164	3372	SET_SREG(load);
3165	3373
3166	3374	if(!SAME_SRC_DST)
r19873	r19874
3171	3379	}
3172	3380	}
3173	3381
3174		cpustate->icount -= cpustate->clock_cycles_1;
	3382	m_icount -= m_clock_cycles_1;
3175	3383	}
3176	3384
3177	3385	//TODO: add trap error
3178		INLINE void hyperstone_stxx1(hyperstone_state *cpustate, struct regs_decode *decode)
	3386	void hyperstone_device::hyperstone_stxx1(struct hyperstone_device::regs_decode *decode)
3179	3387	{
3180	3388	if( SRC_IS_SR )
3181	3389	SREG = SREGF = 0;
r19873	r19874
3187	3395	case 0: // STBS.A
3188	3396
3189	3397	/* TODO: missing trap on range error */
3190		WRITE_B(cpustate, EXTRA_S, SREG & 0xff);
	3398	WRITE_B(EXTRA_S, SREG & 0xff);
3191	3399
3192	3400	break;
3193	3401
3194	3402	case 1: // STBU.A
3195	3403
3196		WRITE_B(cpustate, EXTRA_S, SREG & 0xff);
	3404	WRITE_B(EXTRA_S, SREG & 0xff);
3197	3405
3198	3406	break;
3199	3407
3200	3408	case 2:
3201	3409
3202		WRITE_HW(cpustate, EXTRA_S & ~1, SREG & 0xffff);
	3410	WRITE_HW(EXTRA_S & ~1, SREG & 0xffff);
3203	3411
3204	3412	/*
3205	3413	if( EXTRA_S & 1 ) // STHS.A
r19873	r19874
3218	3426
3219	3427	if( (EXTRA_S & 3) == 3 )      // STD.IOA
3220	3428	{
3221		IO_WRITE_W(cpustate, EXTRA_S & ~3, SREG);
3222		IO_WRITE_W(cpustate, (EXTRA_S & ~3) + 4, SREGF);
	3429	IO_WRITE_W(EXTRA_S & ~3, SREG);
	3430	IO_WRITE_W((EXTRA_S & ~3) + 4, SREGF);
3223	3431
3224		cpustate->icount -= cpustate->clock_cycles_1; // extra cycle
	3432	m_icount -= m_clock_cycles_1; // extra cycle
3225	3433	}
3226	3434	else if( (EXTRA_S & 3) == 2 ) // STW.IOA
3227	3435	{
3228		IO_WRITE_W(cpustate, EXTRA_S & ~3, SREG);
	3436	IO_WRITE_W(EXTRA_S & ~3, SREG);
3229	3437	}
3230	3438	else if( (EXTRA_S & 3) == 1 ) // STD.A
3231	3439	{
3232		WRITE_W(cpustate, EXTRA_S & ~1, SREG);
3233		WRITE_W(cpustate, (EXTRA_S & ~1) + 4, SREGF);
	3440	WRITE_W(EXTRA_S & ~1, SREG);
	3441	WRITE_W((EXTRA_S & ~1) + 4, SREGF);
3234	3442
3235		cpustate->icount -= cpustate->clock_cycles_1; // extra cycle
	3443	m_icount -= m_clock_cycles_1; // extra cycle
3236	3444	}
3237	3445	else                      // STW.A
3238	3446	{
3239		WRITE_W(cpustate, EXTRA_S & ~1, SREG);
	3447	WRITE_W(EXTRA_S & ~1, SREG);
3240	3448	}
3241	3449
3242	3450	break;
r19873	r19874
3249	3457	case 0: // STBS.D
3250	3458
3251	3459	/* TODO: missing trap on range error */
3252		WRITE_B(cpustate, DREG + EXTRA_S, SREG & 0xff);
	3460	WRITE_B(DREG + EXTRA_S, SREG & 0xff);
3253	3461
3254	3462	break;
3255	3463
3256	3464	case 1: // STBU.D
3257	3465
3258		WRITE_B(cpustate, DREG + EXTRA_S, SREG & 0xff);
	3466	WRITE_B(DREG + EXTRA_S, SREG & 0xff);
3259	3467
3260	3468	break;
3261	3469
3262	3470	case 2:
3263	3471
3264		WRITE_HW(cpustate, DREG + (EXTRA_S & ~1), SREG & 0xffff);
	3472	WRITE_HW(DREG + (EXTRA_S & ~1), SREG & 0xffff);
3265	3473
3266	3474	/*
3267	3475	if( EXTRA_S & 1 ) // STHS.D
r19873	r19874
3280	3488
3281	3489	if( (EXTRA_S & 3) == 3 )      // STD.IOD
3282	3490	{
3283		IO_WRITE_W(cpustate, DREG + (EXTRA_S & ~3), SREG);
3284		IO_WRITE_W(cpustate, DREG + (EXTRA_S & ~3) + 4, SREGF);
	3491	IO_WRITE_W(DREG + (EXTRA_S & ~3), SREG);
	3492	IO_WRITE_W(DREG + (EXTRA_S & ~3) + 4, SREGF);
3285	3493
3286		cpustate->icount -= cpustate->clock_cycles_1; // extra cycle
	3494	m_icount -= m_clock_cycles_1; // extra cycle
3287	3495	}
3288	3496	else if( (EXTRA_S & 3) == 2 ) // STW.IOD
3289	3497	{
3290		IO_WRITE_W(cpustate, DREG + (EXTRA_S & ~3), SREG);
	3498	IO_WRITE_W(DREG + (EXTRA_S & ~3), SREG);
3291	3499	}
3292	3500	else if( (EXTRA_S & 3) == 1 ) // STD.D
3293	3501	{
3294		WRITE_W(cpustate, DREG + (EXTRA_S & ~1), SREG);
3295		WRITE_W(cpustate, DREG + (EXTRA_S & ~1) + 4, SREGF);
	3502	WRITE_W(DREG + (EXTRA_S & ~1), SREG);
	3503	WRITE_W(DREG + (EXTRA_S & ~1) + 4, SREGF);
3296	3504
3297		cpustate->icount -= cpustate->clock_cycles_1; // extra cycle
	3505	m_icount -= m_clock_cycles_1; // extra cycle
3298	3506	}
3299	3507	else                      // STW.D
3300	3508	{
3301		WRITE_W(cpustate, DREG + (EXTRA_S & ~1), SREG);
	3509	WRITE_W(DREG + (EXTRA_S & ~1), SREG);
3302	3510	}
3303	3511
3304	3512	break;
3305	3513	}
3306	3514	}
3307	3515
3308		cpustate->icount -= cpustate->clock_cycles_1;
	3516	m_icount -= m_clock_cycles_1;
3309	3517	}
3310	3518
3311		INLINE void hyperstone_stxx2(hyperstone_state *cpustate, struct regs_decode *decode)
	3519	void hyperstone_device::hyperstone_stxx2(struct hyperstone_device::regs_decode *decode)
3312	3520	{
3313	3521	if( SRC_IS_SR )
3314	3522	SREG = SREGF = 0;
r19873	r19874
3324	3532	case 0: // STBS.N
3325	3533
3326	3534	/* TODO: missing trap on range error */
3327		WRITE_B(cpustate, DREG, SREG & 0xff);
	3535	WRITE_B(DREG, SREG & 0xff);
3328	3536	SET_DREG(DREG + EXTRA_S);
3329	3537
3330	3538	break;
3331	3539
3332	3540	case 1: // STBU.N
3333	3541
3334		WRITE_B(cpustate, DREG, SREG & 0xff);
	3542	WRITE_B(DREG, SREG & 0xff);
3335	3543	SET_DREG(DREG + EXTRA_S);
3336	3544
3337	3545	break;
3338	3546
3339	3547	case 2:
3340	3548
3341		WRITE_HW(cpustate, DREG, SREG & 0xffff);
	3549	WRITE_HW(DREG, SREG & 0xffff);
3342	3550	SET_DREG(DREG + (EXTRA_S & ~1));
3343	3551
3344	3552	/*
r19873	r19874
3359	3567	if( (EXTRA_S & 3) == 3 )      // STW.S
3360	3568	{
3361	3569	if(DREG < SP)
3362		WRITE_W(cpustate, DREG, SREG);
	3570	WRITE_W(DREG, SREG);
3363	3571	else
3364	3572	{
3365	3573	if(((DREG & 0xfc) >> 2) == ((decode->src + GET_FP) % 64) && S_BIT == LOCAL)
r19873	r19874
3370	3578
3371	3579	SET_DREG(DREG + (EXTRA_S & ~3));
3372	3580
3373		cpustate->icount -= cpustate->clock_cycles_2; // extra cycles
	3581	m_icount -= m_clock_cycles_2; // extra cycles
3374	3582
3375	3583	}
3376	3584	else if( (EXTRA_S & 3) == 2 ) // Reserved
r19873	r19874
3379	3587	}
3380	3588	else if( (EXTRA_S & 3) == 1 ) // STD.N
3381	3589	{
3382		WRITE_W(cpustate, DREG, SREG);
	3590	WRITE_W(DREG, SREG);
3383	3591	SET_DREG(DREG + (EXTRA_S & ~1));
3384	3592
3385	3593	if( SAME_SRCF_DST )
3386		WRITE_W(cpustate, DREG + 4, SREGF + (EXTRA_S & ~1));  // because DREG == SREGF and DREG has been incremented
	3594	WRITE_W(DREG + 4, SREGF + (EXTRA_S & ~1));  // because DREG == SREGF and DREG has been incremented
3387	3595	else
3388		WRITE_W(cpustate, DREG + 4, SREGF);
	3596	WRITE_W(DREG + 4, SREGF);
3389	3597
3390		cpustate->icount -= cpustate->clock_cycles_1; // extra cycle
	3598	m_icount -= m_clock_cycles_1; // extra cycle
3391	3599	}
3392	3600	else                      // STW.N
3393	3601	{
3394		WRITE_W(cpustate, DREG, SREG);
	3602	WRITE_W(DREG, SREG);
3395	3603	SET_DREG(DREG + (EXTRA_S & ~1));
3396	3604	}
3397	3605
r19873	r19874
3399	3607	}
3400	3608	}
3401	3609
3402		cpustate->icount -= cpustate->clock_cycles_1;
	3610	m_icount -= m_clock_cycles_1;
3403	3611	}
3404	3612
3405		INLINE void hyperstone_shri(hyperstone_state *cpustate, struct regs_decode *decode)
	3613	void hyperstone_device::hyperstone_shri(struct hyperstone_device::regs_decode *decode)
3406	3614	{
3407	3615	UINT32 val;
3408	3616
r19873	r19874
3419	3627	SET_Z( val == 0 ? 1 : 0 );
3420	3628	SET_N( SIGN_BIT(val) );
3421	3629
3422		cpustate->icount -= cpustate->clock_cycles_1;
	3630	m_icount -= m_clock_cycles_1;
3423	3631	}
3424	3632
3425		INLINE void hyperstone_sari(hyperstone_state *cpustate, struct regs_decode *decode)
	3633	void hyperstone_device::hyperstone_sari(struct hyperstone_device::regs_decode *decode)
3426	3634	{
3427	3635	UINT32 val;
3428	3636	UINT8 sign_bit;
r19873	r19874
3450	3658	SET_Z( val == 0 ? 1 : 0 );
3451	3659	SET_N( SIGN_BIT(val) );
3452	3660
3453		cpustate->icount -= cpustate->clock_cycles_1;
	3661	m_icount -= m_clock_cycles_1;
3454	3662	}
3455	3663
3456		INLINE void hyperstone_shli(hyperstone_state *cpustate, struct regs_decode *decode)
	3664	void hyperstone_device::hyperstone_shli(struct hyperstone_device::regs_decode *decode)
3457	3665	{
3458	3666	UINT32 val, val2;
3459	3667	UINT64 mask;
r19873	r19874
3473	3681	SET_Z( val2 == 0 ? 1 : 0 );
3474	3682	SET_N( SIGN_BIT(val2) );
3475	3683
3476		cpustate->icount -= cpustate->clock_cycles_1;
	3684	m_icount -= m_clock_cycles_1;
3477	3685	}
3478	3686
3479		INLINE void hyperstone_mulu(hyperstone_state *cpustate, struct regs_decode *decode)
	3687	void hyperstone_device::hyperstone_mulu(struct hyperstone_device::regs_decode *decode)
3480	3688	{
3481	3689	UINT32 low_order, high_order;
3482	3690	UINT64 double_word;
r19873	r19874
3501	3709	}
3502	3710
3503	3711	if(SREG <= 0xffff && DREG <= 0xffff)
3504		cpustate->icount -= cpustate->clock_cycles_4;
	3712	m_icount -= m_clock_cycles_4;
3505	3713	else
3506		cpustate->icount -= cpustate->clock_cycles_6;
	3714	m_icount -= m_clock_cycles_6;
3507	3715	}
3508	3716
3509		INLINE void hyperstone_muls(hyperstone_state *cpustate, struct regs_decode *decode)
	3717	void hyperstone_device::hyperstone_muls(struct hyperstone_device::regs_decode *decode)
3510	3718	{
3511	3719	UINT32 low_order, high_order;
3512	3720	INT64 double_word;
r19873	r19874
3530	3738	}
3531	3739
3532	3740	if((SREG >= 0xffff8000 && SREG <= 0x7fff) && (DREG >= 0xffff8000 && DREG <= 0x7fff))
3533		cpustate->icount -= cpustate->clock_cycles_4;
	3741	m_icount -= m_clock_cycles_4;
3534	3742	else
3535		cpustate->icount -= cpustate->clock_cycles_6;
	3743	m_icount -= m_clock_cycles_6;
3536	3744	}
3537	3745
3538		INLINE void hyperstone_set(hyperstone_state *cpustate, struct regs_decode *decode)
	3746	void hyperstone_device::hyperstone_set(struct hyperstone_device::regs_decode *decode)
3539	3747	{
3540	3748	int n = N_VALUE;
3541	3749
r19873	r19874
3548	3756	//TODO: add fetch opcode when there's the pipeline
3549	3757
3550	3758	//TODO: no 1!
3551		cpustate->icount -= cpustate->clock_cycles_1;
	3759	m_icount -= m_clock_cycles_1;
3552	3760	}
3553	3761	else
3554	3762	{
r19873	r19874
3877	4085	break;
3878	4086	}
3879	4087
3880		cpustate->icount -= cpustate->clock_cycles_1;
	4088	m_icount -= m_clock_cycles_1;
3881	4089	}
3882	4090	}
3883	4091
3884		INLINE void hyperstone_mul(hyperstone_state *cpustate, struct regs_decode *decode)
	4092	void hyperstone_device::hyperstone_mul(struct hyperstone_device::regs_decode *decode)
3885	4093	{
3886	4094	UINT32 single_word;
3887	4095
r19873	r19874
3901	4109	}
3902	4110
3903	4111	if((SREG >= 0xffff8000 && SREG <= 0x7fff) && (DREG >= 0xffff8000 && DREG <= 0x7fff))
3904		cpustate->icount -= 3 << cpustate->clock_scale;
	4112	m_icount -= 3 << m_clock_scale;
3905	4113	else
3906		cpustate->icount -= 5 << cpustate->clock_scale;
	4114	m_icount -= 5 << m_clock_scale;
3907	4115	}
3908	4116
3909		INLINE void hyperstone_fadd(hyperstone_state *cpustate, struct regs_decode *decode)
	4117	void hyperstone_device::hyperstone_fadd(struct hyperstone_device::regs_decode *decode)
3910	4118	{
3911		execute_software(cpustate, decode);
3912		cpustate->icount -= cpustate->clock_cycles_6;
	4119	execute_software(decode);
	4120	m_icount -= m_clock_cycles_6;
3913	4121	}
3914	4122
3915		INLINE void hyperstone_faddd(hyperstone_state *cpustate, struct regs_decode *decode)
	4123	void hyperstone_device::hyperstone_faddd(struct hyperstone_device::regs_decode *decode)
3916	4124	{
3917		execute_software(cpustate, decode);
3918		cpustate->icount -= cpustate->clock_cycles_6;
	4125	execute_software(decode);
	4126	m_icount -= m_clock_cycles_6;
3919	4127	}
3920	4128
3921		INLINE void hyperstone_fsub(hyperstone_state *cpustate, struct regs_decode *decode)
	4129	void hyperstone_device::hyperstone_fsub(struct hyperstone_device::regs_decode *decode)
3922	4130	{
3923		execute_software(cpustate, decode);
3924		cpustate->icount -= cpustate->clock_cycles_6;
	4131	execute_software(decode);
	4132	m_icount -= m_clock_cycles_6;
3925	4133	}
3926	4134
3927		INLINE void hyperstone_fsubd(hyperstone_state *cpustate, struct regs_decode *decode)
	4135	void hyperstone_device::hyperstone_fsubd(struct hyperstone_device::regs_decode *decode)
3928	4136	{
3929		execute_software(cpustate, decode);
3930		cpustate->icount -= cpustate->clock_cycles_6;
	4137	execute_software(decode);
	4138	m_icount -= m_clock_cycles_6;
3931	4139	}
3932	4140
3933		INLINE void hyperstone_fmul(hyperstone_state *cpustate, struct regs_decode *decode)
	4141	void hyperstone_device::hyperstone_fmul(struct hyperstone_device::regs_decode *decode)
3934	4142	{
3935		execute_software(cpustate, decode);
3936		cpustate->icount -= cpustate->clock_cycles_6;
	4143	execute_software(decode);
	4144	m_icount -= m_clock_cycles_6;
3937	4145	}
3938	4146
3939		INLINE void hyperstone_fmuld(hyperstone_state *cpustate, struct regs_decode *decode)
	4147	void hyperstone_device::hyperstone_fmuld(struct hyperstone_device::regs_decode *decode)
3940	4148	{
3941		execute_software(cpustate, decode);
3942		cpustate->icount -= cpustate->clock_cycles_6;
	4149	execute_software(decode);
	4150	m_icount -= m_clock_cycles_6;
3943	4151	}
3944	4152
3945		INLINE void hyperstone_fdiv(hyperstone_state *cpustate, struct regs_decode *decode)
	4153	void hyperstone_device::hyperstone_fdiv(struct hyperstone_device::regs_decode *decode)
3946	4154	{
3947		execute_software(cpustate, decode);
3948		cpustate->icount -= cpustate->clock_cycles_6;
	4155	execute_software(decode);
	4156	m_icount -= m_clock_cycles_6;
3949	4157	}
3950	4158
3951		INLINE void hyperstone_fdivd(hyperstone_state *cpustate, struct regs_decode *decode)
	4159	void hyperstone_device::hyperstone_fdivd(struct hyperstone_device::regs_decode *decode)
3952	4160	{
3953		execute_software(cpustate, decode);
3954		cpustate->icount -= cpustate->clock_cycles_6;
	4161	execute_software(decode);
	4162	m_icount -= m_clock_cycles_6;
3955	4163	}
3956	4164
3957		INLINE void hyperstone_fcmp(hyperstone_state *cpustate, struct regs_decode *decode)
	4165	void hyperstone_device::hyperstone_fcmp(struct hyperstone_device::regs_decode *decode)
3958	4166	{
3959		execute_software(cpustate, decode);
3960		cpustate->icount -= cpustate->clock_cycles_6;
	4167	execute_software(decode);
	4168	m_icount -= m_clock_cycles_6;
3961	4169	}
3962	4170
3963		INLINE void hyperstone_fcmpd(hyperstone_state *cpustate, struct regs_decode *decode)
	4171	void hyperstone_device::hyperstone_fcmpd(struct hyperstone_device::regs_decode *decode)
3964	4172	{
3965		execute_software(cpustate, decode);
3966		cpustate->icount -= cpustate->clock_cycles_6;
	4173	execute_software(decode);
	4174	m_icount -= m_clock_cycles_6;
3967	4175	}
3968	4176
3969		INLINE void hyperstone_fcmpu(hyperstone_state *cpustate, struct regs_decode *decode)
	4177	void hyperstone_device::hyperstone_fcmpu(struct hyperstone_device::regs_decode *decode)
3970	4178	{
3971		execute_software(cpustate, decode);
3972		cpustate->icount -= cpustate->clock_cycles_6;
	4179	execute_software(decode);
	4180	m_icount -= m_clock_cycles_6;
3973	4181	}
3974	4182
3975		INLINE void hyperstone_fcmpud(hyperstone_state *cpustate, struct regs_decode *decode)
	4183	void hyperstone_device::hyperstone_fcmpud(struct hyperstone_device::regs_decode *decode)
3976	4184	{
3977		execute_software(cpustate, decode);
3978		cpustate->icount -= cpustate->clock_cycles_6;
	4185	execute_software(decode);
	4186	m_icount -= m_clock_cycles_6;
3979	4187	}
3980	4188
3981		INLINE void hyperstone_fcvt(hyperstone_state *cpustate, struct regs_decode *decode)
	4189	void hyperstone_device::hyperstone_fcvt(struct hyperstone_device::regs_decode *decode)
3982	4190	{
3983		execute_software(cpustate, decode);
3984		cpustate->icount -= cpustate->clock_cycles_6;
	4191	execute_software(decode);
	4192	m_icount -= m_clock_cycles_6;
3985	4193	}
3986	4194
3987		INLINE void hyperstone_fcvtd(hyperstone_state *cpustate, struct regs_decode *decode)
	4195	void hyperstone_device::hyperstone_fcvtd(struct hyperstone_device::regs_decode *decode)
3988	4196	{
3989		execute_software(cpustate, decode);
3990		cpustate->icount -= cpustate->clock_cycles_6;
	4197	execute_software(decode);
	4198	m_icount -= m_clock_cycles_6;
3991	4199	}
3992	4200
3993		INLINE void hyperstone_extend(hyperstone_state *cpustate, struct regs_decode *decode)
	4201	void hyperstone_device::hyperstone_extend(struct hyperstone_device::regs_decode *decode)
3994	4202	{
3995	4203	//TODO: add locks, overflow error and other things
3996	4204	UINT32 vals, vald;
r19873	r19874
4188	4396	break;
4189	4397	}
4190	4398
4191		cpustate->icount -= cpustate->clock_cycles_1; //TODO: with the latency it can change
	4399	m_icount -= m_clock_cycles_1; //TODO: with the latency it can change
4192	4400	}
4193	4401
4194		INLINE void hyperstone_do(hyperstone_state *cpustate, struct regs_decode *decode)
	4402	void hyperstone_device::hyperstone_do(struct hyperstone_device::regs_decode *decode)
4195	4403	{
4196	4404	fatalerror("Executed hyperstone_do instruction. PC = %08X\n", PPC);
4197	4405	}
4198	4406
4199		INLINE void hyperstone_ldwr(hyperstone_state *cpustate, struct regs_decode *decode)
	4407	void hyperstone_device::hyperstone_ldwr(struct hyperstone_device::regs_decode *decode)
4200	4408	{
4201		SET_SREG(READ_W(cpustate, DREG));
	4409	SET_SREG(READ_W(DREG));
4202	4410
4203		cpustate->icount -= cpustate->clock_cycles_1;
	4411	m_icount -= m_clock_cycles_1;
4204	4412	}
4205	4413
4206		INLINE void hyperstone_lddr(hyperstone_state *cpustate, struct regs_decode *decode)
	4414	void hyperstone_device::hyperstone_lddr(struct hyperstone_device::regs_decode *decode)
4207	4415	{
4208		SET_SREG(READ_W(cpustate, DREG));
4209		SET_SREGF(READ_W(cpustate, DREG + 4));
	4416	SET_SREG(READ_W(DREG));
	4417	SET_SREGF(READ_W(DREG + 4));
4210	4418
4211		cpustate->icount -= cpustate->clock_cycles_2;
	4419	m_icount -= m_clock_cycles_2;
4212	4420	}
4213	4421
4214		INLINE void hyperstone_ldwp(hyperstone_state *cpustate, struct regs_decode *decode)
	4422	void hyperstone_device::hyperstone_ldwp(struct hyperstone_device::regs_decode *decode)
4215	4423	{
4216		SET_SREG(READ_W(cpustate, DREG));
	4424	SET_SREG(READ_W(DREG));
4217	4425
4218	4426	// post increment the destination register if it's different from the source one
4219	4427	// (needed by Hidden Catch)
4220	4428	if(!(decode->src == decode->dst && S_BIT == LOCAL))
4221	4429	SET_DREG(DREG + 4);
4222	4430
4223		cpustate->icount -= cpustate->clock_cycles_1;
	4431	m_icount -= m_clock_cycles_1;
4224	4432	}
4225	4433
4226		INLINE void hyperstone_lddp(hyperstone_state *cpustate, struct regs_decode *decode)
	4434	void hyperstone_device::hyperstone_lddp(struct hyperstone_device::regs_decode *decode)
4227	4435	{
4228		SET_SREG(READ_W(cpustate, DREG));
4229		SET_SREGF(READ_W(cpustate, DREG + 4));
	4436	SET_SREG(READ_W(DREG));
	4437	SET_SREGF(READ_W(DREG + 4));
4230	4438
4231	4439	// post increment the destination register if it's different from the source one
4232	4440	// and from the "next source" one
r19873	r19874
4239	4447	DEBUG_PRINTF(("LDD.P denoted same regs @ %08X",PPC));
4240	4448	}
4241	4449
4242		cpustate->icount -= cpustate->clock_cycles_2;
	4450	m_icount -= m_clock_cycles_2;
4243	4451	}
4244	4452
4245		INLINE void hyperstone_stwr(hyperstone_state *cpustate, struct regs_decode *decode)
	4453	void hyperstone_device::hyperstone_stwr(struct hyperstone_device::regs_decode *decode)
4246	4454	{
4247	4455	if( SRC_IS_SR )
4248	4456	SREG = 0;
4249	4457
4250		WRITE_W(cpustate, DREG, SREG);
	4458	WRITE_W(DREG, SREG);
4251	4459
4252		cpustate->icount -= cpustate->clock_cycles_1;
	4460	m_icount -= m_clock_cycles_1;
4253	4461	}
4254	4462
4255		INLINE void hyperstone_stdr(hyperstone_state *cpustate, struct regs_decode *decode)
	4463	void hyperstone_device::hyperstone_stdr(struct hyperstone_device::regs_decode *decode)
4256	4464	{
4257	4465	if( SRC_IS_SR )
4258	4466	SREG = SREGF = 0;
4259	4467
4260		WRITE_W(cpustate, DREG, SREG);
4261		WRITE_W(cpustate, DREG + 4, SREGF);
	4468	WRITE_W(DREG, SREG);
	4469	WRITE_W(DREG + 4, SREGF);
4262	4470
4263		cpustate->icount -= cpustate->clock_cycles_2;
	4471	m_icount -= m_clock_cycles_2;
4264	4472	}
4265	4473
4266		INLINE void hyperstone_stwp(hyperstone_state *cpustate, struct regs_decode *decode)
	4474	void hyperstone_device::hyperstone_stwp(struct hyperstone_device::regs_decode *decode)
4267	4475	{
4268	4476	if( SRC_IS_SR )
4269	4477	SREG = 0;
4270	4478
4271		WRITE_W(cpustate, DREG, SREG);
	4479	WRITE_W(DREG, SREG);
4272	4480	SET_DREG(DREG + 4);
4273	4481
4274		cpustate->icount -= cpustate->clock_cycles_1;
	4482	m_icount -= m_clock_cycles_1;
4275	4483	}
4276	4484
4277		INLINE void hyperstone_stdp(hyperstone_state *cpustate, struct regs_decode *decode)
	4485	void hyperstone_device::hyperstone_stdp(struct hyperstone_device::regs_decode *decode)
4278	4486	{
4279	4487	if( SRC_IS_SR )
4280	4488	SREG = SREGF = 0;
4281	4489
4282		WRITE_W(cpustate, DREG, SREG);
	4490	WRITE_W(DREG, SREG);
4283	4491	SET_DREG(DREG + 8);
4284	4492
4285	4493	if( SAME_SRCF_DST )
4286		WRITE_W(cpustate, DREG + 4, SREGF + 8); // because DREG == SREGF and DREG has been incremented
	4494	WRITE_W(DREG + 4, SREGF + 8); // because DREG == SREGF and DREG has been incremented
4287	4495	else
4288		WRITE_W(cpustate, DREG + 4, SREGF);
	4496	WRITE_W(DREG + 4, SREGF);
4289	4497
4290		cpustate->icount -= cpustate->clock_cycles_2;
	4498	m_icount -= m_clock_cycles_2;
4291	4499	}
4292	4500
4293		INLINE void hyperstone_dbv(hyperstone_state *cpustate, struct regs_decode *decode)
	4501	void hyperstone_device::hyperstone_dbv(struct hyperstone_device::regs_decode *decode)
4294	4502	{
4295	4503	if( GET_V )
4296		execute_dbr(cpustate, decode);
	4504	execute_dbr(decode);
4297	4505
4298		cpustate->icount -= cpustate->clock_cycles_1;
	4506	m_icount -= m_clock_cycles_1;
4299	4507	}
4300	4508
4301		INLINE void hyperstone_dbnv(hyperstone_state *cpustate, struct regs_decode *decode)
	4509	void hyperstone_device::hyperstone_dbnv(struct hyperstone_device::regs_decode *decode)
4302	4510	{
4303	4511	if( !GET_V )
4304		execute_dbr(cpustate, decode);
	4512	execute_dbr(decode);
4305	4513
4306		cpustate->icount -= cpustate->clock_cycles_1;
	4514	m_icount -= m_clock_cycles_1;
4307	4515	}
4308	4516
4309		INLINE void hyperstone_dbe(hyperstone_state *cpustate, struct regs_decode *decode) //or DBZ
	4517	void hyperstone_device::hyperstone_dbe(struct hyperstone_device::regs_decode *decode) //or DBZ
4310	4518	{
4311	4519	if( GET_Z )
4312		execute_dbr(cpustate, decode);
	4520	execute_dbr(decode);
4313	4521
4314		cpustate->icount -= cpustate->clock_cycles_1;
	4522	m_icount -= m_clock_cycles_1;
4315	4523	}
4316	4524
4317		INLINE void hyperstone_dbne(hyperstone_state *cpustate, struct regs_decode *decode) //or DBNZ
	4525	void hyperstone_device::hyperstone_dbne(struct hyperstone_device::regs_decode *decode) //or DBNZ
4318	4526	{
4319	4527	if( !GET_Z )
4320		execute_dbr(cpustate, decode);
	4528	execute_dbr(decode);
4321	4529
4322		cpustate->icount -= cpustate->clock_cycles_1;
	4530	m_icount -= m_clock_cycles_1;
4323	4531	}
4324	4532
4325		INLINE void hyperstone_dbc(hyperstone_state *cpustate, struct regs_decode *decode) //or DBST
	4533	void hyperstone_device::hyperstone_dbc(struct hyperstone_device::regs_decode *decode) //or DBST
4326	4534	{
4327	4535	if( GET_C )
4328		execute_dbr(cpustate, decode);
	4536	execute_dbr(decode);
4329	4537
4330		cpustate->icount -= cpustate->clock_cycles_1;
	4538	m_icount -= m_clock_cycles_1;
4331	4539	}
4332	4540
4333		INLINE void hyperstone_dbnc(hyperstone_state *cpustate, struct regs_decode *decode) //or DBHE
	4541	void hyperstone_device::hyperstone_dbnc(struct hyperstone_device::regs_decode *decode) //or DBHE
4334	4542	{
4335	4543	if( !GET_C )
4336		execute_dbr(cpustate, decode);
	4544	execute_dbr(decode);
4337	4545
4338		cpustate->icount -= cpustate->clock_cycles_1;
	4546	m_icount -= m_clock_cycles_1;
4339	4547	}
4340	4548
4341		INLINE void hyperstone_dbse(hyperstone_state *cpustate, struct regs_decode *decode)
	4549	void hyperstone_device::hyperstone_dbse(struct hyperstone_device::regs_decode *decode)
4342	4550	{
4343	4551	if( GET_C || GET_Z )
4344		execute_dbr(cpustate, decode);
	4552	execute_dbr(decode);
4345	4553
4346		cpustate->icount -= cpustate->clock_cycles_1;
	4554	m_icount -= m_clock_cycles_1;
4347	4555	}
4348	4556
4349		INLINE void hyperstone_dbht(hyperstone_state *cpustate, struct regs_decode *decode)
	4557	void hyperstone_device::hyperstone_dbht(struct hyperstone_device::regs_decode *decode)
4350	4558	{
4351	4559	if( !GET_C && !GET_Z )
4352		execute_dbr(cpustate, decode);
	4560	execute_dbr(decode);
4353	4561
4354		cpustate->icount -= cpustate->clock_cycles_1;
	4562	m_icount -= m_clock_cycles_1;
4355	4563	}
4356	4564
4357		INLINE void hyperstone_dbn(hyperstone_state *cpustate, struct regs_decode *decode) //or DBLT
	4565	void hyperstone_device::hyperstone_dbn(struct hyperstone_device::regs_decode *decode) //or DBLT
4358	4566	{
4359	4567	if( GET_N )
4360		execute_dbr(cpustate, decode);
	4568	execute_dbr(decode);
4361	4569
4362		cpustate->icount -= cpustate->clock_cycles_1;
	4570	m_icount -= m_clock_cycles_1;
4363	4571	}
4364	4572
4365		INLINE void hyperstone_dbnn(hyperstone_state *cpustate, struct regs_decode *decode) //or DBGE
	4573	void hyperstone_device::hyperstone_dbnn(struct hyperstone_device::regs_decode *decode) //or DBGE
4366	4574	{
4367	4575	if( !GET_N )
4368		execute_dbr(cpustate, decode);
	4576	execute_dbr(decode);
4369	4577
4370		cpustate->icount -= cpustate->clock_cycles_1;
	4578	m_icount -= m_clock_cycles_1;
4371	4579	}
4372	4580
4373		INLINE void hyperstone_dble(hyperstone_state *cpustate, struct regs_decode *decode)
	4581	void hyperstone_device::hyperstone_dble(struct hyperstone_device::regs_decode *decode)
4374	4582	{
4375	4583	if( GET_N || GET_Z )
4376		execute_dbr(cpustate, decode);
	4584	execute_dbr(decode);
4377	4585
4378		cpustate->icount -= cpustate->clock_cycles_1;
	4586	m_icount -= m_clock_cycles_1;
4379	4587	}
4380	4588
4381		INLINE void hyperstone_dbgt(hyperstone_state *cpustate, struct regs_decode *decode)
	4589	void hyperstone_device::hyperstone_dbgt(struct hyperstone_device::regs_decode *decode)
4382	4590	{
4383	4591	if( !GET_N && !GET_Z )
4384		execute_dbr(cpustate, decode);
	4592	execute_dbr(decode);
4385	4593
4386		cpustate->icount -= cpustate->clock_cycles_1;
	4594	m_icount -= m_clock_cycles_1;
4387	4595	}
4388	4596
4389		INLINE void hyperstone_dbr(hyperstone_state *cpustate, struct regs_decode *decode)
	4597	void hyperstone_device::hyperstone_dbr(struct hyperstone_device::regs_decode *decode)
4390	4598	{
4391		execute_dbr(cpustate, decode);
	4599	execute_dbr(decode);
4392	4600	}
4393	4601
4394		INLINE void hyperstone_frame(hyperstone_state *cpustate, struct regs_decode *decode)
	4602	void hyperstone_device::hyperstone_frame(struct hyperstone_device::regs_decode *decode)
4395	4603	{
4396	4604	INT8 difference; // really it's 7 bits
4397	4605	UINT8 realfp = GET_FP - SRC_CODE;
r19873	r19874
4416	4624
4417	4625	do
4418	4626	{
4419		WRITE_W(cpustate, SP, GET_ABS_L_REG((SP & 0xfc) >> 2));
	4627	WRITE_W(SP, GET_ABS_L_REG((SP & 0xfc) >> 2));
4420	4628	SP += 4;
4421	4629	difference++;
4422	4630
r19873	r19874
4424	4632
4425	4633	if( tmp_flag )
4426	4634	{
4427		UINT32 addr = get_trap_addr(cpustate, TRAPNO_FRAME_ERROR);
4428		execute_exception(cpustate, addr);
	4635	UINT32 addr = get_trap_addr(TRAPNO_FRAME_ERROR);
	4636	execute_exception(addr);
4429	4637	}
4430	4638	}
4431	4639
4432	4640	//TODO: no 1!
4433		cpustate->icount -= cpustate->clock_cycles_1;
	4641	m_icount -= m_clock_cycles_1;
4434	4642	}
4435	4643
4436		INLINE void hyperstone_call(hyperstone_state *cpustate, struct regs_decode *decode)
	4644	void hyperstone_device::hyperstone_call(struct hyperstone_device::regs_decode *decode)
4437	4645	{
4438	4646	if( SRC_IS_SR )
4439	4647	SREG = 0;
r19873	r19874
4443	4651
4444	4652	EXTRA_S = (EXTRA_S & ~1) + SREG;
4445	4653
4446		SET_ILC(cpustate->instruction_length & 3);
	4654	SET_ILC(m_instruction_length & 3);
4447	4655
4448	4656	SET_DREG((PC & 0xfffffffe) | GET_S);
4449	4657	SET_DREGF(SR);
r19873	r19874
4456	4664	PPC = PC;
4457	4665	PC = EXTRA_S; // const value
4458	4666
4459		cpustate->intblock = 2;
	4667	m_intblock = 2;
4460	4668
4461	4669	//TODO: add interrupt locks, errors, ....
4462	4670
4463	4671	//TODO: no 1!
4464		cpustate->icount -= cpustate->clock_cycles_1;
	4672	m_icount -= m_clock_cycles_1;
4465	4673	}
4466	4674
4467		INLINE void hyperstone_bv(hyperstone_state *cpustate, struct regs_decode *decode)
	4675	void hyperstone_device::hyperstone_bv(struct hyperstone_device::regs_decode *decode)
4468	4676	{
4469	4677	if( GET_V )
4470		execute_br(cpustate, decode);
	4678	execute_br(decode);
4471	4679	else
4472		cpustate->icount -= cpustate->clock_cycles_1;
	4680	m_icount -= m_clock_cycles_1;
4473	4681	}
4474	4682
4475		INLINE void hyperstone_bnv(hyperstone_state *cpustate, struct regs_decode *decode)
	4683	void hyperstone_device::hyperstone_bnv(struct hyperstone_device::regs_decode *decode)
4476	4684	{
4477	4685	if( !GET_V )
4478		execute_br(cpustate, decode);
	4686	execute_br(decode);
4479	4687	else
4480		cpustate->icount -= cpustate->clock_cycles_1;
	4688	m_icount -= m_clock_cycles_1;
4481	4689	}
4482	4690
4483		INLINE void hyperstone_be(hyperstone_state *cpustate, struct regs_decode *decode) //or BZ
	4691	void hyperstone_device::hyperstone_be(struct hyperstone_device::regs_decode *decode) //or BZ
4484	4692	{
4485	4693	if( GET_Z )
4486		execute_br(cpustate, decode);
	4694	execute_br(decode);
4487	4695	else
4488		cpustate->icount -= cpustate->clock_cycles_1;
	4696	m_icount -= m_clock_cycles_1;
4489	4697	}
4490	4698
4491		INLINE void hyperstone_bne(hyperstone_state *cpustate, struct regs_decode *decode) //or BNZ
	4699	void hyperstone_device::hyperstone_bne(struct hyperstone_device::regs_decode *decode) //or BNZ
4492	4700	{
4493	4701	if( !GET_Z )
4494		execute_br(cpustate, decode);
	4702	execute_br(decode);
4495	4703	else
4496		cpustate->icount -= cpustate->clock_cycles_1;
	4704	m_icount -= m_clock_cycles_1;
4497	4705	}
4498	4706
4499		INLINE void hyperstone_bc(hyperstone_state *cpustate, struct regs_decode *decode) //or BST
	4707	void hyperstone_device::hyperstone_bc(struct hyperstone_device::regs_decode *decode) //or BST
4500	4708	{
4501	4709	if( GET_C )
4502		execute_br(cpustate, decode);
	4710	execute_br(decode);
4503	4711	else
4504		cpustate->icount -= cpustate->clock_cycles_1;
	4712	m_icount -= m_clock_cycles_1;
4505	4713	}
4506	4714
4507		INLINE void hyperstone_bnc(hyperstone_state *cpustate, struct regs_decode *decode) //or BHE
	4715	void hyperstone_device::hyperstone_bnc(struct hyperstone_device::regs_decode *decode) //or BHE
4508	4716	{
4509	4717	if( !GET_C )
4510		execute_br(cpustate, decode);
	4718	execute_br(decode);
4511	4719	else
4512		cpustate->icount -= cpustate->clock_cycles_1;
	4720	m_icount -= m_clock_cycles_1;
4513	4721	}
4514	4722
4515		INLINE void hyperstone_bse(hyperstone_state *cpustate, struct regs_decode *decode)
	4723	void hyperstone_device::hyperstone_bse(struct hyperstone_device::regs_decode *decode)
4516	4724	{
4517	4725	if( GET_C || GET_Z )
4518		execute_br(cpustate, decode);
	4726	execute_br(decode);
4519	4727	else
4520		cpustate->icount -= cpustate->clock_cycles_1;
	4728	m_icount -= m_clock_cycles_1;
4521	4729	}
4522	4730
4523		INLINE void hyperstone_bht(hyperstone_state *cpustate, struct regs_decode *decode)
	4731	void hyperstone_device::hyperstone_bht(struct hyperstone_device::regs_decode *decode)
4524	4732	{
4525	4733	if( !GET_C && !GET_Z )
4526		execute_br(cpustate, decode);
	4734	execute_br(decode);
4527	4735	else
4528		cpustate->icount -= cpustate->clock_cycles_1;
	4736	m_icount -= m_clock_cycles_1;
4529	4737	}
4530	4738
4531		INLINE void hyperstone_bn(hyperstone_state *cpustate, struct regs_decode *decode) //or BLT
	4739	void hyperstone_device::hyperstone_bn(struct hyperstone_device::regs_decode *decode) //or BLT
4532	4740	{
4533	4741	if( GET_N )
4534		execute_br(cpustate, decode);
	4742	execute_br(decode);
4535	4743	else
4536		cpustate->icount -= cpustate->clock_cycles_1;
	4744	m_icount -= m_clock_cycles_1;
4537	4745	}
4538	4746
4539		INLINE void hyperstone_bnn(hyperstone_state *cpustate, struct regs_decode *decode) //or BGE
	4747	void hyperstone_device::hyperstone_bnn(struct hyperstone_device::regs_decode *decode) //or BGE
4540	4748	{
4541	4749	if( !GET_N )
4542		execute_br(cpustate, decode);
	4750	execute_br(decode);
4543	4751	else
4544		cpustate->icount -= cpustate->clock_cycles_1;
	4752	m_icount -= m_clock_cycles_1;
4545	4753	}
4546	4754
4547		INLINE void hyperstone_ble(hyperstone_state *cpustate, struct regs_decode *decode)
	4755	void hyperstone_device::hyperstone_ble(struct hyperstone_device::regs_decode *decode)
4548	4756	{
4549	4757	if( GET_N || GET_Z )
4550		execute_br(cpustate, decode);
	4758	execute_br(decode);
4551	4759	else
4552		cpustate->icount -= cpustate->clock_cycles_1;
	4760	m_icount -= m_clock_cycles_1;
4553	4761	}
4554	4762
4555		INLINE void hyperstone_bgt(hyperstone_state *cpustate, struct regs_decode *decode)
	4763	void hyperstone_device::hyperstone_bgt(struct hyperstone_device::regs_decode *decode)
4556	4764	{
4557	4765	if( !GET_N && !GET_Z )
4558		execute_br(cpustate, decode);
	4766	execute_br(decode);
4559	4767	else
4560		cpustate->icount -= cpustate->clock_cycles_1;
	4768	m_icount -= m_clock_cycles_1;
4561	4769	}
4562	4770
4563		INLINE void hyperstone_br(hyperstone_state *cpustate, struct regs_decode *decode)
	4771	void hyperstone_device::hyperstone_br(struct hyperstone_device::regs_decode *decode)
4564	4772	{
4565		execute_br(cpustate, decode);
	4773	execute_br(decode);
4566	4774	}
4567	4775
4568		INLINE void hyperstone_trap(hyperstone_state *cpustate, struct regs_decode *decode)
	4776	void hyperstone_device::hyperstone_trap(struct hyperstone_device::regs_decode *decode)
4569	4777	{
4570	4778	UINT8 code, trapno;
4571	4779	UINT32 addr;
4572	4780
4573	4781	trapno = (OP & 0xfc) >> 2;
4574	4782
4575		addr = get_trap_addr(cpustate, trapno);
	4783	addr = get_trap_addr(trapno);
4576	4784	code = ((OP & 0x300) >> 6) | (OP & 0x03);
4577	4785
4578	4786	switch( code )
4579	4787	{
4580	4788	case TRAPLE:
4581	4789	if( GET_N || GET_Z )
4582		execute_trap(cpustate, addr);
	4790	execute_trap(addr);
4583	4791
4584	4792	break;
4585	4793
4586	4794	case TRAPGT:
4587	4795	if( !GET_N && !GET_Z )
4588		execute_trap(cpustate, addr);
	4796	execute_trap(addr);
4589	4797
4590	4798	break;
4591	4799
4592	4800	case TRAPLT:
4593	4801	if( GET_N )
4594		execute_trap(cpustate, addr);
	4802	execute_trap(addr);
4595	4803
4596	4804	break;
4597	4805
4598	4806	case TRAPGE:
4599	4807	if( !GET_N )
4600		execute_trap(cpustate, addr);
	4808	execute_trap(addr);
4601	4809
4602	4810	break;
4603	4811
4604	4812	case TRAPSE:
4605	4813	if( GET_C || GET_Z )
4606		execute_trap(cpustate, addr);
	4814	execute_trap(addr);
4607	4815
4608	4816	break;
4609	4817
4610	4818	case TRAPHT:
4611	4819	if( !GET_C && !GET_Z )
4612		execute_trap(cpustate, addr);
	4820	execute_trap(addr);
4613	4821
4614	4822	break;
4615	4823
4616	4824	case TRAPST:
4617	4825	if( GET_C )
4618		execute_trap(cpustate, addr);
	4826	execute_trap(addr);
4619	4827
4620	4828	break;
4621	4829
4622	4830	case TRAPHE:
4623	4831	if( !GET_C )
4624		execute_trap(cpustate, addr);
	4832	execute_trap(addr);
4625	4833
4626	4834	break;
4627	4835
4628	4836	case TRAPE:
4629	4837	if( GET_Z )
4630		execute_trap(cpustate, addr);
	4838	execute_trap(addr);
4631	4839
4632	4840	break;
4633	4841
4634	4842	case TRAPNE:
4635	4843	if( !GET_Z )
4636		execute_trap(cpustate, addr);
	4844	execute_trap(addr);
4637	4845
4638	4846	break;
4639	4847
4640	4848	case TRAPV:
4641	4849	if( GET_V )
4642		execute_trap(cpustate, addr);
	4850	execute_trap(addr);
4643	4851
4644	4852	break;
4645	4853
4646	4854	case TRAP:
4647		execute_trap(cpustate, addr);
	4855	execute_trap(addr);
4648	4856
4649	4857	break;
4650	4858	}
4651	4859
4652		cpustate->icount -= cpustate->clock_cycles_1;
	4860	m_icount -= m_clock_cycles_1;
4653	4861	}
4654	4862
4655	4863
4656	4864	#include "e132xsop.c"
4657	4865
	4866	//**************************************************************************
	4867	//  CORE EXECUTION LOOP
	4868	//**************************************************************************
4658	4869
4659		static CPU_EXECUTE( hyperstone )
4660		{
4661		hyperstone_state *cpustate = get_safe_token(device);
	4870	//-------------------------------------------------
	4871	//  execute_min_cycles - return minimum number of
	4872	//  cycles it takes for one instruction to execute
	4873	//-------------------------------------------------
4662	4874
4663		if (cpustate->intblock < 0)
4664		cpustate->intblock = 0;
4665		check_interrupts(cpustate);
4666
4667		do
4668		{
4669		UINT32 oldh = SR & 0x00000020;
4670
4671		PPC = PC;   /* copy PC to previous PC */
4672		debugger_instruction_hook(device, PC);
4673
4674		OP = READ_OP(cpustate, PC);
4675		PC += 2;
4676
4677		cpustate->instruction_length = 1;
4678
4679		/* execute opcode */
4680		(*hyperstone_op[(OP & 0xff00) >> 8])(cpustate);
4681
4682		/* clear the H state if it was previously set */
4683		SR ^= oldh;
4684
4685		SET_ILC(cpustate->instruction_length & 3);
4686
4687		if( GET_T && GET_P && cpustate->delay.delay_cmd == NO_DELAY ) /* Not in a Delayed Branch instructions */
4688		{
4689		UINT32 addr = get_trap_addr(cpustate, TRAPNO_TRACE_EXCEPTION);
4690		execute_exception(cpustate, addr);
4691		}
4692
4693		if (--cpustate->intblock == 0)
4694		check_interrupts(cpustate);
4695
4696		} while( cpustate->icount > 0 );
4697		}
4698
4699
4700		/**************************************************************************
4701		* Generic set_info
4702		**************************************************************************/
4703
4704		static CPU_SET_INFO( hyperstone )
	4875	UINT32 hyperstone_device::execute_min_cycles() const
4705	4876	{
4706		hyperstone_state *cpustate = get_safe_token(device);
4707		switch (state)
4708		{
4709		/* --- the following bits of info are set as 64-bit signed integers --- */
4710
4711		case CPUINFO_INT_PC:
4712		case CPUINFO_INT_REGISTER + E132XS_PC:         PC = info->i;                  break;
4713		case CPUINFO_INT_REGISTER + E132XS_SR:         SR = info->i;                  break;
4714		case CPUINFO_INT_REGISTER + E132XS_FER:         FER = info->i;                  break;
4715		case CPUINFO_INT_REGISTER + E132XS_G3:         set_global_register(cpustate, 3, info->i);   break;
4716		case CPUINFO_INT_REGISTER + E132XS_G4:         set_global_register(cpustate, 4, info->i);   break;
4717		case CPUINFO_INT_REGISTER + E132XS_G5:         set_global_register(cpustate, 5, info->i);   break;
4718		case CPUINFO_INT_REGISTER + E132XS_G6:         set_global_register(cpustate, 6, info->i);   break;
4719		case CPUINFO_INT_REGISTER + E132XS_G7:         set_global_register(cpustate, 7, info->i);   break;
4720		case CPUINFO_INT_REGISTER + E132XS_G8:         set_global_register(cpustate, 8, info->i);   break;
4721		case CPUINFO_INT_REGISTER + E132XS_G9:         set_global_register(cpustate, 9, info->i);   break;
4722		case CPUINFO_INT_REGISTER + E132XS_G10:         set_global_register(cpustate, 10, info->i);   break;
4723		case CPUINFO_INT_REGISTER + E132XS_G11:         set_global_register(cpustate, 11, info->i);   break;
4724		case CPUINFO_INT_REGISTER + E132XS_G12:         set_global_register(cpustate, 12, info->i);   break;
4725		case CPUINFO_INT_REGISTER + E132XS_G13:         set_global_register(cpustate, 13, info->i);   break;
4726		case CPUINFO_INT_REGISTER + E132XS_G14:         set_global_register(cpustate, 14, info->i);   break;
4727		case CPUINFO_INT_REGISTER + E132XS_G15:         set_global_register(cpustate, 15, info->i);   break;
4728		case CPUINFO_INT_REGISTER + E132XS_G16:         set_global_register(cpustate, 16, info->i);   break;
4729		case CPUINFO_INT_REGISTER + E132XS_G17:         set_global_register(cpustate, 17, info->i);   break;
4730		case CPUINFO_INT_SP:
4731		case CPUINFO_INT_REGISTER + E132XS_SP:         SP  = info->i;                     break;
4732		case CPUINFO_INT_REGISTER + E132XS_UB:         UB  = info->i;                     break;
4733		case CPUINFO_INT_REGISTER + E132XS_BCR:         BCR = info->i;                     break;
4734		case CPUINFO_INT_REGISTER + E132XS_TPR:         TPR = info->i;                     break;
4735		case CPUINFO_INT_REGISTER + E132XS_TCR:         TCR = info->i;                     break;
4736		case CPUINFO_INT_REGISTER + E132XS_TR:         set_global_register(cpustate, TR_REGISTER, info->i);   break;
4737		case CPUINFO_INT_REGISTER + E132XS_WCR:         WCR = info->i;                     break;
4738		case CPUINFO_INT_REGISTER + E132XS_ISR:         ISR = info->i;                     break;
4739		case CPUINFO_INT_REGISTER + E132XS_FCR:         FCR = info->i;                     break;
4740		case CPUINFO_INT_REGISTER + E132XS_MCR:         MCR = info->i;                     break;
4741		case CPUINFO_INT_REGISTER + E132XS_G28:         set_global_register(cpustate, 28, info->i);   break;
4742		case CPUINFO_INT_REGISTER + E132XS_G29:         set_global_register(cpustate, 29, info->i);   break;
4743		case CPUINFO_INT_REGISTER + E132XS_G30:         set_global_register(cpustate, 30, info->i);   break;
4744		case CPUINFO_INT_REGISTER + E132XS_G31:         set_global_register(cpustate, 31, info->i);   break;
4745		case CPUINFO_INT_REGISTER + E132XS_CL0:         cpustate->local_regs[(0 + GET_FP) % 64] = info->i; break;
4746		case CPUINFO_INT_REGISTER + E132XS_CL1:         cpustate->local_regs[(1 + GET_FP) % 64] = info->i; break;
4747		case CPUINFO_INT_REGISTER + E132XS_CL2:         cpustate->local_regs[(2 + GET_FP) % 64] = info->i; break;
4748		case CPUINFO_INT_REGISTER + E132XS_CL3:         cpustate->local_regs[(3 + GET_FP) % 64] = info->i; break;
4749		case CPUINFO_INT_REGISTER + E132XS_CL4:         cpustate->local_regs[(4 + GET_FP) % 64] = info->i; break;
4750		case CPUINFO_INT_REGISTER + E132XS_CL5:         cpustate->local_regs[(5 + GET_FP) % 64] = info->i; break;
4751		case CPUINFO_INT_REGISTER + E132XS_CL6:         cpustate->local_regs[(6 + GET_FP) % 64] = info->i; break;
4752		case CPUINFO_INT_REGISTER + E132XS_CL7:         cpustate->local_regs[(7 + GET_FP) % 64] = info->i; break;
4753		case CPUINFO_INT_REGISTER + E132XS_CL8:         cpustate->local_regs[(8 + GET_FP) % 64] = info->i; break;
4754		case CPUINFO_INT_REGISTER + E132XS_CL9:         cpustate->local_regs[(9 + GET_FP) % 64] = info->i; break;
4755		case CPUINFO_INT_REGISTER + E132XS_CL10:      cpustate->local_regs[(10 + GET_FP) % 64] = info->i; break;
4756		case CPUINFO_INT_REGISTER + E132XS_CL11:      cpustate->local_regs[(11 + GET_FP) % 64] = info->i; break;
4757		case CPUINFO_INT_REGISTER + E132XS_CL12:      cpustate->local_regs[(12 + GET_FP) % 64] = info->i; break;
4758		case CPUINFO_INT_REGISTER + E132XS_CL13:      cpustate->local_regs[(13 + GET_FP) % 64] = info->i; break;
4759		case CPUINFO_INT_REGISTER + E132XS_CL14:      cpustate->local_regs[(14 + GET_FP) % 64] = info->i; break;
4760		case CPUINFO_INT_REGISTER + E132XS_CL15:      cpustate->local_regs[(15 + GET_FP) % 64] = info->i; break;
4761		case CPUINFO_INT_REGISTER + E132XS_L0:         cpustate->local_regs[0] = info->i;      break;
4762		case CPUINFO_INT_REGISTER + E132XS_L1:         cpustate->local_regs[1] = info->i;      break;
4763		case CPUINFO_INT_REGISTER + E132XS_L2:         cpustate->local_regs[2] = info->i;      break;
4764		case CPUINFO_INT_REGISTER + E132XS_L3:         cpustate->local_regs[3] = info->i;      break;
4765		case CPUINFO_INT_REGISTER + E132XS_L4:         cpustate->local_regs[4] = info->i;      break;
4766		case CPUINFO_INT_REGISTER + E132XS_L5:         cpustate->local_regs[5] = info->i;      break;
4767		case CPUINFO_INT_REGISTER + E132XS_L6:         cpustate->local_regs[6] = info->i;      break;
4768		case CPUINFO_INT_REGISTER + E132XS_L7:         cpustate->local_regs[7] = info->i;      break;
4769		case CPUINFO_INT_REGISTER + E132XS_L8:         cpustate->local_regs[8] = info->i;      break;
4770		case CPUINFO_INT_REGISTER + E132XS_L9:         cpustate->local_regs[9] = info->i;      break;
4771		case CPUINFO_INT_REGISTER + E132XS_L10:         cpustate->local_regs[10] = info->i;   break;
4772		case CPUINFO_INT_REGISTER + E132XS_L11:         cpustate->local_regs[11] = info->i;   break;
4773		case CPUINFO_INT_REGISTER + E132XS_L12:         cpustate->local_regs[12] = info->i;   break;
4774		case CPUINFO_INT_REGISTER + E132XS_L13:         cpustate->local_regs[13] = info->i;   break;
4775		case CPUINFO_INT_REGISTER + E132XS_L14:         cpustate->local_regs[14] = info->i;   break;
4776		case CPUINFO_INT_REGISTER + E132XS_L15:         cpustate->local_regs[15] = info->i;   break;
4777		case CPUINFO_INT_REGISTER + E132XS_L16:         cpustate->local_regs[16] = info->i;   break;
4778		case CPUINFO_INT_REGISTER + E132XS_L17:         cpustate->local_regs[17] = info->i;   break;
4779		case CPUINFO_INT_REGISTER + E132XS_L18:         cpustate->local_regs[18] = info->i;   break;
4780		case CPUINFO_INT_REGISTER + E132XS_L19:         cpustate->local_regs[19] = info->i;   break;
4781		case CPUINFO_INT_REGISTER + E132XS_L20:         cpustate->local_regs[20] = info->i;   break;
4782		case CPUINFO_INT_REGISTER + E132XS_L21:         cpustate->local_regs[21] = info->i;   break;
4783		case CPUINFO_INT_REGISTER + E132XS_L22:         cpustate->local_regs[22] = info->i;   break;
4784		case CPUINFO_INT_REGISTER + E132XS_L23:         cpustate->local_regs[23] = info->i;   break;
4785		case CPUINFO_INT_REGISTER + E132XS_L24:         cpustate->local_regs[24] = info->i;   break;
4786		case CPUINFO_INT_REGISTER + E132XS_L25:         cpustate->local_regs[25] = info->i;   break;
4787		case CPUINFO_INT_REGISTER + E132XS_L26:         cpustate->local_regs[26] = info->i;   break;
4788		case CPUINFO_INT_REGISTER + E132XS_L27:         cpustate->local_regs[27] = info->i;   break;
4789		case CPUINFO_INT_REGISTER + E132XS_L28:         cpustate->local_regs[28] = info->i;   break;
4790		case CPUINFO_INT_REGISTER + E132XS_L29:         cpustate->local_regs[29] = info->i;   break;
4791		case CPUINFO_INT_REGISTER + E132XS_L30:         cpustate->local_regs[30] = info->i;   break;
4792		case CPUINFO_INT_REGISTER + E132XS_L31:         cpustate->local_regs[31] = info->i;   break;
4793		case CPUINFO_INT_REGISTER + E132XS_L32:         cpustate->local_regs[32] = info->i;   break;
4794		case CPUINFO_INT_REGISTER + E132XS_L33:         cpustate->local_regs[33] = info->i;   break;
4795		case CPUINFO_INT_REGISTER + E132XS_L34:         cpustate->local_regs[34] = info->i;   break;
4796		case CPUINFO_INT_REGISTER + E132XS_L35:         cpustate->local_regs[35] = info->i;   break;
4797		case CPUINFO_INT_REGISTER + E132XS_L36:         cpustate->local_regs[36] = info->i;   break;
4798		case CPUINFO_INT_REGISTER + E132XS_L37:         cpustate->local_regs[37] = info->i;   break;
4799		case CPUINFO_INT_REGISTER + E132XS_L38:         cpustate->local_regs[38] = info->i;   break;
4800		case CPUINFO_INT_REGISTER + E132XS_L39:         cpustate->local_regs[39] = info->i;   break;
4801		case CPUINFO_INT_REGISTER + E132XS_L40:         cpustate->local_regs[40] = info->i;   break;
4802		case CPUINFO_INT_REGISTER + E132XS_L41:         cpustate->local_regs[41] = info->i;   break;
4803		case CPUINFO_INT_REGISTER + E132XS_L42:         cpustate->local_regs[42] = info->i;   break;
4804		case CPUINFO_INT_REGISTER + E132XS_L43:         cpustate->local_regs[43] = info->i;   break;
4805		case CPUINFO_INT_REGISTER + E132XS_L44:         cpustate->local_regs[44] = info->i;   break;
4806		case CPUINFO_INT_REGISTER + E132XS_L45:         cpustate->local_regs[45] = info->i;   break;
4807		case CPUINFO_INT_REGISTER + E132XS_L46:         cpustate->local_regs[46] = info->i;   break;
4808		case CPUINFO_INT_REGISTER + E132XS_L47:         cpustate->local_regs[47] = info->i;   break;
4809		case CPUINFO_INT_REGISTER + E132XS_L48:         cpustate->local_regs[48] = info->i;   break;
4810		case CPUINFO_INT_REGISTER + E132XS_L49:         cpustate->local_regs[49] = info->i;   break;
4811		case CPUINFO_INT_REGISTER + E132XS_L50:         cpustate->local_regs[50] = info->i;   break;
4812		case CPUINFO_INT_REGISTER + E132XS_L51:         cpustate->local_regs[51] = info->i;   break;
4813		case CPUINFO_INT_REGISTER + E132XS_L52:         cpustate->local_regs[52] = info->i;   break;
4814		case CPUINFO_INT_REGISTER + E132XS_L53:         cpustate->local_regs[53] = info->i;   break;
4815		case CPUINFO_INT_REGISTER + E132XS_L54:         cpustate->local_regs[54] = info->i;   break;
4816		case CPUINFO_INT_REGISTER + E132XS_L55:         cpustate->local_regs[55] = info->i;   break;
4817		case CPUINFO_INT_REGISTER + E132XS_L56:         cpustate->local_regs[56] = info->i;   break;
4818		case CPUINFO_INT_REGISTER + E132XS_L57:         cpustate->local_regs[57] = info->i;   break;
4819		case CPUINFO_INT_REGISTER + E132XS_L58:         cpustate->local_regs[58] = info->i;   break;
4820		case CPUINFO_INT_REGISTER + E132XS_L59:         cpustate->local_regs[59] = info->i;   break;
4821		case CPUINFO_INT_REGISTER + E132XS_L60:         cpustate->local_regs[60] = info->i;   break;
4822		case CPUINFO_INT_REGISTER + E132XS_L61:         cpustate->local_regs[61] = info->i;   break;
4823		case CPUINFO_INT_REGISTER + E132XS_L62:         cpustate->local_regs[62] = info->i;   break;
4824		case CPUINFO_INT_REGISTER + E132XS_L63:         cpustate->local_regs[63] = info->i;   break;
4825
4826		case CPUINFO_INT_INPUT_STATE + 0:            set_irq_line(cpustate, 0, info->i);            break;
4827		case CPUINFO_INT_INPUT_STATE + 1:            set_irq_line(cpustate, 1, info->i);            break;
4828		case CPUINFO_INT_INPUT_STATE + 2:            set_irq_line(cpustate, 2, info->i);            break;
4829		case CPUINFO_INT_INPUT_STATE + 3:            set_irq_line(cpustate, 3, info->i);            break;
4830		case CPUINFO_INT_INPUT_STATE + 4:            set_irq_line(cpustate, 4, info->i);            break;
4831		case CPUINFO_INT_INPUT_STATE + 5:            set_irq_line(cpustate, 5, info->i);            break;
4832		case CPUINFO_INT_INPUT_STATE + 6:            set_irq_line(cpustate, 6, info->i);            break;
4833		case CPUINFO_INT_INPUT_STATE + 7:            set_irq_line(cpustate, 7, info->i);            break;
4834		}
	4877	return 1;
4835	4878	}
4836	4879
4837		/**************************************************************************
4838		* Generic get_info
4839		**************************************************************************/
4840	4880
4841		static CPU_GET_INFO( hyperstone )
4842		{
4843		hyperstone_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
4844		switch (state)
4845		{
4846		/* --- the following bits of info are returned as 64-bit signed integers --- */
4847		case CPUINFO_INT_CONTEXT_SIZE:               info->i = sizeof(hyperstone_state);      break;
4848		case CPUINFO_INT_INPUT_LINES:               info->i = 8;                     break;
4849		case CPUINFO_INT_DEFAULT_IRQ_VECTOR:         info->i = 0;                     break;
4850		case CPUINFO_INT_ENDIANNESS:               info->i = ENDIANNESS_BIG;               break;
4851		case CPUINFO_INT_CLOCK_MULTIPLIER:            info->i = 1;                     break;
4852		case CPUINFO_INT_CLOCK_DIVIDER:               info->i = 1;                     break;
4853		case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 2;                     break;
4854		case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 6;                     break;
4855		case CPUINFO_INT_MIN_CYCLES:               info->i = 1;                     break;
4856		case CPUINFO_INT_MAX_CYCLES:               info->i = 36;                     break;
	4881	//-------------------------------------------------
	4882	//  execute_max_cycles - return maximum number of
	4883	//  cycles it takes for one instruction to execute
	4884	//-------------------------------------------------
4857	4885
4858		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32;               break;
4859		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0;               break;
4860		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 0;               break;
4861		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 0;               break;
4862		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = 0;               break;
4863		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:      info->i = 15;               break;
4864		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:      info->i = 0;               break;
4865
4866		case CPUINFO_INT_INPUT_STATE + 0:               /* not implemented */            break;
4867
4868		case CPUINFO_INT_PREVIOUSPC:               info->i = PPC;                     break;
4869
4870		case CPUINFO_INT_PC:
4871		case CPUINFO_INT_REGISTER + E132XS_PC:         info->i =  PC;                     break;
4872		case CPUINFO_INT_REGISTER + E132XS_SR:         info->i =  SR;                     break;
4873		case CPUINFO_INT_REGISTER + E132XS_FER:         info->i =  FER;                     break;
4874		case CPUINFO_INT_REGISTER + E132XS_G3:         info->i =  get_global_register(cpustate, 3);   break;
4875		case CPUINFO_INT_REGISTER + E132XS_G4:         info->i =  get_global_register(cpustate, 4);   break;
4876		case CPUINFO_INT_REGISTER + E132XS_G5:         info->i =  get_global_register(cpustate, 5);   break;
4877		case CPUINFO_INT_REGISTER + E132XS_G6:         info->i =  get_global_register(cpustate, 6);   break;
4878		case CPUINFO_INT_REGISTER + E132XS_G7:         info->i =  get_global_register(cpustate, 7);   break;
4879		case CPUINFO_INT_REGISTER + E132XS_G8:         info->i =  get_global_register(cpustate, 8);   break;
4880		case CPUINFO_INT_REGISTER + E132XS_G9:         info->i =  get_global_register(cpustate, 9);   break;
4881		case CPUINFO_INT_REGISTER + E132XS_G10:         info->i =  get_global_register(cpustate, 10);   break;
4882		case CPUINFO_INT_REGISTER + E132XS_G11:         info->i =  get_global_register(cpustate, 11);   break;
4883		case CPUINFO_INT_REGISTER + E132XS_G12:         info->i =  get_global_register(cpustate, 12);   break;
4884		case CPUINFO_INT_REGISTER + E132XS_G13:         info->i =  get_global_register(cpustate, 13);   break;
4885		case CPUINFO_INT_REGISTER + E132XS_G14:         info->i =  get_global_register(cpustate, 14);   break;
4886		case CPUINFO_INT_REGISTER + E132XS_G15:         info->i =  get_global_register(cpustate, 15);   break;
4887		case CPUINFO_INT_REGISTER + E132XS_G16:         info->i =  get_global_register(cpustate, 16);   break;
4888		case CPUINFO_INT_REGISTER + E132XS_G17:         info->i =  get_global_register(cpustate, 17);   break;
4889		case CPUINFO_INT_SP:
4890		case CPUINFO_INT_REGISTER + E132XS_SP:         info->i =  SP;                     break;
4891		case CPUINFO_INT_REGISTER + E132XS_UB:         info->i =  UB;                     break;
4892		case CPUINFO_INT_REGISTER + E132XS_BCR:         info->i =  BCR;                     break;
4893		case CPUINFO_INT_REGISTER + E132XS_TPR:         info->i =  TPR;                     break;
4894		case CPUINFO_INT_REGISTER + E132XS_TCR:         info->i =  TCR;                     break;
4895		case CPUINFO_INT_REGISTER + E132XS_TR:         info->i =  TR;                     break;
4896		case CPUINFO_INT_REGISTER + E132XS_WCR:         info->i =  WCR;                     break;
4897		case CPUINFO_INT_REGISTER + E132XS_ISR:         info->i =  ISR;                     break;
4898		case CPUINFO_INT_REGISTER + E132XS_FCR:         info->i =  FCR;                     break;
4899		case CPUINFO_INT_REGISTER + E132XS_MCR:         info->i =  MCR;                     break;
4900		case CPUINFO_INT_REGISTER + E132XS_G28:         info->i =  get_global_register(cpustate, 28);   break;
4901		case CPUINFO_INT_REGISTER + E132XS_G29:         info->i =  get_global_register(cpustate, 29);   break;
4902		case CPUINFO_INT_REGISTER + E132XS_G30:         info->i =  get_global_register(cpustate, 30);   break;
4903		case CPUINFO_INT_REGISTER + E132XS_G31:         info->i =  get_global_register(cpustate, 31);   break;
4904		case CPUINFO_INT_REGISTER + E132XS_CL0:         info->i =  cpustate->local_regs[(0 + GET_FP) % 64]; break;
4905		case CPUINFO_INT_REGISTER + E132XS_CL1:         info->i =  cpustate->local_regs[(1 + GET_FP) % 64]; break;
4906		case CPUINFO_INT_REGISTER + E132XS_CL2:         info->i =  cpustate->local_regs[(2 + GET_FP) % 64]; break;
4907		case CPUINFO_INT_REGISTER + E132XS_CL3:         info->i =  cpustate->local_regs[(3 + GET_FP) % 64]; break;
4908		case CPUINFO_INT_REGISTER + E132XS_CL4:         info->i =  cpustate->local_regs[(4 + GET_FP) % 64]; break;
4909		case CPUINFO_INT_REGISTER + E132XS_CL5:         info->i =  cpustate->local_regs[(5 + GET_FP) % 64]; break;
4910		case CPUINFO_INT_REGISTER + E132XS_CL6:         info->i =  cpustate->local_regs[(6 + GET_FP) % 64]; break;
4911		case CPUINFO_INT_REGISTER + E132XS_CL7:         info->i =  cpustate->local_regs[(7 + GET_FP) % 64]; break;
4912		case CPUINFO_INT_REGISTER + E132XS_CL8:         info->i =  cpustate->local_regs[(8 + GET_FP) % 64]; break;
4913		case CPUINFO_INT_REGISTER + E132XS_CL9:         info->i =  cpustate->local_regs[(9 + GET_FP) % 64]; break;
4914		case CPUINFO_INT_REGISTER + E132XS_CL10:      info->i =  cpustate->local_regs[(10 + GET_FP) % 64]; break;
4915		case CPUINFO_INT_REGISTER + E132XS_CL11:      info->i =  cpustate->local_regs[(11 + GET_FP) % 64]; break;
4916		case CPUINFO_INT_REGISTER + E132XS_CL12:      info->i =  cpustate->local_regs[(12 + GET_FP) % 64]; break;
4917		case CPUINFO_INT_REGISTER + E132XS_CL13:      info->i =  cpustate->local_regs[(13 + GET_FP) % 64]; break;
4918		case CPUINFO_INT_REGISTER + E132XS_CL14:      info->i =  cpustate->local_regs[(14 + GET_FP) % 64]; break;
4919		case CPUINFO_INT_REGISTER + E132XS_CL15:      info->i =  cpustate->local_regs[(15 + GET_FP) % 64]; break;
4920		case CPUINFO_INT_REGISTER + E132XS_L0:         info->i =  cpustate->local_regs[0];   break;
4921		case CPUINFO_INT_REGISTER + E132XS_L1:         info->i =  cpustate->local_regs[1];   break;
4922		case CPUINFO_INT_REGISTER + E132XS_L2:         info->i =  cpustate->local_regs[2];   break;
4923		case CPUINFO_INT_REGISTER + E132XS_L3:         info->i =  cpustate->local_regs[3];   break;
4924		case CPUINFO_INT_REGISTER + E132XS_L4:         info->i =  cpustate->local_regs[4];   break;
4925		case CPUINFO_INT_REGISTER + E132XS_L5:         info->i =  cpustate->local_regs[5];   break;
4926		case CPUINFO_INT_REGISTER + E132XS_L6:         info->i =  cpustate->local_regs[6];   break;
4927		case CPUINFO_INT_REGISTER + E132XS_L7:         info->i =  cpustate->local_regs[7];   break;
4928		case CPUINFO_INT_REGISTER + E132XS_L8:         info->i =  cpustate->local_regs[8];   break;
4929		case CPUINFO_INT_REGISTER + E132XS_L9:         info->i =  cpustate->local_regs[9];   break;
4930		case CPUINFO_INT_REGISTER + E132XS_L10:         info->i =  cpustate->local_regs[10];   break;
4931		case CPUINFO_INT_REGISTER + E132XS_L11:         info->i =  cpustate->local_regs[11];   break;
4932		case CPUINFO_INT_REGISTER + E132XS_L12:         info->i =  cpustate->local_regs[12];   break;
4933		case CPUINFO_INT_REGISTER + E132XS_L13:         info->i =  cpustate->local_regs[13];   break;
4934		case CPUINFO_INT_REGISTER + E132XS_L14:         info->i =  cpustate->local_regs[14];   break;
4935		case CPUINFO_INT_REGISTER + E132XS_L15:         info->i =  cpustate->local_regs[15];   break;
4936		case CPUINFO_INT_REGISTER + E132XS_L16:         info->i =  cpustate->local_regs[16];   break;
4937		case CPUINFO_INT_REGISTER + E132XS_L17:         info->i =  cpustate->local_regs[17];   break;
4938		case CPUINFO_INT_REGISTER + E132XS_L18:         info->i =  cpustate->local_regs[18];   break;
4939		case CPUINFO_INT_REGISTER + E132XS_L19:         info->i =  cpustate->local_regs[19];   break;
4940		case CPUINFO_INT_REGISTER + E132XS_L20:         info->i =  cpustate->local_regs[20];   break;
4941		case CPUINFO_INT_REGISTER + E132XS_L21:         info->i =  cpustate->local_regs[21];   break;
4942		case CPUINFO_INT_REGISTER + E132XS_L22:         info->i =  cpustate->local_regs[22];   break;
4943		case CPUINFO_INT_REGISTER + E132XS_L23:         info->i =  cpustate->local_regs[23];   break;
4944		case CPUINFO_INT_REGISTER + E132XS_L24:         info->i =  cpustate->local_regs[24];   break;
4945		case CPUINFO_INT_REGISTER + E132XS_L25:         info->i =  cpustate->local_regs[25];   break;
4946		case CPUINFO_INT_REGISTER + E132XS_L26:         info->i =  cpustate->local_regs[26];   break;
4947		case CPUINFO_INT_REGISTER + E132XS_L27:         info->i =  cpustate->local_regs[27];   break;
4948		case CPUINFO_INT_REGISTER + E132XS_L28:         info->i =  cpustate->local_regs[28];   break;
4949		case CPUINFO_INT_REGISTER + E132XS_L29:         info->i =  cpustate->local_regs[29];   break;
4950		case CPUINFO_INT_REGISTER + E132XS_L30:         info->i =  cpustate->local_regs[30];   break;
4951		case CPUINFO_INT_REGISTER + E132XS_L31:         info->i =  cpustate->local_regs[31];   break;
4952		case CPUINFO_INT_REGISTER + E132XS_L32:         info->i =  cpustate->local_regs[32];   break;
4953		case CPUINFO_INT_REGISTER + E132XS_L33:         info->i =  cpustate->local_regs[33];   break;
4954		case CPUINFO_INT_REGISTER + E132XS_L34:         info->i =  cpustate->local_regs[34];   break;
4955		case CPUINFO_INT_REGISTER + E132XS_L35:         info->i =  cpustate->local_regs[35];   break;
4956		case CPUINFO_INT_REGISTER + E132XS_L36:         info->i =  cpustate->local_regs[36];   break;
4957		case CPUINFO_INT_REGISTER + E132XS_L37:         info->i =  cpustate->local_regs[37];   break;
4958		case CPUINFO_INT_REGISTER + E132XS_L38:         info->i =  cpustate->local_regs[38];   break;
4959		case CPUINFO_INT_REGISTER + E132XS_L39:         info->i =  cpustate->local_regs[39];   break;
4960		case CPUINFO_INT_REGISTER + E132XS_L40:         info->i =  cpustate->local_regs[40];   break;
4961		case CPUINFO_INT_REGISTER + E132XS_L41:         info->i =  cpustate->local_regs[41];   break;
4962		case CPUINFO_INT_REGISTER + E132XS_L42:         info->i =  cpustate->local_regs[42];   break;
4963		case CPUINFO_INT_REGISTER + E132XS_L43:         info->i =  cpustate->local_regs[43];   break;
4964		case CPUINFO_INT_REGISTER + E132XS_L44:         info->i =  cpustate->local_regs[44];   break;
4965		case CPUINFO_INT_REGISTER + E132XS_L45:         info->i =  cpustate->local_regs[45];   break;
4966		case CPUINFO_INT_REGISTER + E132XS_L46:         info->i =  cpustate->local_regs[46];   break;
4967		case CPUINFO_INT_REGISTER + E132XS_L47:         info->i =  cpustate->local_regs[47];   break;
4968		case CPUINFO_INT_REGISTER + E132XS_L48:         info->i =  cpustate->local_regs[48];   break;
4969		case CPUINFO_INT_REGISTER + E132XS_L49:         info->i =  cpustate->local_regs[49];   break;
4970		case CPUINFO_INT_REGISTER + E132XS_L50:         info->i =  cpustate->local_regs[50];   break;
4971		case CPUINFO_INT_REGISTER + E132XS_L51:         info->i =  cpustate->local_regs[51];   break;
4972		case CPUINFO_INT_REGISTER + E132XS_L52:         info->i =  cpustate->local_regs[52];   break;
4973		case CPUINFO_INT_REGISTER + E132XS_L53:         info->i =  cpustate->local_regs[53];   break;
4974		case CPUINFO_INT_REGISTER + E132XS_L54:         info->i =  cpustate->local_regs[54];   break;
4975		case CPUINFO_INT_REGISTER + E132XS_L55:         info->i =  cpustate->local_regs[55];   break;
4976		case CPUINFO_INT_REGISTER + E132XS_L56:         info->i =  cpustate->local_regs[56];   break;
4977		case CPUINFO_INT_REGISTER + E132XS_L57:         info->i =  cpustate->local_regs[57];   break;
4978		case CPUINFO_INT_REGISTER + E132XS_L58:         info->i =  cpustate->local_regs[58];   break;
4979		case CPUINFO_INT_REGISTER + E132XS_L59:         info->i =  cpustate->local_regs[59];   break;
4980		case CPUINFO_INT_REGISTER + E132XS_L60:         info->i =  cpustate->local_regs[60];   break;
4981		case CPUINFO_INT_REGISTER + E132XS_L61:         info->i =  cpustate->local_regs[61];   break;
4982		case CPUINFO_INT_REGISTER + E132XS_L62:         info->i =  cpustate->local_regs[62];   break;
4983		case CPUINFO_INT_REGISTER + E132XS_L63:         info->i =  cpustate->local_regs[63];   break;
4984
4985		/* --- the following bits of info are returned as pointers to data or functions --- */
4986		case CPUINFO_FCT_SET_INFO:                  info->setinfo = CPU_SET_INFO_NAME(hyperstone);   break;
4987		case CPUINFO_FCT_INIT:                     info->init = NULL;                  break;
4988		case CPUINFO_FCT_RESET:                     info->reset = CPU_RESET_NAME(hyperstone);         break;
4989		case CPUINFO_FCT_EXIT:                     info->exit = CPU_EXIT_NAME(hyperstone);         break;
4990		case CPUINFO_FCT_EXECUTE:                  info->execute = CPU_EXECUTE_NAME(hyperstone);      break;
4991		case CPUINFO_FCT_BURN:                     info->burn = NULL;                  break;
4992		case CPUINFO_FCT_DISASSEMBLE:               info->disassemble = CPU_DISASSEMBLE_NAME(hyperstone);   break;
4993		case CPUINFO_PTR_INSTRUCTION_COUNTER:         info->icount = &cpustate->icount;      break;
4994
4995		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA:    info->internal_map16 = NULL;   break;
4996		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_IO:      info->internal_map16 = NULL;   break;
4997
4998		/* --- the following bits of info are returned as NULL-terminated strings --- */
4999		case CPUINFO_STR_FAMILY:               strcpy(info->s, "Hyperstone CPU");      break;
5000		case CPUINFO_STR_VERSION:               strcpy(info->s, "0.9");               break;
5001		case CPUINFO_STR_SOURCE_FILE:                  strcpy(info->s, __FILE__);            break;
5002		case CPUINFO_STR_CREDITS:               strcpy(info->s, "Copyright Pierpaolo Prazzoli and Ryan Holtz"); break;
5003
5004		case CPUINFO_STR_FLAGS:
5005		sprintf(info->s, "%c%c%c%c%c%c%c%c%c%c%c%c FTE:%X FRM:%X ILC:%d FL:%d FP:%d",
5006		GET_S ? 'S':'.',
5007		GET_P ? 'P':'.',
5008		GET_T ? 'T':'.',
5009		GET_L ? 'L':'.',
5010		GET_I ? 'I':'.',
5011		cpustate->global_regs[1] & 0x00040 ? '?':'.',
5012		GET_H ? 'H':'.',
5013		GET_M ? 'M':'.',
5014		GET_V ? 'V':'.',
5015		GET_N ? 'N':'.',
5016		GET_Z ? 'Z':'.',
5017		GET_C ? 'C':'.',
5018		GET_FTE,
5019		GET_FRM,
5020		GET_ILC,
5021		GET_FL,
5022		GET_FP);
5023		break;
5024
5025		case CPUINFO_STR_REGISTER + E132XS_PC:        sprintf(info->s, "PC  :%08X", cpustate->global_regs[0]); break;
5026		case CPUINFO_STR_REGISTER + E132XS_SR:        sprintf(info->s, "SR  :%08X", cpustate->global_regs[1]); break;
5027		case CPUINFO_STR_REGISTER + E132XS_FER:       sprintf(info->s, "FER :%08X", cpustate->global_regs[2]); break;
5028		case CPUINFO_STR_REGISTER + E132XS_G3:        sprintf(info->s, "G3  :%08X", cpustate->global_regs[3]); break;
5029		case CPUINFO_STR_REGISTER + E132XS_G4:        sprintf(info->s, "G4  :%08X", cpustate->global_regs[4]); break;
5030		case CPUINFO_STR_REGISTER + E132XS_G5:        sprintf(info->s, "G5  :%08X", cpustate->global_regs[5]); break;
5031		case CPUINFO_STR_REGISTER + E132XS_G6:        sprintf(info->s, "G6  :%08X", cpustate->global_regs[6]); break;
5032		case CPUINFO_STR_REGISTER + E132XS_G7:        sprintf(info->s, "G7  :%08X", cpustate->global_regs[7]); break;
5033		case CPUINFO_STR_REGISTER + E132XS_G8:        sprintf(info->s, "G8  :%08X", cpustate->global_regs[8]); break;
5034		case CPUINFO_STR_REGISTER + E132XS_G9:        sprintf(info->s, "G9  :%08X", cpustate->global_regs[9]); break;
5035		case CPUINFO_STR_REGISTER + E132XS_G10:       sprintf(info->s, "G10 :%08X", cpustate->global_regs[10]); break;
5036		case CPUINFO_STR_REGISTER + E132XS_G11:       sprintf(info->s, "G11 :%08X", cpustate->global_regs[11]); break;
5037		case CPUINFO_STR_REGISTER + E132XS_G12:       sprintf(info->s, "G12 :%08X", cpustate->global_regs[12]); break;
5038		case CPUINFO_STR_REGISTER + E132XS_G13:       sprintf(info->s, "G13 :%08X", cpustate->global_regs[13]); break;
5039		case CPUINFO_STR_REGISTER + E132XS_G14:       sprintf(info->s, "G14 :%08X", cpustate->global_regs[14]); break;
5040		case CPUINFO_STR_REGISTER + E132XS_G15:       sprintf(info->s, "G15 :%08X", cpustate->global_regs[15]); break;
5041		case CPUINFO_STR_REGISTER + E132XS_G16:       sprintf(info->s, "G16 :%08X", cpustate->global_regs[16]); break;
5042		case CPUINFO_STR_REGISTER + E132XS_G17:       sprintf(info->s, "G17 :%08X", cpustate->global_regs[17]); break;
5043		case CPUINFO_STR_REGISTER + E132XS_SP:        sprintf(info->s, "SP  :%08X", cpustate->global_regs[18]); break;
5044		case CPUINFO_STR_REGISTER + E132XS_UB:        sprintf(info->s, "UB  :%08X", cpustate->global_regs[19]); break;
5045		case CPUINFO_STR_REGISTER + E132XS_BCR:       sprintf(info->s, "BCR :%08X", cpustate->global_regs[20]); break;
5046		case CPUINFO_STR_REGISTER + E132XS_TPR:       sprintf(info->s, "TPR :%08X", cpustate->global_regs[21]); break;
5047		case CPUINFO_STR_REGISTER + E132XS_TCR:       sprintf(info->s, "TCR :%08X", cpustate->global_regs[22]); break;
5048		case CPUINFO_STR_REGISTER + E132XS_TR:        sprintf(info->s, "TR  :%08X", cpustate->global_regs[23]); break;
5049		case CPUINFO_STR_REGISTER + E132XS_WCR:       sprintf(info->s, "WCR :%08X", cpustate->global_regs[24]); break;
5050		case CPUINFO_STR_REGISTER + E132XS_ISR:       sprintf(info->s, "ISR :%08X", cpustate->global_regs[25]); break;
5051		case CPUINFO_STR_REGISTER + E132XS_FCR:       sprintf(info->s, "FCR :%08X", cpustate->global_regs[26]); break;
5052		case CPUINFO_STR_REGISTER + E132XS_MCR:       sprintf(info->s, "MCR :%08X", cpustate->global_regs[27]); break;
5053		case CPUINFO_STR_REGISTER + E132XS_G28:       sprintf(info->s, "G28 :%08X", cpustate->global_regs[28]); break;
5054		case CPUINFO_STR_REGISTER + E132XS_G29:       sprintf(info->s, "G29 :%08X", cpustate->global_regs[29]); break;
5055		case CPUINFO_STR_REGISTER + E132XS_G30:       sprintf(info->s, "G30 :%08X", cpustate->global_regs[30]); break;
5056		case CPUINFO_STR_REGISTER + E132XS_G31:       sprintf(info->s, "G31 :%08X", cpustate->global_regs[31]); break;
5057		case CPUINFO_STR_REGISTER + E132XS_CL0:       sprintf(info->s, "CL0 :%08X", cpustate->local_regs[(0 + GET_FP) % 64]); break;
5058		case CPUINFO_STR_REGISTER + E132XS_CL1:       sprintf(info->s, "CL1 :%08X", cpustate->local_regs[(1 + GET_FP) % 64]); break;
5059		case CPUINFO_STR_REGISTER + E132XS_CL2:       sprintf(info->s, "CL2 :%08X", cpustate->local_regs[(2 + GET_FP) % 64]); break;
5060		case CPUINFO_STR_REGISTER + E132XS_CL3:       sprintf(info->s, "CL3 :%08X", cpustate->local_regs[(3 + GET_FP) % 64]); break;
5061		case CPUINFO_STR_REGISTER + E132XS_CL4:       sprintf(info->s, "CL4 :%08X", cpustate->local_regs[(4 + GET_FP) % 64]); break;
5062		case CPUINFO_STR_REGISTER + E132XS_CL5:       sprintf(info->s, "CL5 :%08X", cpustate->local_regs[(5 + GET_FP) % 64]); break;
5063		case CPUINFO_STR_REGISTER + E132XS_CL6:       sprintf(info->s, "CL6 :%08X", cpustate->local_regs[(6 + GET_FP) % 64]); break;
5064		case CPUINFO_STR_REGISTER + E132XS_CL7:       sprintf(info->s, "CL7 :%08X", cpustate->local_regs[(7 + GET_FP) % 64]); break;
5065		case CPUINFO_STR_REGISTER + E132XS_CL8:       sprintf(info->s, "CL8 :%08X", cpustate->local_regs[(8 + GET_FP) % 64]); break;
5066		case CPUINFO_STR_REGISTER + E132XS_CL9:       sprintf(info->s, "CL9 :%08X", cpustate->local_regs[(9 + GET_FP) % 64]); break;
5067		case CPUINFO_STR_REGISTER + E132XS_CL10:      sprintf(info->s, "CL10:%08X", cpustate->local_regs[(10 + GET_FP) % 64]); break;
5068		case CPUINFO_STR_REGISTER + E132XS_CL11:      sprintf(info->s, "CL11:%08X", cpustate->local_regs[(11 + GET_FP) % 64]); break;
5069		case CPUINFO_STR_REGISTER + E132XS_CL12:      sprintf(info->s, "CL12:%08X", cpustate->local_regs[(12 + GET_FP) % 64]); break;
5070		case CPUINFO_STR_REGISTER + E132XS_CL13:      sprintf(info->s, "CL13:%08X", cpustate->local_regs[(13 + GET_FP) % 64]); break;
5071		case CPUINFO_STR_REGISTER + E132XS_CL14:      sprintf(info->s, "CL14:%08X", cpustate->local_regs[(14 + GET_FP) % 64]); break;
5072		case CPUINFO_STR_REGISTER + E132XS_CL15:      sprintf(info->s, "CL15:%08X", cpustate->local_regs[(15 + GET_FP) % 64]); break;
5073		case CPUINFO_STR_REGISTER + E132XS_L0:        sprintf(info->s, "L0  :%08X", cpustate->local_regs[0]); break;
5074		case CPUINFO_STR_REGISTER + E132XS_L1:        sprintf(info->s, "L1  :%08X", cpustate->local_regs[1]); break;
5075		case CPUINFO_STR_REGISTER + E132XS_L2:        sprintf(info->s, "L2  :%08X", cpustate->local_regs[2]); break;
5076		case CPUINFO_STR_REGISTER + E132XS_L3:        sprintf(info->s, "L3  :%08X", cpustate->local_regs[3]); break;
5077		case CPUINFO_STR_REGISTER + E132XS_L4:        sprintf(info->s, "L4  :%08X", cpustate->local_regs[4]); break;
5078		case CPUINFO_STR_REGISTER + E132XS_L5:        sprintf(info->s, "L5  :%08X", cpustate->local_regs[5]); break;
5079		case CPUINFO_STR_REGISTER + E132XS_L6:        sprintf(info->s, "L6  :%08X", cpustate->local_regs[6]); break;
5080		case CPUINFO_STR_REGISTER + E132XS_L7:        sprintf(info->s, "L7  :%08X", cpustate->local_regs[7]); break;
5081		case CPUINFO_STR_REGISTER + E132XS_L8:        sprintf(info->s, "L8  :%08X", cpustate->local_regs[8]); break;
5082		case CPUINFO_STR_REGISTER + E132XS_L9:        sprintf(info->s, "L9  :%08X", cpustate->local_regs[9]); break;
5083		case CPUINFO_STR_REGISTER + E132XS_L10:       sprintf(info->s, "L10 :%08X", cpustate->local_regs[10]); break;
5084		case CPUINFO_STR_REGISTER + E132XS_L11:       sprintf(info->s, "L11 :%08X", cpustate->local_regs[11]); break;
5085		case CPUINFO_STR_REGISTER + E132XS_L12:       sprintf(info->s, "L12 :%08X", cpustate->local_regs[12]); break;
5086		case CPUINFO_STR_REGISTER + E132XS_L13:       sprintf(info->s, "L13 :%08X", cpustate->local_regs[13]); break;
5087		case CPUINFO_STR_REGISTER + E132XS_L14:       sprintf(info->s, "L14 :%08X", cpustate->local_regs[14]); break;
5088		case CPUINFO_STR_REGISTER + E132XS_L15:       sprintf(info->s, "L15 :%08X", cpustate->local_regs[15]); break;
5089		case CPUINFO_STR_REGISTER + E132XS_L16:       sprintf(info->s, "L16 :%08X", cpustate->local_regs[16]); break;
5090		case CPUINFO_STR_REGISTER + E132XS_L17:       sprintf(info->s, "L17 :%08X", cpustate->local_regs[17]); break;
5091		case CPUINFO_STR_REGISTER + E132XS_L18:       sprintf(info->s, "L18 :%08X", cpustate->local_regs[18]); break;
5092		case CPUINFO_STR_REGISTER + E132XS_L19:       sprintf(info->s, "L19 :%08X", cpustate->local_regs[19]); break;
5093		case CPUINFO_STR_REGISTER + E132XS_L20:       sprintf(info->s, "L20 :%08X", cpustate->local_regs[20]); break;
5094		case CPUINFO_STR_REGISTER + E132XS_L21:       sprintf(info->s, "L21 :%08X", cpustate->local_regs[21]); break;
5095		case CPUINFO_STR_REGISTER + E132XS_L22:       sprintf(info->s, "L22 :%08X", cpustate->local_regs[22]); break;
5096		case CPUINFO_STR_REGISTER + E132XS_L23:       sprintf(info->s, "L23 :%08X", cpustate->local_regs[23]); break;
5097		case CPUINFO_STR_REGISTER + E132XS_L24:       sprintf(info->s, "L24 :%08X", cpustate->local_regs[24]); break;
5098		case CPUINFO_STR_REGISTER + E132XS_L25:       sprintf(info->s, "L25 :%08X", cpustate->local_regs[25]); break;
5099		case CPUINFO_STR_REGISTER + E132XS_L26:       sprintf(info->s, "L26 :%08X", cpustate->local_regs[26]); break;
5100		case CPUINFO_STR_REGISTER + E132XS_L27:       sprintf(info->s, "L27 :%08X", cpustate->local_regs[27]); break;
5101		case CPUINFO_STR_REGISTER + E132XS_L28:       sprintf(info->s, "L28 :%08X", cpustate->local_regs[28]); break;
5102		case CPUINFO_STR_REGISTER + E132XS_L29:       sprintf(info->s, "L29 :%08X", cpustate->local_regs[29]); break;
5103		case CPUINFO_STR_REGISTER + E132XS_L30:       sprintf(info->s, "L30 :%08X", cpustate->local_regs[30]); break;
5104		case CPUINFO_STR_REGISTER + E132XS_L31:       sprintf(info->s, "L31 :%08X", cpustate->local_regs[31]); break;
5105		case CPUINFO_STR_REGISTER + E132XS_L32:       sprintf(info->s, "L32 :%08X", cpustate->local_regs[32]); break;
5106		case CPUINFO_STR_REGISTER + E132XS_L33:       sprintf(info->s, "L33 :%08X", cpustate->local_regs[33]); break;
5107		case CPUINFO_STR_REGISTER + E132XS_L34:       sprintf(info->s, "L34 :%08X", cpustate->local_regs[34]); break;
5108		case CPUINFO_STR_REGISTER + E132XS_L35:       sprintf(info->s, "L35 :%08X", cpustate->local_regs[35]); break;
5109		case CPUINFO_STR_REGISTER + E132XS_L36:       sprintf(info->s, "L36 :%08X", cpustate->local_regs[36]); break;
5110		case CPUINFO_STR_REGISTER + E132XS_L37:       sprintf(info->s, "L37 :%08X", cpustate->local_regs[37]); break;
5111		case CPUINFO_STR_REGISTER + E132XS_L38:       sprintf(info->s, "L38 :%08X", cpustate->local_regs[38]); break;
5112		case CPUINFO_STR_REGISTER + E132XS_L39:       sprintf(info->s, "L39 :%08X", cpustate->local_regs[39]); break;
5113		case CPUINFO_STR_REGISTER + E132XS_L40:       sprintf(info->s, "L40 :%08X", cpustate->local_regs[40]); break;
5114		case CPUINFO_STR_REGISTER + E132XS_L41:       sprintf(info->s, "L41 :%08X", cpustate->local_regs[41]); break;
5115		case CPUINFO_STR_REGISTER + E132XS_L42:       sprintf(info->s, "L42 :%08X", cpustate->local_regs[42]); break;
5116		case CPUINFO_STR_REGISTER + E132XS_L43:       sprintf(info->s, "L43 :%08X", cpustate->local_regs[43]); break;
5117		case CPUINFO_STR_REGISTER + E132XS_L44:       sprintf(info->s, "L44 :%08X", cpustate->local_regs[44]); break;
5118		case CPUINFO_STR_REGISTER + E132XS_L45:       sprintf(info->s, "L45 :%08X", cpustate->local_regs[45]); break;
5119		case CPUINFO_STR_REGISTER + E132XS_L46:       sprintf(info->s, "L46 :%08X", cpustate->local_regs[46]); break;
5120		case CPUINFO_STR_REGISTER + E132XS_L47:       sprintf(info->s, "L47 :%08X", cpustate->local_regs[47]); break;
5121		case CPUINFO_STR_REGISTER + E132XS_L48:       sprintf(info->s, "L48 :%08X", cpustate->local_regs[48]); break;
5122		case CPUINFO_STR_REGISTER + E132XS_L49:       sprintf(info->s, "L49 :%08X", cpustate->local_regs[49]); break;
5123		case CPUINFO_STR_REGISTER + E132XS_L50:       sprintf(info->s, "L50 :%08X", cpustate->local_regs[50]); break;
5124		case CPUINFO_STR_REGISTER + E132XS_L51:       sprintf(info->s, "L51 :%08X", cpustate->local_regs[51]); break;
5125		case CPUINFO_STR_REGISTER + E132XS_L52:       sprintf(info->s, "L52 :%08X", cpustate->local_regs[52]); break;
5126		case CPUINFO_STR_REGISTER + E132XS_L53:       sprintf(info->s, "L53 :%08X", cpustate->local_regs[53]); break;
5127		case CPUINFO_STR_REGISTER + E132XS_L54:       sprintf(info->s, "L54 :%08X", cpustate->local_regs[54]); break;
5128		case CPUINFO_STR_REGISTER + E132XS_L55:       sprintf(info->s, "L55 :%08X", cpustate->local_regs[55]); break;
5129		case CPUINFO_STR_REGISTER + E132XS_L56:       sprintf(info->s, "L56 :%08X", cpustate->local_regs[56]); break;
5130		case CPUINFO_STR_REGISTER + E132XS_L57:       sprintf(info->s, "L57 :%08X", cpustate->local_regs[57]); break;
5131		case CPUINFO_STR_REGISTER + E132XS_L58:       sprintf(info->s, "L58 :%08X", cpustate->local_regs[58]); break;
5132		case CPUINFO_STR_REGISTER + E132XS_L59:       sprintf(info->s, "L59 :%08X", cpustate->local_regs[59]); break;
5133		case CPUINFO_STR_REGISTER + E132XS_L60:       sprintf(info->s, "L60 :%08X", cpustate->local_regs[60]); break;
5134		case CPUINFO_STR_REGISTER + E132XS_L61:       sprintf(info->s, "L61 :%08X", cpustate->local_regs[61]); break;
5135		case CPUINFO_STR_REGISTER + E132XS_L62:       sprintf(info->s, "L62 :%08X", cpustate->local_regs[62]); break;
5136		case CPUINFO_STR_REGISTER + E132XS_L63:       sprintf(info->s, "L63 :%08X", cpustate->local_regs[63]); break;
5137		}
5138		}
5139
5140
5141		CPU_GET_INFO( e116t )
	4886	UINT32 hyperstone_device::execute_max_cycles() const
5142	4887	{
5143		switch (state)
5144		{
5145
5146		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 16;               break;
5147		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 16;               break;
5148
5149		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(e116_4k_iram_map); break;
5150
5151		/* --- the following bits of info are returned as pointers to data or functions --- */
5152		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(e116t);               break;
5153
5154		/* --- the following bits of info are returned as NULL-terminated strings --- */
5155		case CPUINFO_STR_NAME:                     strcpy(info->s, "E1-16T");            break;
5156
5157		default:
5158		CPU_GET_INFO_CALL(hyperstone);
5159		}
	4888	return 36;
5160	4889	}
5161	4890
5162		CPU_GET_INFO( e116xt )
5163		{
5164		switch (state)
5165		{
5166	4891
5167		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 16;               break;
5168		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 16;               break;
	4892	//-------------------------------------------------
	4893	//  execute_input_lines - return the number of
	4894	//  input/interrupt lines
	4895	//-------------------------------------------------
5169	4896
5170		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(e116_8k_iram_map); break;
5171
5172		/* --- the following bits of info are returned as pointers to data or functions --- */
5173		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(e116xt);               break;
5174
5175		/* --- the following bits of info are returned as NULL-terminated strings --- */
5176		case CPUINFO_STR_NAME:                     strcpy(info->s, "E1-16XT");            break;
5177
5178		default:
5179		CPU_GET_INFO_CALL(hyperstone);
5180		}
5181		}
5182
5183		CPU_GET_INFO( e116xs )
	4897	UINT32 hyperstone_device::execute_input_lines() const
5184	4898	{
5185		switch (state)
5186		{
5187
5188		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 16;               break;
5189		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 16;               break;
5190
5191		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(e116_16k_iram_map); break;
5192
5193		/* --- the following bits of info are returned as pointers to data or functions --- */
5194		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(e116xs);               break;
5195
5196		/* --- the following bits of info are returned as NULL-terminated strings --- */
5197		case CPUINFO_STR_NAME:                     strcpy(info->s, "E1-16XS");            break;
5198
5199		default:
5200		CPU_GET_INFO_CALL(hyperstone);
5201		}
	4899	return 8;
5202	4900	}
5203	4901
5204		CPU_GET_INFO( e116xsr )
5205		{
5206		switch (state)
5207		{
5208	4902
5209		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 16;               break;
5210		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 16;               break;
5211
5212		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(e116_16k_iram_map); break;
5213
5214		/* --- the following bits of info are returned as pointers to data or functions --- */
5215		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(e116xsr);               break;
5216
5217		/* --- the following bits of info are returned as NULL-terminated strings --- */
5218		case CPUINFO_STR_NAME:                     strcpy(info->s, "E1-16XSR");         break;
5219
5220		default:
5221		CPU_GET_INFO_CALL(hyperstone);
5222		}
5223		}
5224
5225		CPU_GET_INFO( e132n )
	4903	void hyperstone_device::execute_set_input(int inputnum, int state)
5226	4904	{
5227		switch (state)
5228		{
5229
5230		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 32;               break;
5231		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 32;               break;
5232
5233		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(e132_4k_iram_map); break;
5234
5235		/* --- the following bits of info are returned as pointers to data or functions --- */
5236		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(e132n);               break;
5237
5238		/* --- the following bits of info are returned as NULL-terminated strings --- */
5239		case CPUINFO_STR_NAME:                     strcpy(info->s, "E1-32N");            break;
5240
5241		default:
5242		CPU_GET_INFO_CALL(hyperstone);
5243		}
	4905	if (state)
	4906	ISR |= 1 << inputnum;
	4907	else
	4908	ISR &= ~(1 << inputnum);
5244	4909	}
5245	4910
5246		CPU_GET_INFO( e132t )
5247		{
5248		switch (state)
5249		{
5250	4911
5251		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 32;               break;
5252		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 32;               break;
	4912	//-------------------------------------------------
	4913	//  execute_run - execute a timeslice's worth of
	4914	//  opcodes
	4915	//-------------------------------------------------
5253	4916
5254		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(e132_4k_iram_map); break;
5255
5256		/* --- the following bits of info are returned as pointers to data or functions --- */
5257		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(e132t);               break;
5258
5259		/* --- the following bits of info are returned as NULL-terminated strings --- */
5260		case CPUINFO_STR_NAME:                     strcpy(info->s, "E1-32T");            break;
5261
5262		default:
5263		CPU_GET_INFO_CALL(hyperstone);
5264		}
5265		}
5266
5267		CPU_GET_INFO( e132xn )
	4917	void hyperstone_device::execute_run()
5268	4918	{
5269		switch (state)
5270		{
	4919	if (m_intblock < 0)
	4920	m_intblock = 0;
5271	4921
5272		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 32;               break;
5273		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 32;               break;
	4922	check_interrupts();
5274	4923
5275		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(e132_8k_iram_map); break;
5276
5277		/* --- the following bits of info are returned as pointers to data or functions --- */
5278		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(e132xn);               break;
5279
5280		/* --- the following bits of info are returned as NULL-terminated strings --- */
5281		case CPUINFO_STR_NAME:                     strcpy(info->s, "E1-32XN");            break;
5282
5283		default:
5284		CPU_GET_INFO_CALL(hyperstone);
5285		}
5286		}
5287
5288		CPU_GET_INFO( e132xt )
5289		{
5290		switch (state)
	4924	do
5291	4925	{
	4926	UINT32 oldh = SR & 0x00000020;
5292	4927
5293		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 32;               break;
5294		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 32;               break;
	4928	PPC = PC;   /* copy PC to previous PC */
	4929	debugger_instruction_hook(this, PC);
5295	4930
5296		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(e132_8k_iram_map); break;
	4931	OP = READ_OP(PC);
	4932	PC += 2;
5297	4933
5298		/* --- the following bits of info are returned as pointers to data or functions --- */
5299		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(e132xt);               break;
	4934	m_instruction_length = 1;
5300	4935
5301		/* --- the following bits of info are returned as NULL-terminated strings --- */
5302		case CPUINFO_STR_NAME:                     strcpy(info->s, "E1-32XT");            break;
	4936	/* execute opcode */
	4937	(this->*m_opcode[(OP & 0xff00) >> 8])();
5303	4938
5304		default:
5305		CPU_GET_INFO_CALL(hyperstone);
5306		}
5307		}
	4939	/* clear the H state if it was previously set */
	4940	SR ^= oldh;
5308	4941
5309		CPU_GET_INFO( e132xs )
5310		{
5311		switch (state)
5312		{
	4942	SET_ILC(m_instruction_length & 3);
5313	4943
5314		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 32;               break;
5315		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 32;               break;
	4944	if( GET_T && GET_P && m_delay.delay_cmd == NO_DELAY ) /* Not in a Delayed Branch instructions */
	4945	{
	4946	UINT32 addr = get_trap_addr(TRAPNO_TRACE_EXCEPTION);
	4947	execute_exception(addr);
	4948	}
5316	4949
5317		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(e132_16k_iram_map); break;
	4950	if (--m_intblock == 0)
	4951	check_interrupts();
5318	4952
5319		/* --- the following bits of info are returned as pointers to data or functions --- */
5320		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(e132xs);               break;
5321
5322		/* --- the following bits of info are returned as NULL-terminated strings --- */
5323		case CPUINFO_STR_NAME:                     strcpy(info->s, "E1-32XS");            break;
5324
5325		default:
5326		CPU_GET_INFO_CALL(hyperstone);
5327		}
	4953	} while( m_icount > 0 );
5328	4954	}
5329	4955
5330		CPU_GET_INFO( e132xsr )
5331		{
5332		switch (state)
5333		{
5334
5335		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 32;               break;
5336		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 32;               break;
5337
5338		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(e132_16k_iram_map); break;
5339
5340		/* --- the following bits of info are returned as pointers to data or functions --- */
5341		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(e132xsr);               break;
5342
5343		/* --- the following bits of info are returned as NULL-terminated strings --- */
5344		case CPUINFO_STR_NAME:                     strcpy(info->s, "E1-32XSR");         break;
5345
5346		default:
5347		CPU_GET_INFO_CALL(hyperstone);
5348		}
5349		}
5350
5351		CPU_GET_INFO( gms30c2116 )
5352		{
5353		switch (state)
5354		{
5355
5356		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 16;               break;
5357		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 16;               break;
5358
5359		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(e116_4k_iram_map); break;
5360
5361		/* --- the following bits of info are returned as pointers to data or functions --- */
5362		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(gms30c2116);               break;
5363
5364		/* --- the following bits of info are returned as NULL-terminated strings --- */
5365		case CPUINFO_STR_NAME:                     strcpy(info->s, "GMS30C2116");         break;
5366
5367		default:
5368		CPU_GET_INFO_CALL(hyperstone);
5369		}
5370		}
5371
5372		CPU_GET_INFO( gms30c2132 )
5373		{
5374		switch (state)
5375		{
5376
5377		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 32;               break;
5378		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 32;               break;
5379
5380		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(e132_4k_iram_map); break;
5381
5382		/* --- the following bits of info are returned as pointers to data or functions --- */
5383		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(gms30c2132);               break;
5384
5385		/* --- the following bits of info are returned as NULL-terminated strings --- */
5386		case CPUINFO_STR_NAME:                     strcpy(info->s, "GMS30C2132");         break;
5387
5388		default:
5389		CPU_GET_INFO_CALL(hyperstone);
5390		}
5391		}
5392
5393		CPU_GET_INFO( gms30c2216 )
5394		{
5395		switch (state)
5396		{
5397
5398		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 16;               break;
5399		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 16;               break;
5400
5401		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(e116_8k_iram_map); break;
5402
5403		/* --- the following bits of info are returned as pointers to data or functions --- */
5404		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(gms30c2216);               break;
5405
5406		/* --- the following bits of info are returned as NULL-terminated strings --- */
5407		case CPUINFO_STR_NAME:                     strcpy(info->s, "GMS30C2216");         break;
5408
5409		default:
5410		CPU_GET_INFO_CALL(hyperstone);
5411		}
5412		}
5413
5414		CPU_GET_INFO( gms30c2232 )
5415		{
5416		switch (state)
5417		{
5418
5419		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 32;               break;
5420		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 32;               break;
5421
5422		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(e132_8k_iram_map); break;
5423
5424		/* --- the following bits of info are returned as pointers to data or functions --- */
5425		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(gms30c2232);               break;
5426
5427		/* --- the following bits of info are returned as NULL-terminated strings --- */
5428		case CPUINFO_STR_NAME:                     strcpy(info->s, "GMS30C2232");         break;
5429
5430		default:
5431		CPU_GET_INFO_CALL(hyperstone);
5432		}
5433		}
5434
5435		DEFINE_LEGACY_CPU_DEVICE(E116T, e116t);
5436		DEFINE_LEGACY_CPU_DEVICE(E116XT, e116xt);
5437		DEFINE_LEGACY_CPU_DEVICE(E116XS, e116xs);
5438		DEFINE_LEGACY_CPU_DEVICE(E116XSR, e116xsr);
5439		DEFINE_LEGACY_CPU_DEVICE(E132N, e132n);
5440		DEFINE_LEGACY_CPU_DEVICE(E132T, e132t);
5441		DEFINE_LEGACY_CPU_DEVICE(E132XN, e132xn);
5442		DEFINE_LEGACY_CPU_DEVICE(E132XT, e132xt);
5443		DEFINE_LEGACY_CPU_DEVICE(E132XS, e132xs);
5444		DEFINE_LEGACY_CPU_DEVICE(E132XSR, e132xsr);
5445		DEFINE_LEGACY_CPU_DEVICE(GMS30C2116, gms30c2116);
5446		DEFINE_LEGACY_CPU_DEVICE(GMS30C2132, gms30c2132);
5447		DEFINE_LEGACY_CPU_DEVICE(GMS30C2216, gms30c2216);
5448		DEFINE_LEGACY_CPU_DEVICE(GMS30C2232, gms30c2232);
	4956	const device_type E116T = &device_creator<e116t_device>;
	4957	const device_type E116XT = &device_creator<e116xt_device>;
	4958	const device_type E116XS = &device_creator<e116xs_device>;
	4959	const device_type E116XSR = &device_creator<e116xsr_device>;
	4960	const device_type E132N = &device_creator<e132n_device>;
	4961	const device_type E132T = &device_creator<e132t_device>;
	4962	const device_type E132XN = &device_creator<e132xn_device>;
	4963	const device_type E132XT = &device_creator<e132xt_device>;
	4964	const device_type E132XS = &device_creator<e132xs_device>;
	4965	const device_type E132XSR = &device_creator<e132xsr_device>;
	4966	const device_type GMS30C2116 = &device_creator<gms30c2116_device>;
	4967	const device_type GMS30C2132 = &device_creator<gms30c2132_device>;
	4968	const device_type GMS30C2216 = &device_creator<gms30c2216_device>;
	4969	const device_type GMS30C2232 = &device_creator<gms30c2232_device>;

trunk/src/emu/cpu/e132xs/e132xs.h

r19873	r19874
22	22
23	23	/* Functions */
24	24
25		DECLARE_LEGACY_CPU_DEVICE(E116T, e116t);
26		DECLARE_LEGACY_CPU_DEVICE(E116XT, e116xt);
27		DECLARE_LEGACY_CPU_DEVICE(E116XS, e116xs);
28		DECLARE_LEGACY_CPU_DEVICE(E116XSR, e116xsr);
29		DECLARE_LEGACY_CPU_DEVICE(E132N, e132n);
30		DECLARE_LEGACY_CPU_DEVICE(E132T, e132t);
31		DECLARE_LEGACY_CPU_DEVICE(E132XN, e132xn);
32		DECLARE_LEGACY_CPU_DEVICE(E132XT, e132xt);
33		DECLARE_LEGACY_CPU_DEVICE(E132XS, e132xs);
34		DECLARE_LEGACY_CPU_DEVICE(E132XSR, e132xsr);
35		DECLARE_LEGACY_CPU_DEVICE(GMS30C2116, gms30c2116);
36		DECLARE_LEGACY_CPU_DEVICE(GMS30C2132, gms30c2132);
37		DECLARE_LEGACY_CPU_DEVICE(GMS30C2216, gms30c2216);
38		DECLARE_LEGACY_CPU_DEVICE(GMS30C2232, gms30c2232);
	25	/***************************************************************************
	26	COMPILE-TIME DEFINITIONS
	27	***************************************************************************/
39	28
40
41		extern unsigned dasm_hyperstone(char *buffer, unsigned pc, const UINT8 *oprom, unsigned h_flag, int private_fp);
42
43		/* Memory access */
44		/* read byte */
45		#define READ_B(H,addr)         (H)->program->read_byte((addr))
46		/* read half-word */
47		#define READ_HW(H,addr)        (H)->program->read_word((addr) & ~1)
48		/* read word */
49		#define READ_W(H,addr)         (H)->program->read_dword((addr) & ~3)
50
51		/* write byte */
52		#define WRITE_B(H,addr, data)  (H)->program->write_byte(addr, data)
53		/* write half-word */
54		#define WRITE_HW(H,addr, data) (H)->program->write_word((addr) & ~1, data)
55		/* write word */
56		#define WRITE_W(H,addr, data)  (H)->program->write_dword((addr) & ~3, data)
57
58
59		/* I/O access */
60		/* read word */
61		#define IO_READ_W(H,addr)      (H)->io->read_dword(((addr) >> 11) & 0x7ffc)
62		/* write word */
63		#define IO_WRITE_W(H,addr, data) (H)->io->write_dword(((addr) >> 11) & 0x7ffc, data)
64
65
66		#define READ_OP(H,addr)          (H)->direct->read_decrypted_word((addr), (H)->opcodexor)
67
68
69		/* Registers Number */
70	29	#define PC_REGISTER          0
71	30	#define SR_REGISTER          1
72	31	#define BCR_REGISTER      20
r19873	r19874
132	91	#define TRAPNO_RESET            62   // reserved if not mapped @ MEM3
133	92	#define TRAPNO_ERROR_ENTRY         63   // for instruction code of all ones
134	93
135		/* Traps code */
	94	/* Trap codes */
136	95	#define   TRAPLE      4
137	96	#define   TRAPGT      5
138	97	#define   TRAPLT      6
r19873	r19874
153	112	#define   E132XS_ENTRY_IRAM   3
154	113	#define   E132XS_ENTRY_MEM3   7
155	114
	115	/***************************************************************************
	116	REGISTER ENUMERATION
	117	***************************************************************************/
	118
	119	enum
	120	{
	121	E132XS_PC = 1,
	122	E132XS_SR,
	123	E132XS_FER,
	124	E132XS_G3,
	125	E132XS_G4,
	126	E132XS_G5,
	127	E132XS_G6,
	128	E132XS_G7,
	129	E132XS_G8,
	130	E132XS_G9,
	131	E132XS_G10,
	132	E132XS_G11,
	133	E132XS_G12,
	134	E132XS_G13,
	135	E132XS_G14,
	136	E132XS_G15,
	137	E132XS_G16,
	138	E132XS_G17,
	139	E132XS_SP,
	140	E132XS_UB,
	141	E132XS_BCR,
	142	E132XS_TPR,
	143	E132XS_TCR,
	144	E132XS_TR,
	145	E132XS_WCR,
	146	E132XS_ISR,
	147	E132XS_FCR,
	148	E132XS_MCR,
	149	E132XS_G28,
	150	E132XS_G29,
	151	E132XS_G30,
	152	E132XS_G31,
	153	E132XS_CL0, E132XS_CL1, E132XS_CL2, E132XS_CL3,
	154	E132XS_CL4, E132XS_CL5, E132XS_CL6, E132XS_CL7,
	155	E132XS_CL8, E132XS_CL9, E132XS_CL10,E132XS_CL11,
	156	E132XS_CL12,E132XS_CL13,E132XS_CL14,E132XS_CL15,
	157	E132XS_L0,  E132XS_L1,  E132XS_L2,  E132XS_L3,
	158	E132XS_L4,  E132XS_L5,  E132XS_L6,  E132XS_L7,
	159	E132XS_L8,  E132XS_L9,  E132XS_L10, E132XS_L11,
	160	E132XS_L12, E132XS_L13, E132XS_L14, E132XS_L15,
	161	E132XS_L16, E132XS_L17, E132XS_L18, E132XS_L19,
	162	E132XS_L20, E132XS_L21, E132XS_L22, E132XS_L23,
	163	E132XS_L24, E132XS_L25, E132XS_L26, E132XS_L27,
	164	E132XS_L28, E132XS_L29, E132XS_L30, E132XS_L31,
	165	E132XS_L32, E132XS_L33, E132XS_L34, E132XS_L35,
	166	E132XS_L36, E132XS_L37, E132XS_L38, E132XS_L39,
	167	E132XS_L40, E132XS_L41, E132XS_L42, E132XS_L43,
	168	E132XS_L44, E132XS_L45, E132XS_L46, E132XS_L47,
	169	E132XS_L48, E132XS_L49, E132XS_L50, E132XS_L51,
	170	E132XS_L52, E132XS_L53, E132XS_L54, E132XS_L55,
	171	E132XS_L56, E132XS_L57, E132XS_L58, E132XS_L59,
	172	E132XS_L60, E132XS_L61, E132XS_L62, E132XS_L63
	173	};
	174
	175	extern unsigned dasm_hyperstone(char *buffer, unsigned pc, const UINT8 *oprom, unsigned h_flag, int private_fp);
	176
	177	/* Memory access */
	178	/* read byte */
	179	#define READ_B(addr)            m_program->read_byte((addr))
	180	/* read half-word */
	181	#define READ_HW(addr)           m_program->read_word((addr) & ~1)
	182	/* read word */
	183	#define READ_W(addr)            m_program->read_dword((addr) & ~3)
	184
	185	/* write byte */
	186	#define WRITE_B(addr, data)     m_program->write_byte(addr, data)
	187	/* write half-word */
	188	#define WRITE_HW(addr, data)    m_program->write_word((addr) & ~1, data)
	189	/* write word */
	190	#define WRITE_W(addr, data)     m_program->write_dword((addr) & ~3, data)
	191
	192
	193	/* I/O access */
	194	/* read word */
	195	#define IO_READ_W(addr)         m_io->read_dword(((addr) >> 11) & 0x7ffc)
	196	/* write word */
	197	#define IO_WRITE_W(addr, data)   m_io->write_dword(((addr) >> 11) & 0x7ffc, data)
	198
	199
	200	#define READ_OP(addr)          m_direct->read_decrypted_word((addr), m_opcodexor)
	201
	202	//**************************************************************************
	203	//  TYPE DEFINITIONS
	204	//**************************************************************************
	205
	206	// ======================> hyperstone_device
	207
	208	// Used by core CPU interface
	209	class hyperstone_device : public cpu_device
	210	{
	211	public:
	212	// construction/destruction
	213	hyperstone_device(const machine_config &mconfig, const char *name, const char *tag, device_t *owner, UINT32 clock,
	214	const device_type type, UINT32 prg_data_width, UINT32 io_data_width, address_map_constructor internal_map);
	215
	216	// public interfaces
	217
	218	protected:
	219	void init(int scale_mask);
	220
	221	// device-level overrides
	222	virtual void device_start();
	223	virtual void device_reset();
	224	virtual void device_stop();
	225
	226	void make_ops();
	227
	228	// device_execute_interface overrides
	229	virtual UINT32 execute_min_cycles() const;
	230	virtual UINT32 execute_max_cycles() const;
	231	virtual UINT32 execute_input_lines() const;
	232	virtual void execute_run();
	233	virtual void execute_set_input(int inputnum, int state);
	234
	235	// device_memory_interface overrides
	236	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
	237
	238	// device_disasm_interface overrides
	239	virtual UINT32 disasm_min_opcode_bytes() const;
	240	virtual UINT32 disasm_max_opcode_bytes() const;
	241	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	242
	243	// device_state_interface overrides
	244	virtual void state_string_export(const device_state_entry &entry, astring &string);
	245
	246	// address spaces
	247	const address_space_config m_program_config;
	248	const address_space_config m_io_config;
	249	address_space *m_program;
	250	direct_read_data *m_direct;
	251	address_space *m_io;
	252
	253	/* Delay information */
	254	struct delay_info
	255	{
	256	INT32   delay_cmd;
	257	UINT32   delay_pc;
	258	};
	259
	260	// CPU registers
	261	UINT32   m_global_regs[32];
	262	UINT32   m_local_regs[64];
	263
	264	/* internal stuff */
	265	UINT32   m_ppc;         // previous pc
	266	UINT16   m_op;         // opcode
	267	UINT32   m_trap_entry;    // entry point to get trap address
	268
	269	UINT8   m_clock_scale_mask;
	270	UINT8   m_clock_scale;
	271	UINT8   m_clock_cycles_1;
	272	UINT8   m_clock_cycles_2;
	273	UINT8   m_clock_cycles_4;
	274	UINT8   m_clock_cycles_6;
	275
	276	UINT64   m_tr_base_cycles;
	277	UINT32   m_tr_base_value;
	278	UINT32   m_tr_clocks_per_tick;
	279	UINT8   m_timer_int_pending;
	280	emu_timer *m_timer;
	281
	282	delay_info m_delay;
	283
	284	UINT32 m_opcodexor;
	285
	286	INT32 m_instruction_length;
	287	INT32 m_intblock;
	288
	289	// other internal state
	290	int      m_icount;
	291
	292	typedef void (hyperstone_device::*ophandler)();
	293
	294	ophandler m_opcode[256];
	295
	296	static const ophandler s_opcodetable[256];
	297
	298	private:
	299	struct regs_decode
	300	{
	301	UINT8   src, dst;      // destination and source register code
	302	UINT32   src_value;      // current source register value
	303	UINT32   next_src_value; // current next source register value
	304	UINT32   dst_value;      // current destination register value
	305	UINT32   next_dst_value; // current next destination register value
	306	UINT8   sub_type;      // sub type opcode (for DD and X_CODE bits)
	307	union
	308	{
	309	UINT32 u;
	310	INT32  s;
	311	} extra;            // extra value such as immediate value, const, pcrel, ...
	312	UINT8   src_is_local;
	313	UINT8   dst_is_local;
	314	UINT8   same_src_dst;
	315	UINT8   same_src_dstf;
	316	UINT8   same_srcf_dst;
	317	};
	318
	319	// internal functions
	320	void check_interrupts();
	321
	322	void set_global_register(UINT8 code, UINT32 val);
	323	void set_local_register(UINT8 code, UINT32 val);
	324
	325	UINT32 get_global_register(UINT8 code);
	326
	327	UINT32 get_trap_addr(UINT8 trapno);
	328	UINT32 get_emu_code_addr(UINT8 num);
	329	void hyperstone_set_trap_entry(int which);
	330	UINT32 compute_tr();
	331	void update_timer_prescale();
	332	void adjust_timer_interrupt();
	333
	334	TIMER_CALLBACK_MEMBER(timer_callback);
	335
	336	void execute_br(struct regs_decode *decode);
	337	void execute_dbr(struct regs_decode *decode);
	338	void execute_trap(UINT32 addr);
	339	void execute_int(UINT32 addr);
	340	void execute_exception(UINT32 addr);
	341	void execute_software(struct regs_decode *decode);
	342
	343	void hyperstone_chk(struct regs_decode *decode);
	344	void hyperstone_movd(struct regs_decode *decode);
	345	void hyperstone_divu(struct regs_decode *decode);
	346	void hyperstone_divs(struct regs_decode *decode);
	347	void hyperstone_xm(struct regs_decode *decode);
	348	void hyperstone_mask(struct regs_decode *decode);
	349	void hyperstone_sum(struct regs_decode *decode);
	350	void hyperstone_sums(struct regs_decode *decode);
	351	void hyperstone_cmp(struct regs_decode *decode);
	352	void hyperstone_mov(struct regs_decode *decode);
	353	void hyperstone_add(struct regs_decode *decode);
	354	void hyperstone_adds(struct regs_decode *decode);
	355	void hyperstone_cmpb(struct regs_decode *decode);
	356	void hyperstone_andn(struct regs_decode *decode);
	357	void hyperstone_or(struct regs_decode *decode);
	358	void hyperstone_xor(struct regs_decode *decode);
	359	void hyperstone_subc(struct regs_decode *decode);
	360	void hyperstone_not(struct regs_decode *decode);
	361	void hyperstone_sub(struct regs_decode *decode);
	362	void hyperstone_subs(struct regs_decode *decode);
	363	void hyperstone_addc(struct regs_decode *decode);
	364	void hyperstone_and(struct regs_decode *decode);
	365	void hyperstone_neg(struct regs_decode *decode);
	366	void hyperstone_negs(struct regs_decode *decode);
	367	void hyperstone_cmpi(struct regs_decode *decode);
	368	void hyperstone_movi(struct regs_decode *decode);
	369	void hyperstone_addi(struct regs_decode *decode);
	370	void hyperstone_addsi(struct regs_decode *decode);
	371	void hyperstone_cmpbi(struct regs_decode *decode);
	372	void hyperstone_andni(struct regs_decode *decode);
	373	void hyperstone_ori(struct regs_decode *decode);
	374	void hyperstone_xori(struct regs_decode *decode);
	375	void hyperstone_shrdi(struct regs_decode *decode);
	376	void hyperstone_shrd(struct regs_decode *decode);
	377	void hyperstone_shr(struct regs_decode *decode);
	378	void hyperstone_shri(struct regs_decode *decode);
	379	void hyperstone_sardi(struct regs_decode *decode);
	380	void hyperstone_sard(struct regs_decode *decode);
	381	void hyperstone_sar(struct regs_decode *decode);
	382	void hyperstone_sari(struct regs_decode *decode);
	383	void hyperstone_shldi(struct regs_decode *decode);
	384	void hyperstone_shld(struct regs_decode *decode);
	385	void hyperstone_shl(struct regs_decode *decode);
	386	void hyperstone_shli(struct regs_decode *decode);
	387	void hyperstone_testlz(struct regs_decode *decode);
	388	void hyperstone_rol(struct regs_decode *decode);
	389	void hyperstone_ldxx1(struct regs_decode *decode);
	390	void hyperstone_ldxx2(struct regs_decode *decode);
	391	void hyperstone_stxx1(struct regs_decode *decode);
	392	void hyperstone_stxx2(struct regs_decode *decode);
	393	void hyperstone_mulu(struct regs_decode *decode);
	394	void hyperstone_muls(struct regs_decode *decode);
	395	void hyperstone_mul(struct regs_decode *decode);
	396	void hyperstone_set(struct regs_decode *decode);
	397
	398	void hyperstone_fadd(struct regs_decode *decode);
	399	void hyperstone_faddd(struct regs_decode *decode);
	400	void hyperstone_fsub(struct regs_decode *decode);
	401	void hyperstone_fsubd(struct regs_decode *decode);
	402	void hyperstone_fmul(struct regs_decode *decode);
	403	void hyperstone_fmuld(struct regs_decode *decode);
	404	void hyperstone_fdiv(struct regs_decode *decode);
	405	void hyperstone_fdivd(struct regs_decode *decode);
	406
	407	void hyperstone_fcmp(struct regs_decode *decode);
	408	void hyperstone_fcmpd(struct regs_decode *decode);
	409	void hyperstone_fcmpu(struct regs_decode *decode);
	410	void hyperstone_fcmpud(struct regs_decode *decode);
	411
	412	void hyperstone_fcvt(struct regs_decode *decode);
	413	void hyperstone_fcvtd(struct regs_decode *decode);
	414
	415	void hyperstone_extend(struct regs_decode *decode);
	416
	417	void hyperstone_ldwr(struct regs_decode *decode);
	418	void hyperstone_lddr(struct regs_decode *decode);
	419	void hyperstone_ldwp(struct regs_decode *decode);
	420	void hyperstone_lddp(struct regs_decode *decode);
	421
	422	void hyperstone_stwr(struct regs_decode *decode);
	423	void hyperstone_stdr(struct regs_decode *decode);
	424	void hyperstone_stwp(struct regs_decode *decode);
	425	void hyperstone_stdp(struct regs_decode *decode);
	426
	427	void hyperstone_dbv(struct regs_decode *decode);
	428	void hyperstone_dbnv(struct regs_decode *decode);
	429	void hyperstone_dbe(struct regs_decode *decode);
	430	void hyperstone_dbne(struct regs_decode *decode);
	431	void hyperstone_dbc(struct regs_decode *decode);
	432	void hyperstone_dbnc(struct regs_decode *decode);
	433	void hyperstone_dbse(struct regs_decode *decode);
	434	void hyperstone_dbht(struct regs_decode *decode);
	435	void hyperstone_dbn(struct regs_decode *decode);
	436	void hyperstone_dbnn(struct regs_decode *decode);
	437	void hyperstone_dble(struct regs_decode *decode);
	438	void hyperstone_dbgt(struct regs_decode *decode);
	439	void hyperstone_dbr(struct regs_decode *decode);
	440
	441	void hyperstone_frame(struct regs_decode *decode);
	442	void hyperstone_call(struct regs_decode *decode);
	443
	444	void hyperstone_bv(struct regs_decode *decode);
	445	void hyperstone_bnv(struct regs_decode *decode);
	446	void hyperstone_be(struct regs_decode *decode);
	447	void hyperstone_bne(struct regs_decode *decode);
	448	void hyperstone_bc(struct regs_decode *decode);
	449	void hyperstone_bnc(struct regs_decode *decode);
	450	void hyperstone_bse(struct regs_decode *decode);
	451	void hyperstone_bht(struct regs_decode *decode);
	452	void hyperstone_bn(struct regs_decode *decode);
	453	void hyperstone_bnn(struct regs_decode *decode);
	454	void hyperstone_ble(struct regs_decode *decode);
	455	void hyperstone_bgt(struct regs_decode *decode);
	456	void hyperstone_br(struct regs_decode *decode);
	457
	458	void hyperstone_trap(struct regs_decode *decode);
	459	void hyperstone_do(struct regs_decode *decode);
	460
	461	void reserved(struct regs_decode *decode);
	462
	463	void op00();   void op01();   void op02();   void op03();   void op04();   void op05();   void op06();   void op07();
	464	void op08();   void op09();   void op0a();   void op0b();   void op0c();   void op0d();   void op0e();   void op0f();
	465	void op10();   void op11();   void op12();   void op13();   void op14();   void op15();   void op16();   void op17();
	466	void op18();   void op19();   void op1a();   void op1b();   void op1c();   void op1d();   void op1e();   void op1f();
	467	void op20();   void op21();   void op22();   void op23();   void op24();   void op25();   void op26();   void op27();
	468	void op28();   void op29();   void op2a();   void op2b();   void op2c();   void op2d();   void op2e();   void op2f();
	469	void op30();   void op31();   void op32();   void op33();   void op34();   void op35();   void op36();   void op37();
	470	void op38();   void op39();   void op3a();   void op3b();   void op3c();   void op3d();   void op3e();   void op3f();
	471	void op40();   void op41();   void op42();   void op43();   void op44();   void op45();   void op46();   void op47();
	472	void op48();   void op49();   void op4a();   void op4b();   void op4c();   void op4d();   void op4e();   void op4f();
	473	void op50();   void op51();   void op52();   void op53();   void op54();   void op55();   void op56();   void op57();
	474	void op58();   void op59();   void op5a();   void op5b();   void op5c();   void op5d();   void op5e();   void op5f();
	475	void op60();   void op61();   void op62();   void op63();   void op64();   void op65();   void op66();   void op67();
	476	void op68();   void op69();   void op6a();   void op6b();   void op6c();   void op6d();   void op6e();   void op6f();
	477	void op70();   void op71();   void op72();   void op73();   void op74();   void op75();   void op76();   void op77();
	478	void op78();   void op79();   void op7a();   void op7b();   void op7c();   void op7d();   void op7e();   void op7f();
	479	void op80();   void op81();   void op82();   void op83();   void op84();   void op85();   void op86();   void op87();
	480	void op88();   void op89();   void op8a();   void op8b();   void op8c();   void op8d();   void op8e();   void op8f();
	481	void op90();   void op91();   void op92();   void op93();   void op94();   void op95();   void op96();   void op97();
	482	void op98();   void op99();   void op9a();   void op9b();   void op9c();   void op9d();   void op9e();   void op9f();
	483	void opa0();   void opa1();   void opa2();   void opa3();   void opa4();   void opa5();   void opa6();   void opa7();
	484	void opa8();   void opa9();   void opaa();   void opab();   void opac();   void opad();   void opae();   void opaf();
	485	void opb0();   void opb1();   void opb2();   void opb3();   void opb4();   void opb5();   void opb6();   void opb7();
	486	void opb8();   void opb9();   void opba();   void opbb();   void opbc();   void opbd();   void opbe();   void opbf();
	487	void opc0();   void opc1();   void opc2();   void opc3();   void opc4();   void opc5();   void opc6();   void opc7();
	488	void opc8();   void opc9();   void opca();   void opcb();   void opcc();   void opcd();   void opce();   void opcf();
	489	void opd0();   void opd1();   void opd2();   void opd3();   void opd4();   void opd5();   void opd6();   void opd7();
	490	void opd8();   void opd9();   void opda();   void opdb();   void opdc();   void opdd();   void opde();   void opdf();
	491	void ope0();   void ope1();   void ope2();   void ope3();   void ope4();   void ope5();   void ope6();   void ope7();
	492	void ope8();   void ope9();   void opea();   void opeb();   void opec();   void oped();   void opee();   void opef();
	493	void opf0();   void opf1();   void opf2();   void opf3();   void opf4();   void opf5();   void opf6();   void opf7();
	494	void opf8();   void opf9();   void opfa();   void opfb();   void opfc();   void opfd();   void opfe();   void opff();
	495
	496	void set_irq_line(int irqline, int state);
	497	};
	498
	499	// device type definition
	500	extern const device_type E116T;
	501	extern const device_type E116XT;
	502	extern const device_type E116XS;
	503	extern const device_type E116XSR;
	504	extern const device_type E132N;
	505	extern const device_type E132T;
	506	extern const device_type E132XN;
	507	extern const device_type E132XT;
	508	extern const device_type E132XS;
	509	extern const device_type E132XSR;
	510	extern const device_type GMS30C2116;
	511	extern const device_type GMS30C2132;
	512	extern const device_type GMS30C2216;
	513	extern const device_type GMS30C2232;
	514
	515
	516	// ======================> e116t_device
	517
	518	class e116t_device : public hyperstone_device
	519	{
	520	public:
	521	// construction/destruction
	522	e116t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	523
	524	protected:
	525	virtual void device_start();
	526	};
	527
	528
	529	// ======================> e116xt_device
	530
	531	class e116xt_device : public hyperstone_device
	532	{
	533	public:
	534	// construction/destruction
	535	e116xt_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	536
	537	protected:
	538	virtual void device_start();
	539	};
	540
	541
	542	// ======================> e116xs_device
	543
	544	class e116xs_device : public hyperstone_device
	545	{
	546	public:
	547	// construction/destruction
	548	e116xs_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	549
	550	protected:
	551	virtual void device_start();
	552	};
	553
	554
	555	// ======================> e116xsr_device
	556
	557	class e116xsr_device : public hyperstone_device
	558	{
	559	public:
	560	// construction/destruction
	561	e116xsr_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	562
	563	protected:
	564	virtual void device_start();
	565	};
	566
	567
	568	// ======================> e132n_device
	569
	570	class e132n_device : public hyperstone_device
	571	{
	572	public:
	573	// construction/destruction
	574	e132n_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	575
	576	protected:
	577	virtual void device_start();
	578	};
	579
	580
	581	// ======================> e132t_device
	582
	583	class e132t_device : public hyperstone_device
	584	{
	585	public:
	586	// construction/destruction
	587	e132t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	588
	589	protected:
	590	virtual void device_start();
	591	};
	592
	593
	594	// ======================> e132xn_device
	595
	596	class e132xn_device : public hyperstone_device
	597	{
	598	public:
	599	// construction/destruction
	600	e132xn_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	601
	602	protected:
	603	virtual void device_start();
	604	};
	605
	606
	607	// ======================> e132xt_device
	608
	609	class e132xt_device : public hyperstone_device
	610	{
	611	public:
	612	// construction/destruction
	613	e132xt_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	614
	615	protected:
	616	virtual void device_start();
	617	};
	618
	619
	620	// ======================> e132xs_device
	621
	622	class e132xs_device : public hyperstone_device
	623	{
	624	public:
	625	// construction/destruction
	626	e132xs_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	627
	628	protected:
	629	virtual void device_start();
	630	};
	631
	632
	633	// ======================> e132xsr_device
	634
	635	class e132xsr_device : public hyperstone_device
	636	{
	637	public:
	638	// construction/destruction
	639	e132xsr_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	640
	641	protected:
	642	virtual void device_start();
	643	};
	644
	645
	646	// ======================> gms30c2116_device
	647
	648	class gms30c2116_device : public hyperstone_device
	649	{
	650	public:
	651	// construction/destruction
	652	gms30c2116_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	653
	654	protected:
	655	virtual void device_start();
	656	};
	657
	658
	659	// ======================> gms30c2132_device
	660
	661	class gms30c2132_device : public hyperstone_device
	662	{
	663	public:
	664	// construction/destruction
	665	gms30c2132_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	666
	667	protected:
	668	virtual void device_start();
	669	};
	670
	671
	672	// ======================> gms30c2216_device
	673
	674	class gms30c2216_device : public hyperstone_device
	675	{
	676	public:
	677	// construction/destruction
	678	gms30c2216_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	679
	680	protected:
	681	virtual void device_start();
	682	};
	683
	684
	685	// ======================> gms30c2232_device
	686
	687	class gms30c2232_device : public hyperstone_device
	688	{
	689	public:
	690	// construction/destruction
	691	gms30c2232_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	692
	693	protected:
	694	virtual void device_start();
	695	};
	696
156	697	#endif /* __E132XS_H__ */

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team