trunk/src/mess/drivers/a2600.c
| r19868 | r19869 | |
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| 72 | 72 | unsigned m_modeSS_write_enabled; |
| 73 | 73 | unsigned m_modeSS_high_ram_enabled; |
| 74 | 74 | unsigned m_modeSS_diff_adjust; |
| 75 | UINT16 m_modeSS_last_address; |
| 75 | 76 | unsigned m_FVlocked; |
| 76 | 77 | UINT16 m_current_screen_height; |
| 77 | 78 | int m_FETimer; |
| r19868 | r19869 | |
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| 79 | 80 | direct_update_delegate m_FE_old_opbase_handler; |
| 80 | 81 | |
| 81 | 82 | DECLARE_DIRECT_UPDATE_MEMBER(modeF6_opbase); |
| 82 | | DECLARE_DIRECT_UPDATE_MEMBER(modeSS_opbase); |
| 83 | 83 | DECLARE_DIRECT_UPDATE_MEMBER(modeDPC_opbase_handler); |
| 84 | 84 | DECLARE_DIRECT_UPDATE_MEMBER(modeFE_opbase_handler); |
| 85 | 85 | DECLARE_READ8_MEMBER(modeF8_switch_r); |
| r19868 | r19869 | |
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| 888 | 888 | return address; |
| 889 | 889 | } |
| 890 | 890 | |
| 891 | | DIRECT_UPDATE_MEMBER(a2600_state::modeSS_opbase) |
| 892 | | { |
| 893 | | if ( address & 0x1000 ) |
| 894 | | { |
| 895 | | if ( ! direct.space().debugger_access() ) |
| 896 | | { |
| 897 | | if ( address & 0x800 ) |
| 898 | | { |
| 899 | | direct.explicit_configure(( address & 0xf800 ), ( address & 0xf800 ) | 0x7ff, 0x7ff, m_bank_base[2]); |
| 900 | | } |
| 901 | | else |
| 902 | | { |
| 903 | | direct.explicit_configure(( address & 0xf800 ), ( address & 0xf800 ) | 0x7ff, 0x7ff, m_bank_base[1]); |
| 904 | | } |
| 905 | | return ~0; |
| 906 | | } |
| 907 | | } |
| 908 | | return address; |
| 909 | | } |
| 910 | 891 | |
| 911 | 892 | READ8_MEMBER(a2600_state::modeSS_r) |
| 912 | 893 | { |
| 913 | 894 | UINT8 data = ( offset & 0x800 ) ? m_bank_base[2][offset & 0x7FF] : m_bank_base[1][offset]; |
| 914 | 895 | |
| 896 | if ( space.debugger_access() ) |
| 897 | { |
| 898 | return data; |
| 899 | } |
| 900 | |
| 915 | 901 | //logerror("%04X: read from modeSS area offset = %04X\n", machine().device("maincpu")->safe_pc(), offset); |
| 916 | 902 | /* Check for control register "write" */ |
| 917 | 903 | if ( offset == 0xFF8 ) |
| r19868 | r19869 | |
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| 964 | 950 | } |
| 965 | 951 | membank("bank1")->set_base(m_bank_base[1] ); |
| 966 | 952 | membank("bank2")->set_base(m_bank_base[2] ); |
| 953 | // Make sure we do not trigger a spurious RAM write |
| 954 | m_modeSS_byte_started -= 5; |
| 967 | 955 | } |
| 968 | 956 | else if ( offset == 0xFF9 ) |
| 969 | 957 | { |
| r19868 | r19869 | |
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| 978 | 966 | { |
| 979 | 967 | data = 0x01; |
| 980 | 968 | } |
| 969 | // Make sure we do not trigger a spurious RAM write |
| 970 | m_modeSS_byte_started -= 5; |
| 981 | 971 | } |
| 982 | 972 | else |
| 983 | 973 | { |
| 984 | 974 | /* Possible RAM write */ |
| 985 | 975 | if ( m_modeSS_write_enabled ) |
| 986 | 976 | { |
| 977 | /* Check for dummy read from same address */ |
| 978 | if ( m_modeSS_last_address == offset ) |
| 979 | { |
| 980 | m_modeSS_diff_adjust += 1; |
| 981 | } |
| 982 | |
| 987 | 983 | int diff = machine().device<cpu_device>("maincpu")->total_cycles() - m_modeSS_byte_started; |
| 988 | 984 | //logerror("%04X: offset = %04X, %d\n", machine().device("maincpu")->safe_pc(), offset, diff); |
| 989 | 985 | if ( diff - m_modeSS_diff_adjust == 5 ) |
| r19868 | r19869 | |
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| 1007 | 1003 | { |
| 1008 | 1004 | m_modeSS_byte = offset; |
| 1009 | 1005 | m_modeSS_byte_started = machine().device<cpu_device>("maincpu")->total_cycles(); |
| 1010 | | } |
| 1011 | | /* Check for dummy read from same address */ |
| 1012 | | if ( diff == 2 ) |
| 1013 | | { |
| 1014 | | m_modeSS_diff_adjust = 1; |
| 1015 | | } |
| 1016 | | else |
| 1017 | | { |
| 1018 | 1006 | m_modeSS_diff_adjust = 0; |
| 1019 | 1007 | } |
| 1008 | m_modeSS_last_address = offset; |
| 1020 | 1009 | } |
| 1021 | 1010 | else if ( offset < 0x0100 ) |
| 1022 | 1011 | { |
| 1023 | 1012 | m_modeSS_byte = offset; |
| 1024 | 1013 | m_modeSS_byte_started = machine().device<cpu_device>("maincpu")->total_cycles(); |
| 1014 | m_modeSS_last_address = offset; |
| 1015 | m_modeSS_diff_adjust = 0; |
| 1025 | 1016 | } |
| 1026 | 1017 | } |
| 1027 | | /* Because the mame core caches opcode data and doesn't perform reads like normal */ |
| 1028 | | /* we have to put in this little hack here to get Suicide Mission to work. */ |
| 1029 | | if ( offset != 0xFF8 && ( machine().device("maincpu")->safe_pc() & 0x1FFF ) == 0x1FF8 ) |
| 1030 | | { |
| 1031 | | modeSS_r( space, 0xFF8 ); |
| 1032 | | } |
| 1033 | 1018 | return data; |
| 1034 | 1019 | } |
| 1035 | 1020 | |
| r19868 | r19869 | |
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| 1481 | 1466 | m_current_reset_bank_counter = 0xFF; |
| 1482 | 1467 | m_dpc.oscillator = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(a2600_state::modeDPC_timer_callback),this)); |
| 1483 | 1468 | m_cart = CART_MEMBER; |
| 1469 | m_modeSS_last_address = 0; |
| 1484 | 1470 | } |
| 1485 | 1471 | |
| 1486 | 1472 | |
| r19868 | r19869 | |
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| 1835 | 1821 | membank("bank2")->set_base(m_bank_base[2] ); |
| 1836 | 1822 | m_modeSS_write_enabled = 0; |
| 1837 | 1823 | m_modeSS_byte_started = 0; |
| 1838 | | space.set_direct_update_handler(direct_update_delegate(FUNC(a2600_state::modeSS_opbase), this)); |
| 1839 | 1824 | /* The Supercharger has no motor control so just enable it */ |
| 1840 | 1825 | machine().device<cassette_image_device>(CASSETTE_TAG)->change_state(CASSETTE_MOTOR_ENABLED, CASSETTE_MOTOR_DISABLED ); |
| 1841 | 1826 | break; |
| r19868 | r19869 | |
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| 1949 | 1934 | static MACHINE_CONFIG_START( a2600, a2600_state ) |
| 1950 | 1935 | /* basic machine hardware */ |
| 1951 | 1936 | MCFG_CPU_ADD("maincpu", M6502, MASTER_CLOCK_NTSC / 3) /* actually M6507 */ |
| 1937 | MCFG_M6502_DISABLE_DIRECT() |
| 1952 | 1938 | MCFG_CPU_PROGRAM_MAP(a2600_mem) |
| 1953 | 1939 | |
| 1954 | 1940 | MCFG_MACHINE_START_OVERRIDE(a2600_state,a2600) |
| r19868 | r19869 | |
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| 1986 | 1972 | /* basic machine hardware */ |
| 1987 | 1973 | MCFG_CPU_ADD("maincpu", M6502, MASTER_CLOCK_PAL / 3) /* actually M6507 */ |
| 1988 | 1974 | MCFG_CPU_PROGRAM_MAP(a2600_mem) |
| 1975 | MCFG_M6502_DISABLE_DIRECT() |
| 1989 | 1976 | |
| 1990 | 1977 | MCFG_MACHINE_START_OVERRIDE(a2600_state,a2600) |
| 1991 | 1978 | |