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r19755 Sunday 23rd December, 2012 at 18:29:33 UTC by Ryan Holtz
- esrip.c: Modernized Entertainment Sciences Real Time Image Processor (ESRIP) core. [MooglyGuy]

[src/emu/cpu/esrip]	esrip.c esrip.h
[src/emu/cpu/m6809]	m6809.h
[src/mame/drivers]	esripsys.c
[src/mame/includes]	esripsys.h

trunk/src/mame/includes/esripsys.h

r19754	r19755
4	4
5	5	*************************************************************************/
6	6
	7	#ifndef _ESRIPSYS_H_
	8	#define _ESRIPSYS_H_
	9
	10	#pragma once
	11
	12	#include "cpu/esrip/esrip.h"
	13
7	14	/* TODO */
8	15	#define ESRIPSYS_PIXEL_CLOCK   (XTAL_25MHz / 2)
9	16	#define ESRIPSYS_HTOTAL         (512 + 141 + 2)
r19754	r19755
28	35	public:
29	36	esripsys_state(const machine_config &mconfig, device_type type, const char *tag)
30	37	: driver_device(mconfig, type, tag),
	38	m_videocpu(*this, "video_cpu"),
31	39	m_pal_ram(*this, "pal_ram") { }
32	40
	41	required_device<esrip_device> m_videocpu;
	42
33	43	UINT8 m_g_iodata;
34	44	UINT8 m_g_ioaddr;
35	45	UINT8 m_coin_latch;
r19754	r19755
102	112
103	113	/*----------- defined in video/esripsys.c -----------*/
104	114	int esripsys_draw(running_machine &machine, int l, int r, int fig, int attr, int addr, int col, int x_scale, int bank);
	115
	116	#endif // _ESRIPSYS_H_

trunk/src/mame/drivers/esripsys.c

r19754	r19755
95	95
96	96	READ8_MEMBER(esripsys_state::g_status_r)
97	97	{
98		int bank4 = BIT(get_rip_status(machine().device("video_cpu")), 2);
	98	int bank4 = BIT(m_videocpu->get_rip_status(), 2);
99	99	int vblank = machine().primary_screen->vblank();
100	100
101	101	return (!vblank << 7) | (bank4 << 6) | (m_f_status & 0x2f);
r19754	r19755
144	144	READ8_MEMBER(esripsys_state::f_status_r)
145	145	{
146	146	int vblank = machine().primary_screen->vblank();
147		UINT8 rip_status = get_rip_status(machine().device("video_cpu"));
	147	UINT8 rip_status = m_videocpu->get_rip_status();
148	148
149	149	rip_status = (rip_status & 0x18) | (BIT(rip_status, 6) << 1) |  BIT(rip_status, 7);
150	150
r19754	r19755
705	705
706	706	MCFG_CPU_ADD("video_cpu", ESRIP, XTAL_40MHz / 4)
707	707	MCFG_CPU_PROGRAM_MAP(video_cpu_map)
708		MCFG_CPU_CONFIG(rip_config)
	708	MCFG_CPU_ESRIP_CONFIG(rip_config)
709	709
710	710	MCFG_CPU_ADD("sound_cpu", M6809E, XTAL_8MHz)
711	711	MCFG_CPU_PROGRAM_MAP(sound_cpu_map)

trunk/src/emu/cpu/esrip/esrip.c

r19754	r19755
11	11	#include "debugger.h"
12	12	#include "esrip.h"
13	13
14		CPU_DISASSEMBLE( esrip );
15	14
16
17	15	/***************************************************************************
18	16	CONSTANTS
19	17	***************************************************************************/
r19754	r19755
25	23	MACROS
26	24	***************************************************************************/
27	25
28		#define RIP_PC      (cpustate->pc | ((cpustate->status_out & 1) << 8))
	26	#define RIP_PC      (m_pc | ((m_status_out & 1) << 8))
29	27	#define _BIT(x, n)   ((x) & (1 << (n)))
30	28	#define RISING_EDGE(old_val, new_val, bit)   (!(old_val & (1 << bit)) && (new_val & (1 << bit)))
31	29
r19754	r19755
53	51	#define   C_FLAG      (1 << 1)
54	52	#define   Z_FLAG      (1 << 0)
55	53
56		#define CLEAR_FLAGS(a)   (cpustate->new_status &= ~(a))
57		#define SET_FLAGS(a)   (cpustate->new_status |=  (a))
	54	#define CLEAR_FLAGS(a)   (m_new_status &= ~(a))
	55	#define SET_FLAGS(a)   (m_new_status |=  (a))
58	56
59	57
60	58	/***************************************************************************
61	59	STRUCTURES & TYPEDEFS
62	60	***************************************************************************/
63	61
64		struct esrip_state
65		{
66		UINT16   ram[32];
67		UINT16   acc;
68		UINT16   d_latch;
69		UINT16   i_latch;
70		UINT16   result;
71		UINT8   new_status;
72		UINT8   status;
73		UINT16   inst;
74		UINT8   immflag;
75		UINT8   ct;
76		UINT8   t;
77
78		/* Instruction latches - current and previous values */
79		UINT8   l1, pl1;
80		UINT8   l2, pl2;
81		UINT8   l3, pl3;
82		UINT8   l4, pl4;
83		UINT8   l5, pl5;
84		UINT8   l6, pl6;
85		UINT8   l7, pl7;
86
87		UINT8   pc;
88		UINT8   status_out;
89
90		UINT8   x_scale;
91		UINT8   y_scale;
92		UINT8   img_bank;
93		UINT8   line_latch;
94		UINT16   fig_latch;
95		UINT16   attr_latch;
96		UINT16   adl_latch;
97		UINT16   adr_latch;
98		UINT16   iaddr_latch;
99		UINT8   c_latch;
100
101		UINT16   fdt_cnt;
102		UINT16   ipt_cnt;
103
104		UINT8   fig;
105		UINT16   fig_cycles;
106
107		UINT8   *optable;
108
109		UINT16   *ipt_ram;
110		UINT8   *lbrm;
111
112		legacy_cpu_device *device;
113		address_space *program;
114		direct_read_data *direct;
115		int      icount;
116
117		read16_device_func   fdt_r;
118		write16_device_func   fdt_w;
119		UINT8 (*status_in)(running_machine &machine);
120		int (*draw)(running_machine &machine, int l, int r, int fig, int attr, int addr, int col, int x_scale, int bank);
121		};
122
123
124		INLINE esrip_state *get_safe_token(device_t *device)
125		{
126		assert(device != NULL);
127		assert(device->type() == ESRIP);
128		return (esrip_state *)downcast<legacy_cpu_device *>(device)->token();
129		}
130
131
132	62	/***************************************************************************
133	63	PUBLIC FUNCTIONS
134	64	***************************************************************************/
135	65
136		UINT8 get_rip_status(device_t *cpu)
	66	UINT8 esrip_device::get_rip_status()
137	67	{
138		esrip_state *cpustate = get_safe_token(cpu);
139		return cpustate->status_out;
	68	return m_status_out;
140	69	}
141	70
142	71
r19754	r19755
151	80	ROTNR, BONR, BOR1, SONR, SHFTNR, PRTNR, TONR
152	81	};
153	82
154		static void make_ops(esrip_state *cpustate)
	83	void esrip_device::make_ops()
155	84	{
156	85	int inst;
157	86
r19754	r19755
162	91	if (quad == 0)
163	92	{
164	93	if (((inst >> 5) & 0xc) == 0xc)
165		cpustate->optable[inst] = ROTR1;
	94	m_optable[inst] = ROTR1;
166	95	else
167		cpustate->optable[inst] = TOR1;
	96	m_optable[inst] = TOR1;
168	97	}
169	98	else if (quad == 1)
170	99	{
171	100	if (OPCODE < 2)
172		cpustate->optable[inst] = ROTR2;
	101	m_optable[inst] = ROTR2;
173	102	else if (OPCODE < 6)
174		cpustate->optable[inst] = ROTC;
	103	m_optable[inst] = ROTC;
175	104	else
176		cpustate->optable[inst] = ROTM;
	105	m_optable[inst] = ROTM;
177	106	}
178	107	else if (quad == 2)
179	108	{
180	109	if (OPCODE > 11)
181		cpustate->optable[inst] = BOR2;
	110	m_optable[inst] = BOR2;
182	111	else
183	112	{
184	113	int tmp = (inst >> 5) & 0xff;
185	114
186	115	if (tmp == 0x63)
187		cpustate->optable[inst] = CRCF;
	116	m_optable[inst] = CRCF;
188	117	else if (tmp == 0x69)
189		cpustate->optable[inst] = CRCR;
	118	m_optable[inst] = CRCR;
190	119	else if (tmp == 0x7a)
191		cpustate->optable[inst] = SVSTR;
	120	m_optable[inst] = SVSTR;
192	121	else
193	122	{
194	123	if ((SRC > 7) && (SRC < 12))
195		cpustate->optable[inst] = PRT;
	124	m_optable[inst] = PRT;
196	125	else if (SRC > 11)
197		cpustate->optable[inst] = SOR;
	126	m_optable[inst] = SOR;
198	127	else if (SRC < 6)
199		cpustate->optable[inst] = TOR2;
	128	m_optable[inst] = TOR2;
200	129	else
201		cpustate->optable[inst] = SHFTR;
	130	m_optable[inst] = SHFTR;
202	131	}
203	132	}
204	133	}
205	134	else
206	135	{
207	136	if (inst == 0x7140)
208		cpustate->optable[inst] = NOP;
	137	m_optable[inst] = NOP;
209	138	else
210	139	{
211	140	int x = (inst & 0xffe0);
212	141	if (x == 0x7340)
213		cpustate->optable[inst] = TEST;
	142	m_optable[inst] = TEST;
214	143	else if (x == 0x7740)
215		cpustate->optable[inst] = SETST;
	144	m_optable[inst] = SETST;
216	145	else if (x == 0x7540)
217		cpustate->optable[inst] = RSTST;
	146	m_optable[inst] = RSTST;
218	147	else
219	148	{
220	149	int op = OPCODE;
221	150	if (op == 0xc)
222	151	{
223	152	if ((inst & 0x18) == 0x18)
224		cpustate->optable[inst] = ROTNR;
	153	m_optable[inst] = ROTNR;
225	154	else
226		cpustate->optable[inst] = BONR;
	155	m_optable[inst] = BONR;
227	156	}
228	157	else if ((op & 0xc) == 0xc)
229		cpustate->optable[inst] = BOR1;
	158	m_optable[inst] = BOR1;
230	159	else
231	160	{
232	161	int src = SRC;
233	162
234	163	if ((src & 0xc) == 0xc)
235		cpustate->optable[inst] = SONR;
	164	m_optable[inst] = SONR;
236	165	else if ((src & 0x6) == 0x6)
237		cpustate->optable[inst] = SHFTNR;
	166	m_optable[inst] = SHFTNR;
238	167	else if (src & 0x8)
239		cpustate->optable[inst] = PRTNR;
	168	m_optable[inst] = PRTNR;
240	169	else
241		cpustate->optable[inst] = TONR;
	170	m_optable[inst] = TONR;
242	171	}
243	172	}
244	173	}
r19754	r19755
246	175	}
247	176	}
248	177
249		static CPU_INIT( esrip )
	178	void esrip_device::device_start()
250	179	{
251		esrip_state *cpustate = get_safe_token(device);
252		esrip_config* _config = (esrip_config*)device->static_config();
	180	esrip_config* _config = (esrip_config*)static_config();
253	181
254		memset(cpustate, 0, sizeof(*cpustate));
255
256	182	/* Register configuration structure callbacks */
257		cpustate->fdt_r = _config->fdt_r;
258		cpustate->fdt_w = _config->fdt_w;
259		cpustate->lbrm = (UINT8*)device->machine().root_device().memregion(_config->lbrm_prom)->base();
260		cpustate->status_in = _config->status_in;
261		cpustate->draw = _config->draw;
	183	m_fdt_r = _config->fdt_r;
	184	m_fdt_w = _config->fdt_w;
	185	m_lbrm = (UINT8*)machine().root_device().memregion(_config->lbrm_prom)->base();
	186	m_status_in = _config->status_in;
	187	m_draw = _config->draw;
262	188
263	189	/* Allocate image pointer table RAM */
264		cpustate->ipt_ram = auto_alloc_array(device->machine(), UINT16, IPT_RAM_SIZE/2);
	190	m_ipt_ram = auto_alloc_array(machine(), UINT16, IPT_RAM_SIZE/2);
265	191
266		cpustate->device = device;
267		cpustate->program = &device->space(AS_PROGRAM);
268		cpustate->direct = &cpustate->program->direct();
	192	m_program = &space(AS_PROGRAM);
	193	m_direct = &m_program->direct();
269	194
	195	// register our state for the debugger
	196	astring tempstr;
	197	state_add(STATE_GENPC,     "GENPC",     m_rip_pc).noshow();
	198	state_add(STATE_GENFLAGS,  "GENFLAGS",  m_status).callimport().callexport().formatstr("%8s").noshow();
	199	state_add(ESRIP_PC,        "PC:",       m_rip_pc).mask(0xffff);
	200	state_add(ESRIP_ACC,       "ACC:",      m_acc).mask(0xffff);
	201	state_add(ESRIP_DLATCH,    "DLATCH:",   m_d_latch).mask(0xff);
	202	state_add(ESRIP_ILATCH,    "ILATCH:",   m_i_latch).mask(0xffff);
	203	state_add(ESRIP_RAM00,     "RAM[00]:",  m_ram[0x00]).mask(0xffff);
	204	state_add(ESRIP_RAM01,     "RAM[01]:",  m_ram[0x01]).mask(0xffff);
	205	state_add(ESRIP_RAM02,     "RAM[02]:",  m_ram[0x02]).mask(0xffff);
	206	state_add(ESRIP_RAM03,     "RAM[03]:",  m_ram[0x03]).mask(0xffff);
	207	state_add(ESRIP_RAM04,     "RAM[04]:",  m_ram[0x04]).mask(0xffff);
	208	state_add(ESRIP_RAM05,     "RAM[05]:",  m_ram[0x05]).mask(0xffff);
	209	state_add(ESRIP_RAM06,     "RAM[06]:",  m_ram[0x06]).mask(0xffff);
	210	state_add(ESRIP_RAM07,     "RAM[07]:",  m_ram[0x07]).mask(0xffff);
	211	state_add(ESRIP_RAM08,     "RAM[08]:",  m_ram[0x08]).mask(0xffff);
	212	state_add(ESRIP_RAM09,     "RAM[09]:",  m_ram[0x09]).mask(0xffff);
	213	state_add(ESRIP_RAM0A,     "RAM[0A]:",  m_ram[0x0a]).mask(0xffff);
	214	state_add(ESRIP_RAM0B,     "RAM[0B]:",  m_ram[0x0b]).mask(0xffff);
	215	state_add(ESRIP_RAM0C,     "RAM[0C]:",  m_ram[0x0c]).mask(0xffff);
	216	state_add(ESRIP_RAM0D,     "RAM[0D]:",  m_ram[0x0d]).mask(0xffff);
	217	state_add(ESRIP_RAM0E,     "RAM[0E]:",  m_ram[0x0e]).mask(0xffff);
	218	state_add(ESRIP_RAM0F,     "RAM[0F]:",  m_ram[0x0f]).mask(0xffff);
	219	state_add(ESRIP_RAM10,     "RAM[10]:",  m_ram[0x10]).mask(0xffff);
	220	state_add(ESRIP_RAM11,     "RAM[11]:",  m_ram[0x11]).mask(0xffff);
	221	state_add(ESRIP_RAM12,     "RAM[12]:",  m_ram[0x12]).mask(0xffff);
	222	state_add(ESRIP_RAM13,     "RAM[13]:",  m_ram[0x13]).mask(0xffff);
	223	state_add(ESRIP_RAM14,     "RAM[14]:",  m_ram[0x14]).mask(0xffff);
	224	state_add(ESRIP_RAM15,     "RAM[15]:",  m_ram[0x15]).mask(0xffff);
	225	state_add(ESRIP_RAM16,     "RAM[16]:",  m_ram[0x16]).mask(0xffff);
	226	state_add(ESRIP_RAM17,     "RAM[17]:",  m_ram[0x17]).mask(0xffff);
	227	state_add(ESRIP_RAM18,     "RAM[18]:",  m_ram[0x18]).mask(0xffff);
	228	state_add(ESRIP_RAM19,     "RAM[19]:",  m_ram[0x19]).mask(0xffff);
	229	state_add(ESRIP_RAM1A,     "RAM[1A]:",  m_ram[0x1a]).mask(0xffff);
	230	state_add(ESRIP_RAM1B,     "RAM[1B]:",  m_ram[0x1b]).mask(0xffff);
	231	state_add(ESRIP_RAM1C,     "RAM[1C]:",  m_ram[0x1c]).mask(0xffff);
	232	state_add(ESRIP_RAM1D,     "RAM[1D]:",  m_ram[0x1d]).mask(0xffff);
	233	state_add(ESRIP_RAM1E,     "RAM[1E]:",  m_ram[0x1e]).mask(0xffff);
	234	state_add(ESRIP_RAM1F,     "RAM[1F]:",  m_ram[0x1f]).mask(0xffff);
	235	state_add(ESRIP_STATW,     "STAT:",     m_status_out).mask(0xffff);
	236	state_add(ESRIP_FDTC,      "FDTC:",     m_fdt_cnt).mask(0xffff);
	237	state_add(ESRIP_IPTC,      "IPTC:",     m_ipt_cnt).mask(0xffff);
	238	state_add(ESRIP_XSCALE,    "XSCL:",     m_x_scale).mask(0xffff);
	239	state_add(ESRIP_YSCALE,    "YSCL:",     m_y_scale).mask(0xffff);
	240	state_add(ESRIP_BANK,      "BANK:",     m_img_bank).mask(0xffff);
	241	state_add(ESRIP_LINE,      "LINE:",     m_line_latch).mask(0xffff);
	242	state_add(ESRIP_FIG,       "FIG:",      m_fig_latch).mask(0xffff);
	243	state_add(ESRIP_ATTR,      "ATTR:",     m_attr_latch).mask(0xffff);
	244	state_add(ESRIP_ADRL,      "ADRL:",     m_adl_latch).mask(0xffff);
	245	state_add(ESRIP_ADRR,      "ADRR:",     m_adr_latch).mask(0xffff);
	246	state_add(ESRIP_COLR,      "COLR:",     m_c_latch).mask(0xffff);
	247	state_add(ESRIP_IADDR,     "IADR:",     m_iaddr_latch).mask(0xffff);
	248
270	249	/* Create the instruction decode lookup table */
271		cpustate->optable = auto_alloc_array(device->machine(), UINT8, 65536);
272		make_ops(cpustate);
	250	make_ops();
273	251
274	252	/* Register stuff for state saving */
275		device->save_item(NAME(cpustate->acc));
276		device->save_item(NAME(cpustate->ram));
277		device->save_item(NAME(cpustate->d_latch));
278		device->save_item(NAME(cpustate->i_latch));
279		device->save_item(NAME(cpustate->result));
280		device->save_item(NAME(cpustate->new_status));
281		device->save_item(NAME(cpustate->status));
282		device->save_item(NAME(cpustate->inst));
283		device->save_item(NAME(cpustate->immflag));
284		device->save_item(NAME(cpustate->ct));
285		device->save_item(NAME(cpustate->t));
286		device->save_item(NAME(cpustate->l1));
287		device->save_item(NAME(cpustate->l2));
288		device->save_item(NAME(cpustate->l3));
289		device->save_item(NAME(cpustate->l4));
290		device->save_item(NAME(cpustate->l5));
291		device->save_item(NAME(cpustate->l6));
292		device->save_item(NAME(cpustate->l7));
293		device->save_item(NAME(cpustate->pl1));
294		device->save_item(NAME(cpustate->pl2));
295		device->save_item(NAME(cpustate->pl3));
296		device->save_item(NAME(cpustate->pl4));
297		device->save_item(NAME(cpustate->pl5));
298		device->save_item(NAME(cpustate->pl6));
299		device->save_item(NAME(cpustate->pl7));
300		device->save_item(NAME(cpustate->pc));
301		device->save_item(NAME(cpustate->status_out));
302		device->save_item(NAME(cpustate->x_scale));
303		device->save_item(NAME(cpustate->y_scale));
304		device->save_item(NAME(cpustate->img_bank));
305		device->save_item(NAME(cpustate->line_latch));
306		device->save_item(NAME(cpustate->fig_latch));
307		device->save_item(NAME(cpustate->attr_latch));
308		device->save_item(NAME(cpustate->adl_latch));
309		device->save_item(NAME(cpustate->adr_latch));
310		device->save_item(NAME(cpustate->iaddr_latch));
311		device->save_item(NAME(cpustate->c_latch));
312		device->save_item(NAME(cpustate->fdt_cnt));
313		device->save_item(NAME(cpustate->ipt_cnt));
314		device->save_item(NAME(cpustate->fig));
315		device->save_item(NAME(cpustate->fig_cycles));
316		device->save_pointer(NAME(cpustate->ipt_ram), IPT_RAM_SIZE / sizeof(UINT16));
	253	save_item(NAME(m_acc));
	254	save_item(NAME(m_ram));
	255	save_item(NAME(m_d_latch));
	256	save_item(NAME(m_i_latch));
	257	save_item(NAME(m_result));
	258	save_item(NAME(m_new_status));
	259	save_item(NAME(m_status));
	260	save_item(NAME(m_inst));
	261	save_item(NAME(m_immflag));
	262	save_item(NAME(m_ct));
	263	save_item(NAME(m_t));
	264	save_item(NAME(m_l1));
	265	save_item(NAME(m_l2));
	266	save_item(NAME(m_l3));
	267	save_item(NAME(m_l4));
	268	save_item(NAME(m_l5));
	269	save_item(NAME(m_l6));
	270	save_item(NAME(m_l7));
	271	save_item(NAME(m_pl1));
	272	save_item(NAME(m_pl2));
	273	save_item(NAME(m_pl3));
	274	save_item(NAME(m_pl4));
	275	save_item(NAME(m_pl5));
	276	save_item(NAME(m_pl6));
	277	save_item(NAME(m_pl7));
	278	save_item(NAME(m_pc));
	279	save_item(NAME(m_status_out));
	280	save_item(NAME(m_x_scale));
	281	save_item(NAME(m_y_scale));
	282	save_item(NAME(m_img_bank));
	283	save_item(NAME(m_line_latch));
	284	save_item(NAME(m_fig_latch));
	285	save_item(NAME(m_attr_latch));
	286	save_item(NAME(m_adl_latch));
	287	save_item(NAME(m_adr_latch));
	288	save_item(NAME(m_iaddr_latch));
	289	save_item(NAME(m_c_latch));
	290	save_item(NAME(m_fdt_cnt));
	291	save_item(NAME(m_ipt_cnt));
	292	save_item(NAME(m_fig));
	293	save_item(NAME(m_fig_cycles));
	294	save_pointer(NAME(m_ipt_ram), IPT_RAM_SIZE / sizeof(UINT16));
	295
	296	// set our instruction counter
	297	m_icountptr = &m_icount;
317	298	}
318	299
319	300
320		static CPU_RESET( esrip )
	301	void esrip_device::device_reset()
321	302	{
322		esrip_state *cpustate = get_safe_token(device);
	303	m_pc = 0;
323	304
324		cpustate->pc = 0;
	305	m_pl1 = 0xff;
	306	m_pl2 = 0xff;
	307	m_pl3 = 0xff;
	308	m_pl4 = 0xff;
	309	m_pl5 = 0xff;
	310	m_pl6 = 0xff;
	311	m_pl7 = 0xff;
325	312
326		cpustate->pl1 = 0xff;
327		cpustate->pl2 = 0xff;
328		cpustate->pl3 = 0xff;
329		cpustate->pl4 = 0xff;
330		cpustate->pl5 = 0xff;
331		cpustate->pl6 = 0xff;
332		cpustate->pl7 = 0xff;
	313	m_l1 = 0xff;
	314	m_l2 = 0xff;
	315	m_l3 = 0xff;
	316	m_l4 = 0xff;
	317	m_l5 = 0xff;
	318	m_l6 = 0xff;
	319	m_l7 = 0xff;
333	320
334		cpustate->l1 = 0xff;
335		cpustate->l2 = 0xff;
336		cpustate->l3 = 0xff;
337		cpustate->l4 = 0xff;
338		cpustate->l5 = 0xff;
339		cpustate->l6 = 0xff;
340		cpustate->l7 = 0xff;
	321	m_status_out = 0;
	322	m_immflag = 0;
341	323
342		cpustate->status_out = 0;
343		cpustate->immflag = 0;
	324	m_rip_pc = (m_pc | ((m_status_out & 1) << 8));
344	325	}
345	326
	327	void esrip_device::device_stop()
	328	{
346	329
347		static CPU_EXIT( esrip )
	330	}
	331
	332
	333	//-------------------------------------------------
	334	//  memory_space_config - return the configuration
	335	//  of the specified address space, or NULL if
	336	//  the space doesn't exist
	337	//-------------------------------------------------
	338
	339	const address_space_config *esrip_device::memory_space_config(address_spacenum spacenum) const
348	340	{
	341	if (spacenum == AS_PROGRAM)
	342	{
	343	return &m_program_config;
	344	}
	345	return NULL;
	346	}
349	347
	348
	349	//-------------------------------------------------
	350	//  state_string_export - export state as a string
	351	//  for the debugger
	352	//-------------------------------------------------
	353
	354	void esrip_device::state_string_export(const device_state_entry &entry, astring &string)
	355	{
	356	switch (entry.index())
	357	{
	358	case STATE_GENFLAGS:
	359	string.printf("%c%c%c%c%c%c%c%c%c",
	360	(m_status & 0x80) ? '3' : '.',
	361	(m_status & 0x40) ? '2' : '.',
	362	(m_status & 0x20) ? '1' : '.',
	363	(m_status & 0x10) ? 'L' : '.',
	364	(m_status & 0x08) ? 'V' : '.',
	365	(m_status & 0x04) ? 'N' : '.',
	366	(m_status & 0x02) ? 'C' : '.',
	367	(m_status & 0x01) ? 'Z' : '.',
	368	get_hblank() ? 'H' : '.');
	369	break;
	370	}
350	371	}
351	372
352	373
	374	//-------------------------------------------------
	375	//  disasm_min_opcode_bytes - return the length
	376	//  of the shortest instruction, in bytes
	377	//-------------------------------------------------
	378
	379	UINT32 esrip_device::disasm_min_opcode_bytes() const
	380	{
	381	return 8;
	382	}
	383
	384
	385	//-------------------------------------------------
	386	//  disasm_max_opcode_bytes - return the length
	387	//  of the longest instruction, in bytes
	388	//-------------------------------------------------
	389
	390	UINT32 esrip_device::disasm_max_opcode_bytes() const
	391	{
	392	return 8;
	393	}
	394
	395
	396	//-------------------------------------------------
	397	//  disasm_disassemble - call the disassembly
	398	//  helper function
	399	//-------------------------------------------------
	400
	401	offs_t esrip_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
	402	{
	403	extern CPU_DISASSEMBLE( esrip );
	404	return disassemble(buffer, pc, oprom, opram, 0);
	405	}
	406
	407
353	408	/***************************************************************************
354	409	PRIVATE FUNCTIONS
355	410	***************************************************************************/
356	411
357		static int get_hblank(running_machine &machine)
	412	int esrip_device::get_hblank()
358	413	{
359		return machine.primary_screen->hblank();
	414	return machine().primary_screen->hblank();
360	415	}
361	416
362	417	/* Return the state of the LBRM line (Y-scaling related) */
363		static int get_lbrm(esrip_state *cpustate)
	418	int esrip_device::get_lbrm()
364	419	{
365		int addr = ((cpustate->y_scale & 0x3f) << 3) | ((cpustate->line_latch >> 3) & 7);
366		int sel = (cpustate->line_latch & 7);
	420	int addr = ((m_y_scale & 0x3f) << 3) | ((m_line_latch >> 3) & 7);
	421	int sel = (m_line_latch & 7);
367	422
368		UINT8 val = cpustate->lbrm[addr];
	423	UINT8 val = m_lbrm[addr];
369	424
370	425	return (val >> sel) & 1;
371	426	}
372	427
373		INLINE int check_jmp(esrip_state *cpustate, UINT8 jmp_ctrl)
	428	int esrip_device::check_jmp(UINT8 jmp_ctrl)
374	429	{
375	430	int ret = 0;
376	431
r19754	r19755
378	433	{
379	434	switch (jmp_ctrl & 7)
380	435	{
381		/* CT */      case 0: ret = cpustate->ct;         break;
382		/* T1 */      case 4: ret = BIT(cpustate->t, 0);  break;
383		/* T2 */      case 2: ret = BIT(cpustate->t, 1);  break;
384		/* T3 */      case 6: ret = BIT(cpustate->t, 2);  break;
385		/* T4 */      case 1: ret = BIT(cpustate->t, 3);  break;
386		/* /LBRM */   case 5: ret = !get_lbrm(cpustate);  break;
387		/* /HBLANK */ case 3: ret = !get_hblank(cpustate->device->machine()); break;
	436	/* CT */      case 0: ret = m_ct;         break;
	437	/* T1 */      case 4: ret = BIT(m_t, 0);  break;
	438	/* T2 */      case 2: ret = BIT(m_t, 1);  break;
	439	/* T3 */      case 6: ret = BIT(m_t, 2);  break;
	440	/* T4 */      case 1: ret = BIT(m_t, 3);  break;
	441	/* /LBRM */   case 5: ret = !get_lbrm();  break;
	442	/* /HBLANK */ case 3: ret = !get_hblank(); break;
388	443	/* JMP */     case 7: ret = 0;                    break;
389	444	}
390	445
r19754	r19755
394	449	{
395	450	switch (jmp_ctrl & 7)
396	451	{
397		/* CT */      case 0: ret = cpustate->ct;        break;
398		/* T1 */      case 4: ret = BIT(cpustate->t, 0); break;
399		/* T2 */      case 2: ret = BIT(cpustate->t, 1); break;
400		/* T3 */      case 6: ret = BIT(cpustate->t, 2); break;
401		/* T4 */      case 1: ret = BIT(cpustate->t, 3); break;
402		/* /LBRM */   case 5: ret = !get_lbrm(cpustate); break;
403		/* /FIG */    case 3: ret = !cpustate->fig;      break;
	452	/* CT */      case 0: ret = m_ct;        break;
	453	/* T1 */      case 4: ret = BIT(m_t, 0); break;
	454	/* T2 */      case 2: ret = BIT(m_t, 1); break;
	455	/* T3 */      case 6: ret = BIT(m_t, 2); break;
	456	/* T4 */      case 1: ret = BIT(m_t, 3); break;
	457	/* /LBRM */   case 5: ret = !get_lbrm(); break;
	458	/* /FIG */    case 3: ret = !m_fig;      break;
404	459	/* JMP */     case 7: ret = 1;                   break;
405	460	}
406	461	}
407	462	else
	463	{
408	464	assert(!"RIP: Invalid jump control");
	465	}
409	466
410	467	return ret;
411	468	}
412	469
413	470
414		INLINE void calc_z_flag(esrip_state *cpustate, UINT16 res)
	471	void esrip_device::calc_z_flag(UINT16 res)
415	472	{
416		cpustate->new_status &= ~Z_FLAG;
417		cpustate->new_status |= (res == 0);
	473	m_new_status &= ~Z_FLAG;
	474	m_new_status |= (res == 0);
418	475	}
419	476
420		INLINE void calc_c_flag_add(esrip_state *cpustate, UINT16 a, UINT16 b)
	477	void esrip_device::calc_c_flag_add(UINT16 a, UINT16 b)
421	478	{
422		cpustate->new_status &= ~C_FLAG;
423		cpustate->new_status |= ((UINT16)(b) > (UINT16)(~(a))) ? 2 : 0;
	479	m_new_status &= ~C_FLAG;
	480	m_new_status |= ((UINT16)(b) > (UINT16)(~(a))) ? 2 : 0;
424	481	}
425	482
426		INLINE void calc_c_flag_sub(esrip_state *cpustate, UINT16 a, UINT16 b)
	483	void esrip_device::calc_c_flag_sub(UINT16 a, UINT16 b)
427	484	{
428		cpustate->new_status &= ~C_FLAG;
429		cpustate->new_status |= ((UINT16)(b) <= (UINT16)(a)) ? 2 : 0;
	485	m_new_status &= ~C_FLAG;
	486	m_new_status |= ((UINT16)(b) <= (UINT16)(a)) ? 2 : 0;
430	487	}
431	488
432		INLINE void calc_n_flag(esrip_state *cpustate, UINT16 res)
	489	void esrip_device::calc_n_flag(UINT16 res)
433	490	{
434		cpustate->new_status &= ~N_FLAG;
435		cpustate->new_status |= (res & 0x8000) ? 4 : 0;
	491	m_new_status &= ~N_FLAG;
	492	m_new_status |= (res & 0x8000) ? 4 : 0;
436	493	}
437	494
438		INLINE void calc_v_flag_add(esrip_state *cpustate, UINT16 a, UINT16 b, UINT32 r)
	495	void esrip_device::calc_v_flag_add(UINT16 a, UINT16 b, UINT32 r)
439	496	{
440		cpustate->new_status &= ~V_FLAG;
441		cpustate->new_status |= ((a ^ r) & (b ^ r) & 0x8000) ? 8 : 0;
	497	m_new_status &= ~V_FLAG;
	498	m_new_status |= ((a ^ r) & (b ^ r) & 0x8000) ? 8 : 0;
442	499	}
443	500
444		INLINE void calc_v_flag_sub(esrip_state *cpustate, UINT16 a, UINT16 b, UINT32 r)
	501	void esrip_device::calc_v_flag_sub(UINT16 a, UINT16 b, UINT32 r)
445	502	{
446		cpustate->new_status &= ~V_FLAG;
447		cpustate->new_status |= ((a ^ b) & (r ^ b) & 0x8000) ? 8 : 0;
	503	m_new_status &= ~V_FLAG;
	504	m_new_status |= ((a ^ b) & (r ^ b) & 0x8000) ? 8 : 0;
448	505	}
449	506
450	507
r19754	r19755
465	522	*  Single operand
466	523	*
467	524	*************************************/
	525
468	526	enum
469	527	{
470	528	MOVE = 0xc,
r19754	r19755
487	545	SORR  = 0xb
488	546	};
489	547
490		static UINT16 sor_op(esrip_state *cpustate, UINT16 r, UINT16 opcode)
	548	UINT16 esrip_device::sor_op(UINT16 r, UINT16 opcode)
491	549	{
492	550	UINT32 res = 0;
493	551
r19754	r19755
497	555	{
498	556	res = r;
499	557	CLEAR_FLAGS(V_FLAG | C_FLAG);
500		calc_n_flag(cpustate, res);
501		calc_z_flag(cpustate, res);
	558	calc_n_flag(res);
	559	calc_z_flag(res);
502	560	break;
503	561	}
504	562	case COMP:
505	563	{
506	564	res = r ^ 0xffff;
507	565	CLEAR_FLAGS(V_FLAG | C_FLAG);
508		calc_n_flag(cpustate, res);
509		calc_z_flag(cpustate, res);
	566	calc_n_flag(res);
	567	calc_z_flag(res);
510	568	break;
511	569	}
512	570	case INC:
513	571	{
514	572	res = r + 1;
515		calc_v_flag_add(cpustate, r, 1, res);
516		calc_n_flag(cpustate, res);
517		calc_c_flag_add(cpustate, r, 1);
518		calc_z_flag(cpustate, res);
	573	calc_v_flag_add(r, 1, res);
	574	calc_n_flag(res);
	575	calc_c_flag_add(r, 1);
	576	calc_z_flag(res);
519	577	break;
520	578	}
521	579	case NEG:
522	580	{
523	581	res = (r ^ 0xffff) + 1;
524		calc_v_flag_sub(cpustate, 0, r, res);
525		calc_n_flag(cpustate, res);
526		calc_c_flag_sub(cpustate, 0, r);
527		calc_z_flag(cpustate, res);
	582	calc_v_flag_sub(0, r, res);
	583	calc_n_flag(res);
	584	calc_c_flag_sub(0, r);
	585	calc_z_flag(res);
528	586	break;
529	587	}
530	588	default: assert(0);
r19754	r19755
533	591	return res & 0xffff;
534	592	}
535	593
536		static void sor(esrip_state *cpustate, UINT16 inst)
	594	void esrip_device::sor(UINT16 inst)
537	595	{
538	596	UINT16   r = 0;
539	597	UINT16   dst = 0;
r19754	r19755
547	605
548	606	switch ((inst >> 5) & 0xf)
549	607	{
550		case SORA: r = cpustate->ram[RAM_ADDR];      dst = ACC;      break;
551		case SORY: r = cpustate->ram[RAM_ADDR];      dst = Y_BUS;   break;
552		case SORS: r = cpustate->ram[RAM_ADDR];      dst = STATUS;   break;
553		case SOAR: r = cpustate->acc;            dst = RAM;      break;
554		case SODR: r = cpustate->d_latch;         dst = RAM;      break;
	608	case SORA: r = m_ram[RAM_ADDR];      dst = ACC;      break;
	609	case SORY: r = m_ram[RAM_ADDR];      dst = Y_BUS;   break;
	610	case SORS: r = m_ram[RAM_ADDR];      dst = STATUS;   break;
	611	case SOAR: r = m_acc;            dst = RAM;      break;
	612	case SODR: r = m_d_latch;         dst = RAM;      break;
555	613	case SOIR:
556	614	{
557		if (cpustate->immflag == 0)      // Macrofiy this?
	615	if (m_immflag == 0)      // Macrofiy this?
558	616	{
559		cpustate->i_latch = inst;
560		cpustate->immflag = 1;
	617	m_i_latch = inst;
	618	m_immflag = 1;
561	619	return;
562	620	}
563	621	else
564	622	{
565		r = cpustate->inst;
	623	r = m_inst;
566	624	dst = RAM;
567		cpustate->immflag = 0;
	625	m_immflag = 0;
568	626	}
569	627	break;
570	628	}
571	629	case SOZR: r = 0;                  dst = RAM;      break;
572		case SORR: r = cpustate->ram[RAM_ADDR];   dst = RAM;      break;
	630	case SORR: r = m_ram[RAM_ADDR];   dst = RAM;      break;
573	631	default: UNHANDLED;
574	632	}
575	633
576	634	/* Operation */
577		res = sor_op(cpustate, r, (inst >> 9) & 0xf);
	635	res = sor_op(r, (inst >> 9) & 0xf);
578	636
579	637	switch (dst)
580	638	{
581	639	case Y_BUS: break;
582		case ACC: cpustate->acc = res; break;
583		case RAM: cpustate->ram[RAM_ADDR] = res; break;
	640	case ACC: m_acc = res; break;
	641	case RAM: m_ram[RAM_ADDR] = res; break;
584	642	default: UNHANDLED;
585	643	}
586	644
587		cpustate->result = res;
	645	m_result = res;
588	646	}
589	647
590	648	enum
r19754	r19755
605	663	NRAS = 5,
606	664	};
607	665
608		static void sonr(esrip_state *cpustate, UINT16 inst)
	666	void esrip_device::sonr(UINT16 inst)
609	667	{
610	668	UINT16   r = 0;
611	669	UINT16   res = 0;
612	670
613	671	switch ((inst >> 5) & 0xf)
614	672	{
615		case SOA:   r = cpustate->acc;      break;
616		case SOD:   r = cpustate->d_latch;   break;
	673	case SOA:   r = m_acc;      break;
	674	case SOD:   r = m_d_latch;   break;
617	675	case SOI:
618	676	{
619		if (cpustate->immflag == 0)
	677	if (m_immflag == 0)
620	678	{
621		cpustate->i_latch = inst;
622		cpustate->immflag = 1;
	679	m_i_latch = inst;
	680	m_immflag = 1;
623	681	return;
624	682	}
625	683	else
626	684	{
627		r = cpustate->inst;
628		cpustate->immflag = 0;
	685	r = m_inst;
	686	m_immflag = 0;
629	687	}
630	688	break;
631	689	}
r19754	r19755
634	692	}
635	693
636	694	/* Operation */
637		res = sor_op(cpustate, r, (inst >> 9) & 0xf);
	695	res = sor_op(r, (inst >> 9) & 0xf);
638	696
639	697	/* Destination */
640	698	switch (inst & 0x1f)
641	699	{
642	700	case NRY: break;
643		case NRA: cpustate->acc = res; break;
	701	case NRA: m_acc = res; break;
644	702	default: UNHANDLED;
645	703	}
646	704
647		cpustate->result = res;
	705	m_result = res;
648	706	}
649	707
650	708	/*************************************
r19754	r19755
669	727	EXNOR = 0xb
670	728	};
671	729
672		static UINT16 tor_op(esrip_state *cpustate, UINT16 r, UINT16 s, int opcode)
	730	UINT16 esrip_device::tor_op(UINT16 r, UINT16 s, int opcode)
673	731	{
674	732	UINT32 res = 0;
675	733
r19754	r19755
678	736	case SUBR:
679	737	{
680	738	res = s - r;
681		calc_v_flag_sub(cpustate, s, r, res);
682		calc_n_flag(cpustate, res);
683		calc_c_flag_sub(cpustate, s, r);
684		calc_z_flag(cpustate, res);
	739	calc_v_flag_sub(s, r, res);
	740	calc_n_flag(res);
	741	calc_c_flag_sub(s, r);
	742	calc_z_flag(res);
685	743	break;
686	744	}
687	745	case SUBRC: assert(0); break;
688	746	case SUBS:
689	747	{
690	748	res = r - s;
691		calc_v_flag_sub(cpustate, r, s, res);
692		calc_n_flag(cpustate, res);
693		calc_c_flag_sub(cpustate, r, s);
694		calc_z_flag(cpustate, res);
	749	calc_v_flag_sub(r, s, res);
	750	calc_n_flag(res);
	751	calc_c_flag_sub(r, s);
	752	calc_z_flag(res);
695	753	break;
696	754	}
697	755	case SUBSC: assert(0); break;
698	756	case ADD:
699	757	{
700	758	res = r + s;
701		calc_v_flag_add(cpustate, r, s, res);
702		calc_n_flag(cpustate, res);
703		calc_c_flag_add(cpustate, r, s);
704		calc_z_flag(cpustate, res);
	759	calc_v_flag_add(r, s, res);
	760	calc_n_flag(res);
	761	calc_c_flag_add(r, s);
	762	calc_z_flag(res);
705	763	break;
706	764	}
707	765	case ADDC:
708	766	{
709	767	// TODO TODO CHECK ME ETC
710		res = r + s + ((cpustate->status >> 1) & 1);
711		calc_v_flag_add(cpustate, r, s, res);
712		calc_n_flag(cpustate, res);
713		calc_c_flag_add(cpustate, r, s);
714		calc_z_flag(cpustate, res);
	768	res = r + s + ((m_status >> 1) & 1);
	769	calc_v_flag_add(r, s, res);
	770	calc_n_flag(res);
	771	calc_c_flag_add(r, s);
	772	calc_z_flag(res);
715	773	break;
716	774	}
717	775	case AND:
718	776	{
719	777	res = r & s;
720	778	CLEAR_FLAGS(V_FLAG | C_FLAG);
721		calc_n_flag(cpustate, res);
722		calc_z_flag(cpustate, res);
	779	calc_n_flag(res);
	780	calc_z_flag(res);
723	781	break;
724	782	}
725	783	case NAND:
726	784	{
727	785	res = (r & s) ^ 0xffff;
728	786	CLEAR_FLAGS(V_FLAG | C_FLAG);
729		calc_n_flag(cpustate, res);
730		calc_z_flag(cpustate, res);
	787	calc_n_flag(res);
	788	calc_z_flag(res);
731	789	break;
732	790	}
733	791	case EXOR:
734	792	{
735	793	res = r ^ s;
736	794	CLEAR_FLAGS(V_FLAG | C_FLAG);
737		calc_n_flag(cpustate, res);
738		calc_z_flag(cpustate, res);
	795	calc_n_flag(res);
	796	calc_z_flag(res);
739	797	break;
740	798	}
741	799	case NOR:
742	800	{
743	801	res = (r | s) ^ 0xffff;
744	802	CLEAR_FLAGS(V_FLAG | C_FLAG);
745		calc_n_flag(cpustate, res);
746		calc_z_flag(cpustate, res);
	803	calc_n_flag(res);
	804	calc_z_flag(res);
747	805	break;
748	806	}
749	807	case OR:
750	808	{
751	809	res = r | s;
752	810	CLEAR_FLAGS(V_FLAG | C_FLAG);
753		calc_n_flag(cpustate, res);
754		calc_z_flag(cpustate, res);
	811	calc_n_flag(res);
	812	calc_z_flag(res);
755	813	break;
756	814	}
757	815	case EXNOR:
758	816	{
759	817	res = (r ^ s) ^ 0xffff;
760	818	CLEAR_FLAGS(V_FLAG | N_FLAG | C_FLAG);
761		calc_z_flag(cpustate, res);
	819	calc_z_flag(res);
762	820	break;
763	821	}
764	822	default: assert(0);
r19754	r19755
767	825	return res & 0xffff;
768	826	}
769	827
770		static void tor1(esrip_state *cpustate, UINT16 inst)
	828	void esrip_device::tor1(UINT16 inst)
771	829	{
772	830	UINT16 r = 0;
773	831	UINT16 s = 0;
r19754	r19755
789	847
790	848	switch (SRC)
791	849	{
792		case TORAA: r = cpustate->ram[RAM_ADDR];   s = cpustate->acc;   dst = ACC;   break;
	850	case TORAA: r = m_ram[RAM_ADDR];   s = m_acc;   dst = ACC;   break;
793	851	case TORIA:
794	852	{
795		if (cpustate->immflag == 0)
	853	if (m_immflag == 0)
796	854	{
797		cpustate->i_latch = inst;
798		cpustate->immflag = 1;
	855	m_i_latch = inst;
	856	m_immflag = 1;
799	857	return;
800	858	}
801	859	else
802	860	{
803		r = cpustate->ram[RAM_ADDR];
804		s = cpustate->inst;
	861	r = m_ram[RAM_ADDR];
	862	s = m_inst;
805	863	dst = ACC;
806		cpustate->immflag = 0;
	864	m_immflag = 0;
807	865	}
808	866	break;
809	867	}
810		case TODRA: r = cpustate->d_latch;      s = cpustate->ram[RAM_ADDR];   dst = ACC;   break;
811		case TORAY: r = cpustate->ram[RAM_ADDR];   s = cpustate->acc;         dst = Y_BUS;break;
	868	case TODRA: r = m_d_latch;      s = m_ram[RAM_ADDR];   dst = ACC;   break;
	869	case TORAY: r = m_ram[RAM_ADDR];   s = m_acc;         dst = Y_BUS;break;
812	870	case TORIY:
813	871	{
814		if (cpustate->immflag == 0)
	872	if (m_immflag == 0)
815	873	{
816		cpustate->i_latch = inst;
817		cpustate->immflag = 1;
	874	m_i_latch = inst;
	875	m_immflag = 1;
818	876	return;
819	877	}
820	878	else
821	879	{
822		r = cpustate->ram[RAM_ADDR];
823		s = cpustate->inst;
	880	r = m_ram[RAM_ADDR];
	881	s = m_inst;
824	882	dst = Y_BUS;
825		cpustate->immflag = 0;
	883	m_immflag = 0;
826	884	}
827	885	break;
828	886	}
829		case TODRY: r = cpustate->d_latch;      s = cpustate->ram[RAM_ADDR];   dst = Y_BUS;break;
830		case TORAR: r = cpustate->ram[RAM_ADDR];   s = cpustate->acc;         dst = RAM;   break;
	887	case TODRY: r = m_d_latch;      s = m_ram[RAM_ADDR];   dst = Y_BUS;break;
	888	case TORAR: r = m_ram[RAM_ADDR];   s = m_acc;         dst = RAM;   break;
831	889	case TORIR:
832	890	{
833		if (cpustate->immflag == 0)
	891	if (m_immflag == 0)
834	892	{
835		cpustate->i_latch = inst;
836		cpustate->immflag = 1;
	893	m_i_latch = inst;
	894	m_immflag = 1;
837	895	return;
838	896	}
839	897	else
840	898	{
841		r = cpustate->ram[RAM_ADDR];
842		s = cpustate->inst;
	899	r = m_ram[RAM_ADDR];
	900	s = m_inst;
843	901	dst = RAM;
844		cpustate->immflag = 0;
	902	m_immflag = 0;
845	903	}
846	904	break;
847	905	}
848		case TODRR: r = cpustate->d_latch;      s = cpustate->ram[RAM_ADDR];   dst = RAM;   break;
	906	case TODRR: r = m_d_latch;      s = m_ram[RAM_ADDR];   dst = RAM;   break;
849	907	default: INVALID;
850	908	}
851	909
852	910	/* Operation */
853		res = tor_op(cpustate, r, s, (inst >> 5) & 0xf);
	911	res = tor_op(r, s, (inst >> 5) & 0xf);
854	912
855	913	/* Destination */
856	914	switch (dst)
857	915	{
858		case ACC:   cpustate->acc = res; break;
	916	case ACC:   m_acc = res; break;
859	917	case Y_BUS:   break;
860		case RAM:   cpustate->ram[RAM_ADDR] = res; break;
	918	case RAM:   m_ram[RAM_ADDR] = res; break;
861	919	default:   INVALID;
862	920	}
863	921
864		cpustate->result = res;
	922	m_result = res;
865	923	}
866	924
867		static void tor2(esrip_state *cpustate, UINT16 inst)
	925	void esrip_device::tor2(UINT16 inst)
868	926	{
869	927	UINT16 r = 0;
870	928	UINT16 s = 0;
r19754	r19755
879	937
880	938	switch (SRC)
881	939	{
882		case TODAR: r = cpustate->d_latch;   s = cpustate->acc;   break;
	940	case TODAR: r = m_d_latch;   s = m_acc;   break;
883	941	case TOAIR:
884	942	{
885		if (cpustate->immflag == 0)
	943	if (m_immflag == 0)
886	944	{
887		cpustate->i_latch = inst;
888		cpustate->immflag = 1;
	945	m_i_latch = inst;
	946	m_immflag = 1;
889	947	return;
890	948	}
891	949	else
892	950	{
893		r = cpustate->acc;
894		s = cpustate->inst;
895		cpustate->immflag = 0;
	951	r = m_acc;
	952	s = m_inst;
	953	m_immflag = 0;
896	954	}
897	955	break;
898	956	}
899	957	case TODIR:
900	958	{
901		if (cpustate->immflag == 0)
	959	if (m_immflag == 0)
902	960	{
903		cpustate->i_latch = inst;
904		cpustate->immflag = 1;
	961	m_i_latch = inst;
	962	m_immflag = 1;
905	963	return;
906	964	}
907	965	else
908	966	{
909		r = cpustate->d_latch;
910		s = cpustate->inst;
911		cpustate->immflag = 0;
	967	r = m_d_latch;
	968	s = m_inst;
	969	m_immflag = 0;
912	970	}
913	971	break;
914	972	}
r19754	r19755
916	974	}
917	975
918	976	/* Operation */
919		res = tor_op(cpustate, r, s, (inst >> 5) & 0xf);
	977	res = tor_op(r, s, (inst >> 5) & 0xf);
920	978
921	979	/* Destination is always RAM */
922		cpustate->ram[RAM_ADDR] = res;
	980	m_ram[RAM_ADDR] = res;
923	981
924		cpustate->result = res;
	982	m_result = res;
925	983	}
926	984
927		static void tonr(esrip_state *cpustate, UINT16 inst)
	985	void esrip_device::tonr(UINT16 inst)
928	986	{
929	987	enum
930	988	{
r19754	r19755
949	1007	{
950	1008	case TODA:
951	1009	{
952		r = cpustate->d_latch;
953		s = cpustate->acc;
	1010	r = m_d_latch;
	1011	s = m_acc;
954	1012	break;
955	1013	}
956	1014	case TOAI:
r19754	r19755
959	1017	}
960	1018	case TODI:
961	1019	{
962		if (cpustate->immflag == 0)
	1020	if (m_immflag == 0)
963	1021	{
964		cpustate->i_latch = inst;
965		cpustate->immflag = 1;
	1022	m_i_latch = inst;
	1023	m_immflag = 1;
966	1024	return;
967	1025	}
968	1026	else
969	1027	{
970		r = cpustate->d_latch;
971		s = cpustate->inst;
972		cpustate->immflag = 0;
	1028	r = m_d_latch;
	1029	s = m_inst;
	1030	m_immflag = 0;
973	1031	}
974	1032	break;
975	1033	}
r19754	r19755
977	1035	}
978	1036
979	1037	/* Operation */
980		res = tor_op(cpustate, r, s, (inst >> 5) & 0xf);
	1038	res = tor_op(r, s, (inst >> 5) & 0xf);
981	1039
982	1040	/* Destination */
983	1041	switch (DST)
r19754	r19755
985	1043	case NRY:
986	1044	break;
987	1045	case NRA:
988		cpustate->acc = res;
	1046	m_acc = res;
989	1047	break;
990	1048	case NRS:
991	1049	UNHANDLED;
r19754	r19755
996	1054	default:
997	1055	INVALID;
998	1056	}
999		cpustate->result = res;
	1057	m_result = res;
1000	1058	}
1001	1059
1002	1060	/*************************************
r19754	r19755
1005	1063	*
1006	1064	*************************************/
1007	1065
1008		static void bonr(esrip_state *cpustate, UINT16 inst)
	1066	void esrip_device::bonr(UINT16 inst)
1009	1067	{
1010	1068	enum
1011	1069	{
r19754	r19755
1031	1089	{
1032	1090	case TSTNA:
1033	1091	{
1034		res = cpustate->acc & (1 << N);
	1092	res = m_acc & (1 << N);
1035	1093	CLEAR_FLAGS(V_FLAG | C_FLAG);
1036		calc_n_flag(cpustate, res);
1037		calc_z_flag(cpustate, res);
	1094	calc_n_flag(res);
	1095	calc_z_flag(res);
1038	1096	break;
1039	1097	}
1040	1098	case RSTNA:
1041	1099	{
1042		res = cpustate->acc & ~(1 << N);
	1100	res = m_acc & ~(1 << N);
1043	1101	CLEAR_FLAGS(V_FLAG | C_FLAG);
1044		calc_n_flag(cpustate, res);
1045		calc_z_flag(cpustate, res);
1046		cpustate->acc = res;
	1102	calc_n_flag(res);
	1103	calc_z_flag(res);
	1104	m_acc = res;
1047	1105	break;
1048	1106	}
1049	1107	case SETNA:
1050	1108	{
1051		res = cpustate->acc | (1 << N);
	1109	res = m_acc | (1 << N);
1052	1110	CLEAR_FLAGS(V_FLAG | C_FLAG | Z_FLAG);
1053		calc_n_flag(cpustate, res);
1054		cpustate->acc = res;
	1111	calc_n_flag(res);
	1112	m_acc = res;
1055	1113	break;
1056	1114	}
1057	1115	case A2NA:
1058	1116	{
1059		UINT16 r = cpustate->acc;
	1117	UINT16 r = m_acc;
1060	1118	UINT16 s = 1 << N;
1061	1119	res = r + s;
1062		calc_z_flag(cpustate, res);
1063		calc_n_flag(cpustate, res);
1064		calc_c_flag_add(cpustate, r, s);
1065		calc_v_flag_add(cpustate, r, s, res);
1066		cpustate->acc = res;
	1120	calc_z_flag(res);
	1121	calc_n_flag(res);
	1122	calc_c_flag_add(r, s);
	1123	calc_v_flag_add(r, s, res);
	1124	m_acc = res;
1067	1125	break;
1068	1126	}
1069	1127	case S2NA:
1070	1128	{
1071		UINT16 r = cpustate->acc;
	1129	UINT16 r = m_acc;
1072	1130	UINT16 s = 1 << N;
1073	1131	res = r - s;
1074		calc_z_flag(cpustate, res);
1075		calc_n_flag(cpustate, res);
1076		calc_c_flag_sub(cpustate, r, s);
1077		calc_v_flag_sub(cpustate, r, s, res);
1078		cpustate->acc = res;
	1132	calc_z_flag(res);
	1133	calc_n_flag(res);
	1134	calc_c_flag_sub(r, s);
	1135	calc_v_flag_sub(r, s, res);
	1136	m_acc = res;
1079	1137	break;
1080	1138	}
1081	1139
1082	1140	case TSTND:
1083	1141	{
1084		res = cpustate->d_latch & (1 << N);
	1142	res = m_d_latch & (1 << N);
1085	1143	CLEAR_FLAGS(V_FLAG | C_FLAG);
1086		calc_n_flag(cpustate, res);
1087		calc_z_flag(cpustate, res);
	1144	calc_n_flag(res);
	1145	calc_z_flag(res);
1088	1146	break;
1089	1147	}
1090	1148
1091	1149	case SETND:
1092	1150	{
1093		UINT16 r = cpustate->d_latch;
	1151	UINT16 r = m_d_latch;
1094	1152	res = r | (1 << N);
1095		cpustate->d_latch = res;
	1153	m_d_latch = res;
1096	1154
1097	1155	CLEAR_FLAGS(V_FLAG | C_FLAG | Z_FLAG);
1098		calc_n_flag(cpustate, res);
	1156	calc_n_flag(res);
1099	1157	break;
1100	1158	}
1101	1159	case LD2NY:
1102	1160	{
1103	1161	res = (1 << N);
1104	1162	CLEAR_FLAGS(V_FLAG | C_FLAG | Z_FLAG);
1105		calc_n_flag(cpustate, res);
	1163	calc_n_flag(res);
1106	1164	break;
1107	1165	}
1108	1166	case LDC2NY:
1109	1167	{
1110	1168	res = (1 << N) ^ 0xffff;
1111	1169	CLEAR_FLAGS(Z_FLAG | C_FLAG | V_FLAG);
1112		calc_n_flag(cpustate, res);
	1170	calc_n_flag(res);
1113	1171	break;
1114	1172	}
1115	1173
1116	1174	case A2NDY:
1117	1175	{
1118		UINT16 r = cpustate->d_latch;
	1176	UINT16 r = m_d_latch;
1119	1177	UINT16 s = 1 << N;
1120	1178	res = r + s;
1121	1179
1122		calc_z_flag(cpustate, res);
1123		calc_n_flag(cpustate, res);
1124		calc_c_flag_add(cpustate, r, s);
1125		calc_v_flag_add(cpustate, r, s, res);
	1180	calc_z_flag(res);
	1181	calc_n_flag(res);
	1182	calc_c_flag_add(r, s);
	1183	calc_v_flag_add(r, s, res);
1126	1184	break;
1127	1185	}
1128	1186
r19754	r19755
1130	1188	UNHANDLED;
1131	1189	}
1132	1190
1133		cpustate->result = res;
	1191	m_result = res;
1134	1192	}
1135	1193
1136		static void bor1(esrip_state *cpustate, UINT16 inst)
	1194	void esrip_device::bor1(UINT16 inst)
1137	1195	{
1138	1196	enum
1139	1197	{
r19754	r19755
1148	1206	{
1149	1207	case SETNR:
1150	1208	{
1151		res = cpustate->ram[RAM_ADDR] | (1 << N);
1152		cpustate->ram[RAM_ADDR] = res;
	1209	res = m_ram[RAM_ADDR] | (1 << N);
	1210	m_ram[RAM_ADDR] = res;
1153	1211	CLEAR_FLAGS(V_FLAG | C_FLAG | Z_FLAG);
1154		calc_n_flag(cpustate, res);
	1212	calc_n_flag(res);
1155	1213	break;
1156	1214	}
1157	1215	case RSTNR:
1158	1216	{
1159		res = cpustate->ram[RAM_ADDR] & ~(1 << N);
1160		cpustate->ram[RAM_ADDR] = res;
	1217	res = m_ram[RAM_ADDR] & ~(1 << N);
	1218	m_ram[RAM_ADDR] = res;
1161	1219	CLEAR_FLAGS(V_FLAG | C_FLAG);
1162		calc_n_flag(cpustate, res);
1163		calc_z_flag(cpustate, res);
	1220	calc_n_flag(res);
	1221	calc_z_flag(res);
1164	1222	break;
1165	1223	}
1166	1224	case TSTNR:
1167	1225	{
1168		res = cpustate->ram[RAM_ADDR] & (1 << N);
	1226	res = m_ram[RAM_ADDR] & (1 << N);
1169	1227	CLEAR_FLAGS(V_FLAG | C_FLAG);
1170		calc_n_flag(cpustate, res);
1171		calc_z_flag(cpustate, res);
	1228	calc_n_flag(res);
	1229	calc_z_flag(res);
1172	1230	break;
1173	1231	}
1174	1232	default: INVALID;
1175	1233	}
1176	1234
1177		cpustate->result = res;
	1235	m_result = res;
1178	1236	}
1179	1237
1180
1181
1182		static void bor2(esrip_state *cpustate, UINT16 inst)
	1238	void esrip_device::bor2(UINT16 inst)
1183	1239	{
1184	1240	enum
1185	1241	{
r19754	r19755
1197	1253	{
1198	1254	res = 1 << N;
1199	1255	CLEAR_FLAGS(V_FLAG | C_FLAG | Z_FLAG);
1200		calc_n_flag(cpustate, res);
	1256	calc_n_flag(res);
1201	1257	break;
1202	1258	}
1203	1259	case LDC2NR:
1204	1260	{
1205	1261	res = (1 << N) ^ 0xffff;
1206	1262	CLEAR_FLAGS(V_FLAG | C_FLAG | Z_FLAG);
1207		calc_n_flag(cpustate, res);
	1263	calc_n_flag(res);
1208	1264	break;
1209	1265	}
1210	1266	case A2NR:
1211	1267	{
1212		UINT16 r = cpustate->ram[RAM_ADDR];
	1268	UINT16 r = m_ram[RAM_ADDR];
1213	1269	UINT16 s = 1 << N;
1214	1270
1215	1271	res = r + s;
1216		calc_v_flag_add(cpustate, r, s, res);
1217		calc_n_flag(cpustate, res);
1218		calc_c_flag_add(cpustate, r, s);
1219		calc_z_flag(cpustate, res);
	1272	calc_v_flag_add(r, s, res);
	1273	calc_n_flag(res);
	1274	calc_c_flag_add(r, s);
	1275	calc_z_flag(res);
1220	1276	break;
1221	1277	}
1222	1278	case S2NR:
1223	1279	{
1224		UINT16 r = cpustate->ram[RAM_ADDR];
	1280	UINT16 r = m_ram[RAM_ADDR];
1225	1281	UINT16 s = 1 << N;
1226	1282
1227	1283	res = r - s;
1228		calc_v_flag_sub(cpustate, r, s, res);
1229		calc_n_flag(cpustate, res);
1230		calc_c_flag_sub(cpustate, r, s);
1231		calc_z_flag(cpustate, res);
	1284	calc_v_flag_sub(r, s, res);
	1285	calc_n_flag(res);
	1286	calc_c_flag_sub(r, s);
	1287	calc_z_flag(res);
1232	1288	break;
1233	1289	}
1234	1290	default: INVALID;
1235	1291	}
1236	1292
1237	1293	/* Destination is RAM */
1238		cpustate->ram[RAM_ADDR] = res;
1239		cpustate->result = res;
	1294	m_ram[RAM_ADDR] = res;
	1295	m_result = res;
1240	1296	}
1241	1297
1242	1298	/*************************************
r19754	r19755
1246	1302	*************************************/
1247	1303
1248	1304	/* TODO Combine these */
1249		static void rotr1(esrip_state *cpustate, UINT16 inst)
	1305	void esrip_device::rotr1(UINT16 inst)
1250	1306	{
1251	1307	enum
1252	1308	{
r19754	r19755
1262	1318
1263	1319	switch ((inst >> 5) & 0xf)
1264	1320	{
1265		case RTRA: u = cpustate->ram[RAM_ADDR];   dst = ACC;      break;
1266		case RTRY: u = cpustate->ram[RAM_ADDR];   dst = Y_BUS;   break;
1267		case RTRR: u = cpustate->ram[RAM_ADDR];   dst = RAM;      break;
	1321	case RTRA: u = m_ram[RAM_ADDR];   dst = ACC;      break;
	1322	case RTRY: u = m_ram[RAM_ADDR];   dst = Y_BUS;   break;
	1323	case RTRR: u = m_ram[RAM_ADDR];   dst = RAM;      break;
1268	1324	default: INVALID;
1269	1325	}
1270	1326
1271	1327	res = (u << n) | (u >> (16 - n));
1272	1328	CLEAR_FLAGS(V_FLAG | C_FLAG);
1273		calc_n_flag(cpustate, res);
1274		calc_z_flag(cpustate, res);
	1329	calc_n_flag(res);
	1330	calc_z_flag(res);
1275	1331
1276	1332	switch (dst)
1277	1333	{
1278		case ACC: cpustate->acc = res; break;
1279		case RAM: cpustate->ram[RAM_ADDR] = res; break;
	1334	case ACC: m_acc = res; break;
	1335	case RAM: m_ram[RAM_ADDR] = res; break;
1280	1336	}
1281	1337
1282		cpustate->result = res;
	1338	m_result = res;
1283	1339	}
1284	1340
1285		static void rotr2(esrip_state *cpustate, UINT16 inst)
	1341	void esrip_device::rotr2(UINT16 inst)
1286	1342	{
1287	1343	enum
1288	1344	{
r19754	r19755
1295	1351
1296	1352	switch ((inst >> 5) & 0xf)
1297	1353	{
1298		case RTAR: u = cpustate->acc;      break;
1299		case RTDR: u = cpustate->d_latch;   break;
	1354	case RTAR: u = m_acc;      break;
	1355	case RTDR: u = m_d_latch;   break;
1300	1356	default: INVALID;
1301	1357	}
1302	1358
1303	1359	res = (u << N) | (u >> (16 - N));
1304	1360	CLEAR_FLAGS(V_FLAG | C_FLAG);
1305		calc_n_flag(cpustate, res);
1306		calc_z_flag(cpustate, res);
1307		cpustate->ram[RAM_ADDR] = res;
	1361	calc_n_flag(res);
	1362	calc_z_flag(res);
	1363	m_ram[RAM_ADDR] = res;
1308	1364
1309		cpustate->result = res;
	1365	m_result = res;
1310	1366	}
1311	1367
1312		static void rotnr(esrip_state *cpustate, UINT16 inst)
	1368	void esrip_device::rotnr(UINT16 inst)
1313	1369	{
1314	1370	enum
1315	1371	{
r19754	r19755
1325	1381
1326	1382	switch (inst & 0x1f)
1327	1383	{
1328		case RTDY: u = cpustate->d_latch;   dst = Y_BUS;   break;
1329		case RTDA: u = cpustate->d_latch;   dst = ACC;      break;
1330		case RTAY: u = cpustate->acc;      dst = Y_BUS;   break;
1331		case RTAA: u = cpustate->acc;      dst = ACC;      break;
	1384	case RTDY: u = m_d_latch;   dst = Y_BUS;   break;
	1385	case RTDA: u = m_d_latch;   dst = ACC;      break;
	1386	case RTAY: u = m_acc;      dst = Y_BUS;   break;
	1387	case RTAA: u = m_acc;      dst = ACC;      break;
1332	1388	default: INVALID;
1333	1389	}
1334	1390
1335	1391	res = (u << N) | (u >> (16 - N));
1336	1392	CLEAR_FLAGS(V_FLAG | C_FLAG);
1337		calc_n_flag(cpustate, res);
1338		calc_z_flag(cpustate, res);
	1393	calc_n_flag(res);
	1394	calc_z_flag(res);
1339	1395
1340	1396	switch (dst)
1341	1397	{
1342	1398	case Y_BUS: break;
1343		case ACC: cpustate->acc = res; break;
1344		case RAM: cpustate->ram[RAM_ADDR] = res; break;
	1399	case ACC: m_acc = res; break;
	1400	case RAM: m_ram[RAM_ADDR] = res; break;
1345	1401	default: UNHANDLED;
1346	1402	}
1347	1403
1348		cpustate->result = res;
	1404	m_result = res;
1349	1405	}
1350	1406
1351	1407	/*************************************
r19754	r19755
1354	1410	*
1355	1411	*************************************/
1356	1412
1357		static void rotc(esrip_state *cpustate, UINT16 inst)
	1413	void esrip_device::rotc(UINT16 inst)
1358	1414	{
1359	1415	UNHANDLED;
1360	1416	}
r19754	r19755
1365	1421	*
1366	1422	*************************************/
1367	1423
1368		static void rotm(esrip_state *cpustate, UINT16 inst)
	1424	void esrip_device::rotm(UINT16 inst)
1369	1425	{
1370	1426	UNHANDLED;
1371	1427	}
r19754	r19755
1376	1432	*
1377	1433	*************************************/
1378	1434
1379		static void prt(esrip_state *cpustate, UINT16 inst)
	1435	void esrip_device::prt(UINT16 inst)
1380	1436	{
1381	1437	UNHANDLED;
1382	1438	}
1383	1439
1384		static void prtnr(esrip_state *cpustate, UINT16 inst)
	1440	void esrip_device::prtnr(UINT16 inst)
1385	1441	{
1386	1442	UNHANDLED;
1387	1443	}
r19754	r19755
1393	1449	*
1394	1450	*************************************/
1395	1451
1396		static void crcf(esrip_state *cpustate, UINT16 inst)
	1452	void esrip_device::crcf(UINT16 inst)
1397	1453	{
1398	1454	UNHANDLED;
1399	1455	}
1400	1456
1401		static void crcr(esrip_state *cpustate, UINT16 inst)
	1457	void esrip_device::crcr(UINT16 inst)
1402	1458	{
1403	1459	UNHANDLED;
1404	1460	}
r19754	r19755
1421	1477	SHDNOV = 8,
1422	1478	};
1423	1479
1424		#define   SET_LINK_flag(cpustate, x)   (cpustate->new_status &= ~L_FLAG); \
1425		(cpustate->new_status |= x ? L_FLAG : 0)
	1480	#define   SET_LINK_flag(x)   (m_new_status &= ~L_FLAG); \
	1481	(m_new_status |= x ? L_FLAG : 0)
1426	1482
1427		static UINT16 shift_op(esrip_state *cpustate, UINT16 u, int opcode)
	1483	UINT16 esrip_device::shift_op(UINT16 u, int opcode)
1428	1484	{
1429	1485	UINT32 res = 0;
1430	1486
r19754	r19755
1433	1489	case SHUPZ:
1434	1490	{
1435	1491	res = (u << 1);
1436		SET_LINK_flag(cpustate, u & 0x8000);
	1492	SET_LINK_flag(u & 0x8000);
1437	1493	CLEAR_FLAGS(V_FLAG | C_FLAG);
1438		calc_n_flag(cpustate, res);
1439		calc_z_flag(cpustate, res);
	1494	calc_n_flag(res);
	1495	calc_z_flag(res);
1440	1496	break;
1441	1497	}
1442	1498	case SHUP1:
1443	1499	{
1444	1500	res = (u << 1) | 1;
1445		SET_LINK_flag(cpustate, u & 0x8000);
	1501	SET_LINK_flag(u & 0x8000);
1446	1502	CLEAR_FLAGS(V_FLAG | C_FLAG);
1447		calc_n_flag(cpustate, res);
1448		calc_z_flag(cpustate, res);
	1503	calc_n_flag(res);
	1504	calc_z_flag(res);
1449	1505	break;
1450	1506	}
1451	1507	case SHUPL:
1452	1508	{
1453		res = (u << 1) | ((cpustate->status & L_FLAG) ? 1 : 0);
1454		SET_LINK_flag(cpustate, u & 0x8000);
	1509	res = (u << 1) | ((m_status & L_FLAG) ? 1 : 0);
	1510	SET_LINK_flag(u & 0x8000);
1455	1511	CLEAR_FLAGS(V_FLAG | C_FLAG);
1456		calc_n_flag(cpustate, res);
1457		calc_z_flag(cpustate, res);
	1512	calc_n_flag(res);
	1513	calc_z_flag(res);
1458	1514	break;
1459	1515	}
1460	1516
r19754	r19755
1469	1525	return res;
1470	1526	}
1471	1527
1472		static void shftr(esrip_state *cpustate, UINT16 inst)
	1528	void esrip_device::shftr(UINT16 inst)
1473	1529	{
1474	1530	enum
1475	1531	{
r19754	r19755
1482	1538
1483	1539	switch ((inst >> 9) & 0xf)
1484	1540	{
1485		case SHRR: u = cpustate->ram[RAM_ADDR];   break;
1486		case SHDR: u = cpustate->d_latch;         break;
	1541	case SHRR: u = m_ram[RAM_ADDR];   break;
	1542	case SHDR: u = m_d_latch;         break;
1487	1543	default: INVALID;
1488	1544	}
1489	1545
1490		res = shift_op(cpustate, u, (inst >> 5) & 0xf);
	1546	res = shift_op(u, (inst >> 5) & 0xf);
1491	1547
1492	1548	/* Destination is always RAM */
1493		cpustate->ram[RAM_ADDR] = res;
1494		cpustate->result = res;
	1549	m_ram[RAM_ADDR] = res;
	1550	m_result = res;
1495	1551	}
1496	1552
1497		static void shftnr(esrip_state *cpustate, UINT16 inst)
	1553	void esrip_device::shftnr(UINT16 inst)
1498	1554	{
1499	1555	enum
1500	1556	{
r19754	r19755
1507	1563
1508	1564	switch ((inst >> 9) & 0xf)
1509	1565	{
1510		case SHA: u = cpustate->acc;         break;
1511		case SHD: u = cpustate->d_latch;      break;
	1566	case SHA: u = m_acc;         break;
	1567	case SHD: u = m_d_latch;      break;
1512	1568	default: INVALID;
1513	1569	}
1514	1570
1515		res = shift_op(cpustate, u, (inst >> 5) & 0xf);
	1571	res = shift_op(u, (inst >> 5) & 0xf);
1516	1572
1517	1573	switch (DST)
1518	1574	{
1519	1575	case NRY:   break;
1520		case NRA:   cpustate->acc = res; break;
	1576	case NRA:   m_acc = res; break;
1521	1577	default:   INVALID;
1522	1578	}
1523		cpustate->result = res;
	1579	m_result = res;
1524	1580	}
1525	1581
1526	1582
r19754	r19755
1530	1586	*
1531	1587	*************************************/
1532	1588
1533		static void svstr(esrip_state *cpustate, UINT16 inst)
	1589	void esrip_device::svstr(UINT16 inst)
1534	1590	{
1535	1591	UNHANDLED;
1536	1592	}
1537	1593
1538		static void rstst(esrip_state *cpustate, UINT16 inst)
	1594	void esrip_device::rstst(UINT16 inst)
1539	1595	{
1540	1596	enum
1541	1597	{
r19754	r19755
1555	1611	case RF3:   CLEAR_FLAGS(FLAG_3); break;
1556	1612	}
1557	1613
1558		cpustate->result = 0;
	1614	m_result = 0;
1559	1615	}
1560	1616
1561		static void setst(esrip_state *cpustate, UINT16 inst)
	1617	void esrip_device::setst(UINT16 inst)
1562	1618	{
1563	1619	enum
1564	1620	{
r19754	r19755
1578	1634	case SF3:   SET_FLAGS(FLAG_3); break;
1579	1635	}
1580	1636
1581		cpustate->result = 0xffff;
	1637	m_result = 0xffff;
1582	1638	}
1583	1639
1584		static void test(esrip_state *cpustate, UINT16 inst)
	1640	void esrip_device::test(UINT16 inst)
1585	1641	{
1586	1642	enum
1587	1643	{
r19754	r19755
1605	1661	{
1606	1662	case TNOZ: UNHANDLED; break;
1607	1663	case TNO:  UNHANDLED; break;
1608		case TZ:   res = cpustate->status & (Z_FLAG); break;
1609		case TOVR: res = cpustate->status & (V_FLAG); break;
	1664	case TZ:   res = m_status & (Z_FLAG); break;
	1665	case TOVR: res = m_status & (V_FLAG); break;
1610	1666	case TLOW: UNHANDLED; break;
1611		case TC:   res = cpustate->status & (C_FLAG); break;
	1667	case TC:   res = m_status & (C_FLAG); break;
1612	1668	case TZC:  UNHANDLED; break;
1613		case TN:   res = cpustate->status & (N_FLAG); break;
1614		case TL:   res = cpustate->status & (L_FLAG); break;
1615		case TF1:  res = cpustate->status & (FLAG_1); break;
1616		case TF2:  res = cpustate->status & (FLAG_2); break;
1617		case TF3:  res = cpustate->status & (FLAG_3); break;
	1669	case TN:   res = m_status & (N_FLAG); break;
	1670	case TL:   res = m_status & (L_FLAG); break;
	1671	case TF1:  res = m_status & (FLAG_1); break;
	1672	case TF2:  res = m_status & (FLAG_2); break;
	1673	case TF3:  res = m_status & (FLAG_3); break;
1618	1674	default:   INVALID;
1619	1675	}
1620	1676
1621		cpustate->ct = res ? 1 : 0;
	1677	m_ct = res ? 1 : 0;
1622	1678	}
1623	1679
1624	1680
r19754	r19755
1628	1684	*
1629	1685	*************************************/
1630	1686
1631		static void nop(esrip_state *cpustate, UINT16 inst)
	1687	void esrip_device::nop(UINT16 inst)
1632	1688	{
1633		cpustate->result = 0xff;   // Undefined
	1689	m_result = 0xff;   // Undefined
1634	1690	}
1635	1691
1636		static void (*const operations[24])(esrip_state *cpustate, UINT16 inst) =
	1692	//**************************************************************************
	1693	//  DEVICE INTERFACE
	1694	//**************************************************************************
	1695
	1696	const device_type ESRIP = &device_creator<esrip_device>;
	1697
	1698	//-------------------------------------------------
	1699	//  esrip_device - constructor
	1700	//-------------------------------------------------
	1701
	1702	esrip_device::esrip_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	1703	: cpu_device(mconfig, ESRIP, "ESRIP", tag, owner, clock),
	1704	m_program_config("program", ENDIANNESS_BIG, 64, 9, -3)
1637	1705	{
1638		rotr1, tor1, rotr2, rotc, rotm, bor2, crcf, crcr,
1639		svstr, prt, sor, tor2, shftr, test, nop, setst, rstst,
1640		rotnr, bonr, bor1, sonr, shftnr, prtnr, tonr
	1706	// build the opcode table
	1707	for (int op = 0; op < 24; op++)
	1708	m_opcode[op] = s_opcodetable[op];
	1709	}
	1710
	1711
	1712	//-------------------------------------------------
	1713	//  static_set_config - set the configuration
	1714	//  structure
	1715	//-------------------------------------------------
	1716
	1717	void esrip_device::static_set_config(device_t &device, const esrip_config &config)
	1718	{
	1719	esrip_device &esrip = downcast<esrip_device &>(device);
	1720	static_cast<esrip_config &>(esrip) = config;
	1721	static_set_static_config(device, &config);
	1722	}
	1723
	1724
	1725	//**************************************************************************
	1726	//  STATIC OPCODE TABLES
	1727	//**************************************************************************
	1728
	1729	const esrip_device::ophandler esrip_device::s_opcodetable[24] =
	1730	{
	1731	&esrip_device::rotr1,   &esrip_device::tor1,   &esrip_device::rotr2,   &esrip_device::rotc,
	1732	&esrip_device::rotm,   &esrip_device::bor2,   &esrip_device::crcf,   &esrip_device::crcr,
	1733	&esrip_device::svstr,   &esrip_device::prt,      &esrip_device::sor,      &esrip_device::tor2,
	1734	&esrip_device::shftr,   &esrip_device::test,   &esrip_device::nop,      &esrip_device::setst,
	1735	&esrip_device::rstst,   &esrip_device::rotnr,   &esrip_device::bonr,   &esrip_device::bor1,
	1736	&esrip_device::sonr,   &esrip_device::shftnr,   &esrip_device::prtnr,   &esrip_device::tonr
1641	1737	};
1642	1738
1643		INLINE void am29116_execute(esrip_state *cpustate, UINT16 inst, int _sre)
	1739
	1740	void esrip_device::am29116_execute(UINT16 inst, int _sre)
1644	1741	{
1645	1742	/* Status register shadow */
1646		cpustate->new_status = cpustate->status;
	1743	m_new_status = m_status;
1647	1744
1648	1745	/* Required for immediate source instructions */
1649		cpustate->inst = inst;
	1746	m_inst = inst;
1650	1747
1651		if (cpustate->immflag == 1)
1652		inst = cpustate->i_latch;
	1748	if (m_immflag == 1)
	1749	inst = m_i_latch;
1653	1750
1654		(*operations[cpustate->optable[inst]])(cpustate, inst);
	1751	(this->*m_opcode[m_optable[inst]])(inst);
1655	1752
1656	1753	if (!_sre)
1657	1754	{
1658		cpustate->status = cpustate->new_status;
1659		cpustate->t = cpustate->status;
	1755	m_status = m_new_status;
	1756	m_t = m_status;
1660	1757	}
1661	1758	}
1662	1759
1663	1760
1664		static CPU_EXECUTE( esrip )
	1761	//-------------------------------------------------
	1762	//  execute_min_cycles - return minimum number of
	1763	//  cycles it takes for one instruction to execute
	1764	//-------------------------------------------------
	1765
	1766	UINT32 esrip_device::execute_min_cycles() const
1665	1767	{
1666		esrip_state *cpustate = get_safe_token(device);
1667		int calldebugger = (device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0;
	1768	return 1;
	1769	}
	1770
	1771
	1772	//-------------------------------------------------
	1773	//  execute_max_cycles - return maximum number of
	1774	//  cycles it takes for one instruction to execute
	1775	//-------------------------------------------------
	1776
	1777	UINT32 esrip_device::execute_max_cycles() const
	1778	{
	1779	return 1;
	1780	}
	1781
	1782
	1783	//-------------------------------------------------
	1784	//  execute_input_lines - return the number of
	1785	//  input/interrupt lines
	1786	//-------------------------------------------------
	1787
	1788	UINT32 esrip_device::execute_input_lines() const
	1789	{
	1790	return 0;
	1791	}
	1792
	1793
	1794	//-------------------------------------------------
	1795	//  execute_set_input - act on a changed input/
	1796	//  interrupt line
	1797	//-------------------------------------------------
	1798
	1799	void esrip_device::execute_set_input(int inputnum, int state)
	1800	{
	1801	}
	1802
	1803
	1804	void esrip_device::execute_run()
	1805	{
	1806	int calldebugger = (machine().debug_flags & DEBUG_FLAG_ENABLED) != 0;
1668	1807	UINT8 status;
1669	1808
1670	1809	/* I think we can get away with placing this outside of the loop */
1671		status = cpustate->status_in(device->machine());
	1810	status = m_status_in(machine());
1672	1811
1673	1812	/* Core execution loop */
1674	1813	do
r19754	r19755
1679	1818	UINT16   ipt_bus = 0;
1680	1819	UINT16   y_bus = 0;
1681	1820
1682		int yoe = _BIT(cpustate->l5, 1);
1683		int bl46 = BIT(cpustate->l4, 6);
1684		int bl44 = BIT(cpustate->l4, 4);
	1821	int yoe = _BIT(m_l5, 1);
	1822	int bl46 = BIT(m_l4, 6);
	1823	int bl44 = BIT(m_l4, 4);
1685	1824
1686	1825	UINT32 in_h;
1687	1826	UINT32 in_l;
1688	1827
1689		if (cpustate->fig_cycles)
	1828	if (m_fig_cycles)
1690	1829	{
1691		if (--cpustate->fig_cycles == 0)
1692		cpustate->fig = 0;
	1830	if (--m_fig_cycles == 0)
	1831	m_fig = 0;
1693	1832	}
1694	1833
1695	1834	/* /OEY = 1 : Y-bus is high imped */
1696	1835	if (yoe)
1697	1836	{
1698	1837	/* Status In */
1699		if (!_BIT(cpustate->l2, 0))
1700		y_bus = status | (!cpustate->fig << 3);
	1838	if (!_BIT(m_l2, 0))
	1839	y_bus = status | (!m_fig << 3);
1701	1840
1702	1841	/* FDT RAM: /Enable, Direction and /RAM OE */
1703		else if (!bl44 && !_BIT(cpustate->l2, 3) && bl46)
1704		y_bus = cpustate->fdt_r(device, *cpustate->program, cpustate->fdt_cnt, 0);
	1842	else if (!bl44 && !_BIT(m_l2, 3) && bl46)
	1843	y_bus = m_fdt_r(this, *m_program, m_fdt_cnt, 0);
1705	1844
1706	1845	/* IPT RAM: /Enable and /READ */
1707		else if (!_BIT(cpustate->l2, 6) && !_BIT(cpustate->l4, 5))
1708		y_bus = cpustate->ipt_ram[cpustate->ipt_cnt];
	1846	else if (!_BIT(m_l2, 6) && !_BIT(m_l4, 5))
	1847	y_bus = m_ipt_ram[m_ipt_cnt];
1709	1848
1710	1849	/* DLE  - latch the value on the Y-BUS into the data latch */
1711		if (_BIT(cpustate->l5, 0))
1712		cpustate->d_latch = y_bus;
	1850	if (_BIT(m_l5, 0))
	1851	m_d_latch = y_bus;
1713	1852
1714	1853	/* Now execute the AM29116 instruction */
1715		am29116_execute(cpustate, (cpustate->l7 << 8) | cpustate->l6, BIT(cpustate->l5, 2));
	1854	am29116_execute((m_l7 << 8) | m_l6, BIT(m_l5, 2));
1716	1855	}
1717	1856	else
1718	1857	{
1719		am29116_execute(cpustate, (cpustate->l7 << 8) | cpustate->l6, BIT(cpustate->l5, 2));
	1858	am29116_execute((m_l7 << 8) | m_l6, BIT(m_l5, 2));
1720	1859
1721		y_bus = cpustate->result;
	1860	y_bus = m_result;
1722	1861
1723		if (BIT(cpustate->l5, 0))
1724		cpustate->d_latch = y_bus;
	1862	if (BIT(m_l5, 0))
	1863	m_d_latch = y_bus;
1725	1864	}
1726	1865
1727	1866	/* Determine what value is on the X-Bus */
1728	1867
1729	1868	/* FDT RAM */
1730	1869	if (!bl44)
1731		x_bus = cpustate->fdt_r(device, *cpustate->program, cpustate->fdt_cnt, 0);
	1870	x_bus = m_fdt_r(this, *m_program, m_fdt_cnt, 0);
1732	1871
1733	1872	/* Buffer is enabled - write direction */
1734		else if (!BIT(cpustate->l2, 3) && !bl46)
	1873	else if (!BIT(m_l2, 3) && !bl46)
1735	1874	{
1736	1875	if (!yoe)
1737	1876	x_bus = y_bus;
1738		else if ( !BIT(cpustate->l2, 6) && !BIT(cpustate->l4, 5) )
1739		x_bus = cpustate->ipt_ram[cpustate->ipt_cnt];
	1877	else if ( !BIT(m_l2, 6) && !BIT(m_l4, 5) )
	1878	x_bus = m_ipt_ram[m_ipt_cnt];
1740	1879	}
1741	1880
1742	1881	/* IPT BUS */
1743		if (!BIT(cpustate->l2, 6))
1744		ipt_bus = cpustate->ipt_ram[cpustate->ipt_cnt];
1745		else if (!BIT(cpustate->l4, 5))
	1882	if (!BIT(m_l2, 6))
	1883	ipt_bus = m_ipt_ram[m_ipt_cnt];
	1884	else if (!BIT(m_l4, 5))
1746	1885	{
1747		if (!BIT(cpustate->l5, 1))
	1886	if (!BIT(m_l5, 1))
1748	1887	ipt_bus = y_bus;
1749	1888	else
1750	1889	ipt_bus = x_bus;
r19754	r19755
1752	1891
1753	1892
1754	1893	/* Write FDT RAM: /Enable, Direction and WRITE */
1755		if (!BIT(cpustate->l2, 3) && !bl46 && !BIT(cpustate->l4, 3))
1756		cpustate->fdt_w(device, *cpustate->program, cpustate->fdt_cnt, x_bus, 0);
	1894	if (!BIT(m_l2, 3) && !bl46 && !BIT(m_l4, 3))
	1895	m_fdt_w(this, *m_program, m_fdt_cnt, x_bus, 0);
1757	1896
1758	1897	/* Write IPT RAM: /Enable and /WR */
1759		if (!BIT(cpustate->l2, 7) && !BIT(cpustate->l4, 5))
1760		cpustate->ipt_ram[cpustate->ipt_cnt] = ipt_bus;
	1898	if (!BIT(m_l2, 7) && !BIT(m_l4, 5))
	1899	m_ipt_ram[m_ipt_cnt] = ipt_bus;
1761	1900
1762	1901
1763		if ((((cpustate->l5 >> 3) & 0x1f) & 0x18) != 0x18)
	1902	if ((((m_l5 >> 3) & 0x1f) & 0x18) != 0x18)
1764	1903	{
1765		if ( check_jmp(cpustate, (cpustate->l5 >> 3) & 0x1f) )
1766		next_pc = cpustate->l1;
	1904	if ( check_jmp((m_l5 >> 3) & 0x1f) )
	1905	next_pc = m_l1;
1767	1906	else
1768		next_pc = cpustate->pc + 1;
	1907	next_pc = m_pc + 1;
1769	1908	}
1770	1909	else
1771		next_pc = cpustate->pc + 1;
	1910	next_pc = m_pc + 1;
1772	1911
1773		cpustate->pl1 = cpustate->l1;
1774		cpustate->pl2 = cpustate->l2;
1775		cpustate->pl3 = cpustate->l3;
1776		cpustate->pl4 = cpustate->l4;
1777		cpustate->pl5 = cpustate->l5;
1778		cpustate->pl6 = cpustate->l6;
1779		cpustate->pl7 = cpustate->l7;
	1912	m_pl1 = m_l1;
	1913	m_pl2 = m_l2;
	1914	m_pl3 = m_l3;
	1915	m_pl4 = m_l4;
	1916	m_pl5 = m_l5;
	1917	m_pl6 = m_l6;
	1918	m_pl7 = m_l7;
1780	1919
1781	1920	/* Latch instruction */
1782		inst = cpustate->direct->read_decrypted_qword(RIP_PC << 3);
	1921	inst = m_direct->read_decrypted_qword(RIP_PC << 3);
1783	1922
1784	1923	in_h = inst >> 32;
1785	1924	in_l = inst & 0xffffffff;
1786	1925
1787		cpustate->l1 = (in_l >> 8);
1788		cpustate->l2 = (in_l >> 16);
1789		cpustate->l3 = (in_l >> 24);
	1926	m_l1 = (in_l >> 8);
	1927	m_l2 = (in_l >> 16);
	1928	m_l3 = (in_l >> 24);
1790	1929
1791		cpustate->l4 = (in_h >> 0);
1792		cpustate->l5 = (in_h >> 8);
1793		cpustate->l6 = (in_h >> 16);
1794		cpustate->l7 = (in_h >> 24);
	1930	m_l4 = (in_h >> 0);
	1931	m_l5 = (in_h >> 8);
	1932	m_l6 = (in_h >> 16);
	1933	m_l7 = (in_h >> 24);
1795	1934
1796	1935	/* Colour latch */
1797		if (RISING_EDGE(cpustate->pl3, cpustate->l3, 0))
1798		cpustate->c_latch = (x_bus >> 12) & 0xf;
	1936	if (RISING_EDGE(m_pl3, m_l3, 0))
	1937	m_c_latch = (x_bus >> 12) & 0xf;
1799	1938
1800	1939	/* Right pixel line buffer address */
1801		if (RISING_EDGE(cpustate->pl3, cpustate->l3, 1))
1802		cpustate->adr_latch = x_bus & 0xfff;
	1940	if (RISING_EDGE(m_pl3, m_l3, 1))
	1941	m_adr_latch = x_bus & 0xfff;
1803	1942
1804	1943	/* Left pixel line buffer address */
1805		if (RISING_EDGE(cpustate->pl3, cpustate->l3, 2))
1806		cpustate->adl_latch = x_bus & 0xfff;
	1944	if (RISING_EDGE(m_pl3, m_l3, 2))
	1945	m_adl_latch = x_bus & 0xfff;
1807	1946
1808	1947	/* FIGLD: Start the DMA */
1809		if (RISING_EDGE(cpustate->pl3, cpustate->l3, 3))
	1948	if (RISING_EDGE(m_pl3, m_l3, 3))
1810	1949	{
1811		cpustate->attr_latch = x_bus;
	1950	m_attr_latch = x_bus;
1812	1951
1813		cpustate->fig = 1;
1814		cpustate->fig_cycles = cpustate->draw(device->machine(), cpustate->adl_latch, cpustate->adr_latch, cpustate->fig_latch, cpustate->attr_latch, cpustate->iaddr_latch, cpustate->c_latch, cpustate->x_scale, cpustate->img_bank);
	1952	m_fig = 1;
	1953	m_fig_cycles = m_draw(machine(), m_adl_latch, m_adr_latch, m_fig_latch, m_attr_latch, m_iaddr_latch, m_c_latch, m_x_scale, m_img_bank);
1815	1954	}
1816	1955
1817	1956	/* X-scale */
1818		if (RISING_EDGE(cpustate->pl3, cpustate->l3, 4))
1819		cpustate->x_scale = x_bus >> 8;
	1957	if (RISING_EDGE(m_pl3, m_l3, 4))
	1958	m_x_scale = x_bus >> 8;
1820	1959
1821	1960	/* Y-scale and image bank */
1822		if (RISING_EDGE(cpustate->pl4, cpustate->l4, 2))
	1961	if (RISING_EDGE(m_pl4, m_l4, 2))
1823	1962	{
1824		cpustate->y_scale = x_bus & 0xff;
1825		cpustate->img_bank = (y_bus >> 14) & 3;
	1963	m_y_scale = x_bus & 0xff;
	1964	m_img_bank = (y_bus >> 14) & 3;
1826	1965	}
1827	1966
1828	1967	/* Image ROM address */
1829		if (RISING_EDGE(cpustate->pl3, cpustate->l3, 5))
1830		cpustate->iaddr_latch = y_bus;
	1968	if (RISING_EDGE(m_pl3, m_l3, 5))
	1969	m_iaddr_latch = y_bus;
1831	1970
1832	1971	/* IXLLD */
1833		if (RISING_EDGE(cpustate->pl3, cpustate->l3, 6))
	1972	if (RISING_EDGE(m_pl3, m_l3, 6))
1834	1973	{
1835		cpustate->line_latch = ipt_bus >> 10;
1836		cpustate->fig_latch  = ipt_bus & 0x3ff;
	1974	m_line_latch = ipt_bus >> 10;
	1975	m_fig_latch  = ipt_bus & 0x3ff;
1837	1976	}
1838	1977
1839	1978	/* Status write */
1840		if (RISING_EDGE(cpustate->pl3, cpustate->l3, 7))
1841		cpustate->status_out = y_bus & 0xff;
	1979	if (RISING_EDGE(m_pl3, m_l3, 7))
	1980	m_status_out = y_bus & 0xff;
1842	1981
1843	1982	/* FDT address counter */
1844		if (!BIT(cpustate->pl2, 1))
1845		cpustate->fdt_cnt = y_bus & 0xfff;
1846		else if (BIT(cpustate->pl2, 2))
1847		cpustate->fdt_cnt = (cpustate->fdt_cnt + 1) & 0xfff;
	1983	if (!BIT(m_pl2, 1))
	1984	m_fdt_cnt = y_bus & 0xfff;
	1985	else if (BIT(m_pl2, 2))
	1986	m_fdt_cnt = (m_fdt_cnt + 1) & 0xfff;
1848	1987
1849	1988	/* Now we can alter the IPT address counter */
1850		if (!BIT(cpustate->pl2, 4))
1851		cpustate->ipt_cnt = y_bus & 0x1fff;
1852		else if (BIT(cpustate->pl2, 5))
1853		cpustate->ipt_cnt = (cpustate->ipt_cnt + 1) & 0x1fff;
	1989	if (!BIT(m_pl2, 4))
	1990	m_ipt_cnt = y_bus & 0x1fff;
	1991	else if (BIT(m_pl2, 5))
	1992	m_ipt_cnt = (m_ipt_cnt + 1) & 0x1fff;
1854	1993
1855	1994	if (calldebugger)
1856		debugger_instruction_hook(device, RIP_PC);
	1995	debugger_instruction_hook(this, RIP_PC);
1857	1996
1858		cpustate->pc = next_pc;
	1997	m_pc = next_pc;
	1998	m_rip_pc = (m_pc | ((m_status_out & 1) << 8));
1859	1999
1860		cpustate->icount--;
1861		} while (cpustate->icount > 0);
	2000	m_icount--;
	2001	} while (m_icount > 0);
1862	2002	}
1863
1864
1865		/**************************************************************************
1866		* set_info
1867		**************************************************************************/
1868
1869		static CPU_SET_INFO( esrip )
1870		{
1871		esrip_state *cpustate = get_safe_token(device);
1872
1873		switch (state)
1874		{
1875		/* --- the following bits of info are set as 64-bit signed integers --- */
1876		case CPUINFO_INT_PC:
1877		case CPUINFO_INT_REGISTER + ESRIP_PC:   cpustate->pc = info->i & 0xff;
1878		cpustate->status_out &= ~1;
1879		cpustate->status_out |= ((info->i >> 8) & 1);
1880		break;
1881		}
1882		}
1883
1884		/**************************************************************************
1885		* get_info
1886		**************************************************************************/
1887
1888		CPU_GET_INFO( esrip )
1889		{
1890		esrip_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
1891
1892		switch (state)
1893		{
1894		/* --- the following bits of info are returned as 64-bit signed integers --- */
1895		case CPUINFO_INT_CONTEXT_SIZE:               info->i = sizeof(esrip_state);   break;
1896		case CPUINFO_INT_ENDIANNESS:               info->i = ENDIANNESS_BIG;      break;
1897		case CPUINFO_INT_CLOCK_MULTIPLIER:            info->i = 1;               break;
1898		case CPUINFO_INT_CLOCK_DIVIDER:               info->i = 1;               break;
1899		case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 8;               break;
1900		case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 8;               break;
1901		case CPUINFO_INT_MIN_CYCLES:               info->i = 1;               break;
1902		case CPUINFO_INT_MAX_CYCLES:               info->i = 1;               break;
1903
1904		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 64;         break;
1905		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 9;         break;
1906		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = -3;         break;
1907		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 0;         break;
1908		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 0;         break;
1909		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = 0;         break;
1910		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 0;         break;
1911		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:      info->i = 0;         break;
1912		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:      info->i = 0;         break;
1913
1914		case CPUINFO_INT_REGISTER:
1915		case CPUINFO_INT_PC:                     info->i = RIP_PC;   break;
1916		case CPUINFO_INT_REGISTER + ESRIP_STATW:      info->i = cpustate->status_out; break;
1917		case CPUINFO_INT_REGISTER + ESRIP_FDTC:         info->i = cpustate->fdt_cnt; break;
1918		case CPUINFO_INT_REGISTER + ESRIP_IPTC:         info->i = cpustate->ipt_cnt; break;
1919
1920		/* --- the following bits of info are returned as pointers to data or functions --- */
1921		case CPUINFO_FCT_SET_INFO:                  info->setinfo = CPU_SET_INFO_NAME(esrip);      break;
1922		case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(esrip);         break;
1923		case CPUINFO_FCT_RESET:                     info->reset = CPU_RESET_NAME(esrip);         break;
1924		case CPUINFO_FCT_EXIT:                     info->exit = CPU_EXIT_NAME(esrip);         break;
1925		case CPUINFO_FCT_EXECUTE:                  info->execute = CPU_EXECUTE_NAME(esrip);      break;
1926		case CPUINFO_FCT_BURN:                     info->burn = NULL;                  break;
1927		case CPUINFO_FCT_DISASSEMBLE:               info->disassemble = CPU_DISASSEMBLE_NAME(esrip);      break;
1928		case CPUINFO_PTR_INSTRUCTION_COUNTER:         info->icount = &cpustate->icount;      break;
1929
1930		/* --- the following bits of info are returned as NULL-terminated strings --- */
1931		case CPUINFO_STR_NAME:                     strcpy(info->s, "Real Time Image Processor");      break;
1932		case CPUINFO_STR_FAMILY:               strcpy(info->s, "Entertainment Sciences");         break;
1933		case CPUINFO_STR_VERSION:               strcpy(info->s, "1.0");               break;
1934		case CPUINFO_STR_SOURCE_FILE:                  strcpy(info->s, __FILE__);            break;
1935		case CPUINFO_STR_CREDITS:               strcpy(info->s, "Copyright Philip J Bennett"); break;
1936
1937		case CPUINFO_STR_FLAGS:                     sprintf(info->s, "%c%c%c%c%c%c%c%c%c",
1938		cpustate->status & 0x80 ? '3' : '.',
1939		cpustate->status & 0x40 ? '2' : '.',
1940		cpustate->status & 0x20 ? '1' : '.',
1941		cpustate->status & 0x10 ? 'L' : '.',
1942		cpustate->status & 0x08 ? 'V' : '.',
1943		cpustate->status & 0x04 ? 'N' : '.',
1944		cpustate->status & 0x02 ? 'C' : '.',
1945		cpustate->status & 0x01 ? 'Z' : '.',
1946		get_hblank(device->machine()) ? 'H' : '.'); break;
1947
1948		case CPUINFO_STR_REGISTER + ESRIP_PC:         sprintf(info->s, "PC: %04X", RIP_PC); break;
1949		case CPUINFO_STR_REGISTER + ESRIP_ACC:         sprintf(info->s, "ACC: %04X", cpustate->acc); break;
1950		case CPUINFO_STR_REGISTER + ESRIP_DLATCH:      sprintf(info->s, "DLATCH: %04X", cpustate->d_latch); break;
1951		case CPUINFO_STR_REGISTER + ESRIP_ILATCH:      sprintf(info->s, "ILATCH: %04X", cpustate->i_latch); break;
1952		case CPUINFO_STR_REGISTER + ESRIP_RAM00:      sprintf(info->s, "RAM[00]: %04X", cpustate->ram[0x00]); break;
1953		case CPUINFO_STR_REGISTER + ESRIP_RAM01:      sprintf(info->s, "RAM[01]: %04X", cpustate->ram[0x01]); break;
1954		case CPUINFO_STR_REGISTER + ESRIP_RAM02:      sprintf(info->s, "RAM[02]: %04X", cpustate->ram[0x02]); break;
1955		case CPUINFO_STR_REGISTER + ESRIP_RAM03:      sprintf(info->s, "RAM[03]: %04X", cpustate->ram[0x03]); break;
1956		case CPUINFO_STR_REGISTER + ESRIP_RAM04:      sprintf(info->s, "RAM[04]: %04X", cpustate->ram[0x04]); break;
1957		case CPUINFO_STR_REGISTER + ESRIP_RAM05:      sprintf(info->s, "RAM[05]: %04X", cpustate->ram[0x05]); break;
1958		case CPUINFO_STR_REGISTER + ESRIP_RAM06:      sprintf(info->s, "RAM[06]: %04X", cpustate->ram[0x06]); break;
1959		case CPUINFO_STR_REGISTER + ESRIP_RAM07:      sprintf(info->s, "RAM[07]: %04X", cpustate->ram[0x07]); break;
1960		case CPUINFO_STR_REGISTER + ESRIP_RAM08:      sprintf(info->s, "RAM[08]: %04X", cpustate->ram[0x08]); break;
1961		case CPUINFO_STR_REGISTER + ESRIP_RAM09:      sprintf(info->s, "RAM[09]: %04X", cpustate->ram[0x09]); break;
1962		case CPUINFO_STR_REGISTER + ESRIP_RAM0A:      sprintf(info->s, "RAM[0A]: %04X", cpustate->ram[0x0a]); break;
1963		case CPUINFO_STR_REGISTER + ESRIP_RAM0B:      sprintf(info->s, "RAM[0B]: %04X", cpustate->ram[0x0b]); break;
1964		case CPUINFO_STR_REGISTER + ESRIP_RAM0C:      sprintf(info->s, "RAM[0C]: %04X", cpustate->ram[0x0c]); break;
1965		case CPUINFO_STR_REGISTER + ESRIP_RAM0D:      sprintf(info->s, "RAM[0D]: %04X", cpustate->ram[0x0d]); break;
1966		case CPUINFO_STR_REGISTER + ESRIP_RAM0E:      sprintf(info->s, "RAM[0E]: %04X", cpustate->ram[0x0e]); break;
1967		case CPUINFO_STR_REGISTER + ESRIP_RAM0F:      sprintf(info->s, "RAM[0F]: %04X", cpustate->ram[0x0f]); break;
1968		case CPUINFO_STR_REGISTER + ESRIP_RAM10:      sprintf(info->s, "RAM[10]: %04X", cpustate->ram[0x10]); break;
1969		case CPUINFO_STR_REGISTER + ESRIP_RAM11:      sprintf(info->s, "RAM[11]: %04X", cpustate->ram[0x11]); break;
1970		case CPUINFO_STR_REGISTER + ESRIP_RAM12:      sprintf(info->s, "RAM[12]: %04X", cpustate->ram[0x12]); break;
1971		case CPUINFO_STR_REGISTER + ESRIP_RAM13:      sprintf(info->s, "RAM[13]: %04X", cpustate->ram[0x13]); break;
1972		case CPUINFO_STR_REGISTER + ESRIP_RAM14:      sprintf(info->s, "RAM[14]: %04X", cpustate->ram[0x14]); break;
1973		case CPUINFO_STR_REGISTER + ESRIP_RAM15:      sprintf(info->s, "RAM[15]: %04X", cpustate->ram[0x15]); break;
1974		case CPUINFO_STR_REGISTER + ESRIP_RAM16:      sprintf(info->s, "RAM[16]: %04X", cpustate->ram[0x16]); break;
1975		case CPUINFO_STR_REGISTER + ESRIP_RAM17:      sprintf(info->s, "RAM[17]: %04X", cpustate->ram[0x17]); break;
1976		case CPUINFO_STR_REGISTER + ESRIP_RAM18:      sprintf(info->s, "RAM[18]: %04X", cpustate->ram[0x18]); break;
1977		case CPUINFO_STR_REGISTER + ESRIP_RAM19:      sprintf(info->s, "RAM[19]: %04X", cpustate->ram[0x19]); break;
1978		case CPUINFO_STR_REGISTER + ESRIP_RAM1A:      sprintf(info->s, "RAM[1A]: %04X", cpustate->ram[0x1a]); break;
1979		case CPUINFO_STR_REGISTER + ESRIP_RAM1B:      sprintf(info->s, "RAM[1B]: %04X", cpustate->ram[0x1b]); break;
1980		case CPUINFO_STR_REGISTER + ESRIP_RAM1C:      sprintf(info->s, "RAM[1C]: %04X", cpustate->ram[0x1c]); break;
1981		case CPUINFO_STR_REGISTER + ESRIP_RAM1D:      sprintf(info->s, "RAM[1D]: %04X", cpustate->ram[0x1d]); break;
1982		case CPUINFO_STR_REGISTER + ESRIP_RAM1E:      sprintf(info->s, "RAM[1E]: %04X", cpustate->ram[0x1e]); break;
1983		case CPUINFO_STR_REGISTER + ESRIP_RAM1F:      sprintf(info->s, "RAM[1F]: %04X", cpustate->ram[0x1f]); break;
1984		case CPUINFO_STR_REGISTER + ESRIP_STATW:      sprintf(info->s, "STAT: %04X", cpustate->status_out); break;
1985		case CPUINFO_STR_REGISTER + ESRIP_FDTC:         sprintf(info->s, "FDTC: %04X", cpustate->fdt_cnt); break;
1986		case CPUINFO_STR_REGISTER + ESRIP_IPTC:         sprintf(info->s, "IPTC: %04X", cpustate->ipt_cnt); break;
1987		case CPUINFO_STR_REGISTER + ESRIP_XSCALE:      sprintf(info->s, "XSCL: %04X", cpustate->x_scale); break;
1988		case CPUINFO_STR_REGISTER + ESRIP_YSCALE:      sprintf(info->s, "YSCL: %04X", cpustate->y_scale); break;
1989		case CPUINFO_STR_REGISTER + ESRIP_BANK:         sprintf(info->s, "BANK: %04X", cpustate->img_bank); break;
1990		case CPUINFO_STR_REGISTER + ESRIP_LINE:         sprintf(info->s, "LINE: %04X", cpustate->line_latch); break;
1991		case CPUINFO_STR_REGISTER + ESRIP_FIG:         sprintf(info->s, "FIG: %04X", cpustate->fig_latch); break;
1992		case CPUINFO_STR_REGISTER + ESRIP_ATTR:         sprintf(info->s, "ATTR: %04X", cpustate->attr_latch); break;
1993		case CPUINFO_STR_REGISTER + ESRIP_ADRL:         sprintf(info->s, "ADRL: %04X", cpustate->adl_latch); break;
1994		case CPUINFO_STR_REGISTER + ESRIP_ADRR:         sprintf(info->s, "ADRR: %04X", cpustate->adr_latch); break;
1995		case CPUINFO_STR_REGISTER + ESRIP_COLR:         sprintf(info->s, "COLR: %04X", cpustate->c_latch); break;
1996		case CPUINFO_STR_REGISTER + ESRIP_IADDR:      sprintf(info->s, "IADR: %04X", cpustate->iaddr_latch); break;
1997		}
1998		}
1999
2000		DEFINE_LEGACY_CPU_DEVICE(ESRIP, esrip);

trunk/src/emu/cpu/esrip/esrip.h

r19754	r19755
21	21
22	22
23	23	/***************************************************************************
	24	INTERFACE CONFIGURATION MACROS
	25	***************************************************************************/
	26
	27	#define MCFG_CPU_ESRIP_CONFIG(_config) \
	28	esrip_device::static_set_config(*device, _config); \
	29
	30
	31	/***************************************************************************
24	32	REGISTER ENUMERATION
25	33	***************************************************************************/
26	34
r19754	r19755
77	85	ESRIP_IADDR,
78	86	};
79	87
80		/***************************************************************************
81		CONFIGURATION STRUCTURE
82		***************************************************************************/
	88
	89	//**************************************************************************
	90	//  TYPE DEFINITIONS
	91	//**************************************************************************
	92
	93	class esrip_device;
	94
	95	// ======================> esrip_config
	96
83	97	struct esrip_config
84	98	{
85	99	read16_device_func   fdt_r;
86	100	write16_device_func   fdt_w;
87	101	UINT8 (*status_in)(running_machine &machine);
88	102	int (*draw)(running_machine &machine, int l, int r, int fig, int attr, int addr, int col, int x_scale, int bank);
89		const char* const lbrm_prom;
	103	const char* lbrm_prom;
90	104	};
91	105
92		/***************************************************************************
93		PUBLIC FUNCTIONS
94		***************************************************************************/
	106	// device type definition
	107	extern const device_type ESRIP;
95	108
96		DECLARE_LEGACY_CPU_DEVICE(ESRIP, esrip);
	109	// ======================> esrip_device
97	110
98		extern UINT8 get_rip_status(device_t *cpu);
	111	// Used by core CPU interface
	112	class esrip_device : public cpu_device,
	113	public esrip_config
	114	{
	115	public:
	116	// construction/destruction
	117	esrip_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
99	118
	119	// inline configuration helpers
	120	static void static_set_config(device_t &device, const esrip_config &config);
	121
	122	// public interfaces
	123	UINT8 get_rip_status();
	124
	125	protected:
	126	// device-level overrides
	127	virtual void device_start();
	128	virtual void device_reset();
	129	virtual void device_stop();
	130
	131	void make_ops();
	132
	133	// device_execute_interface overrides
	134	virtual UINT32 execute_min_cycles() const;
	135	virtual UINT32 execute_max_cycles() const;
	136	virtual UINT32 execute_input_lines() const;
	137	virtual void execute_run();
	138	virtual void execute_set_input(int inputnum, int state);
	139
	140	// device_memory_interface overrides
	141	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
	142
	143	// device_disasm_interface overrides
	144	virtual UINT32 disasm_min_opcode_bytes() const;
	145	virtual UINT32 disasm_max_opcode_bytes() const;
	146	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	147
	148	// device_state_interface overrides
	149	virtual void state_string_export(const device_state_entry &entry, astring &string);
	150
	151	// address spaces
	152	const address_space_config m_program_config;
	153
	154	// CPU registers
	155	UINT16   m_ram[32];
	156	UINT16   m_acc;
	157	UINT16   m_d_latch;
	158	UINT16   m_i_latch;
	159	UINT16   m_result;
	160	UINT8   m_new_status;
	161	UINT8   m_status;
	162	UINT16   m_inst;
	163	UINT8   m_immflag;
	164	UINT8   m_ct;
	165	UINT8   m_t;
	166
	167	/* Instruction latches - current and previous values */
	168	UINT8   m_l1, m_pl1;
	169	UINT8   m_l2, m_pl2;
	170	UINT8   m_l3, m_pl3;
	171	UINT8   m_l4, m_pl4;
	172	UINT8   m_l5, m_pl5;
	173	UINT8   m_l6, m_pl6;
	174	UINT8   m_l7, m_pl7;
	175
	176	UINT8   m_pc;
	177	UINT16   m_rip_pc;
	178	UINT8   m_status_out;
	179
	180	UINT8   m_x_scale;
	181	UINT8   m_y_scale;
	182	UINT8   m_img_bank;
	183	UINT8   m_line_latch;
	184	UINT16   m_fig_latch;
	185	UINT16   m_attr_latch;
	186	UINT16   m_adl_latch;
	187	UINT16   m_adr_latch;
	188	UINT16   m_iaddr_latch;
	189	UINT8   m_c_latch;
	190
	191	UINT16   m_fdt_cnt;
	192	UINT16   m_ipt_cnt;
	193
	194	UINT8   m_fig;
	195	UINT16   m_fig_cycles;
	196
	197	UINT8   m_optable[65536];
	198
	199	UINT16   *m_ipt_ram;
	200	UINT8   *m_lbrm;
	201
	202	address_space *m_program;
	203	direct_read_data *m_direct;
	204
	205	int      m_icount;
	206
	207	read16_device_func   m_fdt_r;
	208	write16_device_func   m_fdt_w;
	209	UINT8 (*m_status_in)(running_machine &machine);
	210	int (*m_draw)(running_machine &machine, int l, int r, int fig, int attr, int addr, int col, int x_scale, int bank);
	211
	212	typedef void (esrip_device::*ophandler)(UINT16 inst);
	213
	214	ophandler m_opcode[24];
	215
	216	static const ophandler s_opcodetable[24];
	217
	218	private:
	219	int get_hblank();
	220	int get_lbrm();
	221	int check_jmp(UINT8 jmp_ctrl);
	222
	223	// flags
	224	void calc_z_flag(UINT16 res);
	225	void calc_c_flag_add(UINT16 a, UINT16 b);
	226	void calc_c_flag_sub(UINT16 a, UINT16 b);
	227	void calc_n_flag(UINT16 res);
	228	void calc_v_flag_add(UINT16 a, UINT16 b, UINT32 r);
	229	void calc_v_flag_sub(UINT16 a, UINT16 b, UINT32 r);
	230
	231	// opcodes
	232	UINT16 sor_op(UINT16 r, UINT16 opcode);
	233	void sor(UINT16 inst);
	234	void sonr(UINT16 inst);
	235
	236	UINT16 tor_op(UINT16 r, UINT16 s, int opcode);
	237	void tonr(UINT16 inst);
	238	void tor1(UINT16 inst);
	239	void tor2(UINT16 inst);
	240
	241	void bonr(UINT16 inst);
	242	void bor1(UINT16 inst);
	243	void bor2(UINT16 inst);
	244
	245	void rotr1(UINT16 inst);
	246	void rotr2(UINT16 inst);
	247	void rotnr(UINT16 inst);
	248	void rotc(UINT16 inst);
	249	void rotm(UINT16 inst);
	250
	251	void prt(UINT16 inst);
	252	void prtnr(UINT16 inst);
	253
	254	void crcf(UINT16 inst);
	255	void crcr(UINT16 inst);
	256
	257	UINT16 shift_op(UINT16 u, int opcode);
	258	void shftr(UINT16 inst);
	259	void shftnr(UINT16 inst);
	260
	261	void svstr(UINT16 inst);
	262
	263	void rstst(UINT16 inst);
	264	void setst(UINT16 inst);
	265
	266	void test(UINT16 inst);
	267
	268	void nop(UINT16 inst);
	269
	270	void am29116_execute(UINT16 inst, int _sre);
	271	};
	272
	273
	274	CPU_DISASSEMBLE( esrip );
	275
100	276	#endif /* _ESRIP_H */

trunk/src/emu/cpu/m6809/m6809.h

r19754	r19755
129	129	direct_read_data *m_direct;
130	130	};
131	131
132		// device type definition
133		extern const device_type ATMEGA88;
134		extern const device_type ATMEGA644;
135
136	132	// ======================> m6809_device
137	133
138	134	class m6809_device : public m6809_base_device

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