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r19733 Saturday 22nd December, 2012 at 22:09:03 UTC by hap
(order/layout is less spaghetti now. don't bother looking at the huge .diff, there are no other changes)

[src/mame/drivers]

namcos23.c

trunk/src/mame/drivers/namcos23.c

r19732	r19733
1248	1248
1249	1249	enum { MODEL, FLUSH };
1250	1250
1251		struct namcos23_render_entry {
	1251	struct namcos23_render_entry
	1252	{
1252	1253	int type;
1253	1254
1254		union {
1255		struct {
	1255	union
	1256	{
	1257	struct
	1258	{
1256	1259	UINT16 model;
1257	1260	INT16 m[9];
1258	1261	INT32 v[3];
r19732	r19733
1261	1264	};
1262	1265	};
1263	1266
1264		struct namcos23_render_data {
	1267	struct namcos23_render_data
	1268	{
1265	1269	running_machine *machine;
1266	1270	const pen_t *pens;
1267	1271	UINT32 (*texture_lookup)(running_machine &machine, const pen_t *pens, float x, float y);
1268	1272	};
1269	1273
1270		struct namcos23_poly_entry {
	1274	struct namcos23_poly_entry
	1275	{
1271	1276	namcos23_render_data rd;
1272	1277	float zkey;
1273	1278	int front;
r19732	r19733
1338	1343	namcos23_state(const machine_config &mconfig, device_type type, const char *tag)
1339	1344	: driver_device(mconfig, type, tag),
1340	1345	m_maincpu(*this, "maincpu"),
1341		m_audiocpu(*this, "audiocpu"),
	1346	m_subcpu(*this, "subcpu"),
1342	1347	m_iocpu(*this, "iocpu"),
1343	1348	m_rtc(*this, "rtc"),
1344	1349	m_mainram(*this, "mainram"),
r19732	r19733
1352	1357	{ }
1353	1358
1354	1359	required_device<cpu_device> m_maincpu;
1355		required_device<cpu_device> m_audiocpu;
	1360	required_device<cpu_device> m_subcpu;
1356	1361	optional_device<cpu_device> m_iocpu;
1357	1362	required_device<rtc4543_device> m_rtc;
1358	1363	required_shared_ptr<UINT32> m_mainram;
r19732	r19733
1379	1384	bool m_ctl_vbl_active;
1380	1385	UINT8 m_ctl_led;
1381	1386	UINT16 m_ctl_inp_buffer[2];
1382		bool m_audiocpu_running;
	1387	bool m_subcpu_running;
1383	1388	UINT32 m_p3d_address;
1384	1389	UINT32 m_p3d_size;
1385	1390	const UINT32 *m_ptrom;
r19732	r19733
1472	1477	DECLARE_WRITE8_MEMBER(s23_iob_p6_w);
1473	1478	DECLARE_READ8_MEMBER(s23_iob_gun_r);
1474	1479	DECLARE_READ8_MEMBER(s23_iob_analog_r);
1475		DECLARE_DRIVER_INIT(ss23);
	1480	DECLARE_DRIVER_INIT(s23);
1476	1481	TILE_GET_INFO_MEMBER(TextTilemapGetInfo);
1477		DECLARE_VIDEO_START(ss23);
	1482	DECLARE_VIDEO_START(s23);
1478	1483	DECLARE_MACHINE_RESET(gmen);
1479	1484	virtual void machine_start();
1480	1485	virtual void machine_reset();
1481		UINT32 screen_update_ss23(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	1486	UINT32 screen_update_s23(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
1482	1487	INTERRUPT_GEN_MEMBER(s23_interrupt);
1483	1488	TIMER_CALLBACK_MEMBER(c361_timer_cb);
1484	1489	};
r19732	r19733
1497	1502	}
1498	1503
1499	1504
1500		void namcos23_state::update_main_interrupts(UINT32 cause)
1501		{
1502		UINT32 changed = cause ^ m_main_irqcause;
1503		m_main_irqcause = cause;
1504	1505
1505		// level 2: vblank
1506		if (changed & MAIN_VBLANK_IRQ)
1507		m_maincpu->set_input_line(MIPS3_IRQ0, (cause & MAIN_VBLANK_IRQ) ? ASSERT_LINE : CLEAR_LINE);
1508	1506
1509		// level 3: C361/subcpu
1510		if (changed & (MAIN_C361_IRQ | MAIN_SUBCPU_IRQ))
1511		m_maincpu->set_input_line(MIPS3_IRQ1, (cause & (MAIN_C361_IRQ | MAIN_SUBCPU_IRQ)) ? ASSERT_LINE : CLEAR_LINE);
1512	1507
1513		// level 4: C435
1514		if (changed & MAIN_C435_IRQ)
1515		m_maincpu->set_input_line(MIPS3_IRQ2, (cause & MAIN_C435_IRQ) ? ASSERT_LINE : CLEAR_LINE);
	1508	/***************************************************************************
1516	1509
1517		// level 5: C422
1518		if (changed & MAIN_C422_IRQ)
1519		m_maincpu->set_input_line(MIPS3_IRQ3, (cause & MAIN_C422_IRQ) ? ASSERT_LINE : CLEAR_LINE);
	1510	Video
1520	1511
1521		// crszone(sys23ev2) has a different configuration, are they hardwired or configured by software? (where?)..
1522		// level 3: C422/subcpu
1523		// level 4: vblank
1524		// level 5: C451/C361
1525		// level 6: C450
1526		}
	1512	***************************************************************************/
1527	1513
1528
1529		TILE_GET_INFO_MEMBER(namcos23_state::TextTilemapGetInfo)
1530		{
1531		UINT16 data = nthword( m_textram,tile_index );
1532		/**
1533		* xxxx.----.----.---- palette select
1534		* ----.xx--.----.---- flip
1535		* ----.--xx.xxxx.xxxx code
1536		*/
1537		SET_TILE_INFO_MEMBER(0, data&0x03ff, data>>12, TILE_FLIPYX((data&0x0c00)>>10));
1538		}
1539
1540		WRITE32_MEMBER(namcos23_state::s23_textram_w)
1541		{
1542		COMBINE_DATA( &m_textram[offset] );
1543		m_bgtilemap->mark_tile_dirty(offset*2);
1544		m_bgtilemap->mark_tile_dirty((offset*2)+1);
1545		}
1546
1547		WRITE32_MEMBER(namcos23_state::s23_textchar_w)
1548		{
1549		COMBINE_DATA(&m_charram[offset]);
1550		machine().gfx[0]->mark_dirty(offset/32);
1551		}
1552
1553		WRITE32_MEMBER(namcos23_state::s23_paletteram_w)
1554		{
1555		COMBINE_DATA(&m_generic_paletteram_32[offset]);
1556
1557		// each LONGWORD is 2 colors, each OFFSET is 2 colors
1558		for (int i = 0; i < 2; i++)
1559		{
1560		int which = (offset << 2 | i << 1) & 0xfffe;
1561		int r = nthbyte(m_generic_paletteram_32, which|0x00001);
1562		int g = nthbyte(m_generic_paletteram_32, which|0x10001);
1563		int b = nthbyte(m_generic_paletteram_32, which|0x20001);
1564		palette_set_color(machine(), which/2, MAKE_RGB(r,g,b));
1565		}
1566		}
1567
1568		READ16_MEMBER(namcos23_state::s23_c417_r)
1569		{
1570		switch (offset)
1571		{
1572		/* According to timecrs2c, +0 is the status word with bits being:
1573		15: test mode flag (huh?)
1574		10: fifo data ready
1575		9:  cmd ram data ready
1576		8:  matrix busy
1577		7:  output unit busy (inverted)
1578		6:  hokan/tenso unit busy
1579		5:  point unit busy
1580		4:  access unit busy
1581		3:  c403 busy (inverted)
1582		2:  2nd c435 busy (inverted)
1583		1:  1st c435 busy (inverted)
1584		0:  xcpreq
1585		*/
1586		case 0:
1587		return 0x8e | (machine().primary_screen->vblank() ? 0x0000 : 0x8000);
1588		case 1:
1589		return m_c417.adr;
1590		case 4:
1591		//logerror("c417_r %04x = %04x (%08x, %08x)\n", c417.adr, c417.ram[c417.adr], space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1592		return m_c417.ram[m_c417.adr];
1593		case 5:
1594		if (m_c417.pointrom_adr >= m_ptrom_limit)
1595		return 0xffff;
1596		return m_ptrom[m_c417.pointrom_adr] >> 16;
1597		case 6:
1598		if (m_c417.pointrom_adr >= m_ptrom_limit)
1599		return 0xffff;
1600		return m_ptrom[m_c417.pointrom_adr];
1601		}
1602
1603		logerror("c417_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1604		return 0;
1605		}
1606
1607		WRITE16_MEMBER(namcos23_state::s23_c417_w)
1608		{
1609		switch (offset)
1610		{
1611		case 0:
1612		logerror("p3d PIO %04x\n", data);
1613		break;
1614		case 1:
1615		COMBINE_DATA(&m_c417.adr);
1616		break;
1617		case 2:
1618		m_c417.pointrom_adr = (m_c417.pointrom_adr << 16) | data;
1619		break;
1620		case 3:
1621		m_c417.pointrom_adr = 0;
1622		break;
1623		case 4:
1624		//logerror("c417_w %04x = %04x (%08x, %08x)\n", c417.adr, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1625		COMBINE_DATA(m_c417.ram + m_c417.adr);
1626		break;
1627		case 7:
1628		logerror("c417_w: ack IRQ 2 (%x)\n", data);
1629		update_main_interrupts(m_main_irqcause & ~MAIN_C435_IRQ);
1630		break;
1631		default:
1632		logerror("c417_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1633		break;
1634		}
1635		}
1636
1637		READ16_MEMBER(namcos23_state::s23_c412_ram_r)
1638		{
1639		//  logerror("c412_ram_r %06x (%08x, %08x)\n", offset, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1640		if(offset < 0x100000)
1641		return m_c412.sdram_a[offset & 0xfffff];
1642		else if(offset < 0x200000)
1643		return m_c412.sdram_b[offset & 0xfffff];
1644		else if(offset < 0x220000)
1645		return m_c412.sram   [offset & 0x1ffff];
1646		else if(offset < 0x220200)
1647		return m_c412.pczram [offset & 0x001ff];
1648
1649		return 0xffff;
1650		}
1651
1652		WRITE16_MEMBER(namcos23_state::s23_c412_ram_w)
1653		{
1654		//  logerror("c412_ram_w %06x = %04x (%08x, %08x)\n", offset, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1655		if(offset < 0x100000)
1656		COMBINE_DATA(m_c412.sdram_a + (offset & 0xfffff));
1657		else if(offset < 0x200000)
1658		COMBINE_DATA(m_c412.sdram_b + (offset & 0xfffff));
1659		else if(offset < 0x220000)
1660		COMBINE_DATA(m_c412.sram    + (offset & 0x1ffff));
1661		else if(offset < 0x220200)
1662		COMBINE_DATA(m_c412.pczram  + (offset & 0x001ff));
1663		}
1664
1665		READ16_MEMBER(namcos23_state::s23_c412_r)
1666		{
1667		switch (offset)
1668		{
1669		case 0x3:
1670		return 0x0002; // 0001 = busy, 0002 = game uploads things
1671		case 0x8:
1672		return m_c412.adr;
1673		case 0x9:
1674		return m_c412.adr >> 16;
1675		case 0xa:
1676		return s23_c412_ram_r(space, m_c412.adr, mem_mask);
1677		case 0xc:
1678		// unknown status, 500gp reads it and waits for a transition
1679		// no other games use it?
1680		m_c412.status_c ^= 1;
1681		return m_c412.status_c;
1682		}
1683
1684		logerror("c412_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1685		return 0;
1686		}
1687
1688		WRITE16_MEMBER(namcos23_state::s23_c412_w)
1689		{
1690		switch (offset)
1691		{
1692		case 0x2:
1693		// d0: cz on
1694		// other bits: no function?
1695		break;
1696		case 0x8:
1697		m_c412.adr = (data & mem_mask) | (m_c412.adr & (0xffffffff ^ mem_mask));
1698		break;
1699		case 0x9:
1700		m_c412.adr = ((data & mem_mask) << 16) | (m_c412.adr & (0xffffffff ^ (mem_mask << 16)));
1701		break;
1702		case 0xa:
1703		s23_c412_ram_w(space, m_c412.adr, data, mem_mask);
1704		m_c412.adr += 2;
1705		break;
1706		default:
1707		logerror("c412_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1708		break;
1709		}
1710		}
1711
1712		READ16_MEMBER(namcos23_state::s23_c421_ram_r)
1713		{
1714		//  logerror("c421_ram_r %06x (%08x, %08x)\n", offset, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1715		if(offset < 0x40000)
1716		return m_c421.dram_a[offset & 0x3ffff];
1717		else if(offset < 0x80000)
1718		return m_c421.dram_b[offset & 0x3ffff];
1719		else if(offset < 0x88000)
1720		return m_c421.sram  [offset & 0x07fff];
1721
1722		return 0xffff;
1723		}
1724
1725		WRITE16_MEMBER(namcos23_state::s23_c421_ram_w)
1726		{
1727		//  logerror("c421_ram_w %06x = %04x (%08x, %08x)\n", offset, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1728		if(offset < 0x40000)
1729		COMBINE_DATA(m_c421.dram_a + (offset & 0x3ffff));
1730		else if(offset < 0x80000)
1731		COMBINE_DATA(m_c421.dram_b + (offset & 0x3ffff));
1732		else if(offset < 0x88000)
1733		COMBINE_DATA(m_c421.sram   + (offset & 0x07fff));
1734		}
1735
1736		READ16_MEMBER(namcos23_state::s23_c421_r)
1737		{
1738		switch (offset)
1739		{
1740		case 0:
1741		return s23_c421_ram_r(space, m_c421.adr & 0xfffff, mem_mask);
1742
1743		case 2:
1744		return m_c421.adr >> 16;
1745		case 3:
1746		return m_c421.adr;
1747		}
1748
1749		logerror("c421_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1750		return 0;
1751		}
1752
1753		WRITE16_MEMBER(namcos23_state::s23_c421_w)
1754		{
1755		switch (offset)
1756		{
1757		case 0:
1758		s23_c421_ram_w(space, m_c421.adr & 0xfffff, data, mem_mask);
1759		m_c421.adr += 2;
1760		break;
1761		case 2:
1762		m_c421.adr = ((data & mem_mask) << 16) | (m_c421.adr & (0xffffffff ^ (mem_mask << 16)));
1763		break;
1764		case 3:
1765		m_c421.adr = (data & mem_mask) | (m_c421.adr & (0xffffffff ^ mem_mask));
1766		break;
1767		default:
1768		logerror("c421_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1769		break;
1770		}
1771		}
1772
1773		WRITE16_MEMBER(namcos23_state::s23_ctl_w)
1774		{
1775		switch (offset)
1776		{
1777		case 0:
1778		if (m_ctl_led != (data & 0xff))
1779		{
1780		m_ctl_led = data & 0xff;
1781		for (int i = 0; i < 8; i++)
1782		output_set_lamp_value(i, (~data<<i & 0x80) ? 0 : 1);
1783		}
1784		break;
1785
1786		case 2: case 3:
1787		// These may be coming from another CPU, in particular the I/O one
1788		m_ctl_inp_buffer[offset-2] = ioport(offset == 2 ? "P1" : "P2")->read();
1789		break;
1790		case 5:
1791		if(m_ctl_vbl_active)
1792		{
1793		m_ctl_vbl_active = false;
1794		update_main_interrupts(m_main_irqcause & ~MAIN_VBLANK_IRQ);
1795		}
1796		break;
1797
1798		case 6:   // gmen wars spams this heavily with 0 prior to starting the GMEN board test
1799		if (data != 0)
1800		logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1801		break;
1802
1803		default:
1804		logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1805		break;
1806		}
1807		}
1808
1809		READ16_MEMBER(namcos23_state::s23_ctl_r)
1810		{
1811		switch (offset)
1812		{
1813		// 0100 set freezes gorgon (polygon fifo flag)
1814		case 1:
1815		return 0x0000 | ioport("DSW")->read();
1816		case 2: case 3:
1817		{
1818		UINT16 res = m_ctl_inp_buffer[offset-2] & 0x800 ? 0xffff : 0x0000;
1819		m_ctl_inp_buffer[offset-2] = (m_ctl_inp_buffer[offset-2] << 1) | 1;
1820		return res;
1821		}
1822		}
1823
1824		logerror("ctl_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1825		return 0xffff;
1826		}
1827
1828		TIMER_CALLBACK_MEMBER(namcos23_state::c361_timer_cb)
1829		{
1830		if (m_c361.scanline != 0x1ff)
1831		{
1832		// need to do a partial update here, but doesn't work properly yet
1833		//machine().primary_screen->update_partial(machine().primary_screen->vpos());
1834		update_main_interrupts(m_main_irqcause | MAIN_C361_IRQ);
1835
1836		// TC2 indicates it's probably one-shot since it resets it each VBL...
1837		//c361.timer->adjust(machine().primary_screen->time_until_pos(c361.scanline));
1838		}
1839		else
1840		update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
1841		}
1842
1843		WRITE16_MEMBER(namcos23_state::s23_c361_w)
1844		{
1845		switch (offset)
1846		{
1847		case 0:
1848		m_bgtilemap->set_scrollx(0, data&0xfff);
1849		break;
1850
1851		case 1:
1852		m_bgtilemap->set_scrolly(0, data&0xfff);
1853		break;
1854
1855		case 4:   // interrupt control
1856		m_c361.scanline = data & 0x1ff;
1857		m_c361.timer->adjust(machine().primary_screen->time_until_pos(m_c361.scanline));
1858		break;
1859
1860		default:
1861		logerror("c361_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1862		break;
1863		}
1864		}
1865
1866		READ16_MEMBER(namcos23_state::s23_c361_r)
1867		{
1868		switch (offset)
1869		{
1870		// current raster position
1871		// how does it work exactly? it's not understood in namcos22 either (also has a c361)
1872		case 5:
1873		update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
1874		return machine().primary_screen->vpos()*2 | (machine().primary_screen->vblank() ? 1 : 0);
1875		case 6:
1876		update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
1877		return machine().primary_screen->vblank() ? 1 : 0;
1878		}
1879
1880		logerror("c361_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1881		return 0xffff;
1882		}
1883
1884		READ16_MEMBER(namcos23_state::s23_c422_r)
1885		{
1886		return m_c422.regs[offset];
1887		}
1888
1889		WRITE16_MEMBER(namcos23_state::s23_c422_w)
1890		{
1891		switch (offset)
1892		{
1893		case 1:
1894		if (data == 0xfffb)
1895		{
1896		logerror("c422_w: raise IRQ 3\n");
1897		update_main_interrupts(m_main_irqcause | MAIN_C422_IRQ);
1898		}
1899		else if (data == 0x000f)
1900		{
1901		logerror("c422_w: ack IRQ 3\n");
1902		update_main_interrupts(m_main_irqcause & ~MAIN_C422_IRQ);
1903		}
1904		break;
1905
1906		default:
1907		logerror("c422_w: %04x @ %x\n", data, offset);
1908		break;
1909		}
1910
1911		COMBINE_DATA(&m_c422.regs[offset]);
1912		}
1913
1914
1915		WRITE16_MEMBER(namcos23_state::s23_mcuen_w)
1916		{
1917		switch (offset)
1918		{
1919		case 2:
1920		// subcpu irq ack
1921		update_main_interrupts(m_main_irqcause & ~MAIN_SUBCPU_IRQ);
1922		break;
1923
1924		case 5:
1925		// boot/start the audio mcu
1926		if (data)
1927		{
1928		logerror("mcuen_w: booting H8/3002\n");
1929
1930		// Panic Park: writing 1 when it's already running means reboot?
1931		if (m_audiocpu_running)
1932		{
1933		m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
1934		}
1935
1936		m_audiocpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
1937		m_audiocpu_running = true;
1938		}
1939		else
1940		{
1941		logerror("mcuen_w: stopping H8/3002\n");
1942		m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
1943		m_audiocpu_running = false;
1944		}
1945		break;
1946
1947		default:
1948		logerror("mcuen_w: mask %04x, data %04x @ %x\n", mem_mask, data, offset);
1949		break;
1950		}
1951		}
1952
1953		// while getting the subcpu to be ready, panicprk sits in a tight loop waiting for this AND 0002 to be non-zero (at PC=BFC02F00)
1954		// timecrs2 locks up in a similar way as panicprk, at the beginning of the 2nd level, by reading/writing to this register a couple of times
1955		READ16_MEMBER(namcos23_state::s23_sub_comm_r)
1956		{
1957		return 2;
1958		}
1959
1960		WRITE16_MEMBER(namcos23_state::s23_sub_comm_w)
1961		{
1962		;
1963		}
1964
1965	1514	// 3D hardware, to throw at least in part in video/namcos23.c
1966	1515
1967	1516	INLINE INT32 u32_to_s24(UINT32 v)
r19732	r19733
1984	1533	return UINT8(l);
1985	1534	}
1986	1535
1987		static UINT32 texture_lookup_nocache_point(running_machine &machine, const pen_t *pens, float x, float y)
1988		{
1989		namcos23_state *state = machine.driver_data<namcos23_state>();
1990		UINT32 xx = UINT32(x);
1991		UINT32 yy = UINT32(y);
1992		UINT32 tileid = ((xx >> 4) & 0xff) | ((yy << 4) & state->m_tileid_mask);
1993		UINT8 attr = state->m_tmhrom[tileid >> 1];
1994		if(tileid & 1)
1995		attr &= 15;
1996		else
1997		attr >>= 4;
1998		UINT32 tile = (state->m_tmlrom[tileid] | (attr << 16)) & state->m_tile_mask;
1999
2000		// Probably swapx/swapy to add on bits 2-3 of attr
2001		// Bits used by motoxgo at least
2002		UINT8 color = state->m_texrom[(tile << 8) | ((yy << 4) & 0xf0) | (xx & 0x0f)];
2003		return pens[color];
2004		}
2005
2006		static void render_scanline(void *dest, INT32 scanline, const poly_extent *extent, const void *extradata, int threadid)
2007		{
2008		const namcos23_render_data *rd = (const namcos23_render_data *)extradata;
2009
2010		float w = extent->param[0].start;
2011		float u = extent->param[1].start;
2012		float v = extent->param[2].start;
2013		float l = extent->param[3].start;
2014		float dw = extent->param[0].dpdx;
2015		float du = extent->param[1].dpdx;
2016		float dv = extent->param[2].dpdx;
2017		float dl = extent->param[3].dpdx;
2018		bitmap_rgb32 *bitmap = (bitmap_rgb32 *)dest;
2019		UINT32 *img = &bitmap->pix32(scanline, extent->startx);
2020
2021		for(int x = extent->startx; x < extent->stopx; x++)
2022		{
2023		float z = w ? 1/w : 0;
2024		UINT32 pcol = rd->texture_lookup(*rd->machine, rd->pens, u*z, v*z);
2025		float ll = l*z;
2026		*img = (light(pcol >> 16, ll) << 16) | (light(pcol >> 8, ll) << 8) | light(pcol, ll);
2027
2028		w += dw;
2029		u += du;
2030		v += dv;
2031		l += dl;
2032		img++;
2033		}
2034		}
2035
2036	1536	static INT32 *p3d_getv(namcos23_state *state, UINT16 id)
2037	1537	{
2038	1538	if(id == 0x8000)
r19732	r19733
2082	1582	}
2083	1583	}
2084	1584
	1585
2085	1586	static void p3d_scaling_set(namcos23_state *state, const UINT16 *p, int size)
2086	1587	{
2087	1588	if(size != 1)
r19732	r19733
2156	1657	t[8] = INT16((m1[6]*m2[2] + m1[7]*m2[5] + m1[8]*m2[8]) >> 14);
2157	1658	}
2158	1659
	1660
2159	1661	static void p3d_render(namcos23_state *state, const UINT16 *p, int size, bool use_scaling)
2160	1662	{
2161	1663	render_t &render = state->m_render;
r19732	r19733
2305	1807	}
2306	1808	}
2307	1809
	1810
	1811
	1812
	1813	static void render_scanline(void *dest, INT32 scanline, const poly_extent *extent, const void *extradata, int threadid)
	1814	{
	1815	const namcos23_render_data *rd = (const namcos23_render_data *)extradata;
	1816
	1817	float w = extent->param[0].start;
	1818	float u = extent->param[1].start;
	1819	float v = extent->param[2].start;
	1820	float l = extent->param[3].start;
	1821	float dw = extent->param[0].dpdx;
	1822	float du = extent->param[1].dpdx;
	1823	float dv = extent->param[2].dpdx;
	1824	float dl = extent->param[3].dpdx;
	1825	bitmap_rgb32 *bitmap = (bitmap_rgb32 *)dest;
	1826	UINT32 *img = &bitmap->pix32(scanline, extent->startx);
	1827
	1828	for(int x = extent->startx; x < extent->stopx; x++)
	1829	{
	1830	float z = w ? 1/w : 0;
	1831	UINT32 pcol = rd->texture_lookup(*rd->machine, rd->pens, u*z, v*z);
	1832	float ll = l*z;
	1833	*img = (light(pcol >> 16, ll) << 16) | (light(pcol >> 8, ll) << 8) | light(pcol, ll);
	1834
	1835	w += dw;
	1836	u += du;
	1837	v += dv;
	1838	l += dl;
	1839	img++;
	1840	}
	1841	}
	1842
2308	1843	static void render_apply_transform(INT32 xi, INT32 yi, INT32 zi, const namcos23_render_entry *re, poly_vertex &pv)
2309	1844	{
2310	1845	pv.x =    (INT32((re->model.m[0]*INT64(xi) + re->model.m[3]*INT64(yi) + re->model.m[6]*INT64(zi)) >> 14)*re->model.scaling + re->model.v[0])/16384.0;
r19732	r19733
2332	1867	pv.p[0] = w;
2333	1868	}
2334	1869
	1870	static UINT32 render_texture_lookup_nocache_point(running_machine &machine, const pen_t *pens, float x, float y)
	1871	{
	1872	namcos23_state *state = machine.driver_data<namcos23_state>();
	1873	UINT32 xx = UINT32(x);
	1874	UINT32 yy = UINT32(y);
	1875	UINT32 tileid = ((xx >> 4) & 0xff) | ((yy << 4) & state->m_tileid_mask);
	1876	UINT8 attr = state->m_tmhrom[tileid >> 1];
	1877	if(tileid & 1)
	1878	attr &= 15;
	1879	else
	1880	attr >>= 4;
	1881	UINT32 tile = (state->m_tmlrom[tileid] | (attr << 16)) & state->m_tile_mask;
	1882
	1883	// Probably swapx/swapy to add on bits 2-3 of attr
	1884	// Bits used by motoxgo at least
	1885	UINT8 color = state->m_texrom[(tile << 8) | ((yy << 4) & 0xf0) | (xx & 0x0f)];
	1886	return pens[color];
	1887	}
	1888
2335	1889	static void render_one_model(running_machine &machine, const namcos23_render_entry *re)
2336	1890	{
2337	1891	namcos23_state *state = machine.driver_data<namcos23_state>();
2338	1892	render_t &render = state->m_render;
2339	1893	UINT32 adr = state->m_ptrom[re->model.model];
2340		if(adr >= state->m_ptrom_limit) {
	1894	if(adr >= state->m_ptrom_limit)
	1895	{
2341	1896	logerror("WARNING: model %04x base address %08x out-of-bounds - pointram?\n", re->model.model, adr);
2342	1897	return;
2343	1898	}
r19732	r19733
2396	1951	case 2:
2397	1952	pv[i].p[3] = 1.0;
2398	1953	break;
2399		case 3: {
	1954	case 3:
	1955	{
2400	1956	UINT32 norm = state->m_ptrom[extptr++];
2401	1957	INT32 nx = u32_to_s10(norm >> 20);
2402	1958	INT32 ny = u32_to_s10(norm >> 10);
r19732	r19733
2432	1988	p->zkey = 0.5*(minz+maxz);
2433	1989	p->front = !(h & 0x00000001);
2434	1990	p->rd.machine = &machine;
2435		p->rd.texture_lookup = texture_lookup_nocache_point;
	1991	p->rd.texture_lookup = render_texture_lookup_nocache_point;
2436	1992	p->rd.pens = machine.pens + (color << 8);
2437	1993	render.poly_count++;
2438	1994	}
r19732	r19733
2504	2060	}
2505	2061
2506	2062
2507		VIDEO_START_MEMBER(namcos23_state,ss23)
2508		{
2509		machine().gfx[0]->set_source(reinterpret_cast<UINT8 *>(m_charram.target()));
2510		m_bgtilemap = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(namcos23_state::TextTilemapGetInfo),this), TILEMAP_SCAN_ROWS, 16, 16, 64, 64);
2511		m_bgtilemap->set_transparent_pen(0xf);
2512		m_bgtilemap->set_scrolldx(860, 860);
2513		m_render.polymgr = poly_alloc(machine(), 10000, sizeof(namcos23_render_data), 0);
2514		}
2515	2063
	2064	// C404 (gamma/palette)
2516	2065
2517	2066	void namcos23_state::update_mixer()
2518	2067	{
r19732	r19733
2527	2076	m_c404.layer = nthword(m_gammaram, 0x1f) & 0xff;
2528	2077	}
2529	2078
2530		UINT32 namcos23_state::screen_update_ss23(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
	2079	WRITE32_MEMBER(namcos23_state::s23_paletteram_w)
2531	2080	{
	2081	COMBINE_DATA(&m_generic_paletteram_32[offset]);
	2082
	2083	// each LONGWORD is 2 colors, each OFFSET is 2 colors
	2084	for (int i = 0; i < 2; i++)
	2085	{
	2086	int which = (offset << 2 | i << 1) & 0xfffe;
	2087	int r = nthbyte(m_generic_paletteram_32, which|0x00001);
	2088	int g = nthbyte(m_generic_paletteram_32, which|0x10001);
	2089	int b = nthbyte(m_generic_paletteram_32, which|0x20001);
	2090	palette_set_color(machine(), which/2, MAKE_RGB(r,g,b));
	2091	}
	2092	}
	2093
	2094
	2095
	2096	// C361 (text)
	2097
	2098	TILE_GET_INFO_MEMBER(namcos23_state::TextTilemapGetInfo)
	2099	{
	2100	UINT16 data = nthword( m_textram,tile_index );
	2101	/**
	2102	* xxxx.----.----.---- palette select
	2103	* ----.xx--.----.---- flip
	2104	* ----.--xx.xxxx.xxxx code
	2105	*/
	2106	SET_TILE_INFO_MEMBER(0, data&0x03ff, data>>12, TILE_FLIPYX((data&0x0c00)>>10));
	2107	}
	2108
	2109	WRITE32_MEMBER(namcos23_state::s23_textram_w)
	2110	{
	2111	COMBINE_DATA( &m_textram[offset] );
	2112	m_bgtilemap->mark_tile_dirty(offset*2);
	2113	m_bgtilemap->mark_tile_dirty((offset*2)+1);
	2114	}
	2115
	2116	WRITE32_MEMBER(namcos23_state::s23_textchar_w)
	2117	{
	2118	COMBINE_DATA(&m_charram[offset]);
	2119	machine().gfx[0]->mark_dirty(offset/32);
	2120	}
	2121
	2122
	2123
	2124	// Video start/update callbacks
	2125
	2126	VIDEO_START_MEMBER(namcos23_state,s23)
	2127	{
	2128	machine().gfx[0]->set_source(reinterpret_cast<UINT8 *>(m_charram.target()));
	2129	m_bgtilemap = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(namcos23_state::TextTilemapGetInfo),this), TILEMAP_SCAN_ROWS, 16, 16, 64, 64);
	2130	m_bgtilemap->set_transparent_pen(0xf);
	2131	m_bgtilemap->set_scrolldx(860, 860);
	2132	m_render.polymgr = poly_alloc(machine(), 10000, sizeof(namcos23_render_data), 0);
	2133	}
	2134
	2135
	2136	UINT32 namcos23_state::screen_update_s23(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
	2137	{
2532	2138	update_mixer();
2533	2139	bitmap.fill(m_c404.bgcolor, cliprect);
2534	2140
r19732	r19733
2540	2146	return 0;
2541	2147	}
2542	2148
	2149
	2150
	2151
	2152
	2153	/***************************************************************************
	2154
	2155	Main CPU I/O + Memory Map
	2156	(some cpu->video I/O handled above)
	2157
	2158	***************************************************************************/
	2159
	2160	// Interrupts
	2161
	2162	void namcos23_state::update_main_interrupts(UINT32 cause)
	2163	{
	2164	UINT32 changed = cause ^ m_main_irqcause;
	2165	m_main_irqcause = cause;
	2166
	2167	// level 2: vblank
	2168	if (changed & MAIN_VBLANK_IRQ)
	2169	m_maincpu->set_input_line(MIPS3_IRQ0, (cause & MAIN_VBLANK_IRQ) ? ASSERT_LINE : CLEAR_LINE);
	2170
	2171	// level 3: C361/subcpu
	2172	if (changed & (MAIN_C361_IRQ | MAIN_SUBCPU_IRQ))
	2173	m_maincpu->set_input_line(MIPS3_IRQ1, (cause & (MAIN_C361_IRQ | MAIN_SUBCPU_IRQ)) ? ASSERT_LINE : CLEAR_LINE);
	2174
	2175	// level 4: C435
	2176	if (changed & MAIN_C435_IRQ)
	2177	m_maincpu->set_input_line(MIPS3_IRQ2, (cause & MAIN_C435_IRQ) ? ASSERT_LINE : CLEAR_LINE);
	2178
	2179	// level 5: C422
	2180	if (changed & MAIN_C422_IRQ)
	2181	m_maincpu->set_input_line(MIPS3_IRQ3, (cause & MAIN_C422_IRQ) ? ASSERT_LINE : CLEAR_LINE);
	2182
	2183	// crszone(sys23ev2) has a different configuration, are they hardwired or configured by software? (where?)..
	2184	// level 3: C422/subcpu
	2185	// level 4: vblank
	2186	// level 5: C451/C361
	2187	// level 6: C450
	2188	}
	2189
2543	2190	INTERRUPT_GEN_MEMBER(namcos23_state::s23_interrupt)
2544	2191	{
2545	2192	if (!m_ctl_vbl_active)
r19732	r19733
2552	2199	m_render.count[m_render.cur] = 0;
2553	2200	}
2554	2201
2555		void namcos23_state::machine_start()
	2202
	2203
	2204	// C417
	2205
	2206	READ16_MEMBER(namcos23_state::s23_c417_r)
2556	2207	{
2557		m_c361.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(namcos23_state::c361_timer_cb),this));
2558		m_c361.timer->adjust(attotime::never);
	2208	switch (offset)
	2209	{
	2210	/* According to timecrs2c, +0 is the status word with bits being:
	2211	15: test mode flag (huh?)
	2212	10: fifo data ready
	2213	9:  cmd ram data ready
	2214	8:  matrix busy
	2215	7:  output unit busy (inverted)
	2216	6:  hokan/tenso unit busy
	2217	5:  point unit busy
	2218	4:  access unit busy
	2219	3:  c403 busy (inverted)
	2220	2:  2nd c435 busy (inverted)
	2221	1:  1st c435 busy (inverted)
	2222	0:  xcpreq
	2223	*/
	2224	case 0:
	2225	return 0x8e | (machine().primary_screen->vblank() ? 0x0000 : 0x8000);
	2226	case 1:
	2227	return m_c417.adr;
	2228	case 4:
	2229	//logerror("c417_r %04x = %04x (%08x, %08x)\n", c417.adr, c417.ram[c417.adr], space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2230	return m_c417.ram[m_c417.adr];
	2231	case 5:
	2232	if (m_c417.pointrom_adr >= m_ptrom_limit)
	2233	return 0xffff;
	2234	return m_ptrom[m_c417.pointrom_adr] >> 16;
	2235	case 6:
	2236	if (m_c417.pointrom_adr >= m_ptrom_limit)
	2237	return 0xffff;
	2238	return m_ptrom[m_c417.pointrom_adr];
	2239	}
2559	2240
2560		mips3drc_add_fastram(m_maincpu, 0, m_mainram.bytes()-1, FALSE, reinterpret_cast<UINT32 *>(machine().root_device().memshare("mainram")->ptr()));
	2241	logerror("c417_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2242	return 0;
2561	2243	}
2562	2244
	2245	WRITE16_MEMBER(namcos23_state::s23_c417_w)
	2246	{
	2247	switch (offset)
	2248	{
	2249	case 0:
	2250	logerror("p3d PIO %04x\n", data);
	2251	break;
	2252	case 1:
	2253	COMBINE_DATA(&m_c417.adr);
	2254	break;
	2255	case 2:
	2256	m_c417.pointrom_adr = (m_c417.pointrom_adr << 16) | data;
	2257	break;
	2258	case 3:
	2259	m_c417.pointrom_adr = 0;
	2260	break;
	2261	case 4:
	2262	//logerror("c417_w %04x = %04x (%08x, %08x)\n", c417.adr, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2263	COMBINE_DATA(m_c417.ram + m_c417.adr);
	2264	break;
	2265	case 7:
	2266	logerror("c417_w: ack IRQ 2 (%x)\n", data);
	2267	update_main_interrupts(m_main_irqcause & ~MAIN_C435_IRQ);
	2268	break;
	2269	default:
	2270	logerror("c417_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2271	break;
	2272	}
	2273	}
	2274
	2275
	2276
	2277	// C412
	2278
	2279	READ16_MEMBER(namcos23_state::s23_c412_ram_r)
	2280	{
	2281	//  logerror("c412_ram_r %06x (%08x, %08x)\n", offset, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2282	if(offset < 0x100000)
	2283	return m_c412.sdram_a[offset & 0xfffff];
	2284	else if(offset < 0x200000)
	2285	return m_c412.sdram_b[offset & 0xfffff];
	2286	else if(offset < 0x220000)
	2287	return m_c412.sram   [offset & 0x1ffff];
	2288	else if(offset < 0x220200)
	2289	return m_c412.pczram [offset & 0x001ff];
	2290
	2291	return 0xffff;
	2292	}
	2293
	2294	WRITE16_MEMBER(namcos23_state::s23_c412_ram_w)
	2295	{
	2296	//  logerror("c412_ram_w %06x = %04x (%08x, %08x)\n", offset, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2297	if(offset < 0x100000)
	2298	COMBINE_DATA(m_c412.sdram_a + (offset & 0xfffff));
	2299	else if(offset < 0x200000)
	2300	COMBINE_DATA(m_c412.sdram_b + (offset & 0xfffff));
	2301	else if(offset < 0x220000)
	2302	COMBINE_DATA(m_c412.sram    + (offset & 0x1ffff));
	2303	else if(offset < 0x220200)
	2304	COMBINE_DATA(m_c412.pczram  + (offset & 0x001ff));
	2305	}
	2306
	2307	READ16_MEMBER(namcos23_state::s23_c412_r)
	2308	{
	2309	switch (offset)
	2310	{
	2311	case 0x3:
	2312	return 0x0002; // 0001 = busy, 0002 = game uploads things
	2313	case 0x8:
	2314	return m_c412.adr;
	2315	case 0x9:
	2316	return m_c412.adr >> 16;
	2317	case 0xa:
	2318	return s23_c412_ram_r(space, m_c412.adr, mem_mask);
	2319	case 0xc:
	2320	// unknown status, 500gp reads it and waits for a transition
	2321	// no other games use it?
	2322	m_c412.status_c ^= 1;
	2323	return m_c412.status_c;
	2324	}
	2325
	2326	logerror("c412_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2327	return 0;
	2328	}
	2329
	2330	WRITE16_MEMBER(namcos23_state::s23_c412_w)
	2331	{
	2332	switch (offset)
	2333	{
	2334	case 0x2:
	2335	// d0: cz on
	2336	// other bits: no function?
	2337	break;
	2338	case 0x8:
	2339	m_c412.adr = (data & mem_mask) | (m_c412.adr & (0xffffffff ^ mem_mask));
	2340	break;
	2341	case 0x9:
	2342	m_c412.adr = ((data & mem_mask) << 16) | (m_c412.adr & (0xffffffff ^ (mem_mask << 16)));
	2343	break;
	2344	case 0xa:
	2345	s23_c412_ram_w(space, m_c412.adr, data, mem_mask);
	2346	m_c412.adr += 2;
	2347	break;
	2348	default:
	2349	logerror("c412_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2350	break;
	2351	}
	2352	}
	2353
	2354
	2355
	2356	// C421
	2357
	2358	READ16_MEMBER(namcos23_state::s23_c421_ram_r)
	2359	{
	2360	//  logerror("c421_ram_r %06x (%08x, %08x)\n", offset, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2361	if(offset < 0x40000)
	2362	return m_c421.dram_a[offset & 0x3ffff];
	2363	else if(offset < 0x80000)
	2364	return m_c421.dram_b[offset & 0x3ffff];
	2365	else if(offset < 0x88000)
	2366	return m_c421.sram  [offset & 0x07fff];
	2367
	2368	return 0xffff;
	2369	}
	2370
	2371	WRITE16_MEMBER(namcos23_state::s23_c421_ram_w)
	2372	{
	2373	//  logerror("c421_ram_w %06x = %04x (%08x, %08x)\n", offset, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2374	if(offset < 0x40000)
	2375	COMBINE_DATA(m_c421.dram_a + (offset & 0x3ffff));
	2376	else if(offset < 0x80000)
	2377	COMBINE_DATA(m_c421.dram_b + (offset & 0x3ffff));
	2378	else if(offset < 0x88000)
	2379	COMBINE_DATA(m_c421.sram   + (offset & 0x07fff));
	2380	}
	2381
	2382	READ16_MEMBER(namcos23_state::s23_c421_r)
	2383	{
	2384	switch (offset)
	2385	{
	2386	case 0:
	2387	return s23_c421_ram_r(space, m_c421.adr & 0xfffff, mem_mask);
	2388
	2389	case 2:
	2390	return m_c421.adr >> 16;
	2391	case 3:
	2392	return m_c421.adr;
	2393	}
	2394
	2395	logerror("c421_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2396	return 0;
	2397	}
	2398
	2399	WRITE16_MEMBER(namcos23_state::s23_c421_w)
	2400	{
	2401	switch (offset)
	2402	{
	2403	case 0:
	2404	s23_c421_ram_w(space, m_c421.adr & 0xfffff, data, mem_mask);
	2405	m_c421.adr += 2;
	2406	break;
	2407	case 2:
	2408	m_c421.adr = ((data & mem_mask) << 16) | (m_c421.adr & (0xffffffff ^ (mem_mask << 16)));
	2409	break;
	2410	case 3:
	2411	m_c421.adr = (data & mem_mask) | (m_c421.adr & (0xffffffff ^ mem_mask));
	2412	break;
	2413	default:
	2414	logerror("c421_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2415	break;
	2416	}
	2417	}
	2418
	2419
	2420
	2421	// C422
	2422
	2423	READ16_MEMBER(namcos23_state::s23_c422_r)
	2424	{
	2425	return m_c422.regs[offset];
	2426	}
	2427
	2428	WRITE16_MEMBER(namcos23_state::s23_c422_w)
	2429	{
	2430	switch (offset)
	2431	{
	2432	case 1:
	2433	if (data == 0xfffb)
	2434	{
	2435	logerror("c422_w: raise IRQ 3\n");
	2436	update_main_interrupts(m_main_irqcause | MAIN_C422_IRQ);
	2437	}
	2438	else if (data == 0x000f)
	2439	{
	2440	logerror("c422_w: ack IRQ 3\n");
	2441	update_main_interrupts(m_main_irqcause & ~MAIN_C422_IRQ);
	2442	}
	2443	break;
	2444
	2445	default:
	2446	logerror("c422_w: %04x @ %x\n", data, offset);
	2447	break;
	2448	}
	2449
	2450	COMBINE_DATA(&m_c422.regs[offset]);
	2451	}
	2452
	2453
	2454
	2455	// C361 (text)
	2456
	2457	TIMER_CALLBACK_MEMBER(namcos23_state::c361_timer_cb)
	2458	{
	2459	if (m_c361.scanline != 0x1ff)
	2460	{
	2461	// need to do a partial update here, but doesn't work properly yet
	2462	//machine().primary_screen->update_partial(machine().primary_screen->vpos());
	2463	update_main_interrupts(m_main_irqcause | MAIN_C361_IRQ);
	2464
	2465	// TC2 indicates it's probably one-shot since it resets it each VBL...
	2466	//c361.timer->adjust(machine().primary_screen->time_until_pos(c361.scanline));
	2467	}
	2468	else
	2469	update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
	2470	}
	2471
	2472	WRITE16_MEMBER(namcos23_state::s23_c361_w)
	2473	{
	2474	switch (offset)
	2475	{
	2476	case 0:
	2477	m_bgtilemap->set_scrollx(0, data&0xfff);
	2478	break;
	2479
	2480	case 1:
	2481	m_bgtilemap->set_scrolly(0, data&0xfff);
	2482	break;
	2483
	2484	case 4:   // interrupt control
	2485	m_c361.scanline = data & 0x1ff;
	2486	m_c361.timer->adjust(machine().primary_screen->time_until_pos(m_c361.scanline));
	2487	break;
	2488
	2489	default:
	2490	logerror("c361_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2491	break;
	2492	}
	2493	}
	2494
	2495	READ16_MEMBER(namcos23_state::s23_c361_r)
	2496	{
	2497	switch (offset)
	2498	{
	2499	// current raster position
	2500	// how does it work exactly? it's not understood in namcos22 either (also has a c361)
	2501	case 5:
	2502	update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
	2503	return machine().primary_screen->vpos()*2 | (machine().primary_screen->vblank() ? 1 : 0);
	2504	case 6:
	2505	update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
	2506	return machine().primary_screen->vblank() ? 1 : 0;
	2507	}
	2508
	2509	logerror("c361_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2510	return 0xffff;
	2511	}
	2512
	2513
	2514
	2515	// C?? (control)
	2516
	2517	WRITE16_MEMBER(namcos23_state::s23_ctl_w)
	2518	{
	2519	switch (offset)
	2520	{
	2521	case 0:
	2522	if (m_ctl_led != (data & 0xff))
	2523	{
	2524	m_ctl_led = data & 0xff;
	2525	for (int i = 0; i < 8; i++)
	2526	output_set_lamp_value(i, (~data<<i & 0x80) ? 0 : 1);
	2527	}
	2528	break;
	2529
	2530	case 2: case 3:
	2531	// These may be coming from another CPU, in particular the I/O one
	2532	m_ctl_inp_buffer[offset-2] = ioport(offset == 2 ? "P1" : "P2")->read();
	2533	break;
	2534	case 5:
	2535	if(m_ctl_vbl_active)
	2536	{
	2537	m_ctl_vbl_active = false;
	2538	update_main_interrupts(m_main_irqcause & ~MAIN_VBLANK_IRQ);
	2539	}
	2540	break;
	2541
	2542	case 6:   // gmen wars spams this heavily with 0 prior to starting the GMEN board test
	2543	if (data != 0)
	2544	logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2545	break;
	2546
	2547	default:
	2548	logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2549	break;
	2550	}
	2551	}
	2552
	2553	READ16_MEMBER(namcos23_state::s23_ctl_r)
	2554	{
	2555	switch (offset)
	2556	{
	2557	// 0100 set freezes gorgon (polygon fifo flag)
	2558	case 1:
	2559	return 0x0000 | ioport("DSW")->read();
	2560	case 2: case 3:
	2561	{
	2562	UINT16 res = m_ctl_inp_buffer[offset-2] & 0x800 ? 0xffff : 0x0000;
	2563	m_ctl_inp_buffer[offset-2] = (m_ctl_inp_buffer[offset-2] << 1) | 1;
	2564	return res;
	2565	}
	2566	}
	2567
	2568	logerror("ctl_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2569	return 0xffff;
	2570	}
	2571
	2572
	2573
	2574	// C?? (MCU enable)
	2575
	2576	WRITE16_MEMBER(namcos23_state::s23_mcuen_w)
	2577	{
	2578	switch (offset)
	2579	{
	2580	case 2:
	2581	// subcpu irq ack
	2582	update_main_interrupts(m_main_irqcause & ~MAIN_SUBCPU_IRQ);
	2583	break;
	2584
	2585	case 5:
	2586	// boot/start the audio mcu
	2587	if (data)
	2588	{
	2589	logerror("mcuen_w: booting H8/3002\n");
	2590
	2591	// Panic Park: writing 1 when it's already running means reboot?
	2592	if (m_subcpu_running)
	2593	{
	2594	m_subcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
	2595	}
	2596
	2597	m_subcpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
	2598	m_subcpu_running = true;
	2599	}
	2600	else
	2601	{
	2602	logerror("mcuen_w: stopping H8/3002\n");
	2603	m_subcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
	2604	m_subcpu_running = false;
	2605	}
	2606	break;
	2607
	2608	default:
	2609	logerror("mcuen_w: mask %04x, data %04x @ %x\n", mem_mask, data, offset);
	2610	break;
	2611	}
	2612	}
	2613
	2614
	2615
	2616	// C?? (unknown comms)
	2617
	2618	// while getting the subcpu to be ready, panicprk sits in a tight loop waiting for this AND 0002 to be non-zero (at PC=BFC02F00)
	2619	// timecrs2 locks up in a similar way as panicprk, at the beginning of the 2nd level, by reading/writing to this register a couple of times
	2620	READ16_MEMBER(namcos23_state::s23_sub_comm_r)
	2621	{
	2622	return 2;
	2623	}
	2624
	2625	WRITE16_MEMBER(namcos23_state::s23_sub_comm_w)
	2626	{
	2627	;
	2628	}
	2629
	2630
	2631	// System Gorgon
2563	2632	static ADDRESS_MAP_START( gorgon_map, AS_PROGRAM, 32, namcos23_state )
2564	2633	ADDRESS_MAP_GLOBAL_MASK(0xfffffff)
2565	2634	AM_RANGE(0x00000000, 0x003fffff) AM_RAM AM_SHARE("mainram")
r19732	r19733
2584	2653	AM_RANGE(0x0fc00000, 0x0fffffff) AM_WRITENOP AM_ROM AM_REGION("user1", 0)
2585	2654	ADDRESS_MAP_END
2586	2655
2587		static ADDRESS_MAP_START( ss23_map, AS_PROGRAM, 32, namcos23_state )
	2656	// (Super) System 23
	2657	static ADDRESS_MAP_START( s23_map, AS_PROGRAM, 32, namcos23_state )
2588	2658	ADDRESS_MAP_GLOBAL_MASK(0xfffffff)
2589	2659	AM_RANGE(0x00000000, 0x00ffffff) AM_RAM AM_SHARE("mainram")
2590	2660	AM_RANGE(0x01000000, 0x010000ff) AM_READWRITE(p3d_r, p3d_w)
r19732	r19733
2608	2678	AM_RANGE(0x0fc00000, 0x0fffffff) AM_WRITENOP AM_ROM AM_REGION("user1", 0)
2609	2679	ADDRESS_MAP_END
2610	2680
	2681
	2682
	2683	// GMEN interface
	2684
2611	2685	READ32_MEMBER(namcos23_state::gmen_trigger_sh2)
2612	2686	{
2613	2687	logerror("gmen_trigger_sh2: booting SH-2\n");
r19732	r19733
2627	2701	}
2628	2702
2629	2703	static ADDRESS_MAP_START( gmen_mips_map, AS_PROGRAM, 32, namcos23_state )
2630		AM_IMPORT_FROM(ss23_map)
2631		AM_RANGE(0x0e400000, 0x0e400003) AM_READ(gmen_trigger_sh2 )
2632		AM_RANGE(0x0e700000, 0x0e707fff) AM_READWRITE(sh2_shared_r, sh2_shared_w )
	2704	AM_IMPORT_FROM(s23_map)
	2705	AM_RANGE(0x0e400000, 0x0e400003) AM_READ(gmen_trigger_sh2)
	2706	AM_RANGE(0x0e700000, 0x0e707fff) AM_READWRITE(sh2_shared_r, sh2_shared_w)
2633	2707	ADDRESS_MAP_END
2634	2708
2635	2709
	2710	// SH2 memmap
2636	2711	static ADDRESS_MAP_START( gmen_sh2_map, AS_PROGRAM, 32, namcos23_state )
2637	2712	AM_RANGE(0x00000000, 0x00007fff) AM_RAM AM_SHARE("gmen_sh2_shared")
2638	2713	AM_RANGE(0x04000000, 0x043fffff) AM_RAM   // SH-2 main work RAM
2639	2714	ADDRESS_MAP_END
2640	2715
2641		MACHINE_RESET_MEMBER(namcos23_state,gmen)
2642		{
2643		machine_reset();
2644	2716
2645		// halt the SH-2 until we need it
2646		m_gmen_sh2->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
2647		}
2648	2717
	2718
	2719
	2720	/***************************************************************************
	2721
	2722	Sub CPU (H8/3002 MCU) I/O + Memory Map
	2723
	2724	***************************************************************************/
	2725
2649	2726	WRITE16_MEMBER(namcos23_state::sharedram_sub_w)
2650	2727	{
2651	2728	UINT16 *shared16 = reinterpret_cast<UINT16 *>(m_shared_ram.target());
r19732	r19733
2669	2746	return shared16[BYTE_XOR_BE(offset)];
2670	2747	}
2671	2748
	2749
2672	2750	WRITE16_MEMBER(namcos23_state::sub_interrupt_main_w)
2673	2751	{
2674	2752	if  ((mem_mask == 0xffff) && (data == 0x3170))
r19732	r19733
2681	2759	}
2682	2760	}
2683	2761
2684		/* H8/3002 MCU stuff */
2685		static ADDRESS_MAP_START( s23h8rwmap, AS_PROGRAM, 16, namcos23_state )
2686		AM_RANGE(0x000000, 0x07ffff) AM_ROM
2687		AM_RANGE(0x080000, 0x08ffff) AM_READWRITE(sharedram_sub_r, sharedram_sub_w )
2688		AM_RANGE(0x280000, 0x287fff) AM_DEVREADWRITE("c352", c352_device, read, write)
2689		AM_RANGE(0x300000, 0x300003) AM_NOP   // seems to be more inputs, maybe false leftover code from System 12?
2690		AM_RANGE(0x300010, 0x300011) AM_NOP
2691		AM_RANGE(0x300020, 0x300021) AM_WRITE(sub_interrupt_main_w )
2692		AM_RANGE(0x300030, 0x300031) AM_WRITENOP   // timecrs2 writes this when writing to the sync shared ram location, motoxgo doesn't
2693		ADDRESS_MAP_END
2694	2762
2695		// port 8, looks like serial comms, where to/from?
	2763
	2764	// Port 6
	2765
	2766	READ8_MEMBER(namcos23_state::s23_mcu_p6_r)
	2767	{
	2768	// bit 1 = JVS cable present sense (1 = I/O board plugged in)
	2769	return (m_jvssense << 1) | 0xfd;
	2770	}
	2771
	2772	WRITE8_MEMBER(namcos23_state::s23_mcu_p6_w)
	2773	{
	2774	//printf("%02x to port 6\n", data);
	2775	}
	2776
	2777
	2778
	2779	// Port 8, looks like serial comms, where to/from?
	2780
2696	2781	READ8_MEMBER(namcos23_state::s23_mcu_p8_r)
2697	2782	{
2698	2783	return 0x02;
r19732	r19733
2703	2788	;
2704	2789	}
2705	2790
2706		// emulation of the Epson R4543 real time clock
2707		// in System 12, bit 0 of H8/3002 port A is connected to it's chip enable
2708		// the actual I/O takes place through the H8/3002's serial port B.
2709	2791
2710	2792
	2793	// Port A
	2794
2711	2795	READ8_MEMBER(namcos23_state::s23_mcu_pa_r)
2712	2796	{
2713	2797	return m_s23_porta;
r19732	r19733
2720	2804	m_s23_porta = data;
2721	2805	}
2722	2806
2723		READ8_MEMBER(namcos23_state::s23_mcu_rtc_r)
2724		{
2725		UINT8 ret = 0;
2726	2807
2727		for (int i = 0; i < 8; i++)
2728		{
2729		m_rtc->clk_w(0);
2730		m_rtc->clk_w(1);
2731		ret <<= 1;
2732		ret |= m_rtc->data_r();
2733		}
2734	2808
2735		return ret;
2736		}
	2809	// Port B
2737	2810
2738
2739	2811	READ8_MEMBER(namcos23_state::s23_mcu_pb_r)
2740	2812	{
2741	2813	m_s23_lastpb ^= 0x80;
r19732	r19733
2753	2825	m_s23_lastpb = data;
2754	2826	}
2755	2827
	2828
	2829
	2830	// Serial Port 0
	2831
	2832	READ8_MEMBER(namcos23_state::s23_mcu_iob_r)
	2833	{
	2834	UINT8 ret = m_iotomain[m_im_rd];
	2835
	2836	m_im_rd++;
	2837	m_im_rd &= 0x7f;
	2838
	2839	if (m_im_rd == m_im_wr)
	2840	{
	2841	m_subcpu->set_input_line(H8_SCI_0_RX, CLEAR_LINE);
	2842	}
	2843	else
	2844	{
	2845	m_subcpu->set_input_line(H8_SCI_0_RX, CLEAR_LINE);
	2846	m_subcpu->set_input_line(H8_SCI_0_RX, ASSERT_LINE);
	2847	}
	2848
	2849	return ret;
	2850	}
	2851
	2852	WRITE8_MEMBER(namcos23_state::s23_mcu_iob_w)
	2853	{
	2854	m_maintoio[m_mi_wr++] = data;
	2855	m_mi_wr &= 0x7f;
	2856
	2857	m_iocpu->set_input_line(H8_SCI_0_RX, ASSERT_LINE);
	2858	}
	2859
	2860
	2861
	2862	// Serial Port 1
	2863
	2864	READ8_MEMBER(namcos23_state::s23_mcu_rtc_r)
	2865	{
	2866	// emulation of the Epson R4543 real time clock
	2867	// in System 12, bit 0 of H8/3002 port A is connected to it's chip enable
	2868	// the actual I/O takes place through the H8/3002's serial port 1.
	2869	UINT8 ret = 0;
	2870
	2871	for (int i = 0; i < 8; i++)
	2872	{
	2873	m_rtc->clk_w(0);
	2874	m_rtc->clk_w(1);
	2875	ret <<= 1;
	2876	ret |= m_rtc->data_r();
	2877	}
	2878
	2879	return ret;
	2880	}
	2881
2756	2882	WRITE8_MEMBER(namcos23_state::s23_mcu_settings_w)
2757	2883	{
2758	2884	if (m_s23_setstate)
r19732	r19733
2778	2904	}
2779	2905
2780	2906
2781		READ8_MEMBER(namcos23_state::s23_mcu_iob_r)
	2907	static ADDRESS_MAP_START( s23h8rwmap, AS_PROGRAM, 16, namcos23_state )
	2908	AM_RANGE(0x000000, 0x07ffff) AM_ROM
	2909	AM_RANGE(0x080000, 0x08ffff) AM_READWRITE(sharedram_sub_r, sharedram_sub_w )
	2910	AM_RANGE(0x280000, 0x287fff) AM_DEVREADWRITE("c352", c352_device, read, write)
	2911	AM_RANGE(0x300000, 0x300003) AM_NOP   // seems to be more inputs, maybe false leftover code from System 12?
	2912	AM_RANGE(0x300010, 0x300011) AM_NOP
	2913	AM_RANGE(0x300020, 0x300021) AM_WRITE(sub_interrupt_main_w )
	2914	AM_RANGE(0x300030, 0x300031) AM_WRITENOP   // timecrs2 writes this when writing to the sync shared ram location, motoxgo doesn't
	2915	ADDRESS_MAP_END
	2916
	2917
	2918	static ADDRESS_MAP_START( s23h8iomap, AS_IO, 8, namcos23_state )
	2919	AM_RANGE(H8_PORT_6, H8_PORT_6) AM_READWRITE(s23_mcu_p6_r, s23_mcu_p6_w )
	2920	AM_RANGE(H8_PORT_8, H8_PORT_8) AM_READWRITE(s23_mcu_p8_r, s23_mcu_p8_w )
	2921	AM_RANGE(H8_PORT_A, H8_PORT_A) AM_READWRITE(s23_mcu_pa_r, s23_mcu_pa_w )
	2922	AM_RANGE(H8_PORT_B, H8_PORT_B) AM_READWRITE(s23_mcu_pb_r, s23_mcu_pb_w )
	2923	AM_RANGE(H8_SERIAL_0, H8_SERIAL_0) AM_READWRITE(s23_mcu_iob_r, s23_mcu_iob_w )
	2924	AM_RANGE(H8_SERIAL_1, H8_SERIAL_1) AM_READWRITE(s23_mcu_rtc_r, s23_mcu_settings_w )
	2925	AM_RANGE(H8_ADC_0_H, H8_ADC_0_L) AM_NOP
	2926	AM_RANGE(H8_ADC_1_H, H8_ADC_1_L) AM_NOP
	2927	AM_RANGE(H8_ADC_2_H, H8_ADC_2_L) AM_NOP
	2928	AM_RANGE(H8_ADC_3_H, H8_ADC_3_L) AM_NOP
	2929	ADDRESS_MAP_END
	2930
	2931	// version without serial hookup to I/O board for games where the PIC isn't dumped
	2932	static ADDRESS_MAP_START( s23h8noiobmap, AS_IO, 8, namcos23_state )
	2933	AM_RANGE(H8_PORT_6, H8_PORT_6) AM_READWRITE(s23_mcu_p6_r, s23_mcu_p6_w )
	2934	AM_RANGE(H8_PORT_8, H8_PORT_8) AM_READWRITE(s23_mcu_p8_r, s23_mcu_p8_w )
	2935	AM_RANGE(H8_PORT_A, H8_PORT_A) AM_READWRITE(s23_mcu_pa_r, s23_mcu_pa_w )
	2936	AM_RANGE(H8_PORT_B, H8_PORT_B) AM_READWRITE(s23_mcu_pb_r, s23_mcu_pb_w )
	2937	AM_RANGE(H8_SERIAL_1, H8_SERIAL_1) AM_READWRITE(s23_mcu_rtc_r, s23_mcu_settings_w )
	2938	AM_RANGE(H8_ADC_0_H, H8_ADC_0_L) AM_NOP
	2939	AM_RANGE(H8_ADC_1_H, H8_ADC_1_L) AM_NOP
	2940	AM_RANGE(H8_ADC_2_H, H8_ADC_2_L) AM_NOP
	2941	AM_RANGE(H8_ADC_3_H, H8_ADC_3_L) AM_NOP
	2942	ADDRESS_MAP_END
	2943
	2944
	2945
	2946
	2947
	2948	/***************************************************************************
	2949
	2950	I/O Board (H8/3334 MCU "Namco C78") I/O + Memory Map
	2951
	2952	***************************************************************************/
	2953
	2954	// Port 4
	2955
	2956	READ8_MEMBER(namcos23_state::s23_iob_p4_r)
2782	2957	{
2783		UINT8 ret = m_iotomain[m_im_rd];
	2958	return m_s23_tssio_port_4;
	2959	}
2784	2960
2785		m_im_rd++;
2786		m_im_rd &= 0x7f;
	2961	WRITE8_MEMBER(namcos23_state::s23_iob_p4_w)
	2962	{
	2963	m_s23_tssio_port_4 = data;
2787	2964
2788		if (m_im_rd == m_im_wr)
	2965	// bit 2 = SENSE line back to main (0 = asserted, 1 = dropped)
	2966	m_jvssense = (data & 0x04) ? 0 : 1;
	2967	}
	2968
	2969
	2970
	2971	// Port 6
	2972
	2973	READ8_MEMBER(namcos23_state::s23_iob_p6_r)
	2974	{
	2975	// d4 is service button
	2976	UINT8 sb = (ioport("SERVICE")->read() & 1) << 4;
	2977	// other bits: unknown
	2978
	2979	return sb | 0;
	2980	}
	2981
	2982	WRITE8_MEMBER(namcos23_state::s23_iob_p6_w)
	2983	{
	2984	//printf("iob %02x to port 6\n", data);
	2985	}
	2986
	2987
	2988
	2989	// Serial Port 0
	2990
	2991	READ8_MEMBER(namcos23_state::s23_iob_mcu_r)
	2992	{
	2993	UINT8 ret = m_maintoio[m_mi_rd];
	2994
	2995	m_mi_rd++;
	2996	m_mi_rd &= 0x7f;
	2997
	2998	if (m_mi_rd == m_mi_wr)
2789	2999	{
2790		m_audiocpu->set_input_line(H8_SCI_0_RX, CLEAR_LINE);
	3000	m_iocpu->set_input_line(H8_SCI_0_RX, CLEAR_LINE);
2791	3001	}
2792		else
2793		{
2794		m_audiocpu->set_input_line(H8_SCI_0_RX, CLEAR_LINE);
2795		m_audiocpu->set_input_line(H8_SCI_0_RX, ASSERT_LINE);
2796		}
2797	3002
2798	3003	return ret;
2799	3004	}
2800	3005
2801		WRITE8_MEMBER(namcos23_state::s23_mcu_iob_w)
	3006	WRITE8_MEMBER(namcos23_state::s23_iob_mcu_w)
2802	3007	{
2803		m_maintoio[m_mi_wr++] = data;
2804		m_mi_wr &= 0x7f;
	3008	m_iotomain[m_im_wr++] = data;
	3009	m_im_wr &= 0x7f;
2805	3010
2806		m_iocpu->set_input_line(H8_SCI_0_RX, ASSERT_LINE);
	3011	m_subcpu->set_input_line(H8_SCI_0_RX, ASSERT_LINE);
2807	3012	}
2808	3013
2809		static INPUT_PORTS_START( gorgon )
	3014
	3015
	3016	// Analog Ports
	3017
	3018	READ8_MEMBER(namcos23_state::s23_iob_analog_r)
	3019	{
	3020	static const char *const portnames[] = { "ADC0", "ADC1", "ADC2", "ADC3" };
	3021	if (offset & 1)
	3022	return ioport(portnames[offset >> 1 & 3])->read_safe(0) >> 8 & 0xff;
	3023	else
	3024	return ioport(portnames[offset >> 1 & 3])->read_safe(0) & 0xff;
	3025	}
	3026
	3027
	3028	static ADDRESS_MAP_START( s23iobrdmap, AS_PROGRAM, 8, namcos23_state )
	3029	AM_RANGE(0x0000, 0x1fff) AM_ROM AM_REGION("iocpu", 0)
	3030	AM_RANGE(0x6000, 0x6000) AM_READ_PORT("IN0")
	3031	AM_RANGE(0x6001, 0x6001) AM_READ_PORT("IN1")
	3032	AM_RANGE(0x6002, 0x6002) AM_READ_PORT("IN2")
	3033	AM_RANGE(0x6003, 0x6003) AM_READ_PORT("IN3")
	3034	AM_RANGE(0x6004, 0x6005) AM_WRITENOP
	3035	AM_RANGE(0x6006, 0x6007) AM_NOP
	3036
	3037	AM_RANGE(0xc000, 0xf7ff) AM_RAM
	3038	ADDRESS_MAP_END
	3039
	3040	static ADDRESS_MAP_START( s23iobrdiomap, AS_IO, 8, namcos23_state )
	3041	AM_RANGE(H8_PORT_4, H8_PORT_4) AM_READWRITE(s23_iob_p4_r, s23_iob_p4_w)
	3042	AM_RANGE(H8_PORT_5, H8_PORT_5) AM_NOP   // bit 2 = status LED to indicate transmitting packet to main
	3043	AM_RANGE(H8_PORT_6, H8_PORT_6) AM_READWRITE(s23_iob_p6_r, s23_iob_p6_w)
	3044	AM_RANGE(H8_PORT_8, H8_PORT_8) AM_NOP   // unknown - used on ASCA-5 only
	3045	AM_RANGE(H8_PORT_9, H8_PORT_9) AM_NOP   // unknown - used on ASCA-5 only
	3046	AM_RANGE(H8_SERIAL_0, H8_SERIAL_0) AM_READWRITE(s23_iob_mcu_r, s23_iob_mcu_w)
	3047	AM_RANGE(H8_ADC_0_H, H8_ADC_3_L) AM_READ(s23_iob_analog_r)
	3048	ADDRESS_MAP_END
	3049
	3050
	3051
	3052	// Time Crisis lightgun
	3053
	3054	READ8_MEMBER(namcos23_state::s23_iob_gun_r)
	3055	{
	3056	UINT16 xpos = ioport("LIGHTX")->read();
	3057	UINT16 ypos = ioport("LIGHTY")->read();
	3058	// ypos is not completely understood yet, there should be a difference between case 1/4 and 2/5
	3059
	3060	switch(offset)
	3061	{
	3062	case 0: return xpos&0xff;
	3063	case 3: return xpos>>8;
	3064	case 1: return ypos&0xff;
	3065	case 4: return ypos>>8;
	3066	case 2: return ypos&0xff;
	3067	case 5: return ypos>>8;
	3068	default: break;
	3069	}
	3070
	3071	return 0;
	3072	}
	3073
	3074	static ADDRESS_MAP_START( timecrs2iobrdmap, AS_PROGRAM, 8, namcos23_state )
	3075	AM_RANGE(0x7000, 0x700f) AM_READ(s23_iob_gun_r)
	3076	AM_IMPORT_FROM( s23iobrdmap )
	3077	ADDRESS_MAP_END
	3078
	3079
	3080
	3081
	3082
	3083	/***************************************************************************
	3084
	3085	Inputs
	3086
	3087	***************************************************************************/
	3088
	3089	static INPUT_PORTS_START( rapidrvr )
2810	3090	PORT_START("P1")
2811	3091	PORT_BIT( 0xfff, IP_ACTIVE_LOW, IPT_UNKNOWN )
2812	3092
r19732	r19733
2861	3141	PORT_SERVICE_DIPLOC(0x80, IP_ACTIVE_LOW, "DIP:1" )
2862	3142	INPUT_PORTS_END
2863	3143
2864		static INPUT_PORTS_START( finfurl )
2865		PORT_INCLUDE( gorgon )
2866	3144
2867		PORT_MODIFY("IN0")
2868		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT )
2869		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
2870
2871		#if 0 // need to hook these up properly
2872		PORT_START("ADC0")
2873		PORT_BIT( 0xffff, 0x8000, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(100) PORT_NAME("ADC0")
2874		PORT_START("ADC1")
2875		PORT_BIT( 0xffff, 0x8000, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(100) PORT_NAME("ADC1")
2876		PORT_START("ADC2")
2877		PORT_BIT( 0xffff, 0x8000, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(100) PORT_NAME("ADC2")
2878		PORT_START("ADC3")
2879		PORT_BIT( 0xffff, 0x8000, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(100) PORT_NAME("ADC3")
2880		#endif
2881		INPUT_PORTS_END
2882
2883	3145	static INPUT_PORTS_START( rapidrvrp )
2884		PORT_INCLUDE( gorgon )
	3146	PORT_INCLUDE( rapidrvr )
2885	3147
2886	3148	// To fully use test mode, both Service Mode dipswitches need to be enabled.
2887	3149	// Some of the developer menus require you to navigate with the Dev keys,
r19732	r19733
2931	3193	#endif
2932	3194	INPUT_PORTS_END
2933	3195
	3196
	3197	static INPUT_PORTS_START( finfurl )
	3198	PORT_INCLUDE( rapidrvr )
	3199
	3200	PORT_MODIFY("IN0")
	3201	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT )
	3202	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
	3203
	3204	#if 0 // need to hook these up properly
	3205	PORT_START("ADC0")
	3206	PORT_BIT( 0xffff, 0x8000, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(100) PORT_NAME("ADC0")
	3207	PORT_START("ADC1")
	3208	PORT_BIT( 0xffff, 0x8000, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(100) PORT_NAME("ADC1")
	3209	PORT_START("ADC2")
	3210	PORT_BIT( 0xffff, 0x8000, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(100) PORT_NAME("ADC2")
	3211	PORT_START("ADC3")
	3212	PORT_BIT( 0xffff, 0x8000, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(100) PORT_NAME("ADC3")
	3213	#endif
	3214	INPUT_PORTS_END
	3215
	3216
2934	3217	static INPUT_PORTS_START( s23 )
2935	3218	// No idea if start is actually there, but we need buttons to pass error screens
2936	3219	// You can go to the pcb test mode by pressing start, and it doesn't crash anymore somehow
r19732	r19733
2994	3277	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
2995	3278	INPUT_PORTS_END
2996	3279
	3280
2997	3281	static INPUT_PORTS_START( timecrs2 )
2998	3282	PORT_INCLUDE( s23 )
2999	3283
r19732	r19733
3003	3287	PORT_BIT( 0xfff, 38+247/2, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_MINMAX(38, 38+247) PORT_SENSITIVITY(64) PORT_KEYDELTA(4)
3004	3288	INPUT_PORTS_END
3005	3289
	3290
3006	3291	static INPUT_PORTS_START( ss23 )
3007	3292	// No idea if start is actually there, but we need buttons to pass error screens
3008	3293	// You can go to the pcb test mode by pressing start, and it doesn't crash anymore somehow
r19732	r19733
3067	3352	INPUT_PORTS_END
3068	3353
3069	3354
3070		READ8_MEMBER(namcos23_state::s23_mcu_p6_r)
3071		{
3072		// bit 1 = JVS cable present sense (1 = I/O board plugged in)
3073		return (m_jvssense << 1) | 0xfd;
3074		}
3075	3355
3076		WRITE8_MEMBER(namcos23_state::s23_mcu_p6_w)
3077		{
3078		//printf("%02x to port 6\n", data);
3079		}
3080	3356
3081		static ADDRESS_MAP_START( s23h8iomap, AS_IO, 8, namcos23_state )
3082		AM_RANGE(H8_PORT_6, H8_PORT_6) AM_READWRITE(s23_mcu_p6_r, s23_mcu_p6_w )
3083		AM_RANGE(H8_PORT_8, H8_PORT_8) AM_READWRITE(s23_mcu_p8_r, s23_mcu_p8_w )
3084		AM_RANGE(H8_PORT_A, H8_PORT_A) AM_READWRITE(s23_mcu_pa_r, s23_mcu_pa_w )
3085		AM_RANGE(H8_PORT_B, H8_PORT_B) AM_READWRITE(s23_mcu_pb_r, s23_mcu_pb_w )
3086		AM_RANGE(H8_SERIAL_0, H8_SERIAL_0) AM_READWRITE(s23_mcu_iob_r, s23_mcu_iob_w )
3087		AM_RANGE(H8_SERIAL_1, H8_SERIAL_1) AM_READWRITE(s23_mcu_rtc_r, s23_mcu_settings_w )
3088		AM_RANGE(H8_ADC_0_H, H8_ADC_0_L) AM_NOP
3089		AM_RANGE(H8_ADC_1_H, H8_ADC_1_L) AM_NOP
3090		AM_RANGE(H8_ADC_2_H, H8_ADC_2_L) AM_NOP
3091		AM_RANGE(H8_ADC_3_H, H8_ADC_3_L) AM_NOP
3092		ADDRESS_MAP_END
3093	3357
3094		// version without serial hookup to I/O board for games where the PIC isn't dumped
3095		static ADDRESS_MAP_START( s23h8noiobmap, AS_IO, 8, namcos23_state )
3096		AM_RANGE(H8_PORT_6, H8_PORT_6) AM_READWRITE(s23_mcu_p6_r, s23_mcu_p6_w )
3097		AM_RANGE(H8_PORT_8, H8_PORT_8) AM_READWRITE(s23_mcu_p8_r, s23_mcu_p8_w )
3098		AM_RANGE(H8_PORT_A, H8_PORT_A) AM_READWRITE(s23_mcu_pa_r, s23_mcu_pa_w )
3099		AM_RANGE(H8_PORT_B, H8_PORT_B) AM_READWRITE(s23_mcu_pb_r, s23_mcu_pb_w )
3100		AM_RANGE(H8_SERIAL_1, H8_SERIAL_1) AM_READWRITE(s23_mcu_rtc_r, s23_mcu_settings_w )
3101		AM_RANGE(H8_ADC_0_H, H8_ADC_0_L) AM_NOP
3102		AM_RANGE(H8_ADC_1_H, H8_ADC_1_L) AM_NOP
3103		AM_RANGE(H8_ADC_2_H, H8_ADC_2_L) AM_NOP
3104		AM_RANGE(H8_ADC_3_H, H8_ADC_3_L) AM_NOP
3105		ADDRESS_MAP_END
	3358	/***************************************************************************
3106	3359
	3360	Machine Drivers
3107	3361
3108		READ8_MEMBER(namcos23_state::s23_iob_mcu_r)
3109		{
3110		UINT8 ret = m_maintoio[m_mi_rd];
	3362	***************************************************************************/
3111	3363
3112		m_mi_rd++;
3113		m_mi_rd &= 0x7f;
3114
3115		if (m_mi_rd == m_mi_wr)
3116		{
3117		m_iocpu->set_input_line(H8_SCI_0_RX, CLEAR_LINE);
3118		}
3119
3120		return ret;
3121		}
3122
3123		WRITE8_MEMBER(namcos23_state::s23_iob_mcu_w)
	3364	void namcos23_state::machine_start()
3124	3365	{
3125		m_iotomain[m_im_wr++] = data;
3126		m_im_wr &= 0x7f;
	3366	m_c361.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(namcos23_state::c361_timer_cb),this));
	3367	m_c361.timer->adjust(attotime::never);
3127	3368
3128		m_audiocpu->set_input_line(H8_SCI_0_RX, ASSERT_LINE);
	3369	mips3drc_add_fastram(m_maincpu, 0, m_mainram.bytes()-1, FALSE, reinterpret_cast<UINT32 *>(machine().root_device().memshare("mainram")->ptr()));
3129	3370	}
3130	3371
3131	3372
3132		READ8_MEMBER(namcos23_state::s23_iob_p4_r)
	3373	void namcos23_state::machine_reset()
3133	3374	{
3134		return m_s23_tssio_port_4;
	3375	m_subcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
3135	3376	}
3136	3377
3137		WRITE8_MEMBER(namcos23_state::s23_iob_p4_w)
	3378	MACHINE_RESET_MEMBER(namcos23_state,gmen)
3138	3379	{
3139		m_s23_tssio_port_4 = data;
	3380	machine_reset();
3140	3381
3141		m_jvssense = (data & 0x04) ? 0 : 1;
	3382	// halt the SH-2 until we need it
	3383	m_gmen_sh2->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
3142	3384	}
3143	3385
3144		READ8_MEMBER(namcos23_state::s23_iob_p6_r)
3145		{
3146		// d4 is service button
3147		UINT8 sb = (ioport("SERVICE")->read() & 1) << 4;
3148		// other bits: unknown
3149	3386
3150		return sb | 0;
3151		}
3152	3387
3153		WRITE8_MEMBER(namcos23_state::s23_iob_p6_w)
	3388	DRIVER_INIT_MEMBER(namcos23_state,s23)
3154	3389	{
3155		//printf("iob %02x to port 6\n", data);
3156		}
3157
3158		READ8_MEMBER(namcos23_state::s23_iob_gun_r)
3159		{
3160		UINT16 xpos = ioport("LIGHTX")->read();
3161		UINT16 ypos = ioport("LIGHTY")->read();
3162		// ypos is not completely understood yet, there should be a difference between case 1/4 and 2/5
3163
3164		switch(offset)
3165		{
3166		case 0: return xpos&0xff;
3167		case 3: return xpos>>8;
3168		case 1: return ypos&0xff;
3169		case 4: return ypos>>8;
3170		case 2: return ypos&0xff;
3171		case 5: return ypos>>8;
3172		default: break;
3173		}
3174
3175		return 0;
3176		}
3177
3178		READ8_MEMBER(namcos23_state::s23_iob_analog_r)
3179		{
3180		static const char *const portnames[] = { "ADC0", "ADC1", "ADC2", "ADC3" };
3181		if (offset & 1)
3182		return ioport(portnames[offset >> 1 & 3])->read_safe(0) >> 8 & 0xff;
3183		else
3184		return ioport(portnames[offset >> 1 & 3])->read_safe(0) & 0xff;
3185		}
3186
3187		/* H8/3334 (Namco C78) I/O board MCU */
3188		static ADDRESS_MAP_START( s23iobrdmap, AS_PROGRAM, 8, namcos23_state )
3189		AM_RANGE(0x0000, 0x1fff) AM_ROM AM_REGION("iocpu", 0)
3190		AM_RANGE(0x6000, 0x6000) AM_READ_PORT("IN0")
3191		AM_RANGE(0x6001, 0x6001) AM_READ_PORT("IN1")
3192		AM_RANGE(0x6002, 0x6002) AM_READ_PORT("IN2")
3193		AM_RANGE(0x6003, 0x6003) AM_READ_PORT("IN3")
3194		AM_RANGE(0x6004, 0x6005) AM_WRITENOP
3195		AM_RANGE(0x6006, 0x6007) AM_NOP
3196
3197		AM_RANGE(0xc000, 0xf7ff) AM_RAM
3198		ADDRESS_MAP_END
3199
3200		static ADDRESS_MAP_START( timecrs2iobrdmap, AS_PROGRAM, 8, namcos23_state )
3201		AM_RANGE(0x7000, 0x700f) AM_READ(s23_iob_gun_r)
3202		AM_IMPORT_FROM( s23iobrdmap )
3203		ADDRESS_MAP_END
3204
3205		/*
3206		port 5 bit 2 = LED to indicate transmitting packet to main
3207		port 4 bit 2 = SENSE line back to main (0 = asserted, 1 = dropped)
3208		*/
3209		static ADDRESS_MAP_START( s23iobrdiomap, AS_IO, 8, namcos23_state )
3210		AM_RANGE(H8_PORT_4, H8_PORT_4) AM_READWRITE(s23_iob_p4_r, s23_iob_p4_w)
3211		AM_RANGE(H8_PORT_5, H8_PORT_5) AM_NOP   // status LED in bit 2
3212		AM_RANGE(H8_PORT_6, H8_PORT_6) AM_READWRITE(s23_iob_p6_r, s23_iob_p6_w)
3213		AM_RANGE(H8_PORT_8, H8_PORT_8) AM_NOP   // unknown - used on ASCA-5 only
3214		AM_RANGE(H8_PORT_9, H8_PORT_9) AM_NOP   // unknown - used on ASCA-5 only
3215		AM_RANGE(H8_SERIAL_0, H8_SERIAL_0) AM_READWRITE(s23_iob_mcu_r, s23_iob_mcu_w)
3216		AM_RANGE(H8_ADC_0_H, H8_ADC_3_L) AM_READ(s23_iob_analog_r)
3217		ADDRESS_MAP_END
3218
3219		DRIVER_INIT_MEMBER(namcos23_state,ss23)
3220		{
3221	3390	m_ptrom  = (const UINT32 *)memregion("pointrom")->base();
3222	3391	m_tmlrom = (const UINT16 *)memregion("textilemapl")->base();
3223	3392	m_tmhrom = memregion("textilemaph")->base();
r19732	r19733
3237	3406	memset(m_s23_settings, 0, sizeof(m_s23_settings));
3238	3407	m_s23_tssio_port_4 = 0;
3239	3408	m_s23_porta = 0, m_s23_rtcstate = 0;
3240		m_audiocpu_running = false;
	3409	m_subcpu_running = false;
3241	3410	m_render.count[0] = m_render.count[1] = 0;
3242	3411	m_render.cur = 0;
3243	3412
r19732	r19733
3267	3436	}
3268	3437	}
3269	3438
3270		void namcos23_state::machine_reset()
3271		{
3272		m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
3273		}
3274	3439
	3440
3275	3441	#define XOR(a) WORD2_XOR_BE(a)
3276	3442
3277	3443	static const gfx_layout namcos23_cg_layout =
r19732	r19733
3290	3456	GFXDECODE_ENTRY( NULL, 0, namcos23_cg_layout, 0, 0x800 )
3291	3457	GFXDECODE_END
3292	3458
	3459
3293	3460	static const mips3_config r4650_config =
3294	3461	{
3295	3462	8192,            /* code cache size - VERIFIED */
3296	3463	8192            /* data cache size - VERIFIED */
3297	3464	};
3298	3465
	3466
	3467
3299	3468	static MACHINE_CONFIG_START( gorgon, namcos23_state )
3300	3469
3301	3470	/* basic machine hardware */
r19732	r19733
3304	3473	MCFG_CPU_PROGRAM_MAP(gorgon_map)
3305	3474	MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos23_state,  s23_interrupt)
3306	3475
3307		MCFG_CPU_ADD("audiocpu", H83002, S23_H8CLOCK )
	3476	MCFG_CPU_ADD("subcpu", H83002, S23_H8CLOCK )
3308	3477	MCFG_CPU_PROGRAM_MAP( s23h8rwmap )
3309	3478	MCFG_CPU_IO_MAP( s23h8iomap )
3310	3479	MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos23_state,  irq1_line_pulse)
r19732	r19733
3322	3491	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) // Not in any way accurate
3323	3492	MCFG_SCREEN_SIZE(640, 480)
3324	3493	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 479)
3325		MCFG_SCREEN_UPDATE_DRIVER(namcos23_state, screen_update_ss23)
	3494	MCFG_SCREEN_UPDATE_DRIVER(namcos23_state, screen_update_s23)
3326	3495
3327	3496	MCFG_PALETTE_LENGTH(0x8000)
3328	3497
r19732	r19733
3330	3499
3331	3500	MCFG_GFXDECODE(namcos23)
3332	3501
3333		MCFG_VIDEO_START_OVERRIDE(namcos23_state,ss23)
	3502	MCFG_VIDEO_START_OVERRIDE(namcos23_state,s23)
3334	3503
3335	3504	/* sound hardware */
3336	3505	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
r19732	r19733
3342	3511	MCFG_SOUND_ROUTE(3, "lspeaker", 1.00)
3343	3512	MACHINE_CONFIG_END
3344	3513
	3514
3345	3515	static MACHINE_CONFIG_START( s23, namcos23_state )
	3516
3346	3517	/* basic machine hardware */
3347	3518	MCFG_CPU_ADD("maincpu", R4650BE, S23_BUSCLOCK*4)
3348	3519	MCFG_CPU_CONFIG(r4650_config)
3349		MCFG_CPU_PROGRAM_MAP(ss23_map)
	3520	MCFG_CPU_PROGRAM_MAP(s23_map)
3350	3521	MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos23_state,  s23_interrupt)
3351	3522
3352		MCFG_CPU_ADD("audiocpu", H83002, S23_H8CLOCK )
	3523	MCFG_CPU_ADD("subcpu", H83002, S23_H8CLOCK )
3353	3524	MCFG_CPU_PROGRAM_MAP( s23h8rwmap )
3354	3525	MCFG_CPU_IO_MAP( s23h8iomap )
3355	3526	MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos23_state,  irq1_line_pulse)
r19732	r19733
3367	3538	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) // Not in any way accurate
3368	3539	MCFG_SCREEN_SIZE(640, 480)
3369	3540	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 479)
3370		MCFG_SCREEN_UPDATE_DRIVER(namcos23_state, screen_update_ss23)
	3541	MCFG_SCREEN_UPDATE_DRIVER(namcos23_state, screen_update_s23)
3371	3542
3372	3543	MCFG_PALETTE_LENGTH(0x8000)
3373	3544
r19732	r19733
3375	3546
3376	3547	MCFG_NVRAM_ADD_0FILL("nvram")
3377	3548
3378		MCFG_VIDEO_START_OVERRIDE(namcos23_state,ss23)
	3549	MCFG_VIDEO_START_OVERRIDE(namcos23_state,s23)
3379	3550
3380	3551	/* sound hardware */
3381	3552	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
r19732	r19733
3387	3558	MCFG_SOUND_ROUTE(3, "lspeaker", 1.00)
3388	3559	MACHINE_CONFIG_END
3389	3560
	3561	static MACHINE_CONFIG_DERIVED( timecrs2, s23 )
	3562
	3563	MCFG_CPU_MODIFY("iocpu")
	3564	MCFG_CPU_PROGRAM_MAP( timecrs2iobrdmap )
	3565	MACHINE_CONFIG_END
	3566
	3567	static MACHINE_CONFIG_DERIVED( gmen, s23 )
	3568
	3569	MCFG_CPU_MODIFY("maincpu")
	3570	MCFG_CPU_CLOCK(S23_BUSCLOCK*5)
	3571	MCFG_CPU_PROGRAM_MAP(gmen_mips_map)
	3572
	3573	MCFG_CPU_ADD("gmen_sh2", SH2, 28700000)
	3574	MCFG_CPU_PROGRAM_MAP(gmen_sh2_map)
	3575
	3576	MCFG_MACHINE_RESET_OVERRIDE(namcos23_state,gmen)
	3577	MACHINE_CONFIG_END
	3578
	3579
3390	3580	static MACHINE_CONFIG_START( ss23, namcos23_state )
	3581
3391	3582	/* basic machine hardware */
3392	3583	MCFG_CPU_ADD("maincpu", R4650BE, S23_BUSCLOCK*5)
3393	3584	MCFG_CPU_CONFIG(r4650_config)
3394		MCFG_CPU_PROGRAM_MAP(ss23_map)
	3585	MCFG_CPU_PROGRAM_MAP(s23_map)
3395	3586	MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos23_state,  s23_interrupt)
3396	3587
3397		MCFG_CPU_ADD("audiocpu", H83002, S23_H8CLOCK )
	3588	MCFG_CPU_ADD("subcpu", H83002, S23_H8CLOCK )
3398	3589	MCFG_CPU_PROGRAM_MAP( s23h8rwmap )
3399	3590	MCFG_CPU_IO_MAP( s23h8noiobmap )
3400	3591	MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos23_state,  irq1_line_pulse)
r19732	r19733
3408	3599	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) // Not in any way accurate
3409	3600	MCFG_SCREEN_SIZE(640, 480)
3410	3601	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 479)
3411		MCFG_SCREEN_UPDATE_DRIVER(namcos23_state, screen_update_ss23)
	3602	MCFG_SCREEN_UPDATE_DRIVER(namcos23_state, screen_update_s23)
3412	3603
3413	3604	MCFG_PALETTE_LENGTH(0x8000)
3414	3605
r19732	r19733
3416	3607
3417	3608	MCFG_NVRAM_ADD_0FILL("nvram")
3418	3609
3419		MCFG_VIDEO_START_OVERRIDE(namcos23_state,ss23)
	3610	MCFG_VIDEO_START_OVERRIDE(namcos23_state,s23)
3420	3611
3421	3612	/* sound hardware */
3422	3613	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
r19732	r19733
3428	3619	MCFG_SOUND_ROUTE(3, "lspeaker", 1.00)
3429	3620	MACHINE_CONFIG_END
3430	3621
3431		static MACHINE_CONFIG_DERIVED( ss23e2, ss23 )
	3622	static MACHINE_CONFIG_DERIVED( timecrs2c, ss23 )
3432	3623
3433		MCFG_CPU_MODIFY("maincpu")
3434		MCFG_CPU_CLOCK(S23_BUSCLOCK*6)
3435
3436		MCFG_CPU_MODIFY("audiocpu")
	3624	MCFG_CPU_MODIFY("subcpu")
3437	3625	MCFG_CPU_IO_MAP( s23h8iomap )
3438	3626
3439	3627	MCFG_CPU_ADD("iocpu", H83334, S23_H8CLOCK )
3440		MCFG_CPU_PROGRAM_MAP( s23iobrdmap )
	3628	MCFG_CPU_PROGRAM_MAP( timecrs2iobrdmap )
3441	3629	MCFG_CPU_IO_MAP( s23iobrdiomap )
3442	3630	MACHINE_CONFIG_END
3443	3631
3444		static MACHINE_CONFIG_DERIVED( timecrs2, s23 )
	3632	static MACHINE_CONFIG_DERIVED( ss23e2, ss23 )
3445	3633
3446		MCFG_CPU_MODIFY("iocpu")
3447		MCFG_CPU_PROGRAM_MAP( timecrs2iobrdmap )
3448		MACHINE_CONFIG_END
	3634	MCFG_CPU_MODIFY("maincpu")
	3635	MCFG_CPU_CLOCK(S23_BUSCLOCK*6)
3449	3636
3450		static MACHINE_CONFIG_DERIVED( timecrs2c, ss23 )
3451
3452		MCFG_CPU_MODIFY("audiocpu")
	3637	MCFG_CPU_MODIFY("subcpu")
3453	3638	MCFG_CPU_IO_MAP( s23h8iomap )
3454	3639
3455	3640	MCFG_CPU_ADD("iocpu", H83334, S23_H8CLOCK )
3456		MCFG_CPU_PROGRAM_MAP( timecrs2iobrdmap )
	3641	MCFG_CPU_PROGRAM_MAP( s23iobrdmap )
3457	3642	MCFG_CPU_IO_MAP( s23iobrdiomap )
3458	3643	MACHINE_CONFIG_END
3459	3644
3460		static MACHINE_CONFIG_DERIVED( gmen, s23 )
3461	3645
3462		MCFG_CPU_MODIFY("maincpu")
3463		MCFG_CPU_CLOCK(S23_BUSCLOCK*5)
3464		MCFG_CPU_PROGRAM_MAP(gmen_mips_map)
3465	3646
3466		MCFG_CPU_ADD("gmen_sh2", SH2, 28700000)
3467		MCFG_CPU_PROGRAM_MAP(gmen_sh2_map)
3468
3469		MCFG_MACHINE_RESET_OVERRIDE(namcos23_state,gmen)
3470		MACHINE_CONFIG_END
3471
3472	3647	ROM_START( rapidrvr )
3473	3648	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
3474	3649	ROM_LOAD16_BYTE( "rd3verc.ic2",  0x000000, 0x200000, CRC(c15c0f30) SHA1(9f529232818f3e184f81f62408a5cad615b05613) )
3475	3650	ROM_LOAD16_BYTE( "rd3verc.ic1",  0x000001, 0x200000, CRC(9d7f4411) SHA1(d049efaa539d36ed0f73ca3f50a8f7112e67f865) )
3476	3651
3477		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	3652	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
3478	3653	ROM_LOAD16_WORD_SWAP( "rd3verc.ic3",  0x000000, 0x080000, CRC(6e26fbaf) SHA1(4ab6637d22f0d26f7e1d10e9c80059c56f64303d) )
3479	3654
3480	3655	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code */
r19732	r19733
3529	3704	ROM_LOAD( "rd1ccrh.11f",  0x000000, 0x200000, CRC(fafffb86) SHA1(15b0ba0252b99d0cac29fcb374fb895643f528fe) )
3530	3705	ROM_END
3531	3706
	3707
3532	3708	ROM_START( rapidrvr2 )
3533	3709	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
3534	3710	ROM_LOAD16_BYTE( "rd2verc.ic2",  0x000000, 0x200000, CRC(234fc2f4) SHA1(64374f4de19855f1980d8e088049b0c112107f43) )
3535	3711	ROM_LOAD16_BYTE( "rd2verc.ic1",  0x000001, 0x200000, CRC(651c5da4) SHA1(0e73e2cfafda626597d2ce08bf07458509fb79de) )
3536	3712
3537		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	3713	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
3538	3714	ROM_LOAD16_WORD_SWAP( "rd2verc.ic3",  0x000000, 0x080000, CRC(6e26fbaf) SHA1(4ab6637d22f0d26f7e1d10e9c80059c56f64303d) )
3539	3715
3540	3716	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code */
r19732	r19733
3589	3765	ROM_LOAD( "rd1ccrh.11f",  0x000000, 0x200000, CRC(fafffb86) SHA1(15b0ba0252b99d0cac29fcb374fb895643f528fe) )
3590	3766	ROM_END
3591	3767
	3768
3592	3769	ROM_START( rapidrvrp ) // prototype board
3593	3770	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
3594	3771	ROM_LOAD16_BYTE( "29f016.ic2",  0x000000, 0x200000, CRC(9f72a7cd) SHA1(06245f1d3cc6ffb5b0123a8eea0dc8338bdfc0d6) )
3595	3772	ROM_LOAD16_BYTE( "29f016.ic1",  0x000001, 0x200000, CRC(d395a244) SHA1(7f7b7b75b4bf9ac8808a27afed87f503df28e49f) )
3596	3773
3597		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	3774	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
3598	3775	ROM_LOAD16_WORD_SWAP( "29f400.ic3",  0x000000, 0x080000, CRC(f194c942) SHA1(b581c97327dea092e30ba46ad630d10477343a39) )
3599	3776
3600	3777	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code */
r19732	r19733
3649	3826	ROM_LOAD( "rd1ccrh.11f",  0x000000, 0x200000, CRC(fafffb86) SHA1(15b0ba0252b99d0cac29fcb374fb895643f528fe) )
3650	3827	ROM_END
3651	3828
	3829
3652	3830	ROM_START( finfurl )
3653	3831	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
3654	3832	ROM_LOAD16_BYTE( "ff2vera.ic2",  0x000000, 0x200000, CRC(e10f9dfa) SHA1(6f6989cd722fec5e3ed3ad1bb4866c5831041ae1) )
3655	3833	ROM_LOAD16_BYTE( "ff2vera.ic1",  0x000001, 0x200000, CRC(5a90ffbf) SHA1(e22dc0ae2d3c3b3a521369fe3f63412ae2ae0a12) )
3656	3834
3657		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	3835	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
3658	3836	ROM_LOAD16_WORD_SWAP( "ff2vera.ic3",  0x000000, 0x080000, CRC(ab681078) SHA1(ec8367404458a54893ab6bea29c8a2ba3272b816) )
3659	3837
3660	3838	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code */
r19732	r19733
3703	3881	ROM_LOAD( "ff2ccrh.11f",  0x000000, 0x200000, CRC(71228c61) SHA1(b39d0b51f36c0d00a6144ae20613bebee3ed22bc) )
3704	3882	ROM_END
3705	3883
	3884
3706	3885	ROM_START( motoxgo )
3707	3886	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
3708	3887	ROM_LOAD16_BYTE( "mg3vera.ic2",  0x000000, 0x200000, CRC(1bf06f00) SHA1(e9d04e9f19bff7a58cb280dd1d5db12801b68ba0) )
3709	3888	ROM_LOAD16_BYTE( "mg3vera.ic1",  0x000001, 0x200000, CRC(f5e6e25b) SHA1(1de30e8e831be66987112645a9db3a3001b89fe6) )
3710	3889
3711		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	3890	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
3712	3891	ROM_LOAD16_WORD_SWAP( "mg3vera.ic3",  0x000000, 0x080000, CRC(9e3d46a8) SHA1(9ffa5b91ea51cc0fb97def25ce47efa3441f3c6f) )
3713	3892
3714	3893	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code */
r19732	r19733
3750	3929	ROM_LOAD( "mg1ccrh.7k",   0x400000, 0x200000, CRC(2e77597d) SHA1(58dd83c1b0c08115e728c5e7dea5e62135b821ba) )
3751	3930	ROM_END
3752	3931
	3932
3753	3933	ROM_START( motoxgoa )
3754	3934	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
3755	3935	ROM_LOAD16_BYTE( "mg2vera.ic2",  0x000000, 0x200000, CRC(66093336) SHA1(c87874245a70a1642fb9ecfc94cbbc89f0fd633f) )
3756	3936	ROM_LOAD16_BYTE( "mg2vera.ic1",  0x000001, 0x200000, CRC(3dc7736f) SHA1(c5137aa449918a124415f8ea5581e037f841129c) )
3757	3937
3758		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	3938	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
3759	3939	ROM_LOAD16_WORD_SWAP( "mg3vera.ic3",  0x000000, 0x080000, CRC(9e3d46a8) SHA1(9ffa5b91ea51cc0fb97def25ce47efa3441f3c6f) )
3760	3940
3761	3941	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code */
r19732	r19733
3797	3977	ROM_LOAD( "mg1ccrh.7k",   0x400000, 0x200000, CRC(2e77597d) SHA1(58dd83c1b0c08115e728c5e7dea5e62135b821ba) )
3798	3978	ROM_END
3799	3979
	3980
3800	3981	ROM_START( timecrs2 )
3801	3982	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
3802	3983	ROM_LOAD16_BYTE( "tss3verb.2",   0x000000, 0x200000, CRC(c7be691f) SHA1(5e2e7a0db3d8ce6dfeb6c0d99e9fe6a9f9cab467) )
3803	3984	ROM_LOAD16_BYTE( "tss3verb.1",   0x000001, 0x200000, CRC(6e3f232b) SHA1(8007d8f31a605a5df89938d7c9f9d3d209c934be) )
3804	3985
3805		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	3986	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
3806	3987	ROM_LOAD16_WORD_SWAP( "tss3verb.3",   0x000000, 0x080000, CRC(41e41994) SHA1(eabc1a307c329070bfc6486cb68169c94ff8a162) )
3807	3988
3808	3989	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code */
r19732	r19733
3839	4020	ROM_LOAD( "tss1waveh.2a", 0x800000, 0x800000, CRC(5c8758b4) SHA1(b85c8f6869900224ef83a2340b17f5bbb2801af9) )
3840	4021	ROM_END
3841	4022
	4023
3842	4024	ROM_START( timecrs2b )
3843	4025	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
3844	4026	ROM_LOAD16_BYTE( "tss2verb.ic2", 0x000000, 0x200000, BAD_DUMP CRC(9f56a4df) SHA1(5ecb3cd93726ab6be02762853fd6a45266d6c0bc) )
3845	4027	ROM_LOAD16_BYTE( "tss2verb.ic1", 0x000001, 0x200000, BAD_DUMP CRC(aa147f71) SHA1(e00267d1a8286942c83dc35289ad65bd3cb6d8db) )
3846	4028
3847		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	4029	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
3848	4030	ROM_LOAD16_WORD_SWAP( "tss3verb.3",   0x000000, 0x080000, CRC(41e41994) SHA1(eabc1a307c329070bfc6486cb68169c94ff8a162) )
3849	4031
3850	4032	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code */
r19732	r19733
3881	4063	ROM_LOAD( "tss1waveh.2a", 0x800000, 0x800000, CRC(5c8758b4) SHA1(b85c8f6869900224ef83a2340b17f5bbb2801af9) )
3882	4064	ROM_END
3883	4065
	4066
3884	4067	ROM_START( timecrs2c )
3885	4068	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
3886	4069	ROM_LOAD16_BYTE( "tss4vera.2",   0x000000, 0x200000, CRC(c84edd3b) SHA1(0b577a8ef6e74afa991dd81c2db19041787724da) )
3887	4070	ROM_LOAD16_BYTE( "tss4vera.1",   0x000001, 0x200000, CRC(26f57c83) SHA1(c8983c26b7524a35257a242b66a9413eb354ca0d) )
3888	4071
3889		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	4072	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
3890	4073	ROM_LOAD16_WORD_SWAP( "tss4vera.3",   0x000000, 0x080000, CRC(41e41994) SHA1(eabc1a307c329070bfc6486cb68169c94ff8a162) )
3891	4074
3892	4075	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code */
r19732	r19733
3923	4106	ROM_LOAD( "tss1waveh.2a", 0x800000, 0x800000, CRC(5c8758b4) SHA1(b85c8f6869900224ef83a2340b17f5bbb2801af9) )
3924	4107	ROM_END
3925	4108
	4109
3926	4110	ROM_START( 500gp )
3927	4111	/* r4650-generic-xrom-generic: NMON 1.0.8-sys23-19990105 P for SYSTEM23 P1 */
3928	4112	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
3929	4113	ROM_LOAD16_BYTE( "5gp3verc.2",   0x000000, 0x200000, CRC(e2d43468) SHA1(5e861dd223c7fa177febed9803ac353cba18e19d) )
3930	4114	ROM_LOAD16_BYTE( "5gp3verc.1",   0x000001, 0x200000, CRC(f6efc94a) SHA1(785eee2bec5080d4e8ef836f28d446328c942b0e) )
3931	4115
3932		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	4116	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
3933	4117	ROM_LOAD16_WORD_SWAP( "5gp3verc.3",   0x000000, 0x080000, CRC(b323abdf) SHA1(8962e39b48a7074a2d492afb5db3f5f3e5ae2389) )
3934	4118
3935	4119	ROM_REGION32_BE( 0x2000000, "data", 0 )   /* data roms */
r19732	r19733
3969	4153	ROM_LOAD( "5gp1waveh.2a", 0x800000, 0x800000, CRC(1e3523e8) SHA1(cb3d0d389fcbfb728fad29cfc36ef654d28d553a) )
3970	4154	ROM_END
3971	4155
	4156
3972	4157	ROM_START( raceon )
3973	4158	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
3974	4159	ROM_LOAD16_BYTE( "ro2vera.ic2",  0x000000, 0x200000, CRC(08b94548) SHA1(6363f1724540c2671555bc5bb11e22611614baf5) )
3975	4160	ROM_LOAD16_BYTE( "ro2vera.ic1",  0x000001, 0x200000, CRC(4270884b) SHA1(82e4d4376907ee5dbabe047b9d2279f08cff5f71) )
3976	4161
3977		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	4162	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
3978	4163	ROM_LOAD16_WORD_SWAP( "ro2vera.ic3",  0x000000, 0x080000, CRC(a763ecb7) SHA1(6b1ab63bb56342abbf7ddd7d17d413779fbafce1) )
3979	4164
3980	4165	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code */
r19732	r19733
4022	4207	ROM_LOAD( "ro1cguu.5f",   0x000000, 0x800000, CRC(8fef8bd4) SHA1(6870590f585dc8d87ebe5181da870715c9c4fee3) )
4023	4208	ROM_END
4024	4209
	4210
4025	4211	ROM_START( finfurl2 )
4026	4212	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
4027	4213	ROM_LOAD16_BYTE( "29f016.ic2",   0x000000, 0x200000, CRC(13cbc545) SHA1(3e67a7bfbb1c1374e8e3996a0c09e4861b0dca14) )
4028	4214	ROM_LOAD16_BYTE( "29f016.ic1",   0x000001, 0x200000, CRC(5b04e4f2) SHA1(8099fc3deab9ed14a2484a774666fbd928330de8) )
4029	4215
4030		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	4216	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
4031	4217	ROM_LOAD16_WORD_SWAP( "m29f400.ic3",  0x000000, 0x080000, CRC(9fd69bbd) SHA1(53a9bf505de70495dcccc43fdc722b3381aad97c) )
4032	4218
4033	4219	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code */
r19732	r19733
4066	4252	ROM_LOAD( "ffs1waveh.2a", 0x800000, 0x800000, CRC(178e8bd3) SHA1(8ab1a97003914f70b09e96c5924f3a839fe634c7) )
4067	4253	ROM_END
4068	4254
	4255
4069	4256	ROM_START( finfurl2j )
4070	4257	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
4071	4258	ROM_LOAD16_BYTE( "29f016_jap1.ic2", 0x000000, 0x200000, CRC(0215125d) SHA1(a99f601441c152b0b00f4811e5752c71897b1ed4) )
4072	4259	ROM_LOAD16_BYTE( "29f016_jap1.ic1", 0x000001, 0x200000, CRC(38c9ae96) SHA1(b50afc7276662267ff6460f82d0e5e8b00b341ea) )
4073	4260
4074		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	4261	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
4075	4262	ROM_LOAD16_WORD_SWAP( "m29f400.ic3",  0x000000, 0x080000, CRC(9fd69bbd) SHA1(53a9bf505de70495dcccc43fdc722b3381aad97c) )
4076	4263
4077	4264	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code */
r19732	r19733
4109	4296	ROM_LOAD( "ffs1waveh.2a", 0x800000, 0x800000, CRC(178e8bd3) SHA1(8ab1a97003914f70b09e96c5924f3a839fe634c7) )
4110	4297	ROM_END
4111	4298
	4299
4112	4300	ROM_START( panicprk )
4113	4301	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
4114	4302	ROM_LOAD16_BYTE( "pnp2ver-a.ic2", 0x000000, 0x200000, CRC(cd528597) SHA1(cf390e78228eb10d5f50ff7e7e37063a2d87f469) )
4115	4303	ROM_LOAD16_BYTE( "pnp2ver-a.ic1", 0x000001, 0x200000, CRC(80fea853) SHA1(b18003bde060ebb3c892a6d7fa4abf868cadc777) )
4116	4304
4117		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	4305	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
4118	4306	ROM_LOAD16_WORD_SWAP( "pnp2ver-a.ic3", 0x000000, 0x080000, CRC(fe4bc6f4) SHA1(2114dc4bc63d589e6c3b26a73dbc60924f3b1765) )
4119	4307
4120	4308	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code */
r19732	r19733
4155	4343	ROM_LOAD( "pnp1ccrh.7k",  0x000000, 0x200000, CRC(caaf1b73) SHA1(b436992817ab4e4dad05e7429eb102d4fb57fa6a) )
4156	4344	ROM_END
4157	4345
	4346
4158	4347	ROM_START( gunwars )
4159	4348	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
4160	4349	ROM_LOAD16_BYTE( "gm1vera.ic2",  0x000000, 0x200000, CRC(cf61467f) SHA1(eae79e4e540340cba7d576a36085f802b8032f4f) )
4161	4350	ROM_LOAD16_BYTE( "gm1vera.ic1",  0x000001, 0x200000, CRC(abc9ffe6) SHA1(d833b9b9d8bb0cc4b53f30507c9603df9e63fa2f) )
4162	4351
4163		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	4352	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
4164	4353	ROM_LOAD16_WORD_SWAP( "gm1vera.ic3",  0x000000, 0x080000, CRC(5582fdd4) SHA1(8aae8bc6688d531888f2de509c07502ee355b3ab) )
4165	4354
4166	4355	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code. "ASCA-5;Ver 2.09;JPN,Multipurpose" */
r19732	r19733
4200	4389	ROM_LOAD( "gm1ccrh.7k",   0x000000, 0x200000, CRC(8563ef01) SHA1(59f09a08008a71a4bb12bd43a1b5dbe633d3061d) )
4201	4390	ROM_END
4202	4391
	4392
4203	4393	ROM_START( downhill )
4204	4394	ROM_REGION32_BE( 0x400000, "user1", 0 ) /* 4 megs for main R4650 code */
4205	4395	ROM_LOAD16_BYTE( "dh3vera.ic2",  0x000000, 0x200000, CRC(5d9952e9) SHA1(d38422330bd708c247b9968429fbff36fe706598) )
4206	4396	ROM_LOAD16_BYTE( "dh3vera.ic1",  0x000001, 0x200000, CRC(64a236f3) SHA1(aac59e0db5cfefc4b442e6c3a5189a8418742201) )
4207	4397
4208		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	4398	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
4209	4399	ROM_LOAD16_WORD_SWAP( "dh3vera.ic3",  0x000000, 0x080000, CRC(98f9fc8b) SHA1(5152b9e11773033a26da11d1f3774a261e61a2c5) )
4210	4400
4211	4401	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code. "ASCA-3;Ver 2.04;JPN,Multipurpose + Rotary Encoder" */
r19732	r19733
4248	4438	ROM_LOAD( "dh1ccrh.7k",   0x000000, 0x200000, CRC(f21c482d) SHA1(bfcead2ff3d10f996ac0bf81470d050bd6374156) )
4249	4439	ROM_END
4250	4440
	4441
4251	4442	// bfe4b800
4252	4443	ROM_START( crszone )
4253	4444	ROM_REGION32_BE( 0x800000, "user1", 0 ) /* 4 megs for main R4650 code */
4254	4445	ROM_LOAD16_WORD_SWAP( "cszo4verb.ic4", 0x400000, 0x400000, CRC(6192533d) SHA1(d102b91fe193bf255ea4e57a2bd964aa1cdfd21d) )
4255	4446	ROM_CONTINUE( 0x000000, 0x400000 )
4256	4447
4257		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	4448	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
4258	4449	ROM_LOAD16_WORD_SWAP( "cszo3verb.ic1", 0x000000, 0x080000, CRC(c790743b) SHA1(5fa7b83a7a1b1105a3aa0870b782cf2741b7d11c) )
4259	4450
4260	4451	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code. "MIU-I/O;Ver2.05;JPN,GUN-EXTENTION" */
r19732	r19733
4301	4492	ROM_LOAD( "csz1ccrh.7k",  0x000000, 0x200000, CRC(bc2fa03c) SHA1(e63d8e75494a383bf9a213edfa9c472a010f8efe) )
4302	4493	ROM_END
4303	4494
	4495
4304	4496	ROM_START( crszonea )
4305	4497	ROM_REGION32_BE( 0x800000, "user1", 0 ) /* 4 megs for main R4650 code */
4306	4498	ROM_LOAD16_WORD_SWAP( "cszo3verb.ic4", 0x400000, 0x400000, CRC(4cb26465) SHA1(078dfd0d8c920707df14e9a26658fa63421fcb0b) )
4307	4499	ROM_CONTINUE( 0x000000, 0x400000 )
4308	4500
4309		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	4501	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
4310	4502	ROM_LOAD16_WORD_SWAP( "cszo3verb.ic1", 0x000000, 0x080000, CRC(c790743b) SHA1(5fa7b83a7a1b1105a3aa0870b782cf2741b7d11c) )
4311	4503
4312	4504	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code. "MIU-I/O;Ver2.05;JPN,GUN-EXTENTION" */
r19732	r19733
4353	4545	ROM_LOAD( "csz1ccrh.7k",  0x000000, 0x200000, CRC(bc2fa03c) SHA1(e63d8e75494a383bf9a213edfa9c472a010f8efe) )
4354	4546	ROM_END
4355	4547
	4548
4356	4549	ROM_START( crszoneb )
4357	4550	ROM_REGION32_BE( 0x800000, "user1", 0 ) /* 4 megs for main R4650 code */
4358	4551	ROM_LOAD16_WORD_SWAP( "cszo3vera.ic4", 0x400000, 0x400000, CRC(09b0c91e) SHA1(226c3788d6a50272e2544d04d9ca20df81014fb6) )
4359	4552	ROM_CONTINUE( 0x000000, 0x400000 )
4360	4553
4361		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	4554	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
4362	4555	ROM_LOAD16_WORD_SWAP( "cszo3verb.ic1", 0x000000, 0x080000, CRC(c790743b) SHA1(5fa7b83a7a1b1105a3aa0870b782cf2741b7d11c) )
4363	4556
4364	4557	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code. "MIU-I/O;Ver2.05;JPN,GUN-EXTENTION" */
r19732	r19733
4405	4598	ROM_LOAD( "csz1ccrh.7k",  0x000000, 0x200000, CRC(bc2fa03c) SHA1(e63d8e75494a383bf9a213edfa9c472a010f8efe) )
4406	4599	ROM_END
4407	4600
	4601
4408	4602	ROM_START( crszonec )
4409	4603	ROM_REGION32_BE( 0x800000, "user1", 0 ) /* 4 megs for main R4650 code */
4410	4604	ROM_LOAD16_WORD_SWAP( "cszo2vera.ic4", 0x400000, 0x400000, CRC(1426d8d0) SHA1(e8049df1b2db1180f9edf6e5fa9fe8692ae81086) )
4411	4605	ROM_CONTINUE( 0x000000, 0x400000 )
4412	4606
4413		ROM_REGION( 0x80000, "audiocpu", 0 )   /* Hitachi H8/3002 MCU code */
	4607	ROM_REGION( 0x80000, "subcpu", 0 )   /* Hitachi H8/3002 MCU code */
4414	4608	ROM_LOAD16_WORD_SWAP( "cszo3verb.ic1", 0x000000, 0x080000, CRC(c790743b) SHA1(5fa7b83a7a1b1105a3aa0870b782cf2741b7d11c) )
4415	4609
4416	4610	ROM_REGION( 0x40000, "iocpu", 0 )   /* I/O board HD643334 H8/3334 MCU code. "MIU-I/O;Ver2.05;JPN,GUN-EXTENTION" */
r19732	r19733
4457	4651	ROM_LOAD( "csz1ccrh.7k",  0x000000, 0x200000, CRC(bc2fa03c) SHA1(e63d8e75494a383bf9a213edfa9c472a010f8efe) )
4458	4652	ROM_END
4459	4653
	4654
4460	4655	/* Games */
4461	4656	#define GAME_FLAGS (GAME_NOT_WORKING | GAME_UNEMULATED_PROTECTION | GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND)
4462		//    YEAR, NAME,      PARENT,   MACHINE,   INPUT,     INIT,                 MNTR,  COMPANY, FULLNAME,                      FLAGS
4463		GAME( 1997, rapidrvr,  0,        gorgon,    gorgon,    namcos23_state, ss23, ROT0, "Namco", "Rapid River (RD3 Ver. C)",     GAME_FLAGS ) // 97/11/27, USA
4464		GAME( 1997, rapidrvr2, rapidrvr, gorgon,    gorgon,    namcos23_state, ss23, ROT0, "Namco", "Rapid River (RD2 Ver. C)",     GAME_FLAGS ) // 97/11/27, Europe
4465		GAME( 1997, rapidrvrp, rapidrvr, gorgon,    rapidrvrp, namcos23_state, ss23, ROT0, "Namco", "Rapid River (prototype)",      GAME_FLAGS ) // 97/11/10, USA
4466		GAME( 1997, finfurl,   0,        gorgon,    finfurl,   namcos23_state, ss23, ROT0, "Namco", "Final Furlong (FF2 Ver. A)",   GAME_FLAGS )
4467		GAME( 1997, downhill,  0,        s23,       s23,       namcos23_state, ss23, ROT0, "Namco", "Downhill Bikers (DH3 Ver. A)", GAME_FLAGS )
4468		GAME( 1997, motoxgo,   0,        s23,       s23,       namcos23_state, ss23, ROT0, "Namco", "Motocross Go! (MG3 Ver. A)",   GAME_FLAGS )
4469		GAME( 1997, motoxgoa,  motoxgo,  s23,       s23,       namcos23_state, ss23, ROT0, "Namco", "Motocross Go! (MG2 Ver. A)",   GAME_FLAGS )
4470		GAME( 1997, timecrs2,  0,        timecrs2,  timecrs2,  namcos23_state, ss23, ROT0, "Namco", "Time Crisis II (TSS3 Ver. B)", GAME_FLAGS )
4471		GAME( 1997, timecrs2b, timecrs2, timecrs2,  timecrs2,  namcos23_state, ss23, ROT0, "Namco", "Time Crisis II (TSS2 Ver. B)", GAME_FLAGS )
4472		GAME( 1997, timecrs2c, timecrs2, timecrs2c, timecrs2,  namcos23_state, ss23, ROT0, "Namco", "Time Crisis II (TSS4 Ver. A)", GAME_FLAGS )
4473		GAME( 1998, panicprk,  0,        s23,       s23,       namcos23_state, ss23, ROT0, "Namco", "Panic Park (PNP2 Ver. A)",     GAME_FLAGS )
4474		GAME( 1998, gunwars,   0,        gmen,      ss23,      namcos23_state, ss23, ROT0, "Namco", "Gunmen Wars (GM1 Ver. A)",     GAME_FLAGS )
4475		GAME( 1998, raceon,    0,        gmen,      ss23,      namcos23_state, ss23, ROT0, "Namco", "Race On! (RO2 Ver. A)",        GAME_FLAGS )
4476		GAME( 1998, 500gp,     0,        ss23,      ss23,      namcos23_state, ss23, ROT0, "Namco", "500 GP (5GP3 Ver. C)",         GAME_FLAGS )
4477		GAME( 1999, finfurl2,  0,        gmen,      ss23,      namcos23_state, ss23, ROT0, "Namco", "Final Furlong 2 (World)",      GAME_FLAGS )
4478		GAME( 1999, finfurl2j, finfurl2, gmen,      ss23,      namcos23_state, ss23, ROT0, "Namco", "Final Furlong 2 (Japan)",      GAME_FLAGS )
4479		GAME( 2000, crszone,   0,        ss23e2,    ss23,      namcos23_state, ss23, ROT0, "Namco", "Crisis Zone (CSZO4 Ver. B)",   GAME_FLAGS )
4480		GAME( 2000, crszonea,  crszone,  ss23e2,    ss23,      namcos23_state, ss23, ROT0, "Namco", "Crisis Zone (CSZO3 Ver. B)",   GAME_FLAGS )
4481		GAME( 2000, crszoneb,  crszone,  ss23e2,    ss23,      namcos23_state, ss23, ROT0, "Namco", "Crisis Zone (CSZO3 Ver. A)",   GAME_FLAGS )
4482		GAME( 2000, crszonec,  crszone,  ss23e2,    ss23,      namcos23_state, ss23, ROT0, "Namco", "Crisis Zone (CSZO2 Ver. A)",   GAME_FLAGS )
	4657	//    YEAR, NAME,      PARENT,   MACHINE,   INPUT,     INIT,                MNTR,  COMPANY, FULLNAME,                      FLAGS
	4658	GAME( 1997, rapidrvr,  0,        gorgon,    rapidrvr,  namcos23_state, s23, ROT0, "Namco", "Rapid River (RD3 Ver. C)",     GAME_FLAGS ) // 97/11/27, USA
	4659	GAME( 1997, rapidrvr2, rapidrvr, gorgon,    rapidrvr,  namcos23_state, s23, ROT0, "Namco", "Rapid River (RD2 Ver. C)",     GAME_FLAGS ) // 97/11/27, Europe
	4660	GAME( 1997, rapidrvrp, rapidrvr, gorgon,    rapidrvrp, namcos23_state, s23, ROT0, "Namco", "Rapid River (prototype)",      GAME_FLAGS ) // 97/11/10, USA
	4661	GAME( 1997, finfurl,   0,        gorgon,    finfurl,   namcos23_state, s23, ROT0, "Namco", "Final Furlong (FF2 Ver. A)",   GAME_FLAGS )
	4662	GAME( 1997, downhill,  0,        s23,       s23,       namcos23_state, s23, ROT0, "Namco", "Downhill Bikers (DH3 Ver. A)", GAME_FLAGS )
	4663	GAME( 1997, motoxgo,   0,        s23,       s23,       namcos23_state, s23, ROT0, "Namco", "Motocross Go! (MG3 Ver. A)",   GAME_FLAGS )
	4664	GAME( 1997, motoxgoa,  motoxgo,  s23,       s23,       namcos23_state, s23, ROT0, "Namco", "Motocross Go! (MG2 Ver. A)",   GAME_FLAGS )
	4665	GAME( 1997, timecrs2,  0,        timecrs2,  timecrs2,  namcos23_state, s23, ROT0, "Namco", "Time Crisis II (TSS3 Ver. B)", GAME_FLAGS )
	4666	GAME( 1997, timecrs2b, timecrs2, timecrs2,  timecrs2,  namcos23_state, s23, ROT0, "Namco", "Time Crisis II (TSS2 Ver. B)", GAME_FLAGS )
	4667	GAME( 1997, timecrs2c, timecrs2, timecrs2c, timecrs2,  namcos23_state, s23, ROT0, "Namco", "Time Crisis II (TSS4 Ver. A)", GAME_FLAGS )
	4668	GAME( 1998, panicprk,  0,        s23,       s23,       namcos23_state, s23, ROT0, "Namco", "Panic Park (PNP2 Ver. A)",     GAME_FLAGS )
	4669	GAME( 1998, gunwars,   0,        gmen,      ss23,      namcos23_state, s23, ROT0, "Namco", "Gunmen Wars (GM1 Ver. A)",     GAME_FLAGS )
	4670	GAME( 1998, raceon,    0,        gmen,      ss23,      namcos23_state, s23, ROT0, "Namco", "Race On! (RO2 Ver. A)",        GAME_FLAGS )
	4671	GAME( 1998, 500gp,     0,        ss23,      ss23,      namcos23_state, s23, ROT0, "Namco", "500 GP (5GP3 Ver. C)",         GAME_FLAGS )
	4672	GAME( 1999, finfurl2,  0,        gmen,      ss23,      namcos23_state, s23, ROT0, "Namco", "Final Furlong 2 (World)",      GAME_FLAGS )
	4673	GAME( 1999, finfurl2j, finfurl2, gmen,      ss23,      namcos23_state, s23, ROT0, "Namco", "Final Furlong 2 (Japan)",      GAME_FLAGS )
	4674	GAME( 2000, crszone,   0,        ss23e2,    ss23,      namcos23_state, s23, ROT0, "Namco", "Crisis Zone (CSZO4 Ver. B)",   GAME_FLAGS )
	4675	GAME( 2000, crszonea,  crszone,  ss23e2,    ss23,      namcos23_state, s23, ROT0, "Namco", "Crisis Zone (CSZO3 Ver. B)",   GAME_FLAGS )
	4676	GAME( 2000, crszoneb,  crszone,  ss23e2,    ss23,      namcos23_state, s23, ROT0, "Namco", "Crisis Zone (CSZO3 Ver. A)",   GAME_FLAGS )
	4677	GAME( 2000, crszonec,  crszone,  ss23e2,    ss23,      namcos23_state, s23, ROT0, "Namco", "Crisis Zone (CSZO2 Ver. A)",   GAME_FLAGS )
4483	4678

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