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r19731 Saturday 22nd December, 2012 at 18:48:43 UTC by hap
(note on unknown port)
[src/mame/drivers]namcos23.c

trunk/src/mame/drivers/namcos23.c
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14071407
14081408   int m_s23_porta;
14091409   int m_s23_rtcstate;
1410   int m_s23_lastpB;
1410   int m_s23_lastpb;
14111411   int m_s23_setstate;
14121412   int m_s23_setnum;
14131413   int m_s23_settings[8];
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14221422   void update_main_interrupts(UINT32 cause);
14231423   void update_mixer();
14241424
1425   DECLARE_WRITE32_MEMBER(namcos23_textram_w);
1426   DECLARE_WRITE32_MEMBER(s23_txtchar_w);
1427   DECLARE_WRITE32_MEMBER(namcos23_paletteram_w);
1425   DECLARE_WRITE32_MEMBER(s23_textram_w);
1426   DECLARE_WRITE32_MEMBER(s23_textchar_w);
1427   DECLARE_WRITE32_MEMBER(s23_paletteram_w);
14281428   DECLARE_READ16_MEMBER(s23_c417_r);
14291429   DECLARE_WRITE16_MEMBER(s23_c417_w);
14301430   DECLARE_READ16_MEMBER(s23_c412_ram_r);
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14421442   DECLARE_READ16_MEMBER(s23_c422_r);
14431443   DECLARE_WRITE16_MEMBER(s23_c422_w);
14441444   DECLARE_WRITE16_MEMBER(s23_mcuen_w);
1445   DECLARE_READ32_MEMBER(s23_unk_status_r);
1445   DECLARE_READ16_MEMBER(s23_sub_comm_r);
1446   DECLARE_WRITE16_MEMBER(s23_sub_comm_w);
14461447   DECLARE_READ32_MEMBER(p3d_r);
14471448   DECLARE_WRITE32_MEMBER(p3d_w);
14481449   DECLARE_READ32_MEMBER(gmen_trigger_sh2);
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14521453   DECLARE_READ16_MEMBER(sharedram_sub_r);
14531454   DECLARE_WRITE16_MEMBER(sub_interrupt_main_w);
14541455   DECLARE_READ8_MEMBER(s23_mcu_p8_r);
1456   DECLARE_WRITE8_MEMBER(s23_mcu_p8_w);
14551457   DECLARE_READ8_MEMBER(s23_mcu_pa_r);
14561458   DECLARE_WRITE8_MEMBER(s23_mcu_pa_w);
14571459   DECLARE_READ8_MEMBER(s23_mcu_rtc_r);
1458   DECLARE_READ8_MEMBER(s23_mcu_portB_r);
1459   DECLARE_WRITE8_MEMBER(s23_mcu_portB_w);
1460   DECLARE_READ8_MEMBER(s23_mcu_pb_r);
1461   DECLARE_WRITE8_MEMBER(s23_mcu_pb_w);
14601462   DECLARE_WRITE8_MEMBER(s23_mcu_settings_w);
14611463   DECLARE_READ8_MEMBER(s23_mcu_iob_r);
14621464   DECLARE_WRITE8_MEMBER(s23_mcu_iob_w);
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15351537   SET_TILE_INFO_MEMBER(0, data&0x03ff, data>>12, TILE_FLIPYX((data&0x0c00)>>10));
15361538}
15371539
1538WRITE32_MEMBER(namcos23_state::namcos23_textram_w)
1540WRITE32_MEMBER(namcos23_state::s23_textram_w)
15391541{
15401542   COMBINE_DATA( &m_textram[offset] );
15411543   m_bgtilemap->mark_tile_dirty(offset*2);
15421544   m_bgtilemap->mark_tile_dirty((offset*2)+1);
15431545}
15441546
1545WRITE32_MEMBER(namcos23_state::s23_txtchar_w)
1547WRITE32_MEMBER(namcos23_state::s23_textchar_w)
15461548{
15471549   COMBINE_DATA(&m_charram[offset]);
15481550   machine().gfx[0]->mark_dirty(offset/32);
15491551}
15501552
1551WRITE32_MEMBER(namcos23_state::namcos23_paletteram_w)
1553WRITE32_MEMBER(namcos23_state::s23_paletteram_w)
15521554{
15531555   COMBINE_DATA(&m_generic_paletteram_32[offset]);
15541556
r19730r19731
19481950   }
19491951}
19501952
1951// panicprk sits in a tight loop waiting for this AND 0002 to be non-zero (at PC=BFC02F00)
1953// while getting the subcpu to be ready, panicprk sits in a tight loop waiting for this AND 0002 to be non-zero (at PC=BFC02F00)
19521954// timecrs2 locks up in a similar way as panicprk, at the beginning of the 2nd level, by reading/writing to this register a couple of times
1953READ32_MEMBER(namcos23_state::s23_unk_status_r)
1955READ16_MEMBER(namcos23_state::s23_sub_comm_r)
19541956{
1955   return 0x00020002;
1957   return 2;
19561958}
19571959
1960WRITE16_MEMBER(namcos23_state::s23_sub_comm_w)
1961{
1962   ;
1963}
19581964
19591965// 3D hardware, to throw at least in part in video/namcos23.c
19601966
r19730r19731
25642570   AM_RANGE(0x06080000, 0x0608000f) AM_RAM AM_SHARE("czattr")
25652571   AM_RANGE(0x06080200, 0x060803ff) AM_RAM // PCZ Convert RAM (C406) (should be banked)
25662572   AM_RANGE(0x06108000, 0x061087ff) AM_RAM AM_SHARE("gammaram") // Gamma RAM (C404)
2567   AM_RANGE(0x06110000, 0x0613ffff) AM_RAM_WRITE(namcos23_paletteram_w) AM_SHARE("paletteram") // Palette RAM (C404)
2568   AM_RANGE(0x06400000, 0x0641dfff) AM_RAM_WRITE(s23_txtchar_w) AM_SHARE("charram") // Text CGRAM (C361)
2569   AM_RANGE(0x0641e000, 0x0641ffff) AM_RAM_WRITE(namcos23_textram_w) AM_SHARE("textram") // Text VRAM (C361)
2573   AM_RANGE(0x06110000, 0x0613ffff) AM_RAM_WRITE(s23_paletteram_w) AM_SHARE("paletteram") // Palette RAM (C404)
2574   AM_RANGE(0x06400000, 0x0641dfff) AM_RAM_WRITE(s23_textchar_w) AM_SHARE("charram") // Text CGRAM (C361)
2575   AM_RANGE(0x0641e000, 0x0641ffff) AM_RAM_WRITE(s23_textram_w) AM_SHARE("textram") // Text VRAM (C361)
25702576   AM_RANGE(0x06420000, 0x0642000f) AM_READWRITE16(s23_c361_r, s23_c361_w, 0xffffffff) // C361
25712577   AM_RANGE(0x08000000, 0x087fffff) AM_ROM AM_REGION("data", 0) // data ROMs
25722578   AM_RANGE(0x0c000000, 0x0c00ffff) AM_RAM   AM_SHARE("nvram") // Backup RAM
25732579   AM_RANGE(0x0d000000, 0x0d00000f) AM_READWRITE16(s23_ctl_r, s23_ctl_w, 0xffffffff) // write for LEDs at d000000, watchdog at d000004
25742580   AM_RANGE(0x0e000000, 0x0e007fff) AM_RAM // C405 RAM - what is this?
2575   AM_RANGE(0x0f000000, 0x0f000003) AM_READ(s23_unk_status_r) // error status, or protection? (also gets written to)
2581   AM_RANGE(0x0f000000, 0x0f000003) AM_READWRITE16(s23_sub_comm_r, s23_sub_comm_w, 0xffffffff) // not sure
25762582   AM_RANGE(0x0f200000, 0x0f203fff) AM_RAM // C422 RAM
25772583   AM_RANGE(0x0f300000, 0x0f30000f) AM_READWRITE16(s23_c422_r, s23_c422_w, 0xffffffff) // C422 registers
25782584   AM_RANGE(0x0fc00000, 0x0fffffff) AM_WRITENOP AM_ROM AM_REGION("user1", 0)
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25882594   AM_RANGE(0x06000000, 0x0600ffff) AM_RAM AM_SHARE("nvram") // Backup RAM
25892595   AM_RANGE(0x06200000, 0x06203fff) AM_RAM // C422 RAM
25902596   AM_RANGE(0x06400000, 0x0640000f) AM_READWRITE16(s23_c422_r, s23_c422_w, 0xffffffff) // C422 registers
2591   AM_RANGE(0x06800000, 0x0681dfff) AM_RAM_WRITE(s23_txtchar_w) AM_SHARE("charram") // Text CGRAM (C361)
2592   AM_RANGE(0x0681e000, 0x0681ffff) AM_RAM_WRITE(namcos23_textram_w) AM_SHARE("textram") // Text VRAM (C361)
2597   AM_RANGE(0x06800000, 0x0681dfff) AM_RAM_WRITE(s23_textchar_w) AM_SHARE("charram") // Text CGRAM (C361)
2598   AM_RANGE(0x0681e000, 0x0681ffff) AM_RAM_WRITE(s23_textram_w) AM_SHARE("textram") // Text VRAM (C361)
25932599   AM_RANGE(0x06820000, 0x0682000f) AM_READWRITE16(s23_c361_r, s23_c361_w, 0xffffffff) // C361
25942600   AM_RANGE(0x06a08000, 0x06a087ff) AM_RAM AM_SHARE("gammaram") // Gamma RAM (C404)
2595   AM_RANGE(0x06a10000, 0x06a3ffff) AM_RAM_WRITE(namcos23_paletteram_w) AM_SHARE("paletteram") // Palette RAM (C404)
2601   AM_RANGE(0x06a10000, 0x06a3ffff) AM_RAM_WRITE(s23_paletteram_w) AM_SHARE("paletteram") // Palette RAM (C404)
25962602   AM_RANGE(0x08000000, 0x08ffffff) AM_ROM AM_REGION("data", 0x0000000) AM_MIRROR(0x1000000) // data ROMs
25972603   AM_RANGE(0x0a000000, 0x0affffff) AM_ROM AM_REGION("data", 0x1000000) AM_MIRROR(0x1000000)
25982604   AM_RANGE(0x0c000000, 0x0c00001f) AM_READWRITE16(s23_c412_r, s23_c412_w, 0xffffffff)
25992605   AM_RANGE(0x0c400000, 0x0c400007) AM_READWRITE16(s23_c421_r, s23_c421_w, 0xffffffff)
26002606   AM_RANGE(0x0d000000, 0x0d00000f) AM_READWRITE16(s23_ctl_r, s23_ctl_w, 0xffffffff)
2601   AM_RANGE(0x0e800000, 0x0e800003) AM_READ(s23_unk_status_r) // error status, or protection? (also gets written to)
2607   AM_RANGE(0x0e800000, 0x0e800003) AM_READWRITE16(s23_sub_comm_r, s23_sub_comm_w, 0xffffffff) // not sure
26022608   AM_RANGE(0x0fc00000, 0x0fffffff) AM_WRITENOP AM_ROM AM_REGION("user1", 0)
26032609ADDRESS_MAP_END
26042610
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26862692   AM_RANGE(0x300030, 0x300031) AM_WRITENOP   // timecrs2 writes this when writing to the sync shared ram location, motoxgo doesn't
26872693ADDRESS_MAP_END
26882694
2695// port 8, looks like serial comms, where to/from?
26892696READ8_MEMBER(namcos23_state::s23_mcu_p8_r)
26902697{
26912698   return 0x02;
26922699}
26932700
2701WRITE8_MEMBER(namcos23_state::s23_mcu_p8_w)
2702{
2703   ;
2704}
2705
26942706// emulation of the Epson R4543 real time clock
26952707// in System 12, bit 0 of H8/3002 port A is connected to it's chip enable
26962708// the actual I/O takes place through the H8/3002's serial port B.
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27242736}
27252737
27262738
2727READ8_MEMBER(namcos23_state::s23_mcu_portB_r)
2739READ8_MEMBER(namcos23_state::s23_mcu_pb_r)
27282740{
2729   m_s23_lastpB ^= 0x80;
2730   return m_s23_lastpB;
2741   m_s23_lastpb ^= 0x80;
2742   return m_s23_lastpb;
27312743}
27322744
2733WRITE8_MEMBER(namcos23_state::s23_mcu_portB_w)
2745WRITE8_MEMBER(namcos23_state::s23_mcu_pb_w)
27342746{
27352747   // bit 7 = chip enable for the video settings controller
27362748   if (data & 0x80)
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27382750      m_s23_setstate = 0;
27392751   }
27402752
2741   m_s23_lastpB = data;
2753   m_s23_lastpb = data;
27422754}
27432755
27442756WRITE8_MEMBER(namcos23_state::s23_mcu_settings_w)
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30683080
30693081static ADDRESS_MAP_START( s23h8iomap, AS_IO, 8, namcos23_state )
30703082   AM_RANGE(H8_PORT_6, H8_PORT_6) AM_READWRITE(s23_mcu_p6_r, s23_mcu_p6_w )
3071   AM_RANGE(H8_PORT_8, H8_PORT_8) AM_READ(s23_mcu_p8_r ) AM_WRITENOP
3083   AM_RANGE(H8_PORT_8, H8_PORT_8) AM_READWRITE(s23_mcu_p8_r, s23_mcu_p8_w )
30723084   AM_RANGE(H8_PORT_A, H8_PORT_A) AM_READWRITE(s23_mcu_pa_r, s23_mcu_pa_w )
3073   AM_RANGE(H8_PORT_B, H8_PORT_B) AM_READWRITE(s23_mcu_portB_r, s23_mcu_portB_w )
3085   AM_RANGE(H8_PORT_B, H8_PORT_B) AM_READWRITE(s23_mcu_pb_r, s23_mcu_pb_w )
30743086   AM_RANGE(H8_SERIAL_0, H8_SERIAL_0) AM_READWRITE(s23_mcu_iob_r, s23_mcu_iob_w )
30753087   AM_RANGE(H8_SERIAL_1, H8_SERIAL_1) AM_READWRITE(s23_mcu_rtc_r, s23_mcu_settings_w )
30763088   AM_RANGE(H8_ADC_0_H, H8_ADC_0_L) AM_NOP
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30823094// version without serial hookup to I/O board for games where the PIC isn't dumped
30833095static ADDRESS_MAP_START( s23h8noiobmap, AS_IO, 8, namcos23_state )
30843096   AM_RANGE(H8_PORT_6, H8_PORT_6) AM_READWRITE(s23_mcu_p6_r, s23_mcu_p6_w )
3085   AM_RANGE(H8_PORT_8, H8_PORT_8) AM_READ(s23_mcu_p8_r ) AM_WRITENOP
3097   AM_RANGE(H8_PORT_8, H8_PORT_8) AM_READWRITE(s23_mcu_p8_r, s23_mcu_p8_w )
30863098   AM_RANGE(H8_PORT_A, H8_PORT_A) AM_READWRITE(s23_mcu_pa_r, s23_mcu_pa_w )
3087   AM_RANGE(H8_PORT_B, H8_PORT_B) AM_READWRITE(s23_mcu_portB_r, s23_mcu_portB_w )
3099   AM_RANGE(H8_PORT_B, H8_PORT_B) AM_READWRITE(s23_mcu_pb_r, s23_mcu_pb_w )
30883100   AM_RANGE(H8_SERIAL_1, H8_SERIAL_1) AM_READWRITE(s23_mcu_rtc_r, s23_mcu_settings_w )
30893101   AM_RANGE(H8_ADC_0_H, H8_ADC_0_L) AM_NOP
30903102   AM_RANGE(H8_ADC_1_H, H8_ADC_1_L) AM_NOP
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32193231   m_jvssense = 1;
32203232   m_main_irqcause = 0;
32213233   m_ctl_vbl_active = false;
3222   m_s23_lastpB = 0x50;
3234   m_s23_lastpb = 0x50;
32233235   m_s23_setstate = 0;
32243236   m_s23_setnum = 0;
32253237   memset(m_s23_settings, 0, sizeof(m_s23_settings));

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