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r19717 Friday 21st December, 2012 at 16:11:35 UTC by Curt Coder
(MESS) mm1: Trying to fix floppy. (nw)
[src/mess/drivers]mikromik.c
[src/mess/includes]mikromik.h
[src/mess/video]mikromik.c

trunk/src/mess/includes/mikromik.h
r19716r19717
4343        m_floppy0(*this, UPD765_TAG ":0:525qd"),
4444        m_floppy1(*this, UPD765_TAG ":1:525qd"),
4545        m_ram(*this, RAM_TAG),
46        m_video_ram(*this, "video_ram")
46        m_video_ram(*this, "video_ram"),
47        m_a8(0),
48        m_recall(0),
49        m_dack3(1),
50        m_tc(CLEAR_LINE)
4751   { }
4852
4953   required_device<cpu_device> m_maincpu;
r19716r19717
6670   virtual void video_start();
6771   UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
6872
69   DECLARE_READ8_MEMBER( mmu_r );
70   DECLARE_WRITE8_MEMBER( mmu_w );
73   DECLARE_READ8_MEMBER( read );
74   DECLARE_WRITE8_MEMBER( write );
7175   DECLARE_WRITE8_MEMBER( ls259_w );
7276   DECLARE_READ8_MEMBER( kb_r );
73   DECLARE_WRITE_LINE_MEMBER( dma_hrq_changed );
77   DECLARE_WRITE_LINE_MEMBER( dma_hrq_w );
7478   DECLARE_READ8_MEMBER( mpsc_dack_r );
7579   DECLARE_WRITE8_MEMBER( mpsc_dack_w );
76   DECLARE_WRITE_LINE_MEMBER( tc_w );
80   DECLARE_WRITE_LINE_MEMBER( dma_eop_w );
7781   DECLARE_WRITE_LINE_MEMBER( dack3_w );
7882   DECLARE_WRITE_LINE_MEMBER( itxc_w );
7983   DECLARE_WRITE_LINE_MEMBER( irxc_w );
r19716r19717
8185   DECLARE_WRITE_LINE_MEMBER( drq2_w );
8286   DECLARE_WRITE_LINE_MEMBER( drq1_w );
8387   DECLARE_READ_LINE_MEMBER( dsra_r );
84   DECLARE_PALETTE_INIT(mm1);
85   DECLARE_READ8_MEMBER(fdc_dma_r);
86   DECLARE_WRITE8_MEMBER(fdc_dma_w);
8788
88   void fdc_irq(bool state);
89   void fdc_drq(bool state);
89   void update_tc();
90   void fdc_intrq_w(bool state);
91   void fdc_drq_w(bool state);
9092
9193   void scan_keyboard();
9294
r19716r19717
114116   int m_recall;
115117   int m_dack3;
116118   int m_tc;
117   UINT32 screen_update_mm1(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
119
118120   TIMER_DEVICE_CALLBACK_MEMBER(kbclk_tick);
119121   DECLARE_FLOPPY_FORMATS( floppy_formats );
120122};
trunk/src/mess/video/mikromik.c
r19716r19717
4949//-------------------------------------------------
5050
5151static ADDRESS_MAP_START( mm1_upd7220_map, AS_0, 8, mm1_state )
52   AM_RANGE(0x00000, 0x3ffff) AM_RAM AM_SHARE("video_ram")
52   ADDRESS_MAP_GLOBAL_MASK(0x7fff)
53   AM_RANGE(0x0000, 0x7fff) AM_RAM AM_SHARE("video_ram")
5354ADDRESS_MAP_END
5455
5556
r19716r19717
6162{
6263   mm1_state *state = device->machine().driver_data<mm1_state>();
6364
64   UINT8 data = state->m_video_ram[address * 2];
65   UINT8 data = state->m_video_ram[address];
6566
6667   for (int i = 0; i < 8; i++)
6768   {
trunk/src/mess/drivers/mikromik.c
r19716r19717
5959//  MACROS / CONSTANTS
6060//**************************************************************************
6161
62#define LOG 0
62#define LOG 1
6363
64#define MMU_IOEN_MEMEN   0x01
65#define MMU_RAMEN      0x02
66#define MMU_CE4         0x08
67#define MMU_CE0         0x10
68#define MMU_CE1         0x20
69#define MMU_CE2         0x40
70#define MMU_CE3         0x80
64#define MMU_IOEN   0x01
65#define MMU_RAMEN   0x02
66#define MMU_CE4      0x08
67#define MMU_CE0      0x10
68#define MMU_CE1      0x20
69#define MMU_CE2      0x40
70#define MMU_CE3      0x80
7171
7272
7373
r19716r19717
7676//**************************************************************************
7777
7878//-------------------------------------------------
79//  mmu_r -
79//  read -
8080//-------------------------------------------------
8181
82READ8_MEMBER( mm1_state::mmu_r )
82READ8_MEMBER( mm1_state::read )
8383{
8484   UINT8 data = 0;
8585   UINT8 mmu = m_mmu_rom[(m_a8 << 8) | (offset >> 8)];
8686
87   if (mmu & MMU_IOEN_MEMEN)
87   if (mmu & MMU_IOEN)
8888   {
8989      switch ((offset >> 4) & 0x07)
9090      {
r19716r19717
146146
147147
148148//-------------------------------------------------
149//  mmu_w -
149//  write -
150150//-------------------------------------------------
151151
152WRITE8_MEMBER( mm1_state::mmu_w )
152WRITE8_MEMBER( mm1_state::write )
153153{
154154   UINT8 mmu = m_mmu_rom[(m_a8 << 8) | (offset >> 8)];
155155
156   if (mmu & MMU_IOEN_MEMEN)
156   if (mmu & MMU_IOEN)
157157   {
158158      switch ((offset >> 4) & 0x07)
159159      {
r19716r19717
221221   case 1: // RECALL
222222      if (LOG) logerror("RECALL %u\n", d);
223223      m_recall = d;
224      if(d)
225         m_fdc->reset();
224      if (d) m_fdc->reset();
226225      break;
227226
228227   case 2: // _RV28/RX21
r19716r19717
333332//-------------------------------------------------
334333
335334static ADDRESS_MAP_START( mm1_map, AS_PROGRAM, 8, mm1_state )
336   AM_RANGE(0x0000, 0xffff) AM_READWRITE(mmu_r, mmu_w)
335   AM_RANGE(0x0000, 0xffff) AM_READWRITE(read, write)
337336ADDRESS_MAP_END
338337
339338
r19716r19717
485484//  I8237_INTERFACE( dmac_intf )
486485//-------------------------------------------------
487486
488WRITE_LINE_MEMBER( mm1_state::dma_hrq_changed )
487void mm1_state::update_tc()
489488{
489   m_fdc->tc_w(m_tc && !m_dack3);
490}
491
492WRITE_LINE_MEMBER( mm1_state::dma_hrq_w )
493{
490494   m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
491495
492496   // Assert HLDA
r19716r19717
509513   m_dmac->dreq1_w(CLEAR_LINE);
510514}
511515
512WRITE_LINE_MEMBER( mm1_state::tc_w )
516WRITE_LINE_MEMBER( mm1_state::dma_eop_w )
513517{
514   if (!m_dack3)
515   {
516      // floppy terminal count
517      m_fdc->tc_w(!state);
518   }
519
520   m_tc = !state;
521
522518   m_maincpu->set_input_line(I8085_RST75_LINE, state);
519
520   m_tc = state;
521   update_tc();
523522}
524523
525524WRITE_LINE_MEMBER( mm1_state::dack3_w )
526525{
527526   m_dack3 = state;
528
529   if (!m_dack3)
530   {
531      // floppy terminal count
532      m_fdc->tc_w(m_tc);
533   }
527   update_tc();
534528}
535529
536static UINT8 memory_read_byte(address_space &space, offs_t address, UINT8 mem_mask) { return space.read_byte(address); }
537static void memory_write_byte(address_space &space, offs_t address, UINT8 data, UINT8 mem_mask) { space.write_byte(address, data); }
538
539READ8_MEMBER( mm1_state::fdc_dma_r )
540{
541   return m_fdc->dma_r();
542}
543
544WRITE8_MEMBER( mm1_state::fdc_dma_w )
545{
546   m_fdc->dma_w(data);
547}
548
549530static I8237_INTERFACE( dmac_intf )
550531{
551   DEVCB_DRIVER_LINE_MEMBER(mm1_state, dma_hrq_changed),
552   DEVCB_DRIVER_LINE_MEMBER(mm1_state, tc_w),
553   DEVCB_MEMORY_HANDLER(I8085A_TAG, PROGRAM, memory_read_byte),
554   DEVCB_MEMORY_HANDLER(I8085A_TAG, PROGRAM, memory_write_byte),
555   { DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(mm1_state, mpsc_dack_r),  DEVCB_DRIVER_MEMBER(mm1_state, fdc_dma_r) },
556   { DEVCB_DEVICE_HANDLER(I8275_TAG, i8275_dack_w), DEVCB_DRIVER_MEMBER(mm1_state, mpsc_dack_w), DEVCB_NULL, DEVCB_DRIVER_MEMBER(mm1_state, fdc_dma_w) },
532   DEVCB_DRIVER_LINE_MEMBER(mm1_state, dma_hrq_w),
533   DEVCB_DRIVER_LINE_MEMBER(mm1_state, dma_eop_w),
534   DEVCB_DRIVER_MEMBER(mm1_state, read),
535   DEVCB_DRIVER_MEMBER(mm1_state, write),
536   { DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(mm1_state, mpsc_dack_r),  DEVCB_DEVICE_MEMBER(UPD765_TAG, upd765_family_device, mdma_r) },
537   { DEVCB_DEVICE_HANDLER(I8275_TAG, i8275_dack_w), DEVCB_DRIVER_MEMBER(mm1_state, mpsc_dack_w), DEVCB_NULL, DEVCB_DEVICE_MEMBER(UPD765_TAG, upd765_family_device, mdma_w) },
557538   { DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_LINE_MEMBER(mm1_state, dack3_w) }
558539};
559540
r19716r19717
693674   SLOT_INTERFACE( "525qd", FLOPPY_525_QD )
694675SLOT_INTERFACE_END
695676
696void mm1_state::fdc_irq(bool state)
677void mm1_state::fdc_intrq_w(bool state)
697678{
698679   m_maincpu->set_input_line(I8085_RST55_LINE, state ? ASSERT_LINE : CLEAR_LINE);
699680}
700681
701void mm1_state::fdc_drq(bool state)
682void mm1_state::fdc_drq_w(bool state)
702683{
703684   m_dmac->dreq3_w(state);
704685}
r19716r19717
715696void mm1_state::machine_start()
716697{
717698   // floppy callbacks
718   m_fdc->setup_intrq_cb(upd765a_device::line_cb(FUNC(mm1_state::fdc_irq), this));
719   m_fdc->setup_drq_cb(upd765a_device::line_cb(FUNC(mm1_state::fdc_drq), this));
699   m_fdc->setup_intrq_cb(upd765_family_device::line_cb(FUNC(mm1_state::fdc_intrq_w), this));
700   m_fdc->setup_drq_cb(upd765_family_device::line_cb(FUNC(mm1_state::fdc_drq_w), this));
720701
721702   // find memory regions
722703   m_mmu_rom = memregion("address")->base();
r19716r19717
731712   save_item(NAME(m_tx21));
732713   save_item(NAME(m_rcl));
733714   save_item(NAME(m_recall));
734   save_item(NAME(m_dack3));
735715}
736716
737717
r19716r19717
742722void mm1_state::machine_reset()
743723{
744724   address_space &program = m_maincpu->space(AS_PROGRAM);
745   int i;
746725
747726   // reset LS259
748   for (i = 0; i < 8; i++) ls259_w(program, i, 0);
727   for (int i = 0; i < 8; i++)
728   {
729      ls259_w(program, i, 0);
730   }
749731
750732   // reset FDC
751733   m_fdc->reset();
r19716r19717
766748   MCFG_CPU_ADD(I8085A_TAG, I8085A, XTAL_6_144MHz)
767749   MCFG_CPU_PROGRAM_MAP(mm1_map)
768750   MCFG_CPU_CONFIG(i8085_intf)
751   MCFG_QUANTUM_PERFECT_CPU(I8085A_TAG)
769752
770753   MCFG_TIMER_DRIVER_ADD_PERIODIC("kbclk", mm1_state, kbclk_tick, attotime::from_hz(2500))
771754

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