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r19692 Wednesday 19th December, 2012 at 20:02:43 UTC by Phil Bennett
New games added or promoted from NOT_WORKING status
---------------------------------------------------

Rise of the Robots (prototype) [Phil Bennett, Ordyne]
[src/mame]mame.lst mame.mak
[src/mame/drivers]rastersp.c*

trunk/src/mame/mame.mak
r19691r19692
550550   $(DRIVERS)/bfmsys85.o \
551551   $(MACHINE)/sec.o \
552552   $(MACHINE)/bfm_bd1.o $(MACHINE)/bfm_bda.o $(VIDEO)/bfm_dm01.o \
553   $(DRIVERS)/rastersp.o \
553554
554555$(MAMEOBJ)/bmc.a: \
555556   $(DRIVERS)/bmcbowl.o \
trunk/src/mame/drivers/rastersp.c
r0r19692
1/***************************************************************************
2
3    Bell-Fruit/ATD RasterSpeed hardware
4
5    driver by Phil Bennett
6
7   Games supported:
8      * Rise of the Robots (prototype)
9
10   ROMs wanted:
11      * Zool (prototype)
12      * Football Crazy (need HDD/CD image)
13
14****************************************************************************/
15
16#include "emu.h"
17#include "cpu/i386/i386.h"
18#include "cpu/tms32031/tms32031.h"
19#include "machine/53c7xx.h"
20#include "machine/mc146818.h"
21#include "machine/nscsi_hd.h"
22#include "sound/dac.h"
23
24
25/*************************************
26 *
27 *  Defines
28 *
29 *************************************/
30
31#define   SOUND_CLOCK            XTAL_12_288MHz
32#define PLL_CLOCK            XTAL_14_31818MHz
33#define NVRAM_SIZE            0x8000
34
35#define USE_SPEEDUP_HACK      1
36
37
38/*************************************
39 *
40 *  Driver class
41 *
42 *************************************/
43
44static IRQ_CALLBACK( irq_callback );
45
46class rastersp_state : public driver_device
47{
48public:
49   rastersp_state(const machine_config &mconfig, device_type type, const char *tag)
50      : driver_device(mconfig, type, tag),
51        m_maincpu(*this, "maincpu"),
52        m_dsp(*this, "dsp"),
53        m_dram(*this, "dram"),
54        m_dac_l(*this, "dac_l"),
55        m_dac_r(*this, "dac_r"),
56        m_tms_timer1(*this, "tms_timer1"),
57        m_tms_tx_timer(*this, "tms_tx_timer")
58   {}
59
60   #define VIDEO_ADDR_MASK      0x3fffffff
61
62   enum tms_regs
63   {
64      DMA_GLOBAL_CTL      =   0x00,
65      DMA_SOURCE_ADDR      =   0x04,
66      DMA_DEST_ADDR      =   0x06,
67      DMA_TRANSFER_COUNT   =   0x08,
68
69      TIMER0_GLOBAL_CTL   =   0x20,
70      TIMER0_COUNTER      =   0x24,
71      TIMER0_PERIOD      =   0x28,
72
73      TIMER1_GLOBAL_CTL   =   0x30,
74      TIMER1_COUNTER      =   0x34,
75      TIMER1_PERIOD      =   0x38,
76
77      SPORT_GLOBAL_CTL   =   0x40,
78      SPORT_TX_CTL      =   0x42,
79      SPORT_RX_CTL      =   0x43,
80      SPORT_TIMER_CTL      =   0x44,
81      SPORT_TIMER_COUNTER   =   0x45,
82      SPORT_TIMER_PERIOD   =   0x46,
83      SPORT_DATA_TX      =   0x48,
84      SPORT_DATA_RX      =   0x4c,
85   };
86
87   enum irq_status
88   {
89      IRQ_RTC      = 1,
90      IRQ_UART   = 2,
91      IRQ_DSP      = 4,
92      IRQ_VBLANK   = 5,
93      IRQ_SCSI   = 7,
94   };
95
96   required_device<cpu_device>      m_maincpu;
97   required_device<cpu_device>      m_dsp;
98   required_shared_ptr<UINT32>      m_dram;
99   required_device<dac_device>      m_dac_l;
100   required_device<dac_device>      m_dac_r;
101   required_device<timer_device>   m_tms_timer1;
102   required_device<timer_device>   m_tms_tx_timer;
103
104   DECLARE_WRITE32_MEMBER(cyrix_cache_w);
105   DECLARE_READ8_MEMBER(nvram_r);
106   DECLARE_WRITE8_MEMBER(nvram_w);
107   DECLARE_WRITE32_MEMBER(port1_w);
108   DECLARE_WRITE32_MEMBER(port2_w);
109   DECLARE_WRITE32_MEMBER(port3_w);
110   DECLARE_WRITE32_MEMBER(dpylist_w);
111   DECLARE_READ32_MEMBER(tms32031_control_r);
112   DECLARE_WRITE32_MEMBER(tms32031_control_w);
113   DECLARE_WRITE32_MEMBER(dsp_unk_w);
114   DECLARE_WRITE32_MEMBER(dsp_ctrl_w);
115   DECLARE_WRITE32_MEMBER(dsp_486_int_w);
116   DECLARE_READ32_MEMBER(dsp_speedup_r);
117   DECLARE_WRITE32_MEMBER(dsp_speedup_w);
118   DECLARE_WRITE_LINE_MEMBER(scsi_irq);
119
120   TIMER_DEVICE_CALLBACK_MEMBER(tms_timer1);
121   TIMER_DEVICE_CALLBACK_MEMBER(tms_tx_timer);
122   INTERRUPT_GEN_MEMBER(vblank_irq);
123
124   UINT8   *m_nvram8;
125   UINT8   m_io_reg;
126   UINT8   m_irq_status;
127   UINT32   m_dpyaddr;
128   UINT16 *m_palette;
129   UINT32   m_speedup_count;
130   UINT32   m_tms_io_regs[0x80];
131
132   UINT32   screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
133   void   update_irq(UINT32 which, UINT32 state);
134   void   upload_palette(UINT32 word1, UINT32 word2);
135
136protected:
137   // driver_device overrides
138   virtual void machine_reset();
139   virtual void machine_start();
140   virtual void video_start();
141};
142
143
144
145/*************************************
146 *
147 *  Initialisation
148 *
149 *************************************/
150
151void rastersp_state::machine_start()
152{
153   machine().device("maincpu")->execute().set_irq_acknowledge_callback(irq_callback);
154
155   m_nvram8 = auto_alloc_array(machine(), UINT8, NVRAM_SIZE);
156
157   m_palette = auto_alloc_array(machine(), UINT16, 0x8000);
158
159   machine().root_device().membank("bank1")->set_base(m_dram);
160   machine().root_device().membank("bank2")->set_base(&m_dram[0x10000/4]);
161   machine().root_device().membank("bank3")->set_base(&m_dram[0x300000/4]);
162
163#if USE_SPEEDUP_HACK
164   machine().device("dsp")->memory().space(AS_PROGRAM).install_read_handler(0x809923, 0x809923, read32_delegate(FUNC(rastersp_state::dsp_speedup_r), this));
165   machine().device("dsp")->memory().space(AS_PROGRAM).install_write_handler(0x809923, 0x809923, write32_delegate(FUNC(rastersp_state::dsp_speedup_w), this));
166#endif
167}
168
169
170void rastersp_state::machine_reset()
171{
172   m_irq_status = 0;
173   m_dpyaddr = 0;
174
175   // Halt the 486 on reset - the DSP will release it from reset
176   m_maincpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
177
178   // Set IRQ1 line to cause DSP to boot from 0x400000
179   m_dsp->set_input_line(TMS3203X_IRQ1, ASSERT_LINE);
180   m_dsp->set_input_line(TMS3203X_IRQ1, CLEAR_LINE);
181
182   // Reset DSP internal registers
183   m_tms_io_regs[SPORT_GLOBAL_CTL] = 0;
184}
185
186
187
188/*************************************
189 *
190 *  Video hardware
191 *
192 *************************************/
193
194void rastersp_state::video_start()
195{
196
197}
198
199
200WRITE32_MEMBER( rastersp_state::dpylist_w )
201{
202   m_dpyaddr = data;
203
204}
205
206
207void rastersp_state::upload_palette(UINT32 word1, UINT32 word2)
208{
209   if (word1 & 3)
210      fatalerror("Unalligned palette address! (%x, %x)\n", word1, word2);
211
212   UINT32 addr = word1 >> 8;
213   UINT32 entries = (word2 >> 16) & 0x1ff;
214   UINT32 index = ((word2 >> 12) & 0x1f) * 256;
215
216   // The third byte of each entry in RAM appears to contain an index
217   // but appears to be discared when written to palette RAM
218   while (entries--)
219   {
220      UINT32 data = m_dram[addr / 4];
221      m_palette[index++] = data & 0xffff;
222      addr += 4;
223   }
224}
225
226
227/*******************************************************************************
228
229   Display list register:
230
231   ..xxxxxx xxxxxxxx xxxxxxxx ........    Display list base (DWORD granularity)
232   ........ ........ ........ xxxxxxxx  ? (number of entries? Only seems to be valid for basic stuff)
233
234   Display list format:
235
236[0] ..xxxxxx xxxxxxxx xxxxxxxx ........    Source address (4MB mask?)
237
238Palette update: (8d000400)
239[1] 1....... ........ ........ ........  ?
240    ...0.... ........ ........ ........  0 for palette upload?
241   ....11.. ........ ........ ........  ?
242    .......x xxxxxxxx ........ ........  Entry count
243    ........ ........ .....1.. ........  ? (Usually 1)
244
245Pixel data: (94040100)
246[2] 1....... ........ ........ ........  ?
247    ...1.... ........ ........ ........  1 for video update?
248   .....1.. ........ ........ ........  ?
249    .......x xxxxxxxx ........ ........  Pixel count
250    ........ ........ xxxx.... ........  Palette
251   ........ ........ ....xxxx xxxxxxxx  Scale (4.8 signed fixed point)
252
253Unknown: (D4000100) - Present at start of a list
254[3] 1....... ........ ........ .........
255    .1...... ........ ........ ......... ?
256    ..1..... ........ ........ .........
257   .....1.. ........ ........ ......... ?
258   ........ ........ .......1 ......... ?
259
260
261   TODO: I'm not sure about bit 28. When creating the display list if it's 0,
262   0x1000 is added to the source address.
263
264*******************************************************************************/
265
266UINT32 rastersp_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
267{
268   if (m_dpyaddr == 0)
269   {
270      bitmap.fill(get_black_pen(machine()), cliprect);
271      return 0;
272   }
273
274   UINT32 dpladdr = (m_dpyaddr & ~0xff) >> 6;
275
276   if ((m_dpyaddr & 0xff) != 0xb2 && (m_dpyaddr & 0xff) != 0xf2)
277      logerror("Unusual display list data: %x\n", m_dpyaddr);
278
279   int y = cliprect.min_y;
280   int x = cliprect.min_x;
281   UINT16 *bmpptr = &bitmap.pix16(cliprect.min_y, cliprect.min_x);
282
283   while (y <= cliprect.max_y)
284   {
285      UINT32 word1 = m_dram[dpladdr/4];
286
287      if (word1 & 0x80000000)
288      {
289         // TODO: What does this signify?
290         dpladdr += 4;
291      }
292      else
293      {
294         UINT32 word2 = m_dram[(dpladdr + 4)/4];
295
296         dpladdr += 8;
297
298         if (word2 & 0x10000000)
299         {
300            if ((word2 & 0xfe000000) != 0x94000000)
301               logerror("Unusual display list entry: %x %x\n", word1, word2);
302
303            UINT32 srcaddr = word1 >> 8;
304            UINT32 pixels = (word2 >> 16) & 0x1ff;
305            UINT32 palbase = (word2 >> 4) & 0xf00;
306
307            UINT16* palptr = &m_palette[palbase];
308            UINT8* srcptr = reinterpret_cast<UINT8*>(&m_dram[0]);
309
310            UINT32 acc = srcaddr << 8;
311
312            INT32 incr = word2 & 0xfff;
313
314            // Sign extend for our convenience
315            incr |= ~((incr & 0x800) - 1) & ~0xff;
316
317            // TODO: Assumes 8-bit palettized mode - the hardware also supports 16-bit direct
318            while (y <= cliprect.max_y && pixels)
319            {
320               while (x <= cliprect.max_x && pixels)
321               {
322                  *bmpptr++ = palptr[srcptr[BYTE_XOR_LE(acc >> 8)]];
323                  acc = (acc + incr) & VIDEO_ADDR_MASK;
324
325                  --pixels;
326                  ++x;
327               }
328
329               // Advance to the next scanline
330               if (x > cliprect.max_x)
331               {
332                  x = cliprect.min_x;
333                  ++y;
334               }
335            }
336         }
337         else
338         {
339            if ((word2 & 0x0c000000) != 0x0c000000)
340               logerror("Unknown palette upload: %.8x %.8x\n", word1, word2);
341
342            upload_palette(word1, word2);
343         }
344      }
345   }
346
347   return 0;
348}
349
350
351
352/*************************************
353 *
354 *  Interrupt handling
355 *
356 *************************************/
357
358static IRQ_CALLBACK( irq_callback )
359{
360   rastersp_state *state = device->machine().driver_data<rastersp_state>();
361
362   UINT8 vector = 0;
363
364   if (state->m_irq_status & (1 << rastersp_state::IRQ_SCSI))
365   {
366      vector = 11;
367   }
368   else if (state->m_irq_status & (1 << rastersp_state::IRQ_DSP))
369   {
370      state->update_irq(rastersp_state::IRQ_DSP, CLEAR_LINE);
371      vector = 12;
372   }
373   else if (state->m_irq_status & (1 << rastersp_state::IRQ_VBLANK))
374   {
375      state->update_irq(rastersp_state::IRQ_VBLANK, CLEAR_LINE);
376      vector = 13;
377   }
378   else
379   {
380      fatalerror("Unknown x86 IRQ (m_irq_status = %x)", state->m_irq_status);
381   }
382
383   return vector;
384}
385
386
387void rastersp_state::update_irq(UINT32 which, UINT32 state)
388{
389   UINT32 mask = 1 << which;
390
391   if (state)
392      m_irq_status |= mask;
393   else
394      m_irq_status &= ~mask;
395
396   m_maincpu->set_input_line(0, m_irq_status ? HOLD_LINE : CLEAR_LINE);
397}
398
399
400WRITE_LINE_MEMBER( rastersp_state::scsi_irq )
401{
402   update_irq(IRQ_SCSI, state);
403}
404
405
406INTERRUPT_GEN_MEMBER( rastersp_state::vblank_irq )
407{
408   update_irq(IRQ_VBLANK, ASSERT_LINE);
409}
410
411
412
413/*************************************
414 *
415 *  486 I/O
416 *
417 *************************************/
418
419WRITE32_MEMBER( rastersp_state::port1_w )
420{
421   // x... .... - LED?
422   // ..x. .... - DSP IRQ2 line
423   // .... ..xx - LEDs?
424
425   if (data & 0x20)
426   {
427      m_dsp->set_input_line(TMS3203X_IRQ2, ASSERT_LINE);
428      m_dsp->set_input_line(TMS3203X_IRQ2, CLEAR_LINE);
429   }
430}
431
432
433WRITE32_MEMBER( rastersp_state::port2_w )
434{
435   // .x.. .... - X9313WP /INC
436   // ..x. .... - X9313WP U/#D
437}
438
439
440WRITE32_MEMBER( rastersp_state:: port3_w )
441{
442   // xxxx xxxx - 8 LED cluster?
443}
444
445
446
447/*************************************
448 *
449 *  NVRAM
450 *
451 *************************************/
452
453static NVRAM_HANDLER( rastersp )
454{
455   rastersp_state *state = machine.driver_data<rastersp_state>();
456
457   if (read_or_write)
458   {
459      file->write(state->m_nvram8, NVRAM_SIZE);
460   }
461   else if (file)
462   {
463      file->read(state->m_nvram8, NVRAM_SIZE);
464   }
465   else
466   {
467      memcpy(state->m_nvram8, machine.root_device().memregion("nvram")->base(), NVRAM_SIZE);
468   }
469}
470
471
472WRITE8_MEMBER( rastersp_state::nvram_w )
473{
474   offset *= 4;
475
476   if ((offset & 0xc000) || !(offset & 0x2000))
477   {
478      logerror("Unmapped NVRAM write to offset: %x", offset);
479   }
480
481   offset &= ~0x2000;
482
483   UINT32 addr = ((offset & 0x00f0000) >> 5) | ((offset & 0x1fff) / 4);
484
485   m_nvram8[addr] = data & 0xff;
486}
487
488
489READ8_MEMBER( rastersp_state::nvram_r )
490{
491   offset *= 4;
492
493   if ((offset & 0xc000) || !(offset & 0x2000))
494   {
495      logerror("Unmapped NVRAM read from offset: %x", offset);
496   }
497
498   offset &= ~0x2000;
499
500   UINT32 addr = ((offset & 0x00f0000) >> 5) | ((offset & 0x1fff) / 4);
501
502   return m_nvram8[addr];
503}
504
505
506WRITE32_MEMBER( rastersp_state::cyrix_cache_w )
507{
508   // TODO?
509}
510
511
512
513/*************************************
514 *
515 *  DSP
516 *
517 *************************************/
518
519TIMER_DEVICE_CALLBACK_MEMBER( rastersp_state::tms_tx_timer )
520{
521   // Is the transmit shifter full?
522   if (m_tms_io_regs[SPORT_GLOBAL_CTL] & (1 << 3))
523   {
524      UINT32 data = m_tms_io_regs[SPORT_DATA_TX];
525
526      INT16 ldata = data & 0xffff;
527      INT16 rdata = data >> 16;
528
529      m_dac_l->write_signed16(0x8000 + ldata);
530      m_dac_r->write_signed16(0x8000 + rdata);
531   }
532
533   // Set XSREMPTY
534   m_tms_io_regs[SPORT_GLOBAL_CTL] &= ~(1 << 3);
535
536   // Set XRDY
537   m_tms_io_regs[SPORT_GLOBAL_CTL] |= (1 << 1);
538
539   // Signal a transmit interrupt
540   if (m_tms_io_regs[SPORT_GLOBAL_CTL] & (1 << 23))
541   {
542      m_dsp->set_input_line(TMS3203X_XINT0, ASSERT_LINE);
543      m_dsp->set_input_line(TMS3203X_XINT0, CLEAR_LINE);
544   }
545}
546
547
548TIMER_DEVICE_CALLBACK_MEMBER( rastersp_state::tms_timer1 )
549{
550
551}
552
553
554READ32_MEMBER( rastersp_state::tms32031_control_r )
555{
556   UINT32 val = m_tms_io_regs[offset];
557
558   switch (offset)
559   {
560      case TIMER1_COUNTER:
561      {
562         attotime elapsed = m_tms_timer1->time_elapsed();
563         val = m_tms_io_regs[TIMER1_PERIOD] - (elapsed.as_ticks(m_dsp->clock() / 2 / 2));
564
565         break;
566      }
567      default:
568      {
569         logerror("TMS32031: Unhandled I/O read: %x\n", offset);
570      }
571   }
572
573   return val;
574}
575
576
577WRITE32_MEMBER( rastersp_state::tms32031_control_w )
578{
579   UINT32 old = m_tms_io_regs[offset];
580
581   m_tms_io_regs[offset] = data;
582
583   switch (offset)
584   {
585      case TIMER1_GLOBAL_CTL:
586      {
587         // Calculate the DSP clocks
588         attotime period = attotime::from_hz(m_dsp->clock() / 2 / 2);
589
590         period *= m_tms_io_regs[TIMER1_PERIOD];
591
592         m_tms_timer1->adjust(period, 0, period);
593
594         break;
595      }
596      case SPORT_GLOBAL_CTL:
597      {
598         if (!(data & (1 << 26)))
599         {
600            // Reset transmitter
601            m_tms_tx_timer->adjust(attotime::never);
602         }
603         else if (!(old & (1 << 26)) && (data & (1 << 26)))
604         {
605            // Sample rate is 24KHz
606            attotime period = attotime::from_hz(SOUND_CLOCK / 512);
607
608            // Set XRDY
609            m_tms_io_regs[SPORT_GLOBAL_CTL] |= (1 << 1);
610
611            // Set XSREMPTY
612            m_tms_io_regs[SPORT_GLOBAL_CTL] &= ~(1 << 3);
613
614            // Run transmitter
615            m_tms_tx_timer->adjust(period, 0, period);
616         }
617
618         break;
619      }
620      case SPORT_DATA_TX:
621      {
622         // Clear XRDY
623         m_tms_io_regs[SPORT_GLOBAL_CTL] &= ~(1 << 1);
624
625         // Clear XSREMPTY
626         m_tms_io_regs[SPORT_GLOBAL_CTL] |= (1 << 3);
627
628         break;
629      }
630      default:
631      {
632         logerror("TMS32031: Unhandled I/O write: %x %x\n", offset, data);
633      }
634   }
635}
636
637
638WRITE32_MEMBER( rastersp_state::dsp_unk_w )
639{
640   // TODO: Looks like a debug port?
641}
642
643
644WRITE32_MEMBER( rastersp_state::dsp_486_int_w )
645{
646
647   update_irq(IRQ_DSP, ASSERT_LINE);
648}
649
650
651WRITE32_MEMBER( rastersp_state::dsp_ctrl_w )
652{
653   // x... .... LED?
654   // .xx. .... 486 reset control?
655
656   m_maincpu->set_input_line(INPUT_LINE_RESET, (data & 0x60) == 0x60 ? CLEAR_LINE : ASSERT_LINE);
657}
658
659
660WRITE32_MEMBER( rastersp_state::dsp_speedup_w )
661{
662   // 809e90  48fd, 48d5
663   if (space.device().safe_pc() == 0x809c23)
664   {
665      INT32 cycles_left = space.device().execute().cycles_remaining();
666      data += cycles_left / 6;
667      space.device().execute().spin();
668   }
669
670   m_speedup_count = data;
671}
672
673
674READ32_MEMBER( rastersp_state::dsp_speedup_r )
675{
676   return m_speedup_count;
677}
678
679
680/*************************************
681 *
682 *  Memory maps
683 *
684 *************************************/
685
686static ADDRESS_MAP_START( cpu_map, AS_PROGRAM, 32, rastersp_state )
687   AM_RANGE(0x00000000, 0x003fffff) AM_RAM AM_SHARE("dram")
688   AM_RANGE(0x01000000, 0x010bffff) AM_NOP // External ROM
689   AM_RANGE(0x010c0000, 0x010cffff) AM_ROM AM_REGION("bios", 0)
690   AM_RANGE(0x02200800, 0x02200803) AM_WRITENOP // ?
691   AM_RANGE(0x02208000, 0x02208fff) AM_DEVREADWRITE("scsibus:7:ncr53c700", ncr53c7xx_device, read, write)
692   AM_RANGE(0x0220e000, 0x0220e003) AM_WRITE(dpylist_w)
693   AM_RANGE(0x02200000, 0x022fffff) AM_READWRITE8(nvram_r, nvram_w, 0x000000ff)
694   AM_RANGE(0xfff00000, 0xffffffff) AM_RAMBANK("bank3")
695ADDRESS_MAP_END
696
697static ADDRESS_MAP_START( io_map, AS_IO, 32, rastersp_state )
698   AM_RANGE(0x0020, 0x0023) AM_WRITE(cyrix_cache_w)
699   AM_RANGE(0x1000, 0x1003) AM_READ_PORT("P1") AM_WRITE(port1_w)
700   AM_RANGE(0x1004, 0x1007) AM_READ_PORT("P2") AM_WRITE(port2_w)
701   AM_RANGE(0x1008, 0x100b) AM_READ_PORT("COMMON") AM_WRITE(port3_w)
702   AM_RANGE(0x100c, 0x100f) AM_READ_PORT("DSW2")
703   AM_RANGE(0x1010, 0x1013) AM_READ_PORT("DSW1")
704   AM_RANGE(0x1014, 0x1017) AM_READ_PORT("EXTRA")
705   AM_RANGE(0x4000, 0x4007) AM_DEVREADWRITE8("rtc", mc146818_device, read, write, 0x000000ff)
706   AM_RANGE(0x6008, 0x600b) AM_READNOP AM_WRITENOP // RS232
707ADDRESS_MAP_END
708
709
710static ADDRESS_MAP_START( dsp_map, AS_PROGRAM, 32, rastersp_state )
711   AM_RANGE(0x000000, 0x0fffff) AM_RAMBANK("bank1")
712   AM_RANGE(0x400000, 0x40ffff) AM_ROM AM_REGION("dspboot", 0)
713   AM_RANGE(0x808000, 0x80807f) AM_READWRITE(tms32031_control_r, tms32031_control_w)
714   AM_RANGE(0x880402, 0x880402) AM_WRITE(dsp_unk_w)
715   AM_RANGE(0x883c00, 0x883c00) AM_WRITE(dsp_486_int_w)
716   AM_RANGE(0xc00000, 0xc03fff) AM_RAMBANK("bank2")
717   AM_RANGE(0xc80000, 0xc80000) AM_WRITE(dsp_ctrl_w)
718   AM_RANGE(0xfc0000, 0xffffff) AM_RAMBANK("bank3")
719ADDRESS_MAP_END
720
721
722
723/*************************************
724 *
725 *  Inputs
726 *
727 *************************************/
728
729static INPUT_PORTS_START( rotr )
730   PORT_START("P1")
731   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
732   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
733   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
734   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
735   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
736   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
737   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
738   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1)
739
740   PORT_START("P2")
741   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
742   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
743   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
744   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
745   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
746   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
747   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
748   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2)
749
750   PORT_START("COMMON")
751   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
752   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
753   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
754   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
755   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE )
756   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_TILT )
757   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
758   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
759
760   PORT_START("EXTRA")
761   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(1)
762   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(1)
763   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON7 ) PORT_PLAYER(1)
764   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON8 ) PORT_PLAYER(1)
765   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(2)
766   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(2)
767   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON7 ) PORT_PLAYER(2)
768   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON8 ) PORT_PLAYER(2)
769
770   PORT_START("DSW1")
771   PORT_DIPNAME( 0x01, 0x01, "Setup Disk" )
772   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
773   PORT_DIPSETTING(    0x01, DEF_STR( On ) )
774
775   PORT_DIPNAME( 0x02, 0x00, DEF_STR( Service_Mode ) )
776   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
777   PORT_DIPSETTING(    0x02, DEF_STR( On ) )
778
779   PORT_DIPNAME( 0x3c, 0x00, "Load PROG" )
780   PORT_DIPSETTING(    0x00, "0" )
781   PORT_DIPSETTING(    0x04, "1" )
782   PORT_DIPSETTING(    0x08, "2" )
783   PORT_DIPSETTING(    0x0c, "3" )
784   PORT_DIPSETTING(    0x10, "4" )
785   PORT_DIPSETTING(    0x14, "5" )
786   PORT_DIPSETTING(    0x18, "6" )
787   PORT_DIPSETTING(    0x1c, "7" )
788   PORT_DIPSETTING(    0x20, "8" )
789   PORT_DIPSETTING(    0x24, "9" )
790   PORT_DIPSETTING(    0x28, "A" )
791   PORT_DIPSETTING(    0x2c, "B" )
792   PORT_DIPSETTING(    0x30, "C" )
793   PORT_DIPSETTING(    0x34, "D" )
794   PORT_DIPSETTING(    0x38, "E" )
795   PORT_DIPSETTING(    0x3c, "F" )
796
797   PORT_DIPNAME( 0x40, 0x00, "Reserved" )
798   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
799   PORT_DIPSETTING(    0x40, DEF_STR( On ) )
800
801   PORT_DIPNAME( 0x80, 0x00, "Enable Cache" )
802   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
803   PORT_DIPSETTING(    0x80, DEF_STR( On ) )
804
805   PORT_START("DSW2")
806   PORT_DIPNAME( 0x01, 0x00, "Debug Screen" )
807   PORT_DIPSETTING(   0x00, DEF_STR( Off ) )
808   PORT_DIPSETTING(    0x01, DEF_STR( On ) )
809
810   PORT_DIPNAME( 0x0e, 0x00, "FPGA File Source" )
811   PORT_DIPSETTING(   0x00, "Serial PROMs" )
812   PORT_DIPSETTING(    0x0e, "Cable" )
813
814   PORT_DIPNAME( 0x70, 0x50, "Clock speed" )
815   PORT_DIPSETTING(   0x00, "4" )
816   PORT_DIPSETTING(    0x10, "8" )
817   PORT_DIPSETTING(    0x20, "16" )
818   PORT_DIPSETTING(    0x30, "20" )
819   PORT_DIPSETTING(    0x40, "25" )
820   PORT_DIPSETTING(    0x50, "33" )
821   PORT_DIPSETTING(    0x60, "40" )
822   PORT_DIPSETTING(    0x70, "50" )
823
824   PORT_DIPNAME( 0x80, 0x00, "SCSI bus terminated" )
825   PORT_DIPSETTING(   0x00, DEF_STR( Yes ) )
826   PORT_DIPSETTING(    0x80, DEF_STR( No ) )
827INPUT_PORTS_END
828
829
830
831/*************************************
832 *
833 *  SCSI
834 *
835 *************************************/
836
837static UINT32 ncr53c700_r(running_machine &machine, bool io, offs_t addr)
838{
839   return machine.device("maincpu")->memory().space(io ? AS_IO : AS_PROGRAM).read_dword(addr);
840}
841
842static void ncr53c700_w(running_machine &machine, bool io, offs_t addr, UINT32 data, UINT32 mem_mask)
843{
844   machine.device("maincpu")->memory().space(io ? AS_IO : AS_PROGRAM).write_dword(addr, data, mem_mask);
845}
846
847static const struct NCR53C7XXinterface ncr53c700_intf =
848{
849   DEVCB_DRIVER_LINE_MEMBER(rastersp_state, scsi_irq),
850   &ncr53c700_r,
851   &ncr53c700_w,
852};
853
854static SLOT_INTERFACE_START( rastersp_scsi_devices )
855   SLOT_INTERFACE("harddisk", NSCSI_HARDDISK)
856   SLOT_INTERFACE_INTERNAL("ncr53c700", NCR53C7XX)
857SLOT_INTERFACE_END
858
859
860
861/*************************************
862 *
863 *  TMS32031
864 *
865 *************************************/
866
867static const tms3203x_config tms_config =
868{
869   true   // Boot-loader mode
870};
871
872
873
874/*************************************
875 *
876 *  Machine driver
877 *
878 *************************************/
879
880static MACHINE_CONFIG_START( rastersp, rastersp_state )
881   MCFG_CPU_ADD("maincpu", I486, 33330000)
882   MCFG_CPU_PROGRAM_MAP(cpu_map)
883   MCFG_CPU_IO_MAP(io_map)
884   MCFG_CPU_VBLANK_INT_DRIVER("screen", rastersp_state, vblank_irq)
885
886   MCFG_CPU_ADD("dsp", TMS32031, 33330000)
887   MCFG_TMS3203X_CONFIG(tms_config)
888   MCFG_CPU_PROGRAM_MAP(dsp_map)
889
890   /* Devices */
891   MCFG_TIMER_DRIVER_ADD("tms_timer1", rastersp_state, tms_timer1)
892   MCFG_TIMER_DRIVER_ADD("tms_tx_timer", rastersp_state, tms_tx_timer)
893   MCFG_MC146818_ADD("rtc", MC146818_STANDARD)
894   MCFG_NVRAM_HANDLER(rastersp)
895
896   MCFG_NSCSI_BUS_ADD("scsibus")
897   MCFG_NSCSI_ADD("scsibus:0", rastersp_scsi_devices, "harddisk", 0, 0, 0, true)
898   MCFG_NSCSI_ADD("scsibus:7", rastersp_scsi_devices, "ncr53c700", 0, &ncr53c700_intf, 66000000, true)
899
900   /* Video */
901   MCFG_SCREEN_ADD("screen", RASTER)
902   MCFG_SCREEN_SIZE(320, 240)
903   MCFG_SCREEN_VISIBLE_AREA(0, 320-1, 0, 240-1)
904    MCFG_SCREEN_UPDATE_DRIVER(rastersp_state, screen_update)
905      MCFG_SCREEN_REFRESH_RATE(50)
906   MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
907
908   MCFG_PALETTE_INIT(RRRRR_GGGGGG_BBBBB)
909   MCFG_PALETTE_LENGTH(65536)
910
911    /* Sound */
912   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
913
914   MCFG_DAC_ADD("dac_l")
915   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
916   MCFG_DAC_ADD("dac_r")
917   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
918MACHINE_CONFIG_END
919
920
921
922/*************************************
923 *
924 *  ROM definitions
925 *
926 *************************************/
927
928ROM_START( rotr )
929   ROM_REGION(0x100000, "bios", 0)
930   ROM_LOAD( "rasterspeed2.1_bootrom4.u10", 0x00000, 0x10000, CRC(6da142d1) SHA1(e2dbd479034677726fc26fd1ba85c4458d89286c) )
931
932   ROM_REGION(0x1000000, "dspboot", 0)
933   ROM_LOAD32_BYTE( "rasterspeed2.1_bootrom4.u10", 0x00000, 0x10000, CRC(6da142d1) SHA1(e2dbd479034677726fc26fd1ba85c4458d89286c) )
934
935   ROM_REGION(0x8000, "proms", 0) /* Xilinx FPGA PROMs */
936   ROM_LOAD( "17128dpc.u72", 0x0000, 0x4000, CRC(5ddf6ee3) SHA1(f3d15b649b5641374a9e14877cea84ba9c57ef3c) )
937   ROM_LOAD( "17128dpc.u73", 0x2000, 0x4000, CRC(9e274cea) SHA1(e974cad4e4b965bf2c9df7d3d0b4eec64629eeb0) )
938
939   ROM_REGION(0x8000, "nvram", 0) /* Default NVRAM */
940   ROM_LOAD( "rotr.nv", 0x0000, 0x8000, CRC(62543517) SHA1(a4bf3431cdab956839bb155c4a8c140d30e5c7ec) )
941
942   DISK_REGION( "scsibus:0:harddisk" )
943   DISK_IMAGE( "rotr", 0, SHA1(d67d7feb52d8c7ba1d2a190a40d97e84871f2d80) )
944ROM_END
945
946
947
948/*************************************
949 *
950 *  Game drivers
951 *
952 *************************************/
953
954GAME( 1994, rotr, 0, rastersp, rotr, driver_device, 0, ROT0, "BFM/Mirage", "Rise of the Robots (prototype)", 0 )
trunk/src/mame/mame.lst
r19691r19692
1349113491sc1druby
1349213492sc1drubya
1349313493
13494// RasterSpeed
13495rotr      // 1994
13496
1349413497// Scorpion 2 / 3
1349513498
1349613499sc2brkfs   // The Big Breakfast

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