trunk/src/mess/drivers/pc9801.c
| r19676 | r19677 | |
| 87 | 87 | - Bishoujo Audition: Moans with a "(program) ended. remove the floppy disk and turn off the poewr." |
| 88 | 88 | - Bishoujo Hunter ZX: Doesn't color cycle at intro (seems stuck?), doesn't clear text selection at new game screen; |
| 89 | 89 | - Bishoujo Shanshinkan: has white rectangles all over the place; |
| 90 | - Bishoujo Tsuushin: hangs with a beep while writing some intro text; |
| 90 | 91 | |
| 91 | 92 | - Dragon Buster: slight issue with window masking; |
| 92 | 93 | - Far Side Moon: doesn't detect sound board (tied to 0x00ec ports) |
| r19676 | r19677 | |
| 428 | 429 | UINT8 *m_ide_ram; |
| 429 | 430 | UINT8 *m_unk_rom; |
| 430 | 431 | UINT8 *m_ext_gvram; |
| 431 | | UINT8 *m_vram256; |
| 432 | 432 | UINT8 m_pc9821_window_bank; |
| 433 | 433 | UINT8 m_joy_sel; |
| 434 | 434 | UINT8 m_ext2_ff; |
| r19676 | r19677 | |
| 499 | 499 | DECLARE_WRITE8_MEMBER(pc9821_video_ff_w); |
| 500 | 500 | DECLARE_READ8_MEMBER(pc9821_a0_r); |
| 501 | 501 | DECLARE_WRITE8_MEMBER(pc9821_a0_w); |
| 502 | | DECLARE_READ8_MEMBER(pc9821_pit_r); |
| 503 | | DECLARE_WRITE8_MEMBER(pc9821_pit_w); |
| 502 | DECLARE_READ8_MEMBER(pc9801rs_pit_mirror_r); |
| 503 | DECLARE_WRITE8_MEMBER(pc9801rs_pit_mirror_w); |
| 504 | 504 | DECLARE_READ8_MEMBER(ide_status_r); |
| 505 | 505 | DECLARE_READ8_MEMBER(pc9801rs_access_ctrl_r); |
| 506 | 506 | DECLARE_WRITE8_MEMBER(pc9801rs_access_ctrl_w); |
| 507 | 507 | DECLARE_READ8_MEMBER(pc9821_memory_r); |
| 508 | 508 | DECLARE_WRITE8_MEMBER(pc9821_memory_w); |
| 509 | | DECLARE_READ8_MEMBER(pc9821_vram256_r); |
| 510 | | DECLARE_WRITE8_MEMBER(pc9821_vram256_w); |
| 511 | 509 | DECLARE_READ8_MEMBER(opn_porta_r); |
| 512 | 510 | DECLARE_WRITE8_MEMBER(opn_portb_w); |
| 513 | 511 | // DECLARE_READ8_MEMBER(pc9801_ext_opna_r); |
| r19676 | r19677 | |
| 2050 | 2048 | return 0xff; |
| 2051 | 2049 | } |
| 2052 | 2050 | |
| 2051 | READ8_MEMBER(pc9801_state::pc9801rs_pit_mirror_r) |
| 2052 | { |
| 2053 | if((offset & 1) == 0) |
| 2054 | { |
| 2055 | printf("Read to undefined port [%04x]\n",offset+0x3fd8); |
| 2056 | return 0xff; |
| 2057 | } |
| 2058 | else // odd |
| 2059 | { |
| 2060 | if(offset & 0x08) |
| 2061 | printf("Read to undefined port [%02x]\n",offset+0x3fd8); |
| 2062 | else |
| 2063 | return pit8253_r(machine().device("pit8253"), space, (offset & 6) >> 1); |
| 2064 | } |
| 2065 | |
| 2066 | return 0xff; |
| 2067 | } |
| 2068 | |
| 2069 | WRITE8_MEMBER(pc9801_state::pc9801rs_pit_mirror_w) |
| 2070 | { |
| 2071 | if((offset & 1) == 0) |
| 2072 | { |
| 2073 | printf("Write to undefined port [%04x] <- %02x\n",offset+0x3fd8,data); |
| 2074 | } |
| 2075 | else // odd |
| 2076 | { |
| 2077 | if(offset < 0x08) |
| 2078 | pit8253_w(machine().device("pit8253"), space, (offset & 6) >> 1, data); |
| 2079 | else |
| 2080 | printf("Write to undefined port [%04x] <- %02x\n",offset+0x3fd8,data); |
| 2081 | } |
| 2082 | } |
| 2083 | |
| 2053 | 2084 | static ADDRESS_MAP_START( pc9801rs_map, AS_PROGRAM, 32, pc9801_state ) |
| 2054 | 2085 | AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE8(pc9801rs_memory_r,pc9801rs_memory_w,0xffffffff) |
| 2055 | 2086 | ADDRESS_MAP_END |
| r19676 | r19677 | |
| 2076 | 2107 | // AM_RANGE(0x0188, 0x018f) AM_READWRITE8(pc9801_opn_r, pc9801_opn_w, 0xffffffff) //ym2203 opn / <undefined> |
| 2077 | 2108 | AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffffffff) |
| 2078 | 2109 | AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w, 0xffffffff) //ROM/RAM bank |
| 2110 | AM_RANGE(0x3fd8, 0x3fdf) AM_READWRITE8(pc9801rs_pit_mirror_r, pc9801rs_pit_mirror_w, 0xffffffff) // <undefined> / pit mirror ports |
| 2079 | 2111 | AM_RANGE(0x7fd8, 0x7fdf) AM_READWRITE8(pc9801_mouse_r, pc9801_mouse_w, 0xffffffff) // <undefined> / mouse ppi8255 ports |
| 2080 | 2112 | // AM_RANGE(0xa460, 0xa463) AM_READWRITE8(pc9801_ext_opna_r, pc9801_ext_opna_w, 0xffffffff) |
| 2081 | 2113 | AM_RANGE(0xbfd8, 0xbfdf) AM_WRITE8(pc9801rs_mouse_freq_w, 0xffffffff) |
| r19676 | r19677 | |
| 2139 | 2171 | // AM_RANGE(0x0188, 0x018f) AM_READWRITE8(pc9801_opn_r, pc9801_opn_w, 0xffff) //ym2203 opn / <undefined> |
| 2140 | 2172 | AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffff) |
| 2141 | 2173 | AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w, 0xffff) //ROM/RAM bank |
| 2174 | AM_RANGE(0x3fd8, 0x3fdf) AM_READWRITE8(pc9801rs_pit_mirror_r, pc9801rs_pit_mirror_w, 0xffff) // <undefined> / pit mirror ports |
| 2142 | 2175 | AM_RANGE(0x7fd8, 0x7fdf) AM_READWRITE8(pc9801_mouse_r, pc9801_mouse_w, 0xffff) // <undefined> / mouse ppi8255 ports |
| 2143 | 2176 | // AM_RANGE(0xa460, 0xa463) AM_READWRITE8(pc9801_ext_opna_r, pc9801_ext_opna_w, 0xffff) |
| 2144 | 2177 | |
| r19676 | r19677 | |
| 2154 | 2187 | READ8_MEMBER(pc9801_state::pc9821_ide_r) { return m_ide_rom[offset]; } |
| 2155 | 2188 | READ8_MEMBER(pc9801_state::pc9821_unkrom_r) { return m_unk_rom[offset]; } |
| 2156 | 2189 | |
| 2157 | | READ8_MEMBER(pc9801_state::pc9821_vram256_r) |
| 2158 | | { |
| 2159 | | if(m_ex_video_ff[ANALOG_256_MODE]) |
| 2160 | | return m_vram256[offset]; |
| 2161 | | |
| 2162 | | return m_pc9801rs_grcg_r(offset & 0x7fff,0); |
| 2163 | | } |
| 2164 | | |
| 2165 | | WRITE8_MEMBER(pc9801_state::pc9821_vram256_w) |
| 2166 | | { |
| 2167 | | if(m_ex_video_ff[ANALOG_256_MODE]) |
| 2168 | | { |
| 2169 | | m_vram256[offset] = data; |
| 2170 | | return; |
| 2171 | | } |
| 2172 | | |
| 2173 | | m_pc9801rs_grcg_w(offset & 0x7fff,0,data); |
| 2174 | | } |
| 2175 | | |
| 2176 | 2190 | /* Note: not hooking this up causes "MEMORY ERROR" at POST */ |
| 2177 | 2191 | READ8_MEMBER(pc9801_state::pc9821_ideram_r) { return m_ide_ram[offset]; } |
| 2178 | 2192 | WRITE8_MEMBER(pc9801_state::pc9821_ideram_w) { m_ide_ram[offset] = data; } |
| r19676 | r19677 | |
| 2195 | 2209 | // else if(offset >= 0x00080000 && offset <= 0x0009ffff) { return pc9821_winram_r(space,offset & 0x1ffff); } |
| 2196 | 2210 | else if(offset >= 0x000a0000 && offset <= 0x000a3fff) { return pc9801_tvram_r(space,offset-0xa0000); } |
| 2197 | 2211 | else if(offset >= 0x000a4000 && offset <= 0x000a4fff) { return pc9801rs_knjram_r(space,offset & 0xfff); } |
| 2198 | | else if(offset >= 0x000a8000 && offset <= 0x000bffff) { return pc9801_gvram_r(space,offset-0xa8000); } |
| 2212 | else if(offset >= 0x000a8000 && offset <= 0x000affff) { return m_pc9801rs_grcg_r(offset & 0x7fff,1); } |
| 2213 | else if(offset >= 0x000b0000 && offset <= 0x000b7fff) { return m_pc9801rs_grcg_r(offset & 0x7fff,2); } |
| 2214 | else if(offset >= 0x000b8000 && offset <= 0x000bffff) { return m_pc9801rs_grcg_r(offset & 0x7fff,3); } |
| 2199 | 2215 | else if(offset >= 0x000cc000 && offset <= 0x000cffff) { return pc9821_unkrom_r(space,offset & 0x3fff); } |
| 2200 | 2216 | else if(offset >= 0x000d8000 && offset <= 0x000d9fff) { return pc9821_ide_r(space,offset & 0x1fff); } |
| 2201 | 2217 | else if(offset >= 0x000da000 && offset <= 0x000dbfff) { return pc9821_ideram_r(space,offset & 0x1fff); } |
| 2202 | | else if(offset >= 0x000e0000 && offset <= 0x000e7fff) { return pc9821_vram256_r(space,offset & 0x1ffff); } |
| 2218 | else if(offset >= 0x000e0000 && offset <= 0x000e7fff) { return m_pc9801rs_grcg_r(offset & 0x7fff,0); } |
| 2203 | 2219 | else if(offset >= 0x000e0000 && offset <= 0x000fffff) { return pc9801rs_ipl_r(space,offset & 0x1ffff); } |
| 2204 | 2220 | else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1) { return pc9801rs_ex_wram_r(space,offset-0x00100000); } |
| 2205 | 2221 | else if(offset >= 0x00f00000 && offset <= 0x00f9ffff) { return pc9821_ext_gvram_r(space,offset-0x00f00000); } |
| r19676 | r19677 | |
| 2224 | 2240 | // else if(offset >= 0x00080000 && offset <= 0x0009ffff) { pc9821_winram_w(space,offset & 0x1ffff,data); } |
| 2225 | 2241 | else if(offset >= 0x000a0000 && offset <= 0x000a3fff) { pc9801_tvram_w(space,offset-0xa0000,data); } |
| 2226 | 2242 | else if(offset >= 0x000a4000 && offset <= 0x000a4fff) { pc9801rs_knjram_w(space,offset & 0xfff,data); } |
| 2227 | | else if(offset >= 0x000a8000 && offset <= 0x000bffff) { pc9801_gvram_w(space,offset-0xa8000,data); } |
| 2243 | else if(offset >= 0x000a8000 && offset <= 0x000affff) { m_pc9801rs_grcg_w(offset & 0x7fff,1,data); } |
| 2244 | else if(offset >= 0x000b0000 && offset <= 0x000b7fff) { m_pc9801rs_grcg_w(offset & 0x7fff,2,data); } |
| 2245 | else if(offset >= 0x000b8000 && offset <= 0x000bffff) { m_pc9801rs_grcg_w(offset & 0x7fff,3,data); } |
| 2228 | 2246 | else if(offset >= 0x000cc000 && offset <= 0x000cffff) { /* TODO: shadow ROM */ } |
| 2229 | 2247 | else if(offset >= 0x000d8000 && offset <= 0x000d9fff) { /* TODO: shadow ROM */ } |
| 2230 | 2248 | else if(offset >= 0x000da000 && offset <= 0x000dbfff) { pc9821_ideram_w(space,offset & 0x1fff,data); } |
| 2231 | | else if(offset >= 0x000e0000 && offset <= 0x000e7fff) { pc9821_vram256_w(space,offset & 0x1ffff,data); } |
| 2249 | else if(offset >= 0x000e0000 && offset <= 0x000e7fff) { m_pc9801rs_grcg_w(offset & 0x7fff,0,data); } |
| 2232 | 2250 | else if(offset >= 0x000e8000 && offset <= 0x000fffff) { /* TODO: shadow ROM */ } |
| 2233 | 2251 | else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1) { pc9801rs_ex_wram_w(space,offset-0x00100000,data); } |
| 2234 | 2252 | else if(offset >= 0x00f00000 && offset <= 0x00f9ffff) { pc9821_ext_gvram_w(space,offset-0x00f00000,data); } |
| r19676 | r19677 | |
| 2302 | 2320 | pc9801rs_a0_w(space,offset,data); |
| 2303 | 2321 | } |
| 2304 | 2322 | |
| 2305 | | READ8_MEMBER(pc9801_state::pc9821_pit_r) |
| 2306 | | { |
| 2307 | | if((offset & 1) == 0) |
| 2308 | | { |
| 2309 | | printf("Read to undefined port [%04x]\n",offset+0x3fd8); |
| 2310 | | return 0xff; |
| 2311 | | } |
| 2312 | | else // odd |
| 2313 | | { |
| 2314 | | if(offset & 0x08) |
| 2315 | | printf("Read to undefined port [%02x]\n",offset+0x3fd8); |
| 2316 | | else |
| 2317 | | return pit8253_r(machine().device("pit8253"), space, (offset & 6) >> 1); |
| 2318 | | } |
| 2319 | | |
| 2320 | | return 0xff; |
| 2321 | | } |
| 2322 | | |
| 2323 | | WRITE8_MEMBER(pc9801_state::pc9821_pit_w) |
| 2324 | | { |
| 2325 | | if((offset & 1) == 0) |
| 2326 | | { |
| 2327 | | printf("Write to undefined port [%04x] <- %02x\n",offset+0x3fd8,data); |
| 2328 | | } |
| 2329 | | else // odd |
| 2330 | | { |
| 2331 | | if(offset < 0x08) |
| 2332 | | pit8253_w(machine().device("pit8253"), space, (offset & 6) >> 1, data); |
| 2333 | | else |
| 2334 | | printf("Write to undefined port [%04x] <- %02x\n",offset+0x3fd8,data); |
| 2335 | | } |
| 2336 | | } |
| 2337 | | |
| 2338 | 2323 | READ8_MEMBER(pc9801_state::ide_status_r) |
| 2339 | 2324 | { |
| 2340 | 2325 | return 0x50; // status |
| r19676 | r19677 | |
| 2492 | 2477 | // AM_RANGE(0x0c2d, 0x0c2d) cs4231 PCM board hi byte control |
| 2493 | 2478 | // AM_RANGE(0x0cc0, 0x0cc7) SCSI interface / <undefined> |
| 2494 | 2479 | // AM_RANGE(0x0cfc, 0x0cff) PCI bus |
| 2495 | | AM_RANGE(0x3fd8, 0x3fdf) AM_READWRITE8(pc9821_pit_r, pc9821_pit_w, 0xffffffff) // <undefined> / pit mirror ports |
| 2480 | AM_RANGE(0x3fd8, 0x3fdf) AM_READWRITE8(pc9801rs_pit_mirror_r, pc9801rs_pit_mirror_w, 0xffffffff) // <undefined> / pit mirror ports |
| 2496 | 2481 | AM_RANGE(0x7fd8, 0x7fdf) AM_READWRITE8(pc9801_mouse_r, pc9801_mouse_w, 0xffffffff) // <undefined> / mouse ppi8255 ports |
| 2497 | 2482 | AM_RANGE(0x841c, 0x841f) AM_READWRITE8(sdip_0_r,sdip_0_w,0xffffffff) |
| 2498 | 2483 | AM_RANGE(0x851c, 0x851f) AM_READWRITE8(sdip_1_r,sdip_1_w,0xffffffff) |
| r19676 | r19677 | |
| 3477 | 3462 | MACHINE_START_CALL_MEMBER(pc9801rs); |
| 3478 | 3463 | |
| 3479 | 3464 | m_ide_ram = auto_alloc_array(machine(), UINT8, 0x2000); |
| 3480 | | m_vram256 = auto_alloc_array(machine(), UINT8, 0x8000); |
| 3481 | 3465 | m_ext_gvram = auto_alloc_array(machine(), UINT8, 0xa0000); |
| 3482 | 3466 | m_ide_rom = memregion("ide")->base(); |
| 3483 | 3467 | m_unk_rom = memregion("unkrom")->base(); |
| 3484 | 3468 | |
| 3485 | 3469 | state_save_register_global_pointer(machine(), m_sdip, 24); |
| 3486 | 3470 | state_save_register_global_pointer(machine(), m_ide_ram, 0x2000); |
| 3487 | | state_save_register_global_pointer(machine(), m_vram256, 0x8000); |
| 3488 | 3471 | state_save_register_global_pointer(machine(), m_ext_gvram, 0xa0000); |
| 3489 | 3472 | } |
| 3490 | 3473 | |