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r19305 Tuesday 4th December, 2012 at 04:37:49 UTC by Tafoid
Added the ability to view peel18cv8 jed files to the jedutil.  [Kevin Eshbach)

[src/mame]	mame.lst
[src/regtests/jedutil/baseline/18cv8]	18cv8_combinatorial_feedback.txt* 18cv8_register_feedback.txt* pal10h8-to-peel18cv8.txt* pal10l8-to-peel18cv8.txt* pal12h6-to-peel18cv8.txt* pal12l6-to-peel18cv8.txt* pal14h4-to-peel18cv8.txt* pal14l4-to-peel18cv8.txt* pal16h2-to-peel18cv8.txt* pal16l2-to-peel18cv8.txt* pal16l8-to-peel18cv8.txt* pal16r4-to-peel18cv8.txt* pal16r6-to-peel18cv8.txt* pal16r8-to-peel18cv8.txt*
[src/regtests/jedutil/baseline/gal16v8]	pal10h8-to-gal16v8.txt pal10l8-to-gal16v8.txt pal12h6-to-gal16v8.txt pal12l6-to-gal16v8.txt pal14h4-to-gal16v8.txt pal14l4-to-gal16v8.txt pal16h2-to-gal16v8.txt pal16l2-to-gal16v8.txt pal16l8-to-gal16v8.txt pal16r4-to-gal16v8.txt pal16r6-to-gal16v8.txt pal16r8-to-gal16v8.txt
[src/regtests/jedutil/baseline/pal10h8]	pal10h8.txt
[src/regtests/jedutil/baseline/pal10l8]	pal10l8.txt
[src/regtests/jedutil/baseline/pal12h6]	pal12h6.txt
[src/regtests/jedutil/baseline/pal12l6]	pal12l6.txt
[src/regtests/jedutil/baseline/pal14h4]	pal14h4.txt
[src/regtests/jedutil/baseline/pal14l4]	pal14l4.txt
[src/regtests/jedutil/baseline/pal16c1]	pal16c1.txt
[src/regtests/jedutil/baseline/pal16h2]	pal16h2.txt
[src/regtests/jedutil/baseline/pal16l2]	pal16l2.txt
[src/regtests/jedutil/baseline/pal16l8]	pal16l8.txt
[src/regtests/jedutil/baseline/pal16r4]	pal16r4.txt
[src/regtests/jedutil/baseline/pal16r6]	pal16r6.txt
[src/regtests/jedutil/baseline/pal16r8]	pal16r8.txt
[src/regtests/jedutil/baseline/pal20l10]	pal20l10.txt
[src/regtests/jedutil/baseline/pal20l8]	pal20l8.txt
[src/regtests/jedutil/baseline/pal20r4]	pal20r4.txt
[src/regtests/jedutil/baseline/pal20r6]	pal20r6.txt
[src/regtests/jedutil/baseline/pal20r8]	pal20r8.txt
[src/regtests/jedutil/eqns]	readme.txt
[src/regtests/jedutil/eqns/ICT_Place]	readme.txt*
[src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8]	18cv8_bi-directional_io.psf* 18cv8_combinatorial_feedback.psf* 18cv8_register_feedback.psf*
[src/regtests/jedutil/eqns/Opal_Jr]	readme.txt*
[src/regtests/jedutil/eqns/pal10l8]	pal10l8.eqn
[src/regtests/jedutil/eqns/pal12h6]	pal12h6.eqn
[src/regtests/jedutil/eqns/pal12l6]	pal12l6.eqn
[src/regtests/jedutil/eqns/pal14h4]	pal14h4.eqn
[src/regtests/jedutil/eqns/pal14l4]	pal14l4.eqn
[src/regtests/jedutil/eqns/pal16c1]	pal16c1.eqn
[src/regtests/jedutil/eqns/pal16h2]	pal16h2.eqn
[src/regtests/jedutil/eqns/pal16l2]	pal16l2.eqn
[src/regtests/jedutil/eqns/pal16l8]	pal16l8.eqn
[src/regtests/jedutil/eqns/pal16r4]	pal16r4.eqn
[src/regtests/jedutil/eqns/pal16r6]	pal16r6.eqn
[src/regtests/jedutil/eqns/pal16r8]	pal16r8.eqn
[src/regtests/jedutil/eqns/pal20l10]	pal20l10.eqn
[src/regtests/jedutil/eqns/pal20l8]	pal20l8.eqn
[src/regtests/jedutil/eqns/pal20r4]	pal20r4.eqn
[src/regtests/jedutil/eqns/pal20r6]	pal20r6.eqn
[src/regtests/jedutil/eqns/pal20r8]	pal20r8.eqn
[src/regtests/jedutil/jeds/18cv8]	18cv8_combinatorial_feedback.jed* 18cv8_register_feedback.jed* pal10h8-to-peel18cv8.jed* pal12h6-to-peel18cv8.jed* pal12l6-to-peel18cv8.jed* pal14h4-to-peel18cv8.jed* pal14l4-to-peel18cv8.jed* pal16h2-to-peel18cv8.jed* pal16l2-to-peel18cv8.jed* pal16r4-to-peel18cv8.jed* pal16r6-to-peel18cv8.jed* pal16r8-to-peel18cv8.jed*
[src/tools]	jedutil.c

trunk/src/mame/mame.lst

r19304	r19305
9510	9510	spaceacea2      // (c) 1983 Cinematronics
9511	9511	spaceacea      // (c) 1983 Cinematronics
9512	9512	spaceaceeuro   // (c) 1983 Atari
	9513	/*
	9514	dlair2         // (c) 1991 Cinematronics
	9515	dlair2_319e      // (c) 1991 Cinematronics
	9516	dlair2_319s      // (c) 1991 Cinematronics
	9517	dlair2_318      // (c) 1991 Cinematronics
	9518	dlair2_316e      // (c) 1991 Cinematronics
	9519	dlair2_315      // (c) 1991 Cinematronics
	9520	dlair2_315s      // (c) 1991 Cinematronics
	9521	dlair2_314      // (c) 1991 Cinematronics
	9522	dlair2_312      // (c) 1991 Cinematronics
	9523	dlair2_300      // (c) 1991 Cinematronics
	9524	dlair2_211      // (c) 1991 Cinematronics
	9525	*/
9513	9526	aztarac         // (c) 1983 Centuri (vector game)
9514	9527	mole         // (c) 1982 Yachiyo Electronics, Ltd.
9515	9528	thehand         // (c) 1981 T.I.C.

trunk/src/tools/jedutil.c

r19304	r19305
115	115	#define NO_OUTPUT_ENABLE_FUSE_ROW 0xFFFF
116	116
117	117	/* Output pin flags */
118		#define OUTPUT_ACTIVELOW     0x00000001
119		#define OUTPUT_ACTIVEHIGH    0x00000002
120		#define OUTPUT_COMBINATORIAL 0x00000004
121		#define OUTPUT_REGISTERED    0x00000008
	118	#define OUTPUT_ACTIVELOW              0x00000001
	119	#define OUTPUT_ACTIVEHIGH             0x00000002
	120	#define OUTPUT_COMBINATORIAL          0x00000004
	121	#define OUTPUT_REGISTERED             0x00000008
	122	#define OUTPUT_FEEDBACK_OUTPUT        0x00000010 /* Feedback state depends on output enable */
	123	#define OUTPUT_FEEDBACK_COMBINATORIAL 0x00000020 /* Feedback state independant of output enable */
	124	#define OUTPUT_FEEDBACK_REGISTERED    0x00000040 /* Feedback state independant of output enable */
	125	#define OUTPUT_FEEDBACK_NONE          0x00000080 /* Feedback not available */
122	126
	127	/*
	128	Output Feedback Output
	129
	130	OE -----------|
	131	|
	132	|-\
	133	IN ----------|  >----|----< OUT >
	134	|-/     |
	135	|
	136	FEEDBACK ------------|
	137
	138
	139
	140	Output Feedback Combinatorial/Registered
	141
	142	OE ----------------|
	143	|
	144	|-\
	145	IN ----------|----|  >----< OUT >
	146	|    |-/
	147	|
	148	FEEDBACK ----|
	149	*/
	150
	151
	152
123	153	/* Fuse state flag */
124	154	#define LOW_FUSE_BLOWN     0x00000001
125	155	#define HIGH_FUSE_BLOWN    0x00000002
r19304	r19305
168	198	typedef void (*print_product_terms_func)(const pal_data* pal, const jed_data* jed);
169	199	typedef void (*config_pins_func)(const pal_data* pal, const jed_data* jed);
170	200	typedef int (*is_product_term_enabled_func)(const pal_data* pal, const jed_data* jed, UINT16 fuserow);
	201	typedef UINT16 (*get_pin_fuse_state_func)(const pal_data* pal, const jed_data* jed, UINT16 pin, UINT16 fuserow);
171	202
172	203	struct _pal_data
173	204	{
r19304	r19305
179	210	print_product_terms_func print_product_terms;
180	211	config_pins_func config_pins;
181	212	is_product_term_enabled_func is_product_term_enabled;
	213	get_pin_fuse_state_func get_pin_fuse_state;
182	214	};
183	215
184	216
r19304	r19305
210	242	static void print_pal16r6_product_terms(const pal_data* pal, const jed_data* jed);
211	243	static void print_pal16r8_product_terms(const pal_data* pal, const jed_data* jed);
212	244	static void print_gal16v8_product_terms(const pal_data* pal, const jed_data* jed);
213		/*static void print_gal18v10_product_terms(const pal_data* pal, const jed_data* jed);*/
	245	static void print_peel18cv8_product_terms(const pal_data* pal, const jed_data* jed);
	246	#if defined(include_gal18v10)
	247	static void print_gal18v10_product_terms(const pal_data* pal, const jed_data* jed);
	248	#endif
214	249	static void print_pal20l8_product_terms(const pal_data* pal, const jed_data* jed);
215	250	static void print_pal20l10_product_terms(const pal_data* pal, const jed_data* jed);
216	251	static void print_pal20r4_product_terms(const pal_data* pal, const jed_data* jed);
r19304	r19305
233	268	static void config_pal16r6_pins(const pal_data* pal, const jed_data* jed);
234	269	static void config_pal16r8_pins(const pal_data* pal, const jed_data* jed);
235	270	static void config_gal16v8_pins(const pal_data* pal, const jed_data* jed);
236		/*static void config_gal18v10_pins(const pal_data* pal, const jed_data* jed);*/
	271	static void config_peel18cv8_pins(const pal_data* pal, const jed_data* jed);
	272	#if defined(include_gal18v10)
	273	static void config_gal18v10_pins(const pal_data* pal, const jed_data* jed);
	274	#endif
237	275	static void config_pal20l8_pins(const pal_data* pal, const jed_data* jed);
238	276	static void config_pal20l10_pins(const pal_data* pal, const jed_data* jed);
239	277	static void config_pal20r4_pins(const pal_data* pal, const jed_data* jed);
r19304	r19305
246	284
247	285
248	286
	287	static UINT16 get_peel18cv8_pin_fuse_state(const pal_data* pal, const jed_data* jed, UINT16 pin, UINT16 fuserow);
	288
	289
	290
249	291	/***************************************************************************
250	292	GLOBAL VARIABLES
251	293	***************************************************************************/
r19304	r19305
372	414	{18, 0, 0, 0},
373	415	{19, 0, 0, 0}};
374	416
375		/*static pin_fuse_rows gal18v10pinfuserows[] = {
	417	static pin_fuse_rows peel18cv8pinfuserows[] = {
	418	{12, 2556, 2016, 2268},
	419	{13, 2520, 1728, 1980},
	420	{14, 2484, 1440, 1692},
	421	{15, 2448, 1152, 1404},
	422	{16, 2412, 864, 1116},
	423	{17, 2376, 576, 828},
	424	{18, 2340, 288, 540},
	425	{19, 2304, 0, 252}};
	426
	427	#if defined(include_gal18v10)
	428	static pin_fuse_rows gal18v10pinfuserows[] = {
376	429	{9,  3096, 3132, 3384},
377	430	{11, 2772, 2808, 3060},
378	431	{12, 2448, 2484, 2736},
r19304	r19305
382	435	{16, 1008, 1044, 1296},
383	436	{17, 684,  720,  972},
384	437	{18, 360,  396,  648},
385		{19, 36,   72,   324}};*/
	438	{19, 36,   72,   324}};
	439	#endif
386	440
387	441	static pin_fuse_rows pal20l8pinfuserows[] = {
388	442	{15, 2240, 2280, 2520},
r19304	r19305
664	718	{0, 0, 0},
665	719	{0, 0, 0}};
666	720
667		/*static pin_fuse_columns gal18v10pinfusecolumns[] = {
	721	static pin_fuse_columns peel18cv8pinfusecolumns[] = {
	722	{1, 1, 0},
	723	{2, 5, 4},
	724	{3, 9, 8},
	725	{4, 13, 12},
	726	{5, 17, 16},
	727	{6, 21, 20},
	728	{7, 25, 24},
	729	{8, 29, 28},
	730	{9, 33, 32},
	731	{11, 3, 2},
	732	{12, 35, 34},
	733	{13, 31, 30},
	734	{14, 27, 26},
	735	{15, 23, 22},
	736	{16, 19, 18},
	737	{17, 15, 14},
	738	{18, 11, 10},
	739	{19, 7, 6}};
	740
	741	#if defined(include_gal18v10)
	742	static pin_fuse_columns gal18v10pinfusecolumns[] = {
668	743	{1,  1,  0},
669	744	{2,  5,  4},
670	745	{3,  9,  8},
r19304	r19305
682	757	{16, 15, 14},
683	758	{17, 11, 10},
684	759	{18, 7,  6},
685		{19, 3,  2}};*/
	760	{19, 3,  2}};
	761	#endif
686	762
687	763	static pin_fuse_columns pal20l8pinfusecolumns[] = {
688	764	{1, 3, 2},
r19304	r19305
800	876	pal10l8pinfusecolumns, ARRAY_LEN(pal10l8pinfusecolumns),
801	877	print_pal10l8_product_terms,
802	878	config_pal10l8_pins,
	879	NULL,
803	880	NULL},
804	881	{"PAL10H8",
805	882	pal10h8pinfuserows, ARRAY_LEN(pal10h8pinfuserows),
806	883	pal10h8pinfusecolumns, ARRAY_LEN(pal10h8pinfusecolumns),
807	884	print_pal10h8_product_terms,
808	885	config_pal10h8_pins,
	886	NULL,
809	887	NULL},
810	888	{"PAL12H6",
811	889	pal12h6pinfuserows, ARRAY_LEN(pal12h6pinfuserows),
812	890	pal12h6pinfusecolumns, ARRAY_LEN(pal12h6pinfusecolumns),
813	891	print_pal12h6_product_terms,
814	892	config_pal12h6_pins,
	893	NULL,
815	894	NULL},
816	895	{"PAL14H4",
817	896	pal14h4pinfuserows, ARRAY_LEN(pal14h4pinfuserows),
818	897	pal14h4pinfusecolumns, ARRAY_LEN(pal14h4pinfusecolumns),
819	898	print_pal14h4_product_terms,
820	899	config_pal14h4_pins,
	900	NULL,
821	901	NULL},
822	902	{"PAL16H2",
823	903	pal16h2pinfuserows, ARRAY_LEN(pal16h2pinfuserows),
824	904	pal16h2pinfusecolumns, ARRAY_LEN(pal16h2pinfusecolumns),
825	905	print_pal16h2_product_terms,
826	906	config_pal16h2_pins,
	907	NULL,
827	908	NULL},
828	909	{"PAL16C1",
829	910	pal16c1pinfuserows, ARRAY_LEN(pal16c1pinfuserows),
830	911	pal16c1pinfusecolumns, ARRAY_LEN(pal16c1pinfusecolumns),
831	912	print_pal16c1_product_terms,
832	913	config_pal16c1_pins,
	914	NULL,
833	915	NULL},
834	916	{"PAL12L6",
835	917	pal12l6pinfuserows, ARRAY_LEN(pal12l6pinfuserows),
836	918	pal12l6pinfusecolumns, ARRAY_LEN(pal12l6pinfusecolumns),
837	919	print_pal12l6_product_terms,
838	920	config_pal12l6_pins,
	921	NULL,
839	922	NULL},
840	923	{"PAL14L4",
841	924	pal14l4pinfuserows, ARRAY_LEN(pal14l4pinfuserows),
842	925	pal14l4pinfusecolumns, ARRAY_LEN(pal14l4pinfusecolumns),
843	926	print_pal14l4_product_terms,
844	927	config_pal14l4_pins,
	928	NULL,
845	929	NULL},
846	930	{"PAL16L2",
847	931	pal16l2pinfuserows, ARRAY_LEN(pal16l2pinfuserows),
848	932	pal16l2pinfusecolumns, ARRAY_LEN(pal16l2pinfusecolumns),
849	933	print_pal16l2_product_terms,
850	934	config_pal16l2_pins,
	935	NULL,
851	936	NULL},
852		/*{"15S8", NULL, 0, NULL, 0, NULL, NULL, NULL},
853		{"PLS153", NULL, 0, NULL, 0, NULL, NULL, NULL},*/
	937	/*{"15S8", NULL, 0, NULL, 0, NULL, NULL, NULL, NULL},
	938	{"PLS153", NULL, 0, NULL, 0, NULL, NULL, NULL, NULL},*/
854	939	{"PAL16L8",
855	940	pal16l8pinfuserows, ARRAY_LEN(pal16l8pinfuserows),
856	941	pal16l8pinfusecolumns, ARRAY_LEN(pal16l8pinfusecolumns),
857	942	print_pal16l8_product_terms,
858	943	config_pal16l8_pins,
	944	NULL,
859	945	NULL},
860	946	{"PAL16R4",
861	947	pal16r4pinfuserows, ARRAY_LEN(pal16r4pinfuserows),
862	948	pal16r4pinfusecolumns, ARRAY_LEN(pal16r4pinfusecolumns),
863	949	print_pal16r4_product_terms,
864	950	config_pal16r4_pins,
	951	NULL,
865	952	NULL},
866	953	{"PAL16R6",
867	954	pal16r6pinfuserows, ARRAY_LEN(pal16r6pinfuserows),
868	955	pal16r6pinfusecolumns, ARRAY_LEN(pal16r6pinfusecolumns),
869	956	print_pal16r6_product_terms,
870	957	config_pal16r6_pins,
	958	NULL,
871	959	NULL},
872	960	{"PAL16R8",
873	961	pal16r8pinfuserows, ARRAY_LEN(pal16r8pinfuserows),
874	962	pal16r8pinfusecolumns, ARRAY_LEN(pal16r8pinfusecolumns),
875	963	print_pal16r8_product_terms,
876	964	config_pal16r8_pins,
	965	NULL,
877	966	NULL},
878		/*{"PAL16RA8", NULL, 0, NULL, 0, NULL, NULL, NULL},
879		{"PAL16V8R", NULL, 0, NULL, 0, NULL, NULL, NULL},
880		{"PALCE16V8", NULL, 0, NULL, 0, NULL, NULL, NULL},*/
	967	/*{"PAL16RA8", NULL, 0, NULL, 0, NULL, NULL, NULL, NULL},
	968	{"PAL16V8R", NULL, 0, NULL, 0, NULL, NULL, NULL, NULL},
	969	{"PALCE16V8", NULL, 0, NULL, 0, NULL, NULL, NULL, NULL},*/
881	970	{"GAL16V8",
882	971	gal16v8pinfuserows, ARRAY_LEN(gal16v8pinfuserows),
883	972	gal16v8pinfusecolumns, ARRAY_LEN(gal16v8pinfusecolumns),
884	973	print_gal16v8_product_terms,
885	974	config_gal16v8_pins,
886		is_gal16v8_product_term_enabled},
887		/*{"18CV8", NULL, 0, NULL, 0, NULL},
	975	is_gal16v8_product_term_enabled,
	976	NULL},
	977	{"18CV8",
	978	peel18cv8pinfuserows, ARRAY_LEN(peel18cv8pinfuserows),
	979	peel18cv8pinfusecolumns, ARRAY_LEN(peel18cv8pinfusecolumns),
	980	print_peel18cv8_product_terms,
	981	config_peel18cv8_pins,
	982	NULL,
	983	get_peel18cv8_pin_fuse_state},
	984	#if defined(include_gal18v10)
888	985	{"GAL18V10",
889	986	gal18v10pinfuserows, ARRAY_LEN(gal18v10pinfuserows),
890	987	gal18v10pinfusecolumns, ARRAY_LEN(gal18v10pinfusecolumns),
891	988	print_gal18v10_product_terms,
892	989	config_gal18v10_pins,
893		NULL},*/
	990	NULL,
	991	NULL},
	992	#endif
894	993	{"PAL20L8",
895	994	pal20l8pinfuserows, ARRAY_LEN(pal20l8pinfuserows),
896	995	pal20l8pinfusecolumns, ARRAY_LEN(pal20l8pinfusecolumns),
897	996	print_pal20l8_product_terms,
898	997	config_pal20l8_pins,
	998	NULL,
899	999	NULL},
900	1000	{"PAL20L10",
901	1001	pal20l10pinfuserows, ARRAY_LEN(pal20l10pinfuserows),
902	1002	pal20l10pinfusecolumns, ARRAY_LEN(pal20l10pinfusecolumns),
903	1003	print_pal20l10_product_terms,
904	1004	config_pal20l10_pins,
	1005	NULL,
905	1006	NULL},
906	1007	{"PAL20R4",
907	1008	pal20r4pinfuserows, ARRAY_LEN(pal20r4pinfuserows),
908	1009	pal20r4pinfusecolumns, ARRAY_LEN(pal20r4pinfusecolumns),
909	1010	print_pal20r4_product_terms,
910	1011	config_pal20r4_pins,
	1012	NULL,
911	1013	NULL},
912	1014	{"PAL20R6",
913	1015	pal20r6pinfuserows, ARRAY_LEN(pal20r6pinfuserows),
914	1016	pal20r6pinfusecolumns, ARRAY_LEN(pal20r6pinfusecolumns),
915	1017	print_pal20r6_product_terms,
916	1018	config_pal20r6_pins,
	1019	NULL,
917	1020	NULL},
918	1021	{"PAL20R8",
919	1022	pal20r8pinfuserows, ARRAY_LEN(pal20r8pinfuserows),
920	1023	pal20r8pinfusecolumns, ARRAY_LEN(pal20r8pinfusecolumns),
921	1024	print_pal20r8_product_terms,
922		config_pal20r8_pins, NULL}/*,
923		{"PAL20X4", NULL, 0, NULL, 0, NULL, NULL, NULL},
924		{"PAL20X8", NULL, 0, NULL, 0, NULL, NULL, NULL},
925		{"PAL20X10", NULL, 0, NULL, 0, NULL, NULL, NULL},
926		{"PAL22V10", NULL, 0, NULL, 0, NULL, NULL, NULL},
927		{"GAL20V8A", NULL, 0, NULL, 0, NULL, NULL, NULL},
928		{"GAL22V10", NULL, 0, NULL, 0, NULL, NULL, NULL},
929		{"PLS100", NULL, 0, NULL, 0, NULL, NULL, NULL}*/};
	1025	config_pal20r8_pins,
	1026	NULL,
	1027	NULL}/*,
	1028	{"PAL20X4", NULL, 0, NULL, 0, NULL, NULL, NULL, NULL},
	1029	{"PAL20X8", NULL, 0, NULL, 0, NULL, NULL, NULL, NULL},
	1030	{"PAL20X10", NULL, 0, NULL, 0, NULL, NULL, NULL, NULL},
	1031	{"PAL22V10", NULL, 0, NULL, 0, NULL, NULL, NULL, NULL},
	1032	{"GAL20V8A", NULL, 0, NULL, 0, NULL, NULL, NULL, NULL},
	1033	{"GAL22V10", NULL, 0, NULL, 0, NULL, NULL, NULL, NULL},
	1034	{"PLS100", NULL, 0, NULL, 0, NULL, NULL, NULL, NULL}*/};
930	1035
931	1036
932	1037
r19304	r19305
1041	1146
1042	1147
1043	1148	/*-------------------------------------------------
	1149	find_pin_from_fuse_row - finds the pin
	1150	associated with a fuse row
	1151	-------------------------------------------------*/
	1152
	1153	static UINT16 find_pin_from_fuse_row(const pal_data* pal, UINT16 fuserow)
	1154	{
	1155	int index;
	1156
	1157	for (index = 0; index < pal->pinfuserowscount; ++index)
	1158	{
	1159	if (pal->pinfuserows[index].fuserowoutputenable != NO_OUTPUT_ENABLE_FUSE_ROW)
	1160	{
	1161	if (pal->pinfuserows[index].fuserowoutputenable == fuserow)
	1162	{
	1163	return pal->pinfuserows[index].pin;
	1164	}
	1165	}
	1166
	1167	if (fuserow >= pal->pinfuserows[index].fuserowtermstart &&
	1168	fuserow <= pal->pinfuserows[index].fuserowtermend)
	1169	{
	1170	return pal->pinfuserows[index].pin;
	1171	}
	1172	}
	1173
	1174	return 0;
	1175	}
	1176
	1177
	1178
	1179	/*-------------------------------------------------
1044	1180	calc_fuse_column_count - calculates the total
1045	1181	columns of a pal
1046	1182	-------------------------------------------------*/
r19304	r19305
1076	1212
1077	1213
1078	1214	/*-------------------------------------------------
1079		any_fuses_in_row_blown - checks if any fuses in
1080		a row have been blown.
	1215	does_output_enable_fuse_row_allow_output - checks
	1216	if an output enable fuse row contains a product
	1217	term that enables the output.
1081	1218	-------------------------------------------------*/
1082	1219
1083		static int any_fuses_in_row_blown(const pal_data* pal, const jed_data* jed, UINT16 fuserow)
	1220	static int does_output_enable_fuse_row_allow_output(const pal_data* pal, const jed_data* jed, UINT16 fuserow)
1084	1221	{
1085		UINT16 columncount = calc_fuse_column_count(pal);
1086		UINT16 column;
	1222	int lowfusestate, highfusestate;
	1223	UINT16 index;
1087	1224
1088		for (column = 0; column < columncount; ++column)
	1225	for (index = 0; index < pal->pinfusecolumnscount; ++index)
1089	1226	{
1090		if (jed_get_fuse(jed, fuserow + column))
	1227	lowfusestate = jed_get_fuse(jed, fuserow + pal->pinfusecolumns[index].lowfusecolumn);
	1228	highfusestate = jed_get_fuse(jed, fuserow + pal->pinfusecolumns[index].highfusecolumn);
	1229
	1230	if (!lowfusestate && !highfusestate)
1091	1231	{
1092		return 1;
	1232	return 0;
1093	1233	}
1094	1234	}
1095	1235
1096		return 0;
	1236	return 1;
1097	1237	}
1098	1238
1099	1239
r19304	r19305
1240	1380	{
1241	1381	pin = inputpins[index];
1242	1382
1243		fuse_state = get_pin_fuse_state(pal, jed, pin, fuserow);
	1383	if (pal->get_pin_fuse_state)
	1384	{
	1385	fuse_state = pal->get_pin_fuse_state(pal, jed, pin, fuserow);
	1386	}
	1387	else
	1388	{
	1389	fuse_state = get_pin_fuse_state(pal, jed, pin, fuserow);
	1390	}
1244	1391
1245	1392	if (fuse_state == LOW_FUSE_BLOWN)
1246	1393	{
r19304	r19305
1258	1405	{
1259	1406	flags = get_pin_output_flags(pin);
1260	1407
1261		if (flags & OUTPUT_COMBINATORIAL)
	1408	if (flags & OUTPUT_FEEDBACK_OUTPUT)
1262	1409	{
1263		sprintf(tmpbuffer, "/o%d", pin);
	1410	if (flags & OUTPUT_COMBINATORIAL)
	1411	{
	1412	sprintf(tmpbuffer, "/o%d", pin);
	1413	}
	1414	else if (flags & OUTPUT_REGISTERED)
	1415	{
	1416	sprintf(tmpbuffer, "/rfo%d", pin);
	1417	}
	1418	else
	1419	{
	1420	tmpbuffer[0] = 0;
	1421
	1422	fprintf(stderr, "Unknown output feedback controlled by output enable type for pin %d!\n", pin);
	1423	}
1264	1424	}
1265		else if (flags & OUTPUT_REGISTERED)
	1425	else if (flags & OUTPUT_FEEDBACK_COMBINATORIAL)
1266	1426	{
	1427	sprintf(tmpbuffer, "/of%d", pin);
	1428	}
	1429	else if (flags & OUTPUT_FEEDBACK_REGISTERED)
	1430	{
1267	1431	sprintf(tmpbuffer, "/rf%d", pin);
1268	1432	}
	1433	else
	1434	{
	1435	tmpbuffer[0] = 0;
1269	1436
	1437	fprintf(stderr, "Unknown output feedback type for pin %d!\n", pin);
	1438	}
	1439
1270	1440	strcat(buffer, tmpbuffer);
1271	1441	}
1272	1442
r19304	r19305
1289	1459	{
1290	1460	flags = get_pin_output_flags(pin);
1291	1461
1292		if (flags & OUTPUT_COMBINATORIAL)
	1462	if (flags & OUTPUT_FEEDBACK_OUTPUT)
1293	1463	{
1294		sprintf(tmpbuffer, "o%d", pin);
	1464	if (flags & OUTPUT_COMBINATORIAL)
	1465	{
	1466	sprintf(tmpbuffer, "o%d", pin);
	1467	}
	1468	else if (flags & OUTPUT_REGISTERED)
	1469	{
	1470	sprintf(tmpbuffer, "rfo%d", pin);
	1471	}
	1472	else
	1473	{
	1474	tmpbuffer[0] = 0;
	1475
	1476	fprintf(stderr, "Unknown output feedback controlled by output enable type for pin %d!\n", pin);
	1477	}
1295	1478	}
1296		else if (flags & OUTPUT_REGISTERED)
	1479	else if (flags & OUTPUT_FEEDBACK_COMBINATORIAL)
1297	1480	{
	1481	sprintf(tmpbuffer, "of%d", pin);
	1482	}
	1483	else if (flags & OUTPUT_FEEDBACK_REGISTERED)
	1484	{
1298	1485	sprintf(tmpbuffer, "rf%d", pin);
1299	1486	}
	1487	else
	1488	{
	1489	tmpbuffer[0] = 0;
1300	1490
	1491	fprintf(stderr, "Unknown output feedback type for pin %d!\n", pin);
	1492	}
	1493
1301	1494	strcat(buffer, tmpbuffer);
1302	1495	}
1303	1496
r19304	r19305
1309	1502
1310	1503
1311	1504	/*-------------------------------------------------
	1505	print_input_pins - prints out the input pins
	1506	-------------------------------------------------*/
	1507
	1508	static void print_input_pins()
	1509	{
	1510	UINT16 index;
	1511
	1512	printf("Inputs:\n\n");
	1513
	1514	for (index = 0; index < inputpinscount; ++index)
	1515	{
	1516	printf("%d", inputpins[index]);
	1517
	1518	if (index + 1 < inputpinscount)
	1519	{
	1520	printf(", ");
	1521	}
	1522	}
	1523
	1524	printf("\n\n");
	1525	}
	1526
	1527
	1528
	1529	/*-------------------------------------------------
	1530	print_output_pins - prints out the output pins
	1531	-------------------------------------------------*/
	1532
	1533	static void print_output_pins()
	1534	{
	1535	UINT16 index, flags;
	1536
	1537	printf("Outputs:\n\n");
	1538
	1539	for (index = 0; index < outputpinscount; ++index)
	1540	{
	1541	flags = outputpins[index].flags;
	1542
	1543	printf("%d (", outputpins[index].pin);
	1544
	1545	if (flags & OUTPUT_COMBINATORIAL)
	1546	{
	1547	printf("Combinatorial, ");
	1548	}
	1549	else if (flags & OUTPUT_REGISTERED)
	1550	{
	1551	printf("Registered, ");
	1552	}
	1553	else
	1554	{
	1555	fprintf(stderr, "Unknown output type for pin %d!\n", outputpins[index].pin);
	1556	}
	1557
	1558	if (flags & OUTPUT_FEEDBACK_OUTPUT)
	1559	{
	1560	printf("Output feedback output, ");
	1561	}
	1562	else if (flags & OUTPUT_FEEDBACK_COMBINATORIAL)
	1563	{
	1564	printf("Output feedback combinatorial, ");
	1565	}
	1566	else if (flags & OUTPUT_FEEDBACK_REGISTERED)
	1567	{
	1568	printf("Output feedback registered, ");
	1569	}
	1570	else if (flags & OUTPUT_FEEDBACK_NONE)
	1571	{
	1572	printf("No output feedback, ");
	1573	}
	1574	else
	1575	{
	1576	fprintf(stderr, "Unknown output feedback type for pin %d!\n", outputpins[index].pin);
	1577	}
	1578
	1579	if (flags & OUTPUT_ACTIVELOW)
	1580	{
	1581	printf("Active low");
	1582	}
	1583	else if (flags & OUTPUT_ACTIVEHIGH)
	1584	{
	1585	printf("Active high");
	1586	}
	1587	else
	1588	{
	1589	fprintf(stderr, "Unknown output state type for pin %d!\n", outputpins[index].pin);
	1590	}
	1591
	1592	printf(")\n");
	1593	}
	1594
	1595	printf("\n");
	1596	}
	1597
	1598
	1599
	1600	/*-------------------------------------------------
1312	1601	print_product_terms - prints the product terms
1313	1602	for a pal
1314	1603	-------------------------------------------------*/
r19304	r19305
1322	1611
1323	1612	columncount = calc_fuse_column_count(pal);
1324	1613
	1614	print_input_pins();
	1615	print_output_pins();
	1616
	1617	printf("Equations:\n\n");
	1618
1325	1619	for (index = 0; index < outputpinscount; ++index)
1326	1620	{
1327	1621	flags = outputpins[index].flags;
r19304	r19305
1411	1705	}
1412	1706	else if (flags & OUTPUT_REGISTERED)
1413	1707	{
1414		printf("rf%d.oe = OE\n", outputpins[index].pin);
	1708	printf("rf%d.oe = ", outputpins[index].pin);
	1709
	1710	if (fuse_rows->fuserowoutputenable == NO_OUTPUT_ENABLE_FUSE_ROW)
	1711	{
	1712	printf("OE\n");
	1713	}
	1714	else if (all_fuses_in_row_blown(pal, jed, fuse_rows->fuserowoutputenable))
	1715	{
	1716	printf("vcc\n");
	1717	}
	1718	else
	1719	{
	1720	generate_product_terms(pal, jed, fuse_rows->fuserowoutputenable, buffer);
	1721
	1722	printf("%s\n", buffer);
	1723	}
1415	1724	}
1416	1725
1417	1726	printf("\n");
r19304	r19305
1589	1898
1590	1899
1591	1900	/*-------------------------------------------------
	1901	print_peel18cv8_product_terms - prints the product
	1902	terms for a PEEL18CV8
	1903	-------------------------------------------------*/
	1904
	1905	static void print_peel18cv8_product_terms(const pal_data* pal, const jed_data* jed)
	1906	{
	1907	char buffer[200];
	1908
	1909	print_product_terms(pal, jed);
	1910
	1911	/* Synchronous Preset */
	1912
	1913	generate_product_terms(pal, jed, 2592, buffer);
	1914
	1915	if (strlen(buffer))
	1916	{
	1917	printf("Synchronous Preset:\n\n");
	1918	printf("%s\n", buffer);
	1919	printf("\n");
	1920	}
	1921
	1922	/* Asynchronous Clear */
	1923
	1924	generate_product_terms(pal, jed, 2628, buffer);
	1925
	1926	if (strlen(buffer))
	1927	{
	1928	printf("Asynchronous Clear:\n\n");
	1929	printf("%s\n", buffer);
	1930	printf("\n");
	1931	}
	1932	}
	1933
	1934
	1935
	1936	/*-------------------------------------------------
1592	1937	print_gal18v10_product_terms - prints the product
1593	1938	terms for a GAL18V10
1594	1939	-------------------------------------------------*/
1595	1940
1596		/*static void print_gal18v10_product_terms(const pal_data* pal, const jed_data* jed)
	1941	#if defined(include_gal18v10)
	1942	static void print_gal18v10_product_terms(const pal_data* pal, const jed_data* jed)
1597	1943	{
1598		printf("Viewing product terms are not supported.\n");
1599		}*/
	1944	char buffer[200];
1600	1945
	1946	print_product_terms(pal, jed);
1601	1947
	1948	/* Synchronous Reset */
1602	1949
	1950	generate_product_terms(pal, jed, 3420, buffer);
	1951
	1952	if (strlen(buffer))
	1953	{
	1954	printf("Synchronous Reset:\n\n");
	1955	printf("%s\n", buffer);
	1956	printf("\n");
	1957	}
	1958
	1959	/* Asynchronous Reset */
	1960
	1961	generate_product_terms(pal, jed, 0, buffer);
	1962
	1963	if (strlen(buffer))
	1964	{
	1965	printf("Asynchronous Reset:\n\n");
	1966	printf("%s\n", buffer);
	1967	printf("\n");
	1968	}
	1969	}
	1970	#endif
	1971
	1972
	1973
1603	1974	/*-------------------------------------------------
1604	1975	print_pal20l8_product_terms - prints the product
1605	1976	terms for a PAL20L8
r19304	r19305
1669	2040	{
1670	2041	static UINT16 input_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11};
1671	2042	static pin_output_config output_pins[] = {
1672		{12, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1673		{13, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1674		{14, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1675		{15, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1676		{16, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1677		{17, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1678		{18, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1679		{19, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL}};
	2043	{12, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2044	{13, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2045	{14, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2046	{15, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2047	{16, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2048	{17, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2049	{18, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2050	{19, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE}};
1680	2051
1681	2052	set_input_pins(input_pins, ARRAY_LEN(input_pins));
1682	2053	set_output_pins(output_pins, ARRAY_LEN(output_pins));
r19304	r19305
1693	2064	{
1694	2065	static UINT16 input_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11};
1695	2066	static pin_output_config output_pins[] = {
1696		{12, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1697		{13, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1698		{14, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1699		{15, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1700		{16, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1701		{17, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1702		{18, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1703		{19, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL}};
	2067	{12, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2068	{13, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2069	{14, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2070	{15, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2071	{16, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2072	{17, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2073	{18, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2074	{19, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE}};
1704	2075
1705	2076	set_input_pins(input_pins, ARRAY_LEN(input_pins));
1706	2077	set_output_pins(output_pins, ARRAY_LEN(output_pins));
r19304	r19305
1717	2088	{
1718	2089	static UINT16 input_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 19};
1719	2090	static pin_output_config output_pins[] = {
1720		{13, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1721		{14, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1722		{15, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1723		{16, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1724		{17, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1725		{18, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL}};
	2091	{13, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2092	{14, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2093	{15, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2094	{16, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2095	{17, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2096	{18, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE}};
1726	2097
1727	2098	set_input_pins(input_pins, ARRAY_LEN(input_pins));
1728	2099	set_output_pins(output_pins, ARRAY_LEN(output_pins));
r19304	r19305
1739	2110	{
1740	2111	static UINT16 input_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 19};
1741	2112	static pin_output_config output_pins[] = {
1742		{13, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1743		{14, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1744		{15, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1745		{16, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1746		{17, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1747		{18, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL}};
	2113	{13, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2114	{14, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2115	{15, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2116	{16, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2117	{17, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2118	{18, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE}};
1748	2119
1749	2120	set_input_pins(input_pins, ARRAY_LEN(input_pins));
1750	2121	set_output_pins(output_pins, ARRAY_LEN(output_pins));
r19304	r19305
1761	2132	{
1762	2133	static UINT16 input_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 18, 19};
1763	2134	static pin_output_config output_pins[] = {
1764		{14, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1765		{15, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1766		{16, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1767		{17, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL}};
	2135	{14, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2136	{15, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2137	{16, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2138	{17, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE}};
1768	2139
1769	2140	set_input_pins(input_pins, ARRAY_LEN(input_pins));
1770	2141	set_output_pins(output_pins, ARRAY_LEN(output_pins));
r19304	r19305
1781	2152	{
1782	2153	static UINT16 input_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 18, 19};
1783	2154	static pin_output_config output_pins[] = {
1784		{14, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1785		{15, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1786		{16, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1787		{17, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL}};
	2155	{14, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2156	{15, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2157	{16, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2158	{17, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE}};
1788	2159
1789	2160	set_input_pins(input_pins, ARRAY_LEN(input_pins));
1790	2161	set_output_pins(output_pins, ARRAY_LEN(output_pins));
r19304	r19305
1801	2172	{
1802	2173	static UINT16 input_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19};
1803	2174	static pin_output_config output_pins[] = {
1804		{15, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1805		{16, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL}};
	2175	{15, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2176	{16, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE}};
1806	2177
1807	2178	set_input_pins(input_pins, ARRAY_LEN(input_pins));
1808	2179	set_output_pins(output_pins, ARRAY_LEN(output_pins));
r19304	r19305
1819	2190	{
1820	2191	static UINT16 input_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19};
1821	2192	static pin_output_config output_pins[] = {
1822		{15, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL},
1823		{16, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL}};
	2193	{15, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2194	{16, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE}};
1824	2195
1825	2196	set_input_pins(input_pins, ARRAY_LEN(input_pins));
1826	2197	set_output_pins(output_pins, ARRAY_LEN(output_pins));
r19304	r19305
1837	2208	{
1838	2209	static UINT16 input_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19};
1839	2210	static pin_output_config output_pins[] = {
1840		{15, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL},
1841		{16, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL}};
	2211	{15, OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE},
	2212	{16, OUTPUT_ACTIVEHIGH | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_NONE}};
1842	2213
1843	2214	set_input_pins(input_pins, ARRAY_LEN(input_pins));
1844	2215	set_output_pins(output_pins, ARRAY_LEN(output_pins));
r19304	r19305
1861	2232
1862	2233	for (index = 0; index < pal->pinfuserowscount; ++index)
1863	2234	{
1864		if (any_fuses_in_row_blown(pal, jed, pal->pinfuserows[index].fuserowoutputenable))
	2235	if (does_output_enable_fuse_row_allow_output(pal, jed, pal->pinfuserows[index].fuserowoutputenable))
1865	2236	{
1866	2237	output_pins[output_pin_count].pin = pal->pinfuserows[index].pin;
1867		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
	2238	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
1868	2239
1869	2240	++output_pin_count;
1870	2241	}
r19304	r19305
1890	2261
1891	2262	output_pin_count = 0;
1892	2263
1893		if (any_fuses_in_row_blown(pal, jed, 1792))
	2264	if (does_output_enable_fuse_row_allow_output(pal, jed, 1792))
1894	2265	{
1895	2266	output_pins[output_pin_count].pin = 12;
1896		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
	2267	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
1897	2268
1898	2269	++output_pin_count;
1899	2270	}
1900	2271
1901		if (any_fuses_in_row_blown(pal, jed, 1536))
	2272	if (does_output_enable_fuse_row_allow_output(pal, jed, 1536))
1902	2273	{
1903	2274	output_pins[output_pin_count].pin = 13;
1904		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
	2275	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
1905	2276
1906	2277	++output_pin_count;
1907	2278	}
r19304	r19305
1909	2280	for (index = 0; index < ARRAY_LEN(registered_pins); ++index)
1910	2281	{
1911	2282	output_pins[output_pin_count].pin = registered_pins[index];
1912		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_REGISTERED;
	2283	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED;
1913	2284
1914	2285	++output_pin_count;
1915	2286	}
1916	2287
1917		if (any_fuses_in_row_blown(pal, jed, 256))
	2288	if (does_output_enable_fuse_row_allow_output(pal, jed, 256))
1918	2289	{
1919	2290	output_pins[output_pin_count].pin = 18;
1920		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
	2291	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
1921	2292
1922	2293	++output_pin_count;
1923	2294	}
1924	2295
1925		if (any_fuses_in_row_blown(pal, jed, 0))
	2296	if (does_output_enable_fuse_row_allow_output(pal, jed, 0))
1926	2297	{
1927	2298	output_pins[output_pin_count].pin = 19;
1928		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
	2299	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
1929	2300
1930	2301	++output_pin_count;
1931	2302	}
r19304	r19305
1950	2321
1951	2322	output_pin_count = 0;
1952	2323
1953		if (any_fuses_in_row_blown(pal, jed, 1792))
	2324	if (does_output_enable_fuse_row_allow_output(pal, jed, 1792))
1954	2325	{
1955	2326	output_pins[output_pin_count].pin = 12;
1956		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
	2327	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
1957	2328
1958	2329	++output_pin_count;
1959	2330	}
r19304	r19305
1961	2332	for (index = 0; index < ARRAY_LEN(registered_pins); ++index)
1962	2333	{
1963	2334	output_pins[output_pin_count].pin = registered_pins[index];
1964		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_REGISTERED;
	2335	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED;
1965	2336
1966	2337	++output_pin_count;
1967	2338	}
1968	2339
1969		if (any_fuses_in_row_blown(pal, jed, 0))
	2340	if (does_output_enable_fuse_row_allow_output(pal, jed, 0))
1970	2341	{
1971	2342	output_pins[output_pin_count].pin = 19;
1972		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
	2343	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
1973	2344
1974	2345	++output_pin_count;
1975	2346	}
r19304	r19305
1989	2360	{
1990	2361	static UINT16 input_pins[] = {2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19};
1991	2362	static pin_output_config output_pins[] = {
1992		{12, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
1993		{13, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
1994		{14, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
1995		{15, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
1996		{16, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
1997		{17, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
1998		{18, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
1999		{19, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED}};
	2363	{12, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	2364	{13, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	2365	{14, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	2366	{15, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	2367	{16, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	2368	{17, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	2369	{18, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	2370	{19, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED}};
2000	2371
2001	2372	set_input_pins(input_pins, ARRAY_LEN(input_pins));
2002	2373	set_output_pins(output_pins, ARRAY_LEN(output_pins));
r19304	r19305
2124	2495	for (index = 0; index < ARRAY_LEN(macrocells); ++index)
2125	2496	{
2126	2497	if (is_gal16v8_product_term_enabled(pal, jed, pal->pinfuserows[index].fuserowoutputenable) &&
2127		any_fuses_in_row_blown(pal, jed, pal->pinfuserows[index].fuserowoutputenable))
	2498	does_output_enable_fuse_row_allow_output(pal, jed, pal->pinfuserows[index].fuserowoutputenable))
2128	2499	{
2129	2500	output_pins[output_pin_count].pin = macrocells[index].pin;
2130	2501	output_pins[output_pin_count].flags = OUTPUT_COMBINATORIAL;
r19304	r19305
2138	2509	output_pins[output_pin_count].flags |= OUTPUT_ACTIVELOW;
2139	2510	}
2140	2511
	2512	if (output_pins[output_pin_count].pin != 12 &&
	2513	output_pins[output_pin_count].pin != 19)
	2514	{
	2515	output_pins[output_pin_count].flags |= OUTPUT_FEEDBACK_OUTPUT;
	2516	}
	2517	else
	2518	{
	2519	output_pins[output_pin_count].flags |= OUTPUT_FEEDBACK_NONE;
	2520	}
	2521
2141	2522	++output_pin_count;
2142	2523	}
2143	2524	}
r19304	r19305
2177	2558	output_pins[output_pin_count].flags |= OUTPUT_ACTIVELOW;
2178	2559	}
2179	2560
	2561	if (output_pins[output_pin_count].pin != 15 &&
	2562	output_pins[output_pin_count].pin != 16)
	2563	{
	2564	output_pins[output_pin_count].flags |= OUTPUT_FEEDBACK_OUTPUT;
	2565	}
	2566	else
	2567	{
	2568	output_pins[output_pin_count].flags |= OUTPUT_FEEDBACK_NONE;
	2569	}
	2570
2180	2571	++output_pin_count;
2181	2572	}
2182	2573	}
r19304	r19305
2201	2592	gal16v8pinfuserows[index].fuserowtermend = pinfuserows_combinatorial[index].fuserowtermend;
2202	2593
2203	2594	if (is_gal16v8_product_term_enabled(pal, jed, pal->pinfuserows[index].fuserowoutputenable) &&
2204		any_fuses_in_row_blown(pal, jed, pal->pinfuserows[index].fuserowoutputenable))
	2595	does_output_enable_fuse_row_allow_output(pal, jed, pal->pinfuserows[index].fuserowoutputenable))
2205	2596	{
2206	2597	output_pins[output_pin_count].pin = macrocells[index].pin;
2207		output_pins[output_pin_count].flags = OUTPUT_COMBINATORIAL;
	2598	output_pins[output_pin_count].flags = OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
2208	2599
2209	2600	if (jed_get_fuse(jed, macrocells[index].xor_fuse))
2210	2601	{
r19304	r19305
2227	2618	gal16v8pinfuserows[index].fuserowtermend = pinfuserows_registered[index].fuserowtermend;
2228	2619
2229	2620	output_pins[output_pin_count].pin = macrocells[index].pin;
2230		output_pins[output_pin_count].flags = OUTPUT_REGISTERED;
	2621	output_pins[output_pin_count].flags = OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED;
2231	2622
2232	2623	if (jed_get_fuse(jed, macrocells[index].xor_fuse))
2233	2624	{
r19304	r19305
2249	2640
2250	2641
2251	2642	/*-------------------------------------------------
	2643	config_peel18cv8_pins - configures the pins
	2644	for a PEEL18CV8
	2645	-------------------------------------------------*/
	2646
	2647	static void config_peel18cv8_pins(const pal_data* pal, const jed_data* jed)
	2648	{
	2649	typedef struct _output_logic_macrocell output_logic_macrocell;
	2650	struct _output_logic_macrocell
	2651	{
	2652	UINT16 pin;
	2653	UINT16 polarity_fuse; /* 0 = active high or 1 = active low */
	2654	UINT16 type_fuse; /* 1 = registered or 0 = combinatorial */
	2655	UINT16 feedback1_fuse;
	2656	UINT16 feedback2_fuse;
	2657	};
	2658
	2659	static output_logic_macrocell macrocells[] = {
	2660	{12, 2692, 2693, 2694, 2695},
	2661	{13, 2688, 2689, 2690, 2691},
	2662	{14, 2684, 2685, 2686, 2687},
	2663	{15, 2680, 2681, 2682, 2683},
	2664	{16, 2676, 2677, 2678, 2679},
	2665	{17, 2672, 2673, 2674, 2675},
	2666	{18, 2668, 2669, 2670, 2671},
	2667	{19, 2664, 2665, 2666, 2667}};
	2668	static UINT16 input_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19};
	2669	pin_output_config output_pins[ARRAY_LEN(macrocells)];
	2670	UINT16 index, output_pin_count;
	2671
	2672	set_input_pins(input_pins, ARRAY_LEN(input_pins));
	2673
	2674	output_pin_count = 0;
	2675
	2676	for (index = 0; index < ARRAY_LEN(macrocells); ++index)
	2677	{
	2678	if (jed_get_fuse(jed, macrocells[index].feedback1_fuse) &&
	2679	!jed_get_fuse(jed, macrocells[index].feedback2_fuse))
	2680	{
	2681	/* Combinatorial Feedback (pin is output only) */
	2682
	2683	output_pins[output_pin_count].pin = macrocells[index].pin;
	2684	output_pins[output_pin_count].flags = OUTPUT_FEEDBACK_COMBINATORIAL;
	2685
	2686	if (jed_get_fuse(jed, macrocells[index].type_fuse))
	2687	{
	2688	output_pins[output_pin_count].flags |= OUTPUT_REGISTERED;
	2689	}
	2690	else
	2691	{
	2692	output_pins[output_pin_count].flags |= OUTPUT_COMBINATORIAL;
	2693	}
	2694
	2695	if (jed_get_fuse(jed, macrocells[index].polarity_fuse))
	2696	{
	2697	output_pins[output_pin_count].flags |= OUTPUT_ACTIVELOW;
	2698	}
	2699	else
	2700	{
	2701	output_pins[output_pin_count].flags |= OUTPUT_ACTIVEHIGH;
	2702	}
	2703
	2704	++output_pin_count;
	2705	}
	2706	else if (!jed_get_fuse(jed, macrocells[index].feedback1_fuse) &&
	2707	!jed_get_fuse(jed, macrocells[index].feedback2_fuse))
	2708	{
	2709	/* Register Feedback (pin is output only) */
	2710
	2711	output_pins[output_pin_count].pin = macrocells[index].pin;
	2712	output_pins[output_pin_count].flags = OUTPUT_FEEDBACK_REGISTERED;
	2713
	2714	if (jed_get_fuse(jed, macrocells[index].type_fuse))
	2715	{
	2716	output_pins[output_pin_count].flags |= OUTPUT_REGISTERED;
	2717	}
	2718	else
	2719	{
	2720	output_pins[output_pin_count].flags |= OUTPUT_COMBINATORIAL;
	2721	}
	2722
	2723	if (jed_get_fuse(jed, macrocells[index].polarity_fuse))
	2724	{
	2725	output_pins[output_pin_count].flags |= OUTPUT_ACTIVELOW;
	2726	}
	2727	else
	2728	{
	2729	output_pins[output_pin_count].flags |= OUTPUT_ACTIVEHIGH;
	2730	}
	2731
	2732	++output_pin_count;
	2733	}
	2734	else if (jed_get_fuse(jed, macrocells[index].feedback1_fuse) &&
	2735	jed_get_fuse(jed, macrocells[index].feedback2_fuse))
	2736	{
	2737	/* Bi-directional I/O (pin can be input or output) */
	2738
	2739	if (does_output_enable_fuse_row_allow_output(pal, jed, pal->pinfuserows[index].fuserowoutputenable))
	2740	{
	2741	output_pins[output_pin_count].pin = macrocells[index].pin;
	2742	output_pins[output_pin_count].flags = OUTPUT_FEEDBACK_OUTPUT;
	2743
	2744	if (jed_get_fuse(jed, macrocells[index].type_fuse))
	2745	{
	2746	output_pins[output_pin_count].flags |= OUTPUT_REGISTERED;
	2747	}
	2748	else
	2749	{
	2750	output_pins[output_pin_count].flags |= OUTPUT_COMBINATORIAL;
	2751	}
	2752
	2753	if (jed_get_fuse(jed, macrocells[index].polarity_fuse))
	2754	{
	2755	output_pins[output_pin_count].flags |= OUTPUT_ACTIVELOW;
	2756	}
	2757	else
	2758	{
	2759	output_pins[output_pin_count].flags |= OUTPUT_ACTIVEHIGH;
	2760	}
	2761
	2762	++output_pin_count;
	2763	}
	2764	}
	2765	else if (!jed_get_fuse(jed, macrocells[index].feedback1_fuse) &&
	2766	jed_get_fuse(jed, macrocells[index].feedback2_fuse))
	2767	{
	2768	fprintf(stderr, "Unknown input/feedback select configuration.  (Pin %d)\n",
	2769	macrocells[index].pin);
	2770
	2771	continue;
	2772	}
	2773	}
	2774
	2775	set_output_pins(output_pins, output_pin_count);
	2776	}
	2777
	2778
	2779
	2780	/*-------------------------------------------------
2252	2781	config_gal18v10_pins - configures the pins
2253	2782	for a GAL18V10
2254	2783	-------------------------------------------------*/
2255	2784
2256		/*static void config_gal18v10_pins(const pal_data* pal, const jed_data* jed)
	2785	#if defined(include_gal18v10)
	2786	static void config_gal18v10_pins(const pal_data* pal, const jed_data* jed)
2257	2787	{
2258		}*/
	2788	typedef struct _output_logic_macrocell output_logic_macrocell;
	2789	struct _output_logic_macrocell
	2790	{
	2791	UINT16 pin;
	2792	UINT16 s0_fuse; /* 0 - active low, 1 - active high */
	2793	UINT16 s1_fuse; /* 0 - registered, 1 - combinatorial */
	2794	};
2259	2795
	2796	static output_logic_macrocell macrocells[] = {
	2797	{9, 3474, 3475},
	2798	{11, 3472, 3473},
	2799	{12, 3470, 3471},
	2800	{13, 3468, 3469},
	2801	{14, 3466, 3467},
	2802	{15, 3464, 3465},
	2803	{16, 3462, 3463},
	2804	{17, 3460, 3461},
	2805	{18, 3458, 3459},
	2806	{19, 3456, 3457}};
	2807	static UINT16 input_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19};
	2808	pin_output_config output_pins[ARRAY_LEN(macrocells)];
	2809	UINT16 index, output_pin_count;
2260	2810
	2811	output_pin_count = 0;
2261	2812
	2813	for (index = 0; index < ARRAY_LEN(output_pins); ++index)
	2814	{
	2815	if (jed_get_fuse(jed, macrocells[index].s1_fuse))
	2816	{
	2817	/* Combinatorial output or dedicated input */
	2818
	2819	if (does_output_enable_fuse_row_allow_output(pal, jed, pal->pinfuserows[index].fuserowoutputenable))
	2820	{
	2821	output_pins[output_pin_count].pin = macrocells[index].pin;
	2822	output_pins[output_pin_count].flags = OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
	2823
	2824	if (!jed_get_fuse(jed, macrocells[index].s0_fuse))
	2825	{
	2826	output_pins[output_pin_count].flags |= OUTPUT_ACTIVELOW;
	2827	}
	2828	else
	2829	{
	2830	output_pins[output_pin_count].flags |= OUTPUT_ACTIVEHIGH;
	2831	}
	2832
	2833	++output_pin_count;
	2834	}
	2835	}
	2836	else
	2837	{
	2838	/* Registered output */
	2839
	2840	output_pins[output_pin_count].pin = macrocells[index].pin;
	2841	output_pins[output_pin_count].flags = OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED;
	2842
	2843	if (!jed_get_fuse(jed, macrocells[index].s0_fuse))
	2844	{
	2845	output_pins[output_pin_count].flags |= OUTPUT_ACTIVELOW;
	2846	}
	2847	else
	2848	{
	2849	output_pins[output_pin_count].flags |= OUTPUT_ACTIVEHIGH;
	2850	}
	2851
	2852	++output_pin_count;
	2853	}
	2854	}
	2855
	2856	set_input_pins(input_pins, ARRAY_LEN(input_pins));
	2857	set_output_pins(output_pins, output_pin_count);
	2858	}
	2859	#endif
	2860
	2861
	2862
2262	2863	/*-------------------------------------------------
2263	2864	config_pal20l8_pins - configures the pins for
2264	2865	a PAL20L8
r19304	r19305
2274	2875
2275	2876	for (index = 0; index < pal->pinfuserowscount; ++index)
2276	2877	{
2277		if (any_fuses_in_row_blown(pal, jed, pal->pinfuserows[index].fuserowoutputenable))
	2878	if (does_output_enable_fuse_row_allow_output(pal, jed, pal->pinfuserows[index].fuserowoutputenable))
2278	2879	{
2279	2880	output_pins[output_pin_count].pin = pal->pinfuserows[index].pin;
2280	2881	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
2281	2882
	2883	if (pal->pinfuserows[index].pin != 15 &&
	2884	pal->pinfuserows[index].pin != 22)
	2885	{
	2886	output_pins[output_pin_count].flags |= OUTPUT_FEEDBACK_OUTPUT;
	2887	}
	2888	else
	2889	{
	2890	output_pins[output_pin_count].flags |= OUTPUT_FEEDBACK_NONE;
	2891	}
	2892
2282	2893	++output_pin_count;
2283	2894	}
2284	2895	}
r19304	r19305
2304	2915
2305	2916	for (index = 0; index < pal->pinfuserowscount; ++index)
2306	2917	{
2307		if (any_fuses_in_row_blown(pal, jed, pal->pinfuserows[index].fuserowoutputenable))
	2918	if (does_output_enable_fuse_row_allow_output(pal, jed, pal->pinfuserows[index].fuserowoutputenable))
2308	2919	{
2309	2920	output_pins[output_pin_count].pin = pal->pinfuserows[index].pin;
2310	2921	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
2311	2922
	2923	if (pal->pinfuserows[index].pin != 23 &&
	2924	pal->pinfuserows[index].pin != 14)
	2925	{
	2926	output_pins[output_pin_count].flags |= OUTPUT_FEEDBACK_OUTPUT;
	2927	}
	2928	else
	2929	{
	2930	output_pins[output_pin_count].flags |= OUTPUT_FEEDBACK_NONE;
	2931	}
	2932
2312	2933	++output_pin_count;
2313	2934	}
2314	2935	}
r19304	r19305
2333	2954
2334	2955	output_pin_count = 0;
2335	2956
2336		if (any_fuses_in_row_blown(pal, jed, 2240))
	2957	if (does_output_enable_fuse_row_allow_output(pal, jed, 2240))
2337	2958	{
2338	2959	output_pins[output_pin_count].pin = 15;
2339		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
	2960	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
2340	2961
2341	2962	++output_pin_count;
2342	2963	}
2343	2964
2344		if (any_fuses_in_row_blown(pal, jed, 1920))
	2965	if (does_output_enable_fuse_row_allow_output(pal, jed, 1920))
2345	2966	{
2346	2967	output_pins[output_pin_count].pin = 16;
2347		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
	2968	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
2348	2969
2349	2970	++output_pin_count;
2350	2971	}
r19304	r19305
2352	2973	for (index = 0; index < ARRAY_LEN(registered_pins); ++index)
2353	2974	{
2354	2975	output_pins[output_pin_count].pin = registered_pins[index];
2355		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_REGISTERED;
	2976	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED;
2356	2977
2357	2978	++output_pin_count;
2358	2979	}
2359	2980
2360		if (any_fuses_in_row_blown(pal, jed, 320))
	2981	if (does_output_enable_fuse_row_allow_output(pal, jed, 320))
2361	2982	{
2362	2983	output_pins[output_pin_count].pin = 21;
2363		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
	2984	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
2364	2985
2365	2986	++output_pin_count;
2366	2987	}
2367	2988
2368		if (any_fuses_in_row_blown(pal, jed, 0))
	2989	if (does_output_enable_fuse_row_allow_output(pal, jed, 0))
2369	2990	{
2370	2991	output_pins[output_pin_count].pin = 22;
2371		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
	2992	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
2372	2993
2373	2994	++output_pin_count;
2374	2995	}
r19304	r19305
2393	3014
2394	3015	output_pin_count = 0;
2395	3016
2396		if (any_fuses_in_row_blown(pal, jed, 2240))
	3017	if (does_output_enable_fuse_row_allow_output(pal, jed, 2240))
2397	3018	{
2398	3019	output_pins[output_pin_count].pin = 15;
2399		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
	3020	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
2400	3021
2401	3022	++output_pin_count;
2402	3023	}
r19304	r19305
2404	3025	for (index = 0; index < ARRAY_LEN(registered_pins); ++index)
2405	3026	{
2406	3027	output_pins[output_pin_count].pin = registered_pins[index];
2407		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_REGISTERED;
	3028	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED;
2408	3029
2409	3030	++output_pin_count;
2410	3031	}
2411	3032
2412		if (any_fuses_in_row_blown(pal, jed, 0))
	3033	if (does_output_enable_fuse_row_allow_output(pal, jed, 0))
2413	3034	{
2414	3035	output_pins[output_pin_count].pin = 22;
2415		output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL;
	3036	output_pins[output_pin_count].flags = OUTPUT_ACTIVELOW | OUTPUT_COMBINATORIAL | OUTPUT_FEEDBACK_OUTPUT;
2416	3037
2417	3038	++output_pin_count;
2418	3039	}
2419	3040
2420
2421	3041	set_input_pins(input_pins, ARRAY_LEN(input_pins));
2422	3042	set_output_pins(output_pins, output_pin_count);
2423	3043	}
r19304	r19305
2433	3053	{
2434	3054	static UINT16 input_pins[] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23};
2435	3055	static pin_output_config output_pins[] = {
2436		{15, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
2437		{16, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
2438		{17, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
2439		{18, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
2440		{19, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
2441		{20, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
2442		{21, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED},
2443		{22, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED}};
	3056	{15, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	3057	{16, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	3058	{17, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	3059	{18, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	3060	{19, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	3061	{20, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	3062	{21, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED},
	3063	{22, OUTPUT_ACTIVELOW | OUTPUT_REGISTERED | OUTPUT_FEEDBACK_REGISTERED}};
2444	3064
2445	3065	set_input_pins(input_pins, ARRAY_LEN(input_pins));
2446	3066	set_output_pins(output_pins, ARRAY_LEN(output_pins));
r19304	r19305
2449	3069
2450	3070
2451	3071	/*-------------------------------------------------
2452		is_gal16v8_product_term_enabled - determins if
	3072	is_gal16v8_product_term_enabled - determines if
2453	3073	a fuse row in a GAL16V8 is enabled
2454	3074	-------------------------------------------------*/
2455	3075
r19304	r19305
2472	3092
2473	3093
2474	3094	/*-------------------------------------------------
	3095	get_peel18cv8_pin_fuse_state - determines the
	3096	fuse state of an input pin in a fuse row
	3097	-------------------------------------------------*/
	3098
	3099	static UINT16 get_peel18cv8_pin_fuse_state(const pal_data* pal, const jed_data* jed, UINT16 pin, UINT16 fuserow)
	3100	{
	3101	const pin_fuse_columns* fuse_columns;
	3102	int lowfusestate, highfusestate, tmpfusestate, swapfusestates;
	3103	UINT16 cfgpin;
	3104
	3105	/* Synchronous Preset or Asynchronous Clear fuse row? */
	3106
	3107	if (fuserow == 2592 || fuserow == 2628)
	3108	{
	3109	return get_pin_fuse_state(pal, jed, pin, fuserow);
	3110	}
	3111
	3112	fuse_columns = find_fuse_columns(pal, pin);
	3113
	3114	if (!fuse_columns)
	3115	{
	3116	fprintf(stderr, "Fuse column data missing for pin %d!\n", pin);
	3117
	3118	return NO_FUSE_BLOWN;
	3119	}
	3120
	3121	cfgpin = find_pin_from_fuse_row(pal, fuserow);
	3122
	3123	if (!cfgpin)
	3124	{
	3125	fprintf(stderr, "Pin from fuse row failed!  (Fuse row: %d)\n", fuserow);
	3126
	3127	return get_pin_fuse_state(pal, jed, pin, fuserow);
	3128	}
	3129
	3130	lowfusestate = jed_get_fuse(jed, fuserow + fuse_columns->lowfusecolumn);
	3131	highfusestate = jed_get_fuse(jed, fuserow + fuse_columns->highfusecolumn);
	3132	swapfusestates = 0;
	3133
	3134	if (is_output_pin(pin) && is_output_pin(cfgpin))
	3135	{
	3136	if (get_pin_output_flags(cfgpin) & OUTPUT_FEEDBACK_COMBINATORIAL)
	3137	{
	3138	if ((get_pin_output_flags(pin) & OUTPUT_ACTIVELOW) &&
	3139	(get_pin_output_flags(pin) & OUTPUT_FEEDBACK_COMBINATORIAL))
	3140	{
	3141	swapfusestates = 1;
	3142	}
	3143	}
	3144	else if (get_pin_output_flags(cfgpin) & OUTPUT_FEEDBACK_REGISTERED)
	3145	{
	3146	if ((get_pin_output_flags(pin) & OUTPUT_ACTIVELOW) &&
	3147	(get_pin_output_flags(pin) & OUTPUT_FEEDBACK_REGISTERED))
	3148	{
	3149	swapfusestates = 1;
	3150	}
	3151	}
	3152	else if (get_pin_output_flags(cfgpin) & OUTPUT_FEEDBACK_OUTPUT)
	3153	{
	3154	if ((get_pin_output_flags(pin) & OUTPUT_ACTIVELOW) &&
	3155	(get_pin_output_flags(pin) & OUTPUT_FEEDBACK_REGISTERED))
	3156	{
	3157	swapfusestates = 1;
	3158	}
	3159	}
	3160	else
	3161	{
	3162	fprintf(stderr, "Unknown output pin type!  (Fuse row: %d)\n", fuserow);
	3163	}
	3164	}
	3165
	3166	if (swapfusestates)
	3167	{
	3168	tmpfusestate = lowfusestate;
	3169	lowfusestate = highfusestate;
	3170	highfusestate = tmpfusestate;
	3171	}
	3172
	3173	if (!lowfusestate && highfusestate)
	3174	{
	3175	return LOW_FUSE_BLOWN;
	3176	}
	3177	else if (lowfusestate && !highfusestate)
	3178	{
	3179	return HIGH_FUSE_BLOWN;
	3180	}
	3181	else if (!lowfusestate && !highfusestate)
	3182	{
	3183	return NO_FUSE_BLOWN;
	3184	}
	3185
	3186	return LOWHIGH_FUSE_BLOWN;
	3187	}
	3188
	3189
	3190
	3191	/*-------------------------------------------------
2475	3192	read_source_file - read a raw source file
2476	3193	into an allocated memory buffer
2477	3194	-------------------------------------------------*/
r19304	r19305
2564	3281	"  jedutil -convert <source.jed> <target.bin> [fuses] -- convert JEDEC to binary form\n"
2565	3282	"  jedutil -convert <source.pla> <target.bin> [fuses] -- convert Berkeley standard PLA to binary form\n"
2566	3283	"  jedutil -convert <source.bin> <target.jed> -- convert binary to JEDEC form\n"
2567		"  jedutil -view <source.jed> <pal name> -- dump JED logic equations\n"
2568		"  jedutil -view <source.bin> <pal name> -- dump binary logic equations\n"
	3284	"  jedutil -view <source.jed> <device> -- dump JED logic equations\n"
	3285	"  jedutil -view <source.bin> <device> -- dump binary logic equations\n"
2569	3286	"  jedutil -viewlist -- view list of supported devices\n"
2570	3287	);
2571	3288

trunk/src/regtests/jedutil/baseline/pal20l8/pal20l8.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 16, 17, 18, 19, 20, 21, 23
	4
	5	Outputs:
	6
	7	15 (Combinatorial, No output feedback, Active low)
	8	16 (Combinatorial, Output feedback output, Active low)
	9	17 (Combinatorial, Output feedback output, Active low)
	10	18 (Combinatorial, Output feedback output, Active low)
	11	19 (Combinatorial, Output feedback output, Active low)
	12	20 (Combinatorial, Output feedback output, Active low)
	13	21 (Combinatorial, Output feedback output, Active low)
	14	22 (Combinatorial, No output feedback, Active low)
	15
	16	Equations:
	17
1	18	/o15 = /i1 & i2 & /i3 & i4 & i11 +
2	19	/i1 & i2 & /i3 & /i5 & /i13 +
3	20	/i1 & i2 & /i3 & i6 & i14 +

trunk/src/regtests/jedutil/baseline/pal20r4/pal20r4.txt

r19304	r19305
	1	Inputs:
	2
	3	2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23
	4
	5	Outputs:
	6
	7	15 (Combinatorial, Output feedback output, Active low)
	8	16 (Combinatorial, Output feedback output, Active low)
	9	17 (Registered, Output feedback registered, Active low)
	10	18 (Registered, Output feedback registered, Active low)
	11	19 (Registered, Output feedback registered, Active low)
	12	20 (Registered, Output feedback registered, Active low)
	13	21 (Combinatorial, Output feedback output, Active low)
	14	22 (Combinatorial, Output feedback output, Active low)
	15
	16	Equations:
	17
1	18	/o15 = i2 & i6 & i7 +
2	19	i6 & o16 +
3	20	i3 & /o16 +

trunk/src/regtests/jedutil/baseline/pal20r6/pal20r6.txt

r19304	r19305
	1	Inputs:
	2
	3	2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23
	4
	5	Outputs:
	6
	7	15 (Combinatorial, Output feedback output, Active low)
	8	16 (Registered, Output feedback registered, Active low)
	9	17 (Registered, Output feedback registered, Active low)
	10	18 (Registered, Output feedback registered, Active low)
	11	19 (Registered, Output feedback registered, Active low)
	12	20 (Registered, Output feedback registered, Active low)
	13	21 (Registered, Output feedback registered, Active low)
	14	22 (Combinatorial, Output feedback output, Active low)
	15
	16	Equations:
	17
1	18	/o15 = i2 & i6 & i7 +
2	19	i6 & rf16 +
3	20	i3 & /rf16 +

trunk/src/regtests/jedutil/baseline/pal16l8/pal16l8.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 14, 15, 16, 17, 18
	4
	5	Outputs:
	6
	7	12 (Combinatorial, Output feedback output, Active low)
	8	13 (Combinatorial, Output feedback output, Active low)
	9	14 (Combinatorial, Output feedback output, Active low)
	10	15 (Combinatorial, Output feedback output, Active low)
	11	16 (Combinatorial, Output feedback output, Active low)
	12	17 (Combinatorial, Output feedback output, Active low)
	13	18 (Combinatorial, Output feedback output, Active low)
	14	19 (Combinatorial, Output feedback output, Active low)
	15
	16	Equations:
	17
1	18	/o12 = i3 & i7 & /i9 +
2	19	i1 & o13 +
3	20	i3 +

trunk/src/regtests/jedutil/baseline/gal16v8/pal16r8-to-gal16v8.txt

r19304	r19305
	1	Inputs:
	2
	3	2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Registered, Output feedback registered, Active low)
	8	13 (Registered, Output feedback registered, Active low)
	9	14 (Registered, Output feedback registered, Active low)
	10	15 (Registered, Output feedback registered, Active low)
	11	16 (Registered, Output feedback registered, Active low)
	12	17 (Registered, Output feedback registered, Active low)
	13	18 (Registered, Output feedback registered, Active low)
	14	19 (Registered, Output feedback registered, Active low)
	15
	16	Equations:
	17
1	18	/rf12 := /i2 & /i3 +
2	19	i4 & rf13 +
3	20	i3 +

trunk/src/regtests/jedutil/baseline/gal16v8/pal10h8-to-gal16v8.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Combinatorial, Output feedback output, Active high)
	8	13 (Combinatorial, Output feedback output, Active high)
	9	14 (Combinatorial, Output feedback output, Active high)
	10	15 (Combinatorial, No output feedback, Active high)
	11	16 (Combinatorial, No output feedback, Active high)
	12	17 (Combinatorial, Output feedback output, Active high)
	13	18 (Combinatorial, Output feedback output, Active high)
	14	19 (Combinatorial, Output feedback output, Active high)
	15
	16	Equations:
	17
1	18	o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
2	19	i9 & i11
3	20	o12.oe = vcc

trunk/src/regtests/jedutil/baseline/gal16v8/pal12h6-to-gal16v8.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
	4
	5	Outputs:
	6
	7	13 (Combinatorial, Output feedback output, Active high)
	8	14 (Combinatorial, Output feedback output, Active high)
	9	15 (Combinatorial, No output feedback, Active high)
	10	16 (Combinatorial, No output feedback, Active high)
	11	17 (Combinatorial, Output feedback output, Active high)
	12	18 (Combinatorial, Output feedback output, Active high)
	13
	14	Equations:
	15
1	16	o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
2	17	i9 & i11 +
3	18	/i19 +

trunk/src/regtests/jedutil/baseline/gal16v8/pal14h4-to-gal16v8.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
	4
	5	Outputs:
	6
	7	14 (Combinatorial, Output feedback output, Active high)
	8	15 (Combinatorial, No output feedback, Active high)
	9	16 (Combinatorial, No output feedback, Active high)
	10	17 (Combinatorial, Output feedback output, Active high)
	11
	12	Equations:
	13
1	14	o14 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
2	15	i9 & i11 +
3	16	/i12 & /i13 +

trunk/src/regtests/jedutil/baseline/gal16v8/pal16h2-to-gal16v8.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
	4
	5	Outputs:
	6
	7	15 (Combinatorial, No output feedback, Active high)
	8	16 (Combinatorial, No output feedback, Active high)
	9
	10	Equations:
	11
1	12	o15 = i1 & i2 & i3 & /i4 & i5 & /i6 & i7 & i8 +
2	13	i9 +
3	14	/i11 +

trunk/src/regtests/jedutil/baseline/gal16v8/pal16l2-to-gal16v8.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
	4
	5	Outputs:
	6
	7	15 (Combinatorial, No output feedback, Active low)
	8	16 (Combinatorial, No output feedback, Active low)
	9
	10	Equations:
	11
1	12	/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
2	13	/i9 +
3	14	/i11 +

trunk/src/regtests/jedutil/baseline/gal16v8/pal14l4-to-gal16v8.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
	4
	5	Outputs:
	6
	7	14 (Combinatorial, Output feedback output, Active low)
	8	15 (Combinatorial, No output feedback, Active low)
	9	16 (Combinatorial, No output feedback, Active low)
	10	17 (Combinatorial, Output feedback output, Active low)
	11
	12	Equations:
	13
1	14	/o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
2	15	/i9 & i11 +
3	16	i12 & /i13 +

trunk/src/regtests/jedutil/baseline/gal16v8/pal12l6-to-gal16v8.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
	4
	5	Outputs:
	6
	7	13 (Combinatorial, Output feedback output, Active low)
	8	14 (Combinatorial, Output feedback output, Active low)
	9	15 (Combinatorial, No output feedback, Active low)
	10	16 (Combinatorial, No output feedback, Active low)
	11	17 (Combinatorial, Output feedback output, Active low)
	12	18 (Combinatorial, Output feedback output, Active low)
	13
	14	Equations:
	15
1	16	/o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
2	17	i9 & i11 +
3	18	/i19 +

trunk/src/regtests/jedutil/baseline/gal16v8/pal10l8-to-gal16v8.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Combinatorial, Output feedback output, Active low)
	8	13 (Combinatorial, Output feedback output, Active low)
	9	14 (Combinatorial, Output feedback output, Active low)
	10	15 (Combinatorial, No output feedback, Active low)
	11	16 (Combinatorial, No output feedback, Active low)
	12	17 (Combinatorial, Output feedback output, Active low)
	13	18 (Combinatorial, Output feedback output, Active low)
	14	19 (Combinatorial, Output feedback output, Active low)
	15
	16	Equations:
	17
1	18	/o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
2	19	i9 & i11
3	20	o12.oe = vcc

trunk/src/regtests/jedutil/baseline/gal16v8/pal16l8-to-gal16v8.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 14, 15, 16, 17, 18
	4
	5	Outputs:
	6
	7	12 (Combinatorial, No output feedback, Active low)
	8	13 (Combinatorial, Output feedback output, Active low)
	9	14 (Combinatorial, Output feedback output, Active low)
	10	15 (Combinatorial, Output feedback output, Active low)
	11	16 (Combinatorial, Output feedback output, Active low)
	12	17 (Combinatorial, Output feedback output, Active low)
	13	18 (Combinatorial, Output feedback output, Active low)
	14	19 (Combinatorial, No output feedback, Active low)
	15
	16	Equations:
	17
1	18	/o12 = i3 & i7 & /i9 +
2	19	i1 & o13 +
3	20	i3 +

trunk/src/regtests/jedutil/baseline/gal16v8/pal16r4-to-gal16v8.txt

r19304	r19305
	1	Inputs:
	2
	3	2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Combinatorial, Output feedback output, Active low)
	8	13 (Combinatorial, Output feedback output, Active low)
	9	14 (Registered, Output feedback registered, Active low)
	10	15 (Registered, Output feedback registered, Active low)
	11	16 (Registered, Output feedback registered, Active low)
	12	17 (Registered, Output feedback registered, Active low)
	13	18 (Combinatorial, Output feedback output, Active low)
	14	19 (Combinatorial, Output feedback output, Active low)
	15
	16	Equations:
	17
1	18	/o12 = /i2 & /i3 +
2	19	i4 & o13 +
3	20	i3 +

trunk/src/regtests/jedutil/baseline/gal16v8/pal16r6-to-gal16v8.txt

r19304	r19305
	1	Inputs:
	2
	3	2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Combinatorial, Output feedback output, Active low)
	8	13 (Registered, Output feedback registered, Active low)
	9	14 (Registered, Output feedback registered, Active low)
	10	15 (Registered, Output feedback registered, Active low)
	11	16 (Registered, Output feedback registered, Active low)
	12	17 (Registered, Output feedback registered, Active low)
	13	18 (Registered, Output feedback registered, Active low)
	14	19 (Combinatorial, Output feedback output, Active low)
	15
	16	Equations:
	17
1	18	/o12 = /i2 & /i3 +
2	19	i4 & rf13 +
3	20	i3 +

trunk/src/regtests/jedutil/baseline/pal20r8/pal20r8.txt

r19304	r19305
	1	Inputs:
	2
	3	2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23
	4
	5	Outputs:
	6
	7	15 (Registered, Output feedback registered, Active low)
	8	16 (Registered, Output feedback registered, Active low)
	9	17 (Registered, Output feedback registered, Active low)
	10	18 (Registered, Output feedback registered, Active low)
	11	19 (Registered, Output feedback registered, Active low)
	12	20 (Registered, Output feedback registered, Active low)
	13	21 (Registered, Output feedback registered, Active low)
	14	22 (Registered, Output feedback registered, Active low)
	15
	16	Equations:
	17
1	18	/rf15 := i2 & i6 & i7 +
2	19	i6 & rf16 +
3	20	i3 & /rf16 +

trunk/src/regtests/jedutil/baseline/pal16r4/pal16r4.txt

r19304	r19305
	1	Inputs:
	2
	3	2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Combinatorial, Output feedback output, Active low)
	8	13 (Combinatorial, Output feedback output, Active low)
	9	14 (Registered, Output feedback registered, Active low)
	10	15 (Registered, Output feedback registered, Active low)
	11	16 (Registered, Output feedback registered, Active low)
	12	17 (Registered, Output feedback registered, Active low)
	13	18 (Combinatorial, Output feedback output, Active low)
	14	19 (Combinatorial, Output feedback output, Active low)
	15
	16	Equations:
	17
1	18	/o12 = /i2 & /i3 +
2	19	i4 & o13 +
3	20	i3 +

trunk/src/regtests/jedutil/baseline/pal16r6/pal16r6.txt

r19304	r19305
	1	Inputs:
	2
	3	2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Combinatorial, Output feedback output, Active low)
	8	13 (Registered, Output feedback registered, Active low)
	9	14 (Registered, Output feedback registered, Active low)
	10	15 (Registered, Output feedback registered, Active low)
	11	16 (Registered, Output feedback registered, Active low)
	12	17 (Registered, Output feedback registered, Active low)
	13	18 (Registered, Output feedback registered, Active low)
	14	19 (Combinatorial, Output feedback output, Active low)
	15
	16	Equations:
	17
1	18	/o12 = /i2 & /i3 +
2	19	i4 & rf13 +
3	20	i3 +

trunk/src/regtests/jedutil/baseline/pal20l10/pal20l10.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 16, 17, 18, 19, 20, 21, 22
	4
	5	Outputs:
	6
	7	14 (Combinatorial, No output feedback, Active low)
	8	15 (Combinatorial, Output feedback output, Active low)
	9	16 (Combinatorial, Output feedback output, Active low)
	10	17 (Combinatorial, Output feedback output, Active low)
	11	18 (Combinatorial, Output feedback output, Active low)
	12	19 (Combinatorial, Output feedback output, Active low)
	13	20 (Combinatorial, Output feedback output, Active low)
	14	21 (Combinatorial, Output feedback output, Active low)
	15	22 (Combinatorial, Output feedback output, Active low)
	16	23 (Combinatorial, No output feedback, Active low)
	17
	18	Equations:
	19
1	20	/o14 = /i11 +
2	21	i10 +
3	22	i9 & /o15

trunk/src/regtests/jedutil/baseline/pal16r8/pal16r8.txt

r19304	r19305
	1	Inputs:
	2
	3	2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Registered, Output feedback registered, Active low)
	8	13 (Registered, Output feedback registered, Active low)
	9	14 (Registered, Output feedback registered, Active low)
	10	15 (Registered, Output feedback registered, Active low)
	11	16 (Registered, Output feedback registered, Active low)
	12	17 (Registered, Output feedback registered, Active low)
	13	18 (Registered, Output feedback registered, Active low)
	14	19 (Registered, Output feedback registered, Active low)
	15
	16	Equations:
	17
1	18	/rf12 := /i2 & /i3 +
2	19	i4 & rf13 +
3	20	i3 +

trunk/src/regtests/jedutil/baseline/pal16c1/pal16c1.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
	4
	5	Outputs:
	6
	7	15 (Combinatorial, No output feedback, Active low)
	8	16 (Combinatorial, No output feedback, Active high)
	9
	10	Equations:
	11
1	12	/o15 = i1 & i2 +
2	13	i3 & i4 +
3	14	i5 & i6 +

trunk/src/regtests/jedutil/baseline/18cv8/pal16r6-to-peel18cv8.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Combinatorial, Output feedback output, Active low)
	8	13 (Registered, Output feedback registered, Active low)
	9	14 (Registered, Output feedback registered, Active low)
	10	15 (Registered, Output feedback registered, Active low)
	11	16 (Registered, Output feedback registered, Active low)
	12	17 (Registered, Output feedback registered, Active low)
	13	18 (Registered, Output feedback registered, Active low)
	14	19 (Combinatorial, Output feedback output, Active low)
	15
	16	Equations:
	17
	18	/o12 = /i2 & /i3 +
	19	i4 & rf13 +
	20	i3 +
	21	/i6 +
	22	i8 +
	23	/i9 +
	24	i7 & /rf13
	25	o12.oe = rf14
	26
	27	/rf13 := /rf14 +
	28	/i9 +
	29	i8 +
	30	/i7 +
	31	/i6 & /rf14 +
	32	i5 & rf14 +
	33	i4 +
	34	/i2
	35	rf13.oe = /i11
	36
	37	/rf14 := /rf15 +
	38	/i8 +
	39	i8 +
	40	/i2 & /rf15 +
	41	/i2 +
	42	i2 & /i8 & rf15 +
	43	/i4 +
	44	i3
	45	rf14.oe = /i11
	46
	47	/rf15 := i3 & i6 & i7 +
	48	i6 & rf16 +
	49	i3 & /rf16 +
	50	i7 +
	51	/i4 +
	52	i6 & i7 +
	53	i4 & i7 +
	54	/i2 & /i7
	55	rf15.oe = /i11
	56
	57	/rf16 := /i3 & /rf17 +
	58	/i4 +
	59	/i3 +
	60	/i3 & i4 +
	61	/i7 & rf17 +
	62	/i7 +
	63	i4 +
	64	i2 & i3
	65	rf16.oe = /i11
	66
	67	/rf17 := i2 & i5 & i6 & /i7 +
	68	i2 & /rf18 +
	69	i5 +
	70	i6 +
	71	/i7 & rf18 +
	72	i2 & /i7 +
	73	i5 & i6 +
	74	/i3
	75	rf17.oe = /i11
	76
	77	/rf18 := /i2 & i5 & i6 & /i7 +
	78	i3 & i6 & i7 +
	79	i3 +
	80	/i2 & /i7 +
	81	/i3 +
	82	i5 & i6 & /i7 +
	83	i7 +
	84	i4
	85	rf18.oe = /i11
	86
	87	/o19 = i5 & i6 & /i7 +
	88	i3 & i6 & i7 +
	89	i5 +
	90	i6 +
	91	i7 +
	92	/i4 +
	93	/i7
	94	o19.oe = vcc
	95

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/pal16r6-to-peel18cv8.txt

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/baseline/18cv8/pal16r8-to-peel18cv8.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Registered, Output feedback registered, Active low)
	8	13 (Registered, Output feedback registered, Active low)
	9	14 (Registered, Output feedback registered, Active low)
	10	15 (Registered, Output feedback registered, Active low)
	11	16 (Registered, Output feedback registered, Active low)
	12	17 (Registered, Output feedback registered, Active low)
	13	18 (Registered, Output feedback registered, Active low)
	14	19 (Registered, Output feedback registered, Active low)
	15
	16	Equations:
	17
	18	/rf12 := /i2 & /i3 +
	19	i4 & rf13 +
	20	i3 +
	21	/i6 +
	22	i8 +
	23	/i9 +
	24	i7 & /rf13 +
	25	i5
	26	rf12.oe = /i11
	27
	28	/rf13 := /rf14 +
	29	/i9 +
	30	i8 +
	31	/i7 +
	32	/i6 & rf14 +
	33	i5 +
	34	i4 +
	35	/i3
	36	rf13.oe = /i11
	37
	38	/rf14 := /rf15 +
	39	/i8 +
	40	i8 +
	41	/i2 & /rf15 +
	42	/i2 +
	43	i2 & /i8 & rf15 +
	44	/i4 +
	45	i3
	46	rf14.oe = /i11
	47
	48	/rf15 := i3 & i6 & i7 +
	49	i6 & rf16 +
	50	i3 & /rf16 +
	51	i7 +
	52	/i4 +
	53	i6 & i7 +
	54	i4 & i7 +
	55	/i2 & /i7
	56	rf15.oe = /i11
	57
	58	/rf16 := /i3 & /rf17 +
	59	/i4 +
	60	/i3 +
	61	/i3 & i4 +
	62	/i7 & rf17 +
	63	/i7 +
	64	i4 +
	65	i2 & i3
	66	rf16.oe = /i11
	67
	68	/rf17 := i2 & i5 & i6 & /i7 +
	69	i2 & /rf18 +
	70	i5 +
	71	i6 +
	72	/i7 & rf18 +
	73	i2 & /i7 +
	74	i5 & i6 +
	75	/i3
	76	rf17.oe = /i11
	77
	78	/rf18 := /i2 & i5 & i6 & /i7 +
	79	i3 & i6 & i7 +
	80	i3 & rf19 +
	81	/i2 & /i7 +
	82	/i3 & /rf19 +
	83	i5 & i6 & /i7 +
	84	i7 +
	85	/i4
	86	rf18.oe = /i11
	87
	88	/rf19 := i5 & i6 & /i7 +
	89	i3 & i6 & i7 +
	90	i5 & rf12 +
	91	i6 +
	92	i7 +
	93	/i4 & /rf12 +
	94	/i7 +
	95	i2
	96	rf19.oe = /i11
	97

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/pal16r8-to-peel18cv8.txt

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/baseline/18cv8/pal10h8-to-peel18cv8.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Combinatorial, Output feedback output, Active high)
	8	13 (Combinatorial, Output feedback output, Active high)
	9	14 (Combinatorial, Output feedback output, Active high)
	10	15 (Combinatorial, Output feedback output, Active high)
	11	16 (Combinatorial, Output feedback output, Active high)
	12	17 (Combinatorial, Output feedback output, Active high)
	13	18 (Combinatorial, Output feedback output, Active high)
	14	19 (Combinatorial, Output feedback output, Active high)
	15
	16	Equations:
	17
	18	o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
	19	i9 & i11
	20	o12.oe = vcc
	21
	22	o13 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
	23	/i9 & i11
	24	o13.oe = vcc
	25
	26	o14 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
	27	i9 & /i11
	28	o14.oe = vcc
	29
	30	o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
	31	/i9 & /i11
	32	o15.oe = vcc
	33
	34	o16 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
	35	/i9 & /i11
	36	o16.oe = vcc
	37
	38	o17 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
	39	i9 & /i11
	40	o17.oe = vcc
	41
	42	o18 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
	43	/i9 & i11
	44	o18.oe = vcc
	45
	46	o19 = i1 & i2 & i3 & i4 & i5 & i6 & i7 & /i8 +
	47	i11
	48	o19.oe = vcc
	49

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/pal10h8-to-peel18cv8.txt

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/baseline/18cv8/pal12h6-to-peel18cv8.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	13 (Combinatorial, Output feedback output, Active high)
	8	14 (Combinatorial, Output feedback output, Active high)
	9	15 (Combinatorial, Output feedback output, Active high)
	10	16 (Combinatorial, Output feedback output, Active high)
	11	17 (Combinatorial, Output feedback output, Active high)
	12	18 (Combinatorial, Output feedback output, Active high)
	13
	14	Equations:
	15
	16	o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
	17	i9 & i11 +
	18	/i19 +
	19	i12
	20	o13.oe = vcc
	21
	22	o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
	23	/i9 & i11
	24	o14.oe = vcc
	25
	26	o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
	27	/i9 & /i11
	28	o15.oe = vcc
	29
	30	o16 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
	31	i9 & /i11
	32	o16.oe = vcc
	33
	34	o17 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
	35	/i9 & /i11
	36	o17.oe = vcc
	37
	38	o18 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
	39	/i9 & i11 +
	40	i19 +
	41	/i12
	42	o18.oe = vcc
	43

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/pal12h6-to-peel18cv8.txt

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/baseline/18cv8/pal14h4-to-peel18cv8.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	14 (Combinatorial, Output feedback output, Active high)
	8	15 (Combinatorial, Output feedback output, Active high)
	9	16 (Combinatorial, Output feedback output, Active high)
	10	17 (Combinatorial, Output feedback output, Active high)
	11
	12	Equations:
	13
	14	o14 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
	15	i9 & i11 +
	16	/i12 & /i13 +
	17	i18 & /i19
	18	o14.oe = vcc
	19
	20	o15 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
	21	i9 & /i11 +
	22	i12 & i13 +
	23	/i18 & i19
	24	o15.oe = vcc
	25
	26	o16 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
	27	/i9 & i11 +
	28	i12 & /i13 +
	29	/i18 & /i19
	30	o16.oe = vcc
	31
	32	o17 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
	33	i9 & i11 +
	34	/i12 & i13 +
	35	i18 & i19
	36	o17.oe = vcc
	37

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/pal14h4-to-peel18cv8.txt

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/baseline/18cv8/pal16h2-to-peel18cv8.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	15 (Combinatorial, Output feedback output, Active high)
	8	16 (Combinatorial, Output feedback output, Active high)
	9
	10	Equations:
	11
	12	o15 = i1 & i2 & i3 & /i4 & i5 & /i6 & i7 & i8 +
	13	i9 +
	14	/i11 +
	15	i12 +
	16	/i13 +
	17	i14 +
	18	/i17 +
	19	i18 & /i19
	20	o15.oe = vcc
	21
	22	o16 = i1 & i2 & /i3 & i4 & /i5 & i6 & i7 & i8 +
	23	/i9 +
	24	i11 +
	25	/i12 +
	26	i13 +
	27	/i14 +
	28	i17 +
	29	/i18 & i19
	30	o16.oe = vcc
	31

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/pal16h2-to-peel18cv8.txt

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/baseline/18cv8/pal16l2-to-peel18cv8.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	15 (Combinatorial, Output feedback output, Active low)
	8	16 (Combinatorial, Output feedback output, Active low)
	9
	10	Equations:
	11
	12	/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
	13	/i9 +
	14	/i11 +
	15	/i12 +
	16	i13 +
	17	i14 +
	18	i17 +
	19	i18 & i19
	20	o15.oe = vcc
	21
	22	/o16 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
	23	i9 +
	24	i11 +
	25	i12 +
	26	/i13 +
	27	/i14 +
	28	/i17 +
	29	/i18 & /i19
	30	o16.oe = vcc
	31

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/pal16l2-to-peel18cv8.txt

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/baseline/18cv8/pal14l4-to-peel18cv8.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	14 (Combinatorial, Output feedback output, Active low)
	8	15 (Combinatorial, Output feedback output, Active low)
	9	16 (Combinatorial, Output feedback output, Active low)
	10	17 (Combinatorial, Output feedback output, Active low)
	11
	12	Equations:
	13
	14	/o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
	15	/i9 & i11 +
	16	i12 & /i13 +
	17	i18 & i19
	18	o14.oe = vcc
	19
	20	/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
	21	/i9 & /i11 +
	22	/i12 & i13 +
	23	/i18 & i19
	24	o15.oe = vcc
	25
	26	/o16 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
	27	/i9 & /i11 +
	28	i12 & i13 +
	29	i18 & /i19
	30	o16.oe = vcc
	31
	32	/o17 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
	33	/i9 & i11 +
	34	/i12 & /i13 +
	35	/i18 & /i19
	36	o17.oe = vcc
	37

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/pal14l4-to-peel18cv8.txt

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/baseline/18cv8/pal12l6-to-peel18cv8.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	13 (Combinatorial, Output feedback output, Active low)
	8	14 (Combinatorial, Output feedback output, Active low)
	9	15 (Combinatorial, Output feedback output, Active low)
	10	16 (Combinatorial, Output feedback output, Active low)
	11	17 (Combinatorial, Output feedback output, Active low)
	12	18 (Combinatorial, Output feedback output, Active low)
	13
	14	Equations:
	15
	16	/o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
	17	i9 & i11 +
	18	/i19 +
	19	i12
	20	o13.oe = vcc
	21
	22	/o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
	23	/i9 & i11
	24	o14.oe = vcc
	25
	26	/o15 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
	27	i9 & i11
	28	o15.oe = vcc
	29
	30	/o16 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
	31	/i9 & /i11
	32	o16.oe = vcc
	33
	34	/o17 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
	35	/i9 & /i11
	36	o17.oe = vcc
	37
	38	/o18 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
	39	/i9 & i11 +
	40	i19 +
	41	/i12
	42	o18.oe = vcc
	43

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/pal12l6-to-peel18cv8.txt

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/baseline/18cv8/pal10l8-to-peel18cv8.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Combinatorial, Output feedback output, Active low)
	8	13 (Combinatorial, Output feedback output, Active low)
	9	14 (Combinatorial, Output feedback output, Active low)
	10	15 (Combinatorial, Output feedback output, Active low)
	11	16 (Combinatorial, Output feedback output, Active low)
	12	17 (Combinatorial, Output feedback output, Active low)
	13	18 (Combinatorial, Output feedback output, Active low)
	14	19 (Combinatorial, Output feedback output, Active low)
	15
	16	Equations:
	17
	18	/o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
	19	i9 & i11
	20	o12.oe = vcc
	21
	22	/o13 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
	23	/i9 & i11
	24	o13.oe = vcc
	25
	26	/o14 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
	27	i9 & /i11
	28	o14.oe = vcc
	29
	30	/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
	31	/i9 & /i11
	32	o15.oe = vcc
	33
	34	/o16 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
	35	/i9 & /i11
	36	o16.oe = vcc
	37
	38	/o17 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
	39	i9 & /i11
	40	o17.oe = vcc
	41
	42	/o18 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
	43	i11
	44	o18.oe = vcc
	45
	46	/o19 = i1 & i2 & i3 & i4 & i5 & i6 & i7 & /i8 +
	47	/i9
	48	o19.oe = vcc
	49

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/pal10l8-to-peel18cv8.txt

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/baseline/18cv8/18cv8_combinatorial_feedback.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	13 (Registered, Output feedback combinatorial, Active low)
	8	15 (Registered, Output feedback combinatorial, Active high)
	9	17 (Combinatorial, Output feedback combinatorial, Active high)
	10	19 (Combinatorial, Output feedback combinatorial, Active low)
	11
	12	Equations:
	13
	14	/rf13 := /i3 & /i4 & /i5 & i6 +
	15	i1 & /i2 & of19 +
	16	/of17 & /of19 +
	17	i14 & of15 +
	18	i12 & /of15
	19	rf13.oe = of17
	20
	21	rf15 := of17 & of19 +
	22	/of19 +
	23	i11 & /i12 & of13 & /of17
	24	rf15.oe = /of13
	25
	26	o17 = /of19 +
	27	/of13 & of15 & i16 & of19 +
	28	of13 & /of15
	29	o17.oe = vcc
	30
	31	/o19 = of13 & i16 & /of17 & /i18 +
	32	/i9 & /i11 & of15 +
	33	/i7 & i8 & /of13 & /of15
	34	o19.oe = of17
	35

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/18cv8_combinatorial_feedback.txt

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/baseline/18cv8/18cv8_register_feedback.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	13 (Combinatorial, Output feedback registered, Active high)
	8	15 (Registered, Output feedback registered, Active low)
	9	17 (Combinatorial, Output feedback registered, Active low)
	10	19 (Registered, Output feedback registered, Active high)
	11
	12	Equations:
	13
	14	o13 = i3 & rf17 +
	15	/i12 & rf15 +
	16	/rf15 & /rf17 +
	17	i7 & rf19 +
	18	/i9 & /rf19
	19	o13.oe = vcc
	20
	21	/rf15 := /rf17 +
	22	/rf13 & rf19 +
	23	rf13 & rf17 & /rf19
	24	rf15.oe = rf17
	25
	26	/o17 = rf13 +
	27	i1 & /rf13 & /rf15 & i16 +
	28	rf15 & rf19
	29	o17.oe = /rf19
	30
	31	rf19 := rf13 & /rf17 +
	32	i8 & rf15 & rf17 +
	33	i1 & i2 & /rf15
	34	rf19.oe = /rf13
	35

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/18cv8_register_feedback.txt

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/baseline/18cv8/pal16l8-to-peel18cv8.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Combinatorial, Output feedback output, Active low)
	8	13 (Combinatorial, Output feedback output, Active low)
	9	14 (Combinatorial, Output feedback output, Active low)
	10	15 (Combinatorial, Output feedback output, Active low)
	11	16 (Combinatorial, Output feedback output, Active low)
	12	17 (Combinatorial, Output feedback output, Active low)
	13	18 (Combinatorial, Output feedback output, Active low)
	14	19 (Combinatorial, Output feedback output, Active low)
	15
	16	Equations:
	17
	18	/o12 = i3 & i7 & /i9 +
	19	i1 & o13 +
	20	i3 +
	21	/i6 +
	22	i8 +
	23	/i9 +
	24	i7 & /o13
	25	o12.oe = vcc
	26
	27	/o13 = i11 & /o14 +
	28	/i9 +
	29	i8 +
	30	/i7 +
	31	/i6 & o14 +
	32	i5 +
	33	i4
	34	o13.oe = i2 & o14
	35
	36	/o14 = i1 & /o15 +
	37	/i8 +
	38	i1 & /i8 +
	39	i1 & /i2 & /o15 +
	40	/i2 +
	41	i2 & /i8 & o15 +
	42	i3
	43	o14.oe = vcc
	44
	45	/o15 = i3 & i6 & i7 & /i11 +
	46	i6 & o16 +
	47	i3 & /o16 +
	48	i7 +
	49	/i11 +
	50	i6 & i7 +
	51	i7 & /i11
	52	o15.oe = vcc
	53
	54	/o16 = /i3 & /o17 +
	55	/i4 & /i11 +
	56	/i3 & /i4 +
	57	/i3 & i4 +
	58	/i7 & o17 +
	59	/i7 & /i11 +
	60	i4
	61	o16.oe = vcc
	62
	63	/o17 = i2 & i5 & i6 & /i7 +
	64	i2 & /o18 +
	65	i5 +
	66	i6 +
	67	/i7 & o18 +
	68	i2 & /i7 +
	69	i5 & i6
	70	o17.oe = /o16
	71
	72	/o18 = /i2 & i5 & i6 & /i7 +
	73	i3 & i6 & i7 & i11 +
	74	i3 +
	75	/i2 & /i7 +
	76	i3 & i11 +
	77	i5 & i6 & /i7 +
	78	i7 & i11
	79	o18.oe = vcc
	80
	81	/o19 = i5 & i6 & /i7 & i11 +
	82	i3 & i6 & i7 +
	83	i5 +
	84	i6 +
	85	i7 +
	86	i11 +
	87	/i7
	88	o19.oe = vcc
	89

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/pal16l8-to-peel18cv8.txt

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/baseline/18cv8/pal16r4-to-peel18cv8.txt

r0	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
	4
	5	Outputs:
	6
	7	12 (Combinatorial, Output feedback output, Active low)
	8	13 (Combinatorial, Output feedback output, Active low)
	9	14 (Registered, Output feedback registered, Active low)
	10	15 (Registered, Output feedback registered, Active low)
	11	16 (Registered, Output feedback registered, Active low)
	12	17 (Registered, Output feedback registered, Active low)
	13	18 (Combinatorial, Output feedback output, Active low)
	14	19 (Combinatorial, Output feedback output, Active low)
	15
	16	Equations:
	17
	18	/o12 = /i2 & /i3 +
	19	i4 & o13 +
	20	i3 +
	21	/i6 +
	22	i8 +
	23	/i9 +
	24	i7 & /o13
	25	o12.oe = rf14
	26
	27	/o13 = /rf14 +
	28	/i9 +
	29	i8 +
	30	/i7 +
	31	/i6 & /rf14 +
	32	i5 +
	33	i4
	34	o13.oe = i2 & rf14
	35
	36	/rf14 := /rf15 +
	37	/i8 +
	38	i8 +
	39	/i2 & /rf15 +
	40	/i2 +
	41	i2 & /i8 & rf15 +
	42	/i4 +
	43	i3
	44	rf14.oe = /i11
	45
	46	/rf15 := i3 & i6 & i7 +
	47	i6 & rf16 +
	48	i3 & /rf16 +
	49	i7 +
	50	/i4 +
	51	i6 & i7 +
	52	i4 & i7 +
	53	/i2 & /i7
	54	rf15.oe = /i11
	55
	56	/rf16 := /i3 & /rf17 +
	57	/i4 +
	58	/i3 +
	59	/i3 & i4 +
	60	/i7 & rf17 +
	61	/i7 +
	62	i4 +
	63	i2 & i3
	64	rf16.oe = /i11
	65
	66	/rf17 := i2 & i5 & i6 & /i7 +
	67	i2 & /o18 +
	68	i5 +
	69	i6 +
	70	/i7 & o18 +
	71	i2 & /i7 +
	72	i5 & i6 +
	73	/i3
	74	rf17.oe = /i11
	75
	76	/o18 = /i2 & i5 & i6 & /i7 +
	77	i3 & i6 & i7 +
	78	i3 +
	79	/i2 & /i7 +
	80	/i3 +
	81	i5 & i6 & /i7 +
	82	i7
	83	o18.oe = vcc
	84
	85	/o19 = i5 & i6 & /i7 +
	86	i3 & i6 & i7 +
	87	i5 +
	88	i6 +
	89	i7 +
	90	/i4 +
	91	/i7
	92	o19.oe = vcc
	93

Property changes on: trunk/src/regtests/jedutil/baseline/18cv8/pal16r4-to-peel18cv8.txt

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/baseline/pal14h4/pal14h4.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 18, 19
	4
	5	Outputs:
	6
	7	14 (Combinatorial, No output feedback, Active high)
	8	15 (Combinatorial, No output feedback, Active high)
	9	16 (Combinatorial, No output feedback, Active high)
	10	17 (Combinatorial, No output feedback, Active high)
	11
	12	Equations:
	13
1	14	o14 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
2	15	i9 & i11 +
3	16	/i12 & /i13 +

trunk/src/regtests/jedutil/baseline/pal16h2/pal16h2.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
	4
	5	Outputs:
	6
	7	15 (Combinatorial, No output feedback, Active high)
	8	16 (Combinatorial, No output feedback, Active high)
	9
	10	Equations:
	11
1	12	o15 = i1 & i2 & i3 & /i4 & i5 & /i6 & i7 & i8 +
2	13	i9 +
3	14	/i11 +

trunk/src/regtests/jedutil/baseline/pal10h8/pal10h8.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11
	4
	5	Outputs:
	6
	7	12 (Combinatorial, No output feedback, Active high)
	8	13 (Combinatorial, No output feedback, Active high)
	9	14 (Combinatorial, No output feedback, Active high)
	10	15 (Combinatorial, No output feedback, Active high)
	11	16 (Combinatorial, No output feedback, Active high)
	12	17 (Combinatorial, No output feedback, Active high)
	13	18 (Combinatorial, No output feedback, Active high)
	14	19 (Combinatorial, No output feedback, Active high)
	15
	16	Equations:
	17
1	18	o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
2	19	i9 & i11
3	20	o12.oe = vcc

trunk/src/regtests/jedutil/baseline/pal12h6/pal12h6.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 19
	4
	5	Outputs:
	6
	7	13 (Combinatorial, No output feedback, Active high)
	8	14 (Combinatorial, No output feedback, Active high)
	9	15 (Combinatorial, No output feedback, Active high)
	10	16 (Combinatorial, No output feedback, Active high)
	11	17 (Combinatorial, No output feedback, Active high)
	12	18 (Combinatorial, No output feedback, Active high)
	13
	14	Equations:
	15
1	16	o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
2	17	i9 & i11 +
3	18	/i19 +

trunk/src/regtests/jedutil/baseline/pal12l6/pal12l6.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 19
	4
	5	Outputs:
	6
	7	13 (Combinatorial, No output feedback, Active low)
	8	14 (Combinatorial, No output feedback, Active low)
	9	15 (Combinatorial, No output feedback, Active low)
	10	16 (Combinatorial, No output feedback, Active low)
	11	17 (Combinatorial, No output feedback, Active low)
	12	18 (Combinatorial, No output feedback, Active low)
	13
	14	Equations:
	15
1	16	/o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
2	17	i9 & i11 +
3	18	/i19 +

trunk/src/regtests/jedutil/baseline/pal14l4/pal14l4.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 18, 19
	4
	5	Outputs:
	6
	7	14 (Combinatorial, No output feedback, Active low)
	8	15 (Combinatorial, No output feedback, Active low)
	9	16 (Combinatorial, No output feedback, Active low)
	10	17 (Combinatorial, No output feedback, Active low)
	11
	12	Equations:
	13
1	14	/o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
2	15	/i9 & i11 +
3	16	i12 & /i13 +

trunk/src/regtests/jedutil/baseline/pal16l2/pal16l2.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
	4
	5	Outputs:
	6
	7	15 (Combinatorial, No output feedback, Active low)
	8	16 (Combinatorial, No output feedback, Active low)
	9
	10	Equations:
	11
1	12	/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
2	13	/i9 +
3	14	/i11 +

trunk/src/regtests/jedutil/baseline/pal10l8/pal10l8.txt

r19304	r19305
	1	Inputs:
	2
	3	1, 2, 3, 4, 5, 6, 7, 8, 9, 11
	4
	5	Outputs:
	6
	7	12 (Combinatorial, No output feedback, Active low)
	8	13 (Combinatorial, No output feedback, Active low)
	9	14 (Combinatorial, No output feedback, Active low)
	10	15 (Combinatorial, No output feedback, Active low)
	11	16 (Combinatorial, No output feedback, Active low)
	12	17 (Combinatorial, No output feedback, Active low)
	13	18 (Combinatorial, No output feedback, Active low)
	14	19 (Combinatorial, No output feedback, Active low)
	15
	16	Equations:
	17
1	18	/o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
2	19	i9 & i11
3	20	o12.oe = vcc

trunk/src/regtests/jedutil/jeds/18cv8/pal16r4-to-peel18cv8.jed

r0	r19305
	1	
	2	JEDEC PEEL file Translated from: PAL16R4     Mon 10-8-2012  22:43:51
	3	PA
	4	*QP20
	5	*QF2696
	6	*F0
	7	*
	8	N Output Pin 19  *
	9	L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	10	L0036 1111 1111 1111 1111 0111 0111 1011 1111 1111  *
	11	L0072 1111 1111 0111 1111 1111 0111 0111 1111 1111  *
	12	L0108 1111 1111 1111 1111 0111 1111 1111 1111 1111  *
	13	L0144 1111 1111 1111 1111 1111 0111 1111 1111 1111  *
	14	L0180 1111 1111 1111 1111 1111 1111 0111 1111 1111  *
	15	L0216 1111 1111 1111 1011 1111 1111 1111 1111 1111  *
	16	L0252 1111 1111 1111 1111 1111 1111 1011 1111 1111  *
	17
	18	N Output Pin 18  *
	19	L0288 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	20	L0324 1111 1011 1111 1111 0111 0111 1011 1111 1111  *
	21	L0360 1111 1111 0111 1111 1111 0111 0111 1111 1111  *
	22	L0396 1111 1111 0111 1111 1111 1111 1111 1111 1111  *
	23	L0432 1111 1011 1111 1111 1111 1111 1011 1111 1111  *
	24	L0468 1111 1111 1011 1111 1111 1111 1111 1111 1111  *
	25	L0504 1111 1111 1111 1111 0111 0111 1011 1111 1111  *
	26	L0540 1111 1111 1111 1111 1111 1111 0111 1111 1111  *
	27
	28	N Output Pin 17  *
	29	L0576 1111 0111 1111 1111 0111 0111 1011 1111 1111  *
	30	L0612 1111 0111 1110 1111 1111 1111 1111 1111 1111  *
	31	L0648 1111 1111 1111 1111 0111 1111 1111 1111 1111  *
	32	L0684 1111 1111 1111 1111 1111 0111 1111 1111 1111  *
	33	L0720 1111 1111 1101 1111 1111 1111 1011 1111 1111  *
	34	L0756 1111 0111 1111 1111 1111 1111 1011 1111 1111  *
	35	L0792 1111 1111 1111 1111 0111 0111 1111 1111 1111  *
	36	L0828 1111 1111 1011 1111 1111 1111 1111 1111 1111  *
	37
	38	N Output Pin 16  *
	39	L0864 1111 1111 1011 1101 1111 1111 1111 1111 1111  *
	40	L0900 1111 1111 1111 1011 1111 1111 1111 1111 1111  *
	41	L0936 1111 1111 1011 1111 1111 1111 1111 1111 1111  *
	42	L0972 1111 1111 1011 0111 1111 1111 1111 1111 1111  *
	43	L1008 1111 1111 1111 1110 1111 1111 1011 1111 1111  *
	44	L1044 1111 1111 1111 1111 1111 1111 1011 1111 1111  *
	45	L1080 1111 1111 1111 0111 1111 1111 1111 1111 1111  *
	46	L1116 1111 0111 0111 1111 1111 1111 1111 1111 1111  *
	47
	48	N Output Pin 15  *
	49	L1152 1111 1111 0111 1111 1111 0111 0111 1111 1111  *
	50	L1188 1111 1111 1111 1111 1110 0111 1111 1111 1111  *
	51	L1224 1111 1111 0111 1111 1101 1111 1111 1111 1111  *
	52	L1260 1111 1111 1111 1111 1111 1111 0111 1111 1111  *
	53	L1296 1111 1111 1111 1011 1111 1111 1111 1111 1111  *
	54	L1332 1111 1111 1111 1111 1111 0111 0111 1111 1111  *
	55	L1368 1111 1111 1111 0111 1111 1111 0111 1111 1111  *
	56	L1404 1111 1011 1111 1111 1111 1111 1011 1111 1111  *
	57
	58	N Output Pin 14  *
	59	L1440 1111 1111 1111 1111 1111 1101 1111 1111 1111  *
	60	L1476 1111 1111 1111 1111 1111 1111 1111 1011 1111  *
	61	L1512 1111 1111 1111 1111 1111 1111 1111 0111 1111  *
	62	L1548 1111 1011 1111 1111 1111 1101 1111 1111 1111  *
	63	L1584 1111 1011 1111 1111 1111 1111 1111 1111 1111  *
	64	L1620 1111 0111 1111 1111 1111 1110 1111 1011 1111  *
	65	L1656 1111 1111 1111 1011 1111 1111 1111 1111 1111  *
	66	L1692 1111 1111 0111 1111 1111 1111 1111 1111 1111  *
	67
	68	N Output Pin 13  *
	69	L1728 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	70	L1764 1111 1111 1111 1111 1111 1111 1101 1111 1111  *
	71	L1800 1111 1111 1111 1111 1111 1111 1111 1111 1011  *
	72	L1836 1111 1111 1111 1111 1111 1111 1111 0111 1111  *
	73	L1872 1111 1111 1111 1111 1111 1111 1011 1111 1111  *
	74	L1908 1111 1111 1111 1111 1111 1011 1101 1111 1111  *
	75	L1944 1111 1111 1111 1111 0111 1111 1111 1111 1111  *
	76	L1980 1111 1111 1111 0111 1111 1111 1111 1111 1111  *
	77
	78	N Output Pin 12  *
	79	L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	80	L2052 1111 1011 1011 1111 1111 1111 1111 1111 1111  *
	81	L2088 1111 1111 1111 0111 1111 1111 1111 1101 1111  *
	82	L2124 1111 1111 0111 1111 1111 1111 1111 1111 1111  *
	83	L2160 1111 1111 1111 1111 1111 1011 1111 1111 1111  *
	84	L2196 1111 1111 1111 1111 1111 1111 1111 0111 1111  *
	85	L2232 1111 1111 1111 1111 1111 1111 1111 1111 1011  *
	86	L2268 1111 1111 1111 1111 1111 1111 0111 1110 1111  *
	87
	88	N Output Enable 19,18,...12  *
	89	L2304 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	90	L2340 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	91	L2376 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	92	L2412 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	93	L2448 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	94	L2484 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	95	L2520 1111 0111 1111 1111 1111 1111 1110 1111 1111  *
	96	L2556 1111 1111 1111 1111 1111 1111 1110 1111 1111  *
	97
	98	N Sync Preset, Async Clear, Macrocell 19,18,...12  *
	99	L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	100	L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	101	L2664 1011 1011 1100 1100 1100 1100 1011 1011  *
	102
	103	C2C6E *
	104	0000

Property changes on: trunk/src/regtests/jedutil/jeds/18cv8/pal16r4-to-peel18cv8.jed

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/jeds/18cv8/pal16r6-to-peel18cv8.jed

r0	r19305
	1	
	2	JEDEC PEEL file Translated from: PAL16R6     Mon 10-8-2012  22:44:19
	3	PA
	4	*QP20
	5	*QF2696
	6	*F0
	7	*
	8	N Output Pin 19  *
	9	L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	10	L0036 1111 1111 1111 1111 0111 0111 1011 1111 1111  *
	11	L0072 1111 1111 0111 1111 1111 0111 0111 1111 1111  *
	12	L0108 1111 1111 1111 1111 0111 1111 1111 1111 1111  *
	13	L0144 1111 1111 1111 1111 1111 0111 1111 1111 1111  *
	14	L0180 1111 1111 1111 1111 1111 1111 0111 1111 1111  *
	15	L0216 1111 1111 1111 1011 1111 1111 1111 1111 1111  *
	16	L0252 1111 1111 1111 1111 1111 1111 1011 1111 1111  *
	17
	18	N Output Pin 18  *
	19	L0288 1111 1011 1111 1111 0111 0111 1011 1111 1111  *
	20	L0324 1111 1111 0111 1111 1111 0111 0111 1111 1111  *
	21	L0360 1111 1111 0111 1111 1111 1111 1111 1111 1111  *
	22	L0396 1111 1011 1111 1111 1111 1111 1011 1111 1111  *
	23	L0432 1111 1111 1011 1111 1111 1111 1111 1111 1111  *
	24	L0468 1111 1111 1111 1111 0111 0111 1011 1111 1111  *
	25	L0504 1111 1111 1111 1111 1111 1111 0111 1111 1111  *
	26	L0540 1111 1111 1111 0111 1111 1111 1111 1111 1111  *
	27
	28	N Output Pin 17  *
	29	L0576 1111 0111 1111 1111 0111 0111 1011 1111 1111  *
	30	L0612 1111 0111 1101 1111 1111 1111 1111 1111 1111  *
	31	L0648 1111 1111 1111 1111 0111 1111 1111 1111 1111  *
	32	L0684 1111 1111 1111 1111 1111 0111 1111 1111 1111  *
	33	L0720 1111 1111 1110 1111 1111 1111 1011 1111 1111  *
	34	L0756 1111 0111 1111 1111 1111 1111 1011 1111 1111  *
	35	L0792 1111 1111 1111 1111 0111 0111 1111 1111 1111  *
	36	L0828 1111 1111 1011 1111 1111 1111 1111 1111 1111  *
	37
	38	N Output Pin 16  *
	39	L0864 1111 1111 1011 1101 1111 1111 1111 1111 1111  *
	40	L0900 1111 1111 1111 1011 1111 1111 1111 1111 1111  *
	41	L0936 1111 1111 1011 1111 1111 1111 1111 1111 1111  *
	42	L0972 1111 1111 1011 0111 1111 1111 1111 1111 1111  *
	43	L1008 1111 1111 1111 1110 1111 1111 1011 1111 1111  *
	44	L1044 1111 1111 1111 1111 1111 1111 1011 1111 1111  *
	45	L1080 1111 1111 1111 0111 1111 1111 1111 1111 1111  *
	46	L1116 1111 0111 0111 1111 1111 1111 1111 1111 1111  *
	47
	48	N Output Pin 15  *
	49	L1152 1111 1111 0111 1111 1111 0111 0111 1111 1111  *
	50	L1188 1111 1111 1111 1111 1110 0111 1111 1111 1111  *
	51	L1224 1111 1111 0111 1111 1101 1111 1111 1111 1111  *
	52	L1260 1111 1111 1111 1111 1111 1111 0111 1111 1111  *
	53	L1296 1111 1111 1111 1011 1111 1111 1111 1111 1111  *
	54	L1332 1111 1111 1111 1111 1111 0111 0111 1111 1111  *
	55	L1368 1111 1111 1111 0111 1111 1111 0111 1111 1111  *
	56	L1404 1111 1011 1111 1111 1111 1111 1011 1111 1111  *
	57
	58	N Output Pin 14  *
	59	L1440 1111 1111 1111 1111 1111 1101 1111 1111 1111  *
	60	L1476 1111 1111 1111 1111 1111 1111 1111 1011 1111  *
	61	L1512 1111 1111 1111 1111 1111 1111 1111 0111 1111  *
	62	L1548 1111 1011 1111 1111 1111 1101 1111 1111 1111  *
	63	L1584 1111 1011 1111 1111 1111 1111 1111 1111 1111  *
	64	L1620 1111 0111 1111 1111 1111 1110 1111 1011 1111  *
	65	L1656 1111 1111 1111 1011 1111 1111 1111 1111 1111  *
	66	L1692 1111 1111 0111 1111 1111 1111 1111 1111 1111  *
	67
	68	N Output Pin 13  *
	69	L1728 1111 1111 1111 1111 1111 1111 1101 1111 1111  *
	70	L1764 1111 1111 1111 1111 1111 1111 1111 1111 1011  *
	71	L1800 1111 1111 1111 1111 1111 1111 1111 0111 1111  *
	72	L1836 1111 1111 1111 1111 1111 1111 1011 1111 1111  *
	73	L1872 1111 1111 1111 1111 1111 1011 1101 1111 1111  *
	74	L1908 1111 1111 1111 1111 0111 1111 1110 1111 1111  *
	75	L1944 1111 1111 1111 0111 1111 1111 1111 1111 1111  *
	76	L1980 1111 1011 1111 1111 1111 1111 1111 1111 1111  *
	77
	78	N Output Pin 12  *
	79	L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	80	L2052 1111 1011 1011 1111 1111 1111 1111 1111 1111  *
	81	L2088 1111 1111 1111 0111 1111 1111 1111 1110 1111  *
	82	L2124 1111 1111 0111 1111 1111 1111 1111 1111 1111  *
	83	L2160 1111 1111 1111 1111 1111 1011 1111 1111 1111  *
	84	L2196 1111 1111 1111 1111 1111 1111 1111 0111 1111  *
	85	L2232 1111 1111 1111 1111 1111 1111 1111 1111 1011  *
	86	L2268 1111 1111 1111 1111 1111 1111 0111 1101 1111  *
	87
	88	N Output Enable 19,18,...12  *
	89	L2304 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	90	L2340 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	91	L2376 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	92	L2412 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	93	L2448 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	94	L2484 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	95	L2520 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	96	L2556 1111 1111 1111 1111 1111 1111 1110 1111 1111  *
	97
	98	N Sync Preset, Async Clear, Macrocell 19,18,...12  *
	99	L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	100	L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	101	L2664 1011 1100 1100 1100 1100 1100 1100 1011  *
	102
	103	C32E7 *
	104	0000

Property changes on: trunk/src/regtests/jedutil/jeds/18cv8/pal16r6-to-peel18cv8.jed

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/jeds/18cv8/pal16r8-to-peel18cv8.jed

r0	r19305
	1	
	2	JEDEC PEEL file Translated from: PAL16R8     Mon 10-8-2012  22:46:06
	3	PA
	4	*QP20
	5	*QF2696
	6	*F0
	7	*
	8	N Output Pin 19  *
	9	L0000 1111 1111 1111 1111 0111 0111 1011 1111 1111  *
	10	L0036 1111 1111 0111 1111 1111 0111 0111 1111 1111  *
	11	L0072 1111 1111 1111 1111 0111 1111 1111 1111 1110  *
	12	L0108 1111 1111 1111 1111 1111 0111 1111 1111 1111  *
	13	L0144 1111 1111 1111 1111 1111 1111 0111 1111 1111  *
	14	L0180 1111 1111 1111 1011 1111 1111 1111 1111 1101  *
	15	L0216 1111 1111 1111 1111 1111 1111 1011 1111 1111  *
	16	L0252 1111 0111 1111 1111 1111 1111 1111 1111 1111  *
	17
	18	N Output Pin 18  *
	19	L0288 1111 1011 1111 1111 0111 0111 1011 1111 1111  *
	20	L0324 1111 1111 0111 1111 1111 0111 0111 1111 1111  *
	21	L0360 1111 1110 0111 1111 1111 1111 1111 1111 1111  *
	22	L0396 1111 1011 1111 1111 1111 1111 1011 1111 1111  *
	23	L0432 1111 1101 1011 1111 1111 1111 1111 1111 1111  *
	24	L0468 1111 1111 1111 1111 0111 0111 1011 1111 1111  *
	25	L0504 1111 1111 1111 1111 1111 1111 0111 1111 1111  *
	26	L0540 1111 1111 1111 1011 1111 1111 1111 1111 1111  *
	27
	28	N Output Pin 17  *
	29	L0576 1111 0111 1111 1111 0111 0111 1011 1111 1111  *
	30	L0612 1111 0111 1101 1111 1111 1111 1111 1111 1111  *
	31	L0648 1111 1111 1111 1111 0111 1111 1111 1111 1111  *
	32	L0684 1111 1111 1111 1111 1111 0111 1111 1111 1111  *
	33	L0720 1111 1111 1110 1111 1111 1111 1011 1111 1111  *
	34	L0756 1111 0111 1111 1111 1111 1111 1011 1111 1111  *
	35	L0792 1111 1111 1111 1111 0111 0111 1111 1111 1111  *
	36	L0828 1111 1111 1011 1111 1111 1111 1111 1111 1111  *
	37
	38	N Output Pin 16  *
	39	L0864 1111 1111 1011 1101 1111 1111 1111 1111 1111  *
	40	L0900 1111 1111 1111 1011 1111 1111 1111 1111 1111  *
	41	L0936 1111 1111 1011 1111 1111 1111 1111 1111 1111  *
	42	L0972 1111 1111 1011 0111 1111 1111 1111 1111 1111  *
	43	L1008 1111 1111 1111 1110 1111 1111 1011 1111 1111  *
	44	L1044 1111 1111 1111 1111 1111 1111 1011 1111 1111  *
	45	L1080 1111 1111 1111 0111 1111 1111 1111 1111 1111  *
	46	L1116 1111 0111 0111 1111 1111 1111 1111 1111 1111  *
	47
	48	N Output Pin 15  *
	49	L1152 1111 1111 0111 1111 1111 0111 0111 1111 1111  *
	50	L1188 1111 1111 1111 1111 1110 0111 1111 1111 1111  *
	51	L1224 1111 1111 0111 1111 1101 1111 1111 1111 1111  *
	52	L1260 1111 1111 1111 1111 1111 1111 0111 1111 1111  *
	53	L1296 1111 1111 1111 1011 1111 1111 1111 1111 1111  *
	54	L1332 1111 1111 1111 1111 1111 0111 0111 1111 1111  *
	55	L1368 1111 1111 1111 0111 1111 1111 0111 1111 1111  *
	56	L1404 1111 1011 1111 1111 1111 1111 1011 1111 1111  *
	57
	58	N Output Pin 14  *
	59	L1440 1111 1111 1111 1111 1111 1101 1111 1111 1111  *
	60	L1476 1111 1111 1111 1111 1111 1111 1111 1011 1111  *
	61	L1512 1111 1111 1111 1111 1111 1111 1111 0111 1111  *
	62	L1548 1111 1011 1111 1111 1111 1101 1111 1111 1111  *
	63	L1584 1111 1011 1111 1111 1111 1111 1111 1111 1111  *
	64	L1620 1111 0111 1111 1111 1111 1110 1111 1011 1111  *
	65	L1656 1111 1111 1111 1011 1111 1111 1111 1111 1111  *
	66	L1692 1111 1111 0111 1111 1111 1111 1111 1111 1111  *
	67
	68	N Output Pin 13  *
	69	L1728 1111 1111 1111 1111 1111 1111 1101 1111 1111  *
	70	L1764 1111 1111 1111 1111 1111 1111 1111 1111 1011  *
	71	L1800 1111 1111 1111 1111 1111 1111 1111 0111 1111  *
	72	L1836 1111 1111 1111 1111 1111 1111 1011 1111 1111  *
	73	L1872 1111 1111 1111 1111 1111 1011 1110 1111 1111  *
	74	L1908 1111 1111 1111 1111 0111 1111 1111 1111 1111  *
	75	L1944 1111 1111 1111 0111 1111 1111 1111 1111 1111  *
	76	L1980 1111 1111 1011 1111 1111 1111 1111 1111 1111  *
	77
	78	N Output Pin 12  *
	79	L2016 1111 1011 1011 1111 1111 1111 1111 1111 1111  *
	80	L2052 1111 1111 1111 0111 1111 1111 1111 1110 1111  *
	81	L2088 1111 1111 0111 1111 1111 1111 1111 1111 1111  *
	82	L2124 1111 1111 1111 1111 1111 1011 1111 1111 1111  *
	83	L2160 1111 1111 1111 1111 1111 1111 1111 0111 1111  *
	84	L2196 1111 1111 1111 1111 1111 1111 1111 1111 1011  *
	85	L2232 1111 1111 1111 1111 1111 1111 0111 1101 1111  *
	86	L2268 1111 1111 1111 1111 0111 1111 1111 1111 1111  *
	87
	88	N Output Enable 19,18,...12  *
	89	L2304 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	90	L2340 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	91	L2376 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	92	L2412 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	93	L2448 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	94	L2484 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	95	L2520 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	96	L2556 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	97
	98	N Sync Preset, Async Clear, Macrocell 19,18,...12  *
	99	L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	100	L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	101	L2664 1100 1100 1100 1100 1100 1100 1100 1100  *
	102
	103	C3A61 *
	104	0000

Property changes on: trunk/src/regtests/jedutil/jeds/18cv8/pal16r8-to-peel18cv8.jed

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/jeds/18cv8/pal16h2-to-peel18cv8.jed

r0	r19305
	1	
	2	JEDEC PEEL file Translated from: PAL16H2     Mon 10-8-2012  22:42:12
	3	PA
	4	*QP20
	5	*QF2696
	6	*F0
	7	*
	8	N Output Pin 19  *
	9	L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	10	L0036 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	11	L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	12	L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	13	L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	14	L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	15	L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	16	L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	17
	18	N Output Pin 18  *
	19	L0288 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	20	L0324 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	21	L0360 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	22	L0396 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	23	L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	24	L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	25	L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	26	L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	27
	28	N Output Pin 17  *
	29	L0576 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	30	L0612 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	31	L0648 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	32	L0684 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	33	L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	34	L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	35	L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	36	L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	37
	38	N Output Pin 16  *
	39	L0864 0111 0111 1011 0111 1011 0111 0111 0111 1111  *
	40	L0900 1111 1111 1111 1111 1111 1111 1111 1111 1011  *
	41	L0936 1101 1111 1111 1111 1111 1111 1111 1111 1111  *
	42	L0972 1111 1111 1111 1111 1111 1111 1111 1111 1110  *
	43	L1008 1111 1111 1111 1111 1111 1111 1111 1101 1111  *
	44	L1044 1111 1111 1111 1111 1111 1111 1110 1111 1111  *
	45	L1080 1111 1111 1111 1101 1111 1111 1111 1111 1111  *
	46	L1116 1111 1101 1110 1111 1111 1111 1111 1111 1111  *
	47
	48	N Output Pin 15  *
	49	L1152 0111 0111 0111 1011 0111 1011 0111 0111 1111  *
	50	L1188 1111 1111 1111 1111 1111 1111 1111 1111 0111  *
	51	L1224 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	52	L1260 1111 1111 1111 1111 1111 1111 1111 1111 1101  *
	53	L1296 1111 1111 1111 1111 1111 1111 1111 1110 1111  *
	54	L1332 1111 1111 1111 1111 1111 1111 1101 1111 1111  *
	55	L1368 1111 1111 1111 1110 1111 1111 1111 1111 1111  *
	56	L1404 1111 1110 1101 1111 1111 1111 1111 1111 1111  *
	57
	58	N Output Pin 14  *
	59	L1440 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	60	L1476 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	61	L1512 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	62	L1548 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	63	L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	64	L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	65	L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	66	L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	67
	68	N Output Pin 13  *
	69	L1728 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	70	L1764 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	71	L1800 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	72	L1836 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	73	L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	74	L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	75	L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	76	L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	77
	78	N Output Pin 12  *
	79	L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	80	L2052 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	81	L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	82	L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	83	L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	84	L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	85	L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	86	L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	87
	88	N Output Enable 19,18,...12  *
	89	L2304 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	90	L2340 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	91	L2376 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	92	L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	93	L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	94	L2484 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	95	L2520 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	96	L2556 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	97
	98	N Sync Preset, Async Clear, Macrocell 19,18,...12  *
	99	L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	100	L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	101	L2664 0011 0011 0011 0011 0011 0011 0011 0011  *
	102
	103	C4F2D *
	104	0000

Property changes on: trunk/src/regtests/jedutil/jeds/18cv8/pal16h2-to-peel18cv8.jed

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/jeds/18cv8/pal14h4-to-peel18cv8.jed

r0	r19305
	1	
	2	JEDEC PEEL file Translated from: PAL14H4     Mon 10-8-2012  22:40:43
	3	PA
	4	*QP20
	5	*QF2696
	6	*F0
	7	*
	8	N Output Pin 19  *
	9	L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	10	L0036 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	11	L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	12	L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	13	L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	14	L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	15	L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	16	L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	17
	18	N Output Pin 18  *
	19	L0288 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	20	L0324 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	21	L0360 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	22	L0396 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	23	L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	24	L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	25	L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	26	L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	27
	28	N Output Pin 17  *
	29	L0576 0111 0111 0111 1011 0111 0111 0111 0111 1111  *
	30	L0612 1101 1111 1111 1111 1111 1111 1111 1111 0111  *
	31	L0648 1111 1111 1111 1111 1111 1111 1111 1101 1110  *
	32	L0684 1111 1101 1101 1111 1111 1111 1111 1111 1111  *
	33	L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	34	L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	35	L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	36	L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	37
	38	N Output Pin 16  *
	39	L0864 0111 0111 1011 0111 0111 0111 0111 0111 1111  *
	40	L0900 1101 1111 1111 1111 1111 1111 1111 1111 1011  *
	41	L0936 1111 1111 1111 1111 1111 1111 1111 1110 1101  *
	42	L0972 1111 1110 1110 1111 1111 1111 1111 1111 1111  *
	43	L1008 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	44	L1044 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	45	L1080 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	46	L1116 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	47
	48	N Output Pin 15  *
	49	L1152 0111 1011 0111 0111 0111 0111 0111 0111 1111  *
	50	L1188 1110 1111 1111 1111 1111 1111 1111 1111 0111  *
	51	L1224 1111 1111 1111 1111 1111 1111 1111 1101 1101  *
	52	L1260 1111 1101 1110 1111 1111 1111 1111 1111 1111  *
	53	L1296 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	54	L1332 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	55	L1368 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	56	L1404 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	57
	58	N Output Pin 14  *
	59	L1440 1011 0111 0111 0111 0111 0111 0111 0111 1111  *
	60	L1476 1101 1111 1111 1111 1111 1111 1111 1111 0111  *
	61	L1512 1111 1111 1111 1111 1111 1111 1111 1110 1110  *
	62	L1548 1111 1110 1101 1111 1111 1111 1111 1111 1111  *
	63	L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	64	L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	65	L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	66	L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	67
	68	N Output Pin 13  *
	69	L1728 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	70	L1764 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	71	L1800 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	72	L1836 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	73	L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	74	L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	75	L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	76	L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	77
	78	N Output Pin 12  *
	79	L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	80	L2052 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	81	L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	82	L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	83	L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	84	L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	85	L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	86	L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	87
	88	N Output Enable 19,18,...12  *
	89	L2304 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	90	L2340 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	91	L2376 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	92	L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	93	L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	94	L2484 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	95	L2520 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	96	L2556 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	97
	98	N Sync Preset, Async Clear, Macrocell 19,18,...12  *
	99	L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	100	L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	101	L2664 0011 0011 0011 0011 0011 0011 0011 0011  *
	102
	103	C56E4 *
	104	0000

Property changes on: trunk/src/regtests/jedutil/jeds/18cv8/pal14h4-to-peel18cv8.jed

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/jeds/18cv8/pal12h6-to-peel18cv8.jed

r0	r19305
	1	
	2	JEDEC PEEL file Translated from: PAL12H6     Mon 10-8-2012  22:39:42
	3	PA
	4	*QP20
	5	*QF2696
	6	*F0
	7	*
	8	N Output Pin 19  *
	9	L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	10	L0036 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	11	L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	12	L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	13	L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	14	L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	15	L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	16	L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	17
	18	N Output Pin 18  *
	19	L0288 0111 0111 0111 0111 0111 1011 0111 0111 1111  *
	20	L0324 1101 1111 1111 1111 1111 1111 1111 1111 1011  *
	21	L0360 1111 1101 1111 1111 1111 1111 1111 1111 1111  *
	22	L0396 1111 1111 1111 1111 1111 1111 1111 1111 1110  *
	23	L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	24	L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	25	L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	26	L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	27
	28	N Output Pin 17  *
	29	L0576 0111 0111 0111 0111 1011 0111 0111 0111 1111  *
	30	L0612 1110 1111 1111 1111 1111 1111 1111 1111 1011  *
	31	L0648 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	32	L0684 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	33	L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	34	L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	35	L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	36	L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	37
	38	N Output Pin 16  *
	39	L0864 0111 0111 0111 0111 0111 0111 1011 0111 1111  *
	40	L0900 1110 1111 1111 1111 1111 1111 1111 1111 0111  *
	41	L0936 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	42	L0972 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	43	L1008 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	44	L1044 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	45	L1080 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	46	L1116 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	47
	48	N Output Pin 15  *
	49	L1152 0111 0111 0111 1011 0111 0111 0111 0111 1111  *
	50	L1188 1110 1111 1111 1111 1111 1111 1111 1111 1011  *
	51	L1224 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	52	L1260 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	53	L1296 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	54	L1332 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	55	L1368 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	56	L1404 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	57
	58	N Output Pin 14  *
	59	L1440 0111 1011 0111 0111 0111 0111 0111 0111 1111  *
	60	L1476 1101 1111 1111 1111 1111 1111 1111 1111 1011  *
	61	L1512 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	62	L1548 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	63	L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	64	L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	65	L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	66	L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	67
	68	N Output Pin 13  *
	69	L1728 1011 0111 0111 0111 0111 0111 0111 0111 1111  *
	70	L1764 1101 1111 1111 1111 1111 1111 1111 1111 0111  *
	71	L1800 1111 1110 1111 1111 1111 1111 1111 1111 1111  *
	72	L1836 1111 1111 1111 1111 1111 1111 1111 1111 1101  *
	73	L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	74	L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	75	L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	76	L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	77
	78	N Output Pin 12  *
	79	L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	80	L2052 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	81	L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	82	L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	83	L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	84	L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	85	L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	86	L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	87
	88	N Output Enable 19,18,...12  *
	89	L2304 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	90	L2340 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	91	L2376 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	92	L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	93	L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	94	L2484 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	95	L2520 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	96	L2556 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	97
	98	N Sync Preset, Async Clear, Macrocell 19,18,...12  *
	99	L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	100	L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	101	L2664 0011 0011 0011 0011 0011 0011 0011 0011  *
	102
	103	C5FA2 *
	104	0000

Property changes on: trunk/src/regtests/jedutil/jeds/18cv8/pal12h6-to-peel18cv8.jed

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/jeds/18cv8/pal10h8-to-peel18cv8.jed

r0	r19305
	1	
	2	JEDEC PEEL file Translated from: PAL10H8     Mon 10-8-2012  22:35:56
	3	PA
	4	*QP20
	5	*QF2696
	6	*F0
	7	*
	8	N Output Pin 19  *
	9	L0000 0111 0111 0111 0111 0111 0111 0111 1011 1111  *
	10	L0036 1101 1111 1111 1111 1111 1111 1111 1111 1111  *
	11	L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	12	L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	13	L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	14	L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	15	L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	16	L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	17
	18	N Output Pin 18  *
	19	L0288 0111 0111 0111 0111 0111 0111 1011 0111 1111  *
	20	L0324 1101 1111 1111 1111 1111 1111 1111 1111 1011  *
	21	L0360 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	22	L0396 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	23	L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	24	L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	25	L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	26	L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	27
	28	N Output Pin 17  *
	29	L0576 0111 0111 0111 0111 0111 1011 0111 0111 1111  *
	30	L0612 1110 1111 1111 1111 1111 1111 1111 1111 0111  *
	31	L0648 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	32	L0684 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	33	L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	34	L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	35	L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	36	L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	37
	38	N Output Pin 16  *
	39	L0864 0111 0111 0111 0111 1011 0111 0111 0111 1111  *
	40	L0900 1110 1111 1111 1111 1111 1111 1111 1111 1011  *
	41	L0936 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	42	L0972 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	43	L1008 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	44	L1044 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	45	L1080 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	46	L1116 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	47
	48	N Output Pin 15  *
	49	L1152 0111 0111 0111 1011 0111 0111 0111 0111 1111  *
	50	L1188 1110 1111 1111 1111 1111 1111 1111 1111 1011  *
	51	L1224 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	52	L1260 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	53	L1296 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	54	L1332 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	55	L1368 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	56	L1404 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	57
	58	N Output Pin 14  *
	59	L1440 0111 0111 1011 0111 0111 0111 0111 0111 1111  *
	60	L1476 1110 1111 1111 1111 1111 1111 1111 1111 0111  *
	61	L1512 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	62	L1548 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	63	L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	64	L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	65	L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	66	L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	67
	68	N Output Pin 13  *
	69	L1728 0111 1011 0111 0111 0111 0111 0111 0111 1111  *
	70	L1764 1101 1111 1111 1111 1111 1111 1111 1111 1011  *
	71	L1800 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	72	L1836 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	73	L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	74	L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	75	L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	76	L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	77
	78	N Output Pin 12  *
	79	L2016 1011 0111 0111 0111 0111 0111 0111 0111 1111  *
	80	L2052 1101 1111 1111 1111 1111 1111 1111 1111 0111  *
	81	L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	82	L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	83	L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	84	L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	85	L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	86	L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	87
	88	N Output Enable 19,18,...12  *
	89	L2304 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	90	L2340 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	91	L2376 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	92	L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	93	L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	94	L2484 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	95	L2520 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	96	L2556 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	97
	98	N Sync Preset, Async Clear, Macrocell 19,18,...12  *
	99	L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	100	L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	101	L2664 0011 0011 0011 0011 0011 0011 0011 0011  *
	102
	103	C68B0 *
	104	0000

Property changes on: trunk/src/regtests/jedutil/jeds/18cv8/pal10h8-to-peel18cv8.jed

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/jeds/18cv8/pal12l6-to-peel18cv8.jed

r0	r19305
	1	
	2	JEDEC PEEL file Translated from: PAL12L6     Mon 10-8-2012  22:40:14
	3	PA
	4	*QP20
	5	*QF2696
	6	*F0
	7	*
	8	N Output Pin 19  *
	9	L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	10	L0036 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	11	L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	12	L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	13	L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	14	L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	15	L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	16	L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	17
	18	N Output Pin 18  *
	19	L0288 0111 0111 0111 0111 0111 1011 0111 0111 1111  *
	20	L0324 1101 1111 1111 1111 1111 1111 1111 1111 1011  *
	21	L0360 1111 1101 1111 1111 1111 1111 1111 1111 1111  *
	22	L0396 1111 1111 1111 1111 1111 1111 1111 1111 1110  *
	23	L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	24	L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	25	L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	26	L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	27
	28	N Output Pin 17  *
	29	L0576 0111 0111 0111 0111 1011 0111 0111 0111 1111  *
	30	L0612 1110 1111 1111 1111 1111 1111 1111 1111 1011  *
	31	L0648 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	32	L0684 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	33	L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	34	L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	35	L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	36	L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	37
	38	N Output Pin 16  *
	39	L0864 0111 0111 0111 1011 0111 0111 0111 0111 1111  *
	40	L0900 1110 1111 1111 1111 1111 1111 1111 1111 1011  *
	41	L0936 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	42	L0972 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	43	L1008 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	44	L1044 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	45	L1080 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	46	L1116 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	47
	48	N Output Pin 15  *
	49	L1152 0111 0111 1011 0111 0111 0111 0111 0111 1111  *
	50	L1188 1101 1111 1111 1111 1111 1111 1111 1111 0111  *
	51	L1224 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	52	L1260 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	53	L1296 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	54	L1332 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	55	L1368 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	56	L1404 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	57
	58	N Output Pin 14  *
	59	L1440 0111 1011 0111 0111 0111 0111 0111 0111 1111  *
	60	L1476 1101 1111 1111 1111 1111 1111 1111 1111 1011  *
	61	L1512 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	62	L1548 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	63	L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	64	L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	65	L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	66	L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	67
	68	N Output Pin 13  *
	69	L1728 1011 0111 0111 0111 0111 0111 0111 0111 1111  *
	70	L1764 1101 1111 1111 1111 1111 1111 1111 1111 0111  *
	71	L1800 1111 1110 1111 1111 1111 1111 1111 1111 1111  *
	72	L1836 1111 1111 1111 1111 1111 1111 1111 1111 1101  *
	73	L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	74	L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	75	L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	76	L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	77
	78	N Output Pin 12  *
	79	L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	80	L2052 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	81	L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	82	L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	83	L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	84	L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	85	L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	86	L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	87
	88	N Output Enable 19,18,...12  *
	89	L2304 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	90	L2340 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	91	L2376 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	92	L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	93	L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	94	L2484 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	95	L2520 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	96	L2556 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	97
	98	N Sync Preset, Async Clear, Macrocell 19,18,...12  *
	99	L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	100	L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	101	L2664 1011 1011 1011 1011 1011 1011 1011 1011  *
	102
	103	C6026 *
	104	0000

Property changes on: trunk/src/regtests/jedutil/jeds/18cv8/pal12l6-to-peel18cv8.jed

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/jeds/18cv8/pal14l4-to-peel18cv8.jed

r0	r19305
	1	
	2	JEDEC PEEL file Translated from: PAL14L4     Mon 10-8-2012  22:41:22
	3	PA
	4	*QP20
	5	*QF2696
	6	*F0
	7	*
	8	N Output Pin 19  *
	9	L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	10	L0036 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	11	L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	12	L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	13	L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	14	L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	15	L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	16	L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	17
	18	N Output Pin 18  *
	19	L0288 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	20	L0324 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	21	L0360 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	22	L0396 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	23	L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	24	L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	25	L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	26	L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	27
	28	N Output Pin 17  *
	29	L0576 0111 0111 0111 0111 0111 1011 0111 0111 1111  *
	30	L0612 1101 1111 1111 1111 1111 1111 1111 1111 1011  *
	31	L0648 1111 1111 1111 1111 1111 1111 1111 1110 1110  *
	32	L0684 1111 1110 1110 1111 1111 1111 1111 1111 1111  *
	33	L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	34	L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	35	L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	36	L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	37
	38	N Output Pin 16  *
	39	L0864 0111 0111 0111 0111 1011 0111 0111 0111 1111  *
	40	L0900 1110 1111 1111 1111 1111 1111 1111 1111 1011  *
	41	L0936 1111 1111 1111 1111 1111 1111 1111 1101 1101  *
	42	L0972 1111 1110 1101 1111 1111 1111 1111 1111 1111  *
	43	L1008 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	44	L1044 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	45	L1080 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	46	L1116 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	47
	48	N Output Pin 15  *
	49	L1152 0111 0111 0111 1011 0111 0111 0111 0111 1111  *
	50	L1188 1110 1111 1111 1111 1111 1111 1111 1111 1011  *
	51	L1224 1111 1111 1111 1111 1111 1111 1111 1101 1110  *
	52	L1260 1111 1101 1110 1111 1111 1111 1111 1111 1111  *
	53	L1296 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	54	L1332 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	55	L1368 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	56	L1404 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	57
	58	N Output Pin 14  *
	59	L1440 0111 1011 0111 0111 0111 0111 0111 0111 1111  *
	60	L1476 1101 1111 1111 1111 1111 1111 1111 1111 1011  *
	61	L1512 1111 1111 1111 1111 1111 1111 1111 1110 1101  *
	62	L1548 1111 1101 1101 1111 1111 1111 1111 1111 1111  *
	63	L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	64	L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	65	L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	66	L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	67
	68	N Output Pin 13  *
	69	L1728 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	70	L1764 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	71	L1800 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	72	L1836 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	73	L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	74	L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	75	L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	76	L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	77
	78	N Output Pin 12  *
	79	L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	80	L2052 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	81	L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	82	L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	83	L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	84	L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	85	L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	86	L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	87
	88	N Output Enable 19,18,...12  *
	89	L2304 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	90	L2340 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	91	L2376 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	92	L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	93	L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	94	L2484 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	95	L2520 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	96	L2556 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	97
	98	N Sync Preset, Async Clear, Macrocell 19,18,...12  *
	99	L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	100	L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	101	L2664 1011 1011 1011 1011 1011 1011 1011 1011  *
	102
	103	C56A9 *
	104	0000

Property changes on: trunk/src/regtests/jedutil/jeds/18cv8/pal14l4-to-peel18cv8.jed

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trunk/src/regtests/jedutil/jeds/18cv8/pal16l2-to-peel18cv8.jed

r0	r19305
	1	
	2	JEDEC PEEL file Translated from: PAL16L2     Mon 10-8-2012  22:42:40
	3	PA
	4	*QP20
	5	*QF2696
	6	*F0
	7	*
	8	N Output Pin 19  *
	9	L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	10	L0036 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	11	L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	12	L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	13	L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	14	L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	15	L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	16	L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	17
	18	N Output Pin 18  *
	19	L0288 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	20	L0324 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	21	L0360 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	22	L0396 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	23	L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	24	L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	25	L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	26	L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	27
	28	N Output Pin 17  *
	29	L0576 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	30	L0612 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	31	L0648 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	32	L0684 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	33	L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	34	L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	35	L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	36	L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	37
	38	N Output Pin 16  *
	39	L0864 0111 0111 0111 0111 0111 0111 1011 0111 1111  *
	40	L0900 1111 1111 1111 1111 1111 1111 1111 1111 0111  *
	41	L0936 1101 1111 1111 1111 1111 1111 1111 1111 1111  *
	42	L0972 1111 1111 1111 1111 1111 1111 1111 1111 1101  *
	43	L1008 1111 1111 1111 1111 1111 1111 1111 1110 1111  *
	44	L1044 1111 1111 1111 1111 1111 1111 1110 1111 1111  *
	45	L1080 1111 1111 1111 1110 1111 1111 1111 1111 1111  *
	46	L1116 1111 1110 1110 1111 1111 1111 1111 1111 1111  *
	47
	48	N Output Pin 15  *
	49	L1152 0111 0111 0111 1011 0111 0111 0111 0111 1111  *
	50	L1188 1111 1111 1111 1111 1111 1111 1111 1111 1011  *
	51	L1224 1110 1111 1111 1111 1111 1111 1111 1111 1111  *
	52	L1260 1111 1111 1111 1111 1111 1111 1111 1111 1110  *
	53	L1296 1111 1111 1111 1111 1111 1111 1111 1101 1111  *
	54	L1332 1111 1111 1111 1111 1111 1111 1101 1111 1111  *
	55	L1368 1111 1111 1111 1101 1111 1111 1111 1111 1111  *
	56	L1404 1111 1101 1101 1111 1111 1111 1111 1111 1111  *
	57
	58	N Output Pin 14  *
	59	L1440 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	60	L1476 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	61	L1512 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	62	L1548 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	63	L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	64	L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	65	L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	66	L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	67
	68	N Output Pin 13  *
	69	L1728 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	70	L1764 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	71	L1800 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	72	L1836 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	73	L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	74	L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	75	L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	76	L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	77
	78	N Output Pin 12  *
	79	L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	80	L2052 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	81	L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	82	L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	83	L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	84	L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	85	L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	86	L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	87
	88	N Output Enable 19,18,...12  *
	89	L2304 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	90	L2340 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	91	L2376 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	92	L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	93	L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111  *
	94	L2484 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	95	L2520 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	96	L2556 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	97
	98	N Sync Preset, Async Clear, Macrocell 19,18,...12  *
	99	L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	100	L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000  *
	101	L2664 1011 1011 1011 1011 1011 1011 1011 1011  *
	102
	103	C4F82 *
	104	0000

Property changes on: trunk/src/regtests/jedutil/jeds/18cv8/pal16l2-to-peel18cv8.jed

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trunk/src/regtests/jedutil/jeds/18cv8/18cv8_combinatorial_feedback.jed

r0	r19305
	1	JEDEC PLD file 18CV8_~1.JED created on   Sun 11-25-2012  21:36:51
	2	Place Compile Version: 3.0.0
	3	PEEL18CV8 Combinatorial Feedback Test Data
	4	*QP20
	5	*QF2696
	6	*F0
	7	*
	8	N Output Pin 19*
	9	L0000 1111 1111 1110 1110 1101 1111 1111 1110 1111 *
	10	L0036 1110 1111 1111 1111 1111 1101 1111 1111 1011 *
	11	L0072 1111 1111 1111 1111 1111 1110 1011 0101 1111 *
	12	L0108 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	13	L0144 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	14	L0180 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	15	L0216 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	16	L0252 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	17
	18	N Output Pin 18*
	19	L0288 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	20	L0324 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	21	L0360 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	22	L0396 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	23	L0432 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	24	L0468 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	25	L0504 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	26	L0540 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	27
	28	N Output Pin 17*
	29	L0576 1111 1101 1111 1111 1111 1111 1111 1111 1111 *
	30	L0612 1111 1110 1111 1111 1101 1101 1111 1101 1111 *
	31	L0648 1111 1111 1111 1111 1111 1110 1111 1110 1111 *
	32	L0684 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	33	L0720 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	34	L0756 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	35	L0792 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	36	L0828 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	37
	38	N Output Pin 16*
	39	L0864 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	40	L0900 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	41	L0936 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	42	L0972 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	43	L1008 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	44	L1044 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	45	L1080 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	46	L1116 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	47
	48	N Output Pin 15*
	49	L1152 1111 1110 1111 1101 1111 1111 1111 1111 1111 *
	50	L1188 1111 1101 1111 1111 1111 1111 1111 1111 1111 *
	51	L1224 1101 1111 1111 1110 1111 1111 1111 1110 1110 *
	52	L1260 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	53	L1296 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	54	L1332 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	55	L1368 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	56	L1404 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	57
	58	N Output Pin 14*
	59	L1440 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	60	L1476 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	61	L1512 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	62	L1548 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	63	L1584 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	64	L1620 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	65	L1656 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	66	L1692 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	67
	68	N Output Pin 13*
	69	L1728 1111 1111 1011 1011 1011 0111 1111 1111 1111 *
	70	L1764 0111 1010 1111 1111 1111 1111 1111 1111 1111 *
	71	L1800 1111 1101 1111 1110 1111 1111 1111 1111 1111 *
	72	L1836 1111 1111 1111 1111 1111 1101 1101 1111 1111 *
	73	L1872 1111 1111 1111 1111 1111 1110 1111 1111 1101 *
	74	L1908 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	75	L1944 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	76	L1980 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	77
	78	N Output Pin 12*
	79	L2016 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	80	L2052 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	81	L2088 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	82	L2124 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	83	L2160 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	84	L2196 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	85	L2232 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	86	L2268 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	87
	88	N Output Enable 19,18,...12*
	89	L2304 1111 1111 1111 1101 1111 1111 1111 1111 1111 *
	90	L2340 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	91	L2376 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
	92	L2412 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	93	L2448 1111 1111 1111 1111 1111 1111 1111 1101 1111 *
	94	L2484 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	95	L2520 1111 1111 1111 1101 1111 1111 1111 1111 1111 *
	96	L2556 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	97
	98	N Sync Preset, Async Clear, Macrocell 19,18,...12*
	99	L2592 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	100	L2628 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	101	L2664 1010 1011 0010 1011 0110 0011 1110 0011 *
	102
	103	C2709*
	104	0000

Property changes on: trunk/src/regtests/jedutil/jeds/18cv8/18cv8_combinatorial_feedback.jed

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/jeds/18cv8/18cv8_register_feedback.jed

r0	r19305
	1	JEDEC PLD file 18CV8_~1.JED created on   Mon 11-26-2012  22:21:12
	2	Place Compile Version: 3.0.0
	3	PEEL18CV8 Register Feedback Test Data
	4	*QP20
	5	*QF2696
	6	*F0
	7	*
	8	N Output Pin 19*
	9	L0000 1111 1111 1111 1101 1111 1111 1111 1101 1111 *
	10	L0036 1111 1111 1111 1110 1111 1110 1111 0111 1111 *
	11	L0072 0111 0111 1111 1111 1111 1101 1111 1111 1111 *
	12	L0108 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	13	L0144 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	14	L0180 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	15	L0216 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	16	L0252 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	17
	18	N Output Pin 18*
	19	L0288 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	20	L0324 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	21	L0360 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	22	L0396 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	23	L0432 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	24	L0468 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	25	L0504 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	26	L0540 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	27
	28	N Output Pin 17*
	29	L0576 1111 1111 1111 1111 1111 1111 1111 1101 1111 *
	30	L0612 0111 1111 1111 1111 1101 1101 1111 1110 1111 *
	31	L0648 1111 1101 1111 1111 1111 1110 1111 1111 1111 *
	32	L0684 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	33	L0720 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	34	L0756 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	35	L0792 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	36	L0828 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	37
	38	N Output Pin 16*
	39	L0864 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	40	L0900 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	41	L0936 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	42	L0972 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	43	L1008 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	44	L1044 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	45	L1080 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	46	L1116 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	47
	48	N Output Pin 15*
	49	L1152 1111 1111 1111 1101 1111 1111 1111 1111 1111 *
	50	L1188 1111 1101 1111 1111 1111 1111 1111 1110 1111 *
	51	L1224 1111 1110 1111 1110 1111 1111 1111 1101 1111 *
	52	L1260 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	53	L1296 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	54	L1332 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	55	L1368 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	56	L1404 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	57
	58	N Output Pin 14*
	59	L1440 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	60	L1476 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	61	L1512 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	62	L1548 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	63	L1584 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	64	L1620 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	65	L1656 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	66	L1692 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	67
	68	N Output Pin 13*
	69	L1728 1111 1111 0111 1110 1111 1111 1111 1111 1111 *
	70	L1764 1111 1111 1111 1111 1111 1110 1111 1111 1110 *
	71	L1800 1111 1111 1111 1101 1111 1101 1111 1111 1111 *
	72	L1836 1111 1101 1111 1111 1111 1111 0111 1111 1111 *
	73	L1872 1111 1110 1111 1111 1111 1111 1111 1111 1011 *
	74	L1908 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	75	L1944 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	76	L1980 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	77
	78	N Output Pin 12*
	79	L2016 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	80	L2052 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	81	L2088 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	82	L2124 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	83	L2160 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	84	L2196 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	85	L2232 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	86	L2268 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	87
	88	N Output Enable 19,18,...12*
	89	L2304 1111 1111 1111 1111 1111 1111 1111 1110 1111 *
	90	L2340 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	91	L2376 1111 1110 1111 1111 1111 1111 1111 1111 1111 *
	92	L2412 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	93	L2448 1111 1111 1111 1110 1111 1111 1111 1111 1111 *
	94	L2484 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	95	L2520 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
	96	L2556 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	97
	98	N Sync Preset, Async Clear, Macrocell 19,18,...12*
	99	L2592 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	100	L2628 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
	101	L2664 0100 1011 1000 1011 1100 0011 0000 0011 *
	102
	103	C2808*
	104	0000

Property changes on: trunk/src/regtests/jedutil/jeds/18cv8/18cv8_register_feedback.jed

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/eqns/pal16c1/pal16c1.eqn

r19304	r19305
1		chip 2000 PAL16C1
2
3		i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
4		i12=12 i13=13 i14=14 o15=15 o16=16 i17=17 i18=18 i19=19 VCC=20
5
6		equations
7
8		/o15 = i1 & i2 +
9		i3 & i4 +
10		i5 & i6 +
11		i7 & i8 +
12		i9 & i11 +
13		i12 & i13 +
14		i14 & i17 +
15		i18 & i19 +
16		/i1 & /i2 +
17		/i3 & /i4 +
18		/i5 & /i6 +
19		/i7 & /i8 +
20		/i9 & /i11 +
21		/i12 & /i13 +
22		/i14 & /i17 +
23		/i18 & /i19

trunk/src/regtests/jedutil/eqns/readme.txt

r19304	r19305
1		This files are for use with the utility eqn2jed which is a tool included with Opal Jr.  The tools takes this equation files and automatically creates a jed file.

trunk/src/regtests/jedutil/eqns/pal16h2/pal16h2.eqn

r19304	r19305
1		chip 2000 PAL16H2
2
3		i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
4		i12=12 i13=13 i14=14 o15=15 o16=16 i17=17 i18=18 i19=19 VCC=20
5
6		equations
7
8		o15 = i1 & i2 & i3 & /i4 & i5 & /i6 & i7 & i8 +
9		i9 +
10		/i11 +
11		i12 +
12		/i13 +
13		i14 +
14		/i17 +
15		i18 & /i19
16
17		o16 = i1 & i2 & /i3 & i4 & /i5 & i6 & i7 & i8 +
18		/i9 +
19		i11 +
20		/i12 +
21		i13 +
22		/i14 +
23		i17 +
24		/i18 & i19

trunk/src/regtests/jedutil/eqns/pal14h4/pal14h4.eqn

r19304	r19305
1		chip 2000 PAL14H4
2
3		i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
4		i12=12 i13=13 o14=14 o15=15 o16=16 o17=17 i18=18 i19=19 VCC=20
5
6		equations
7
8		o14 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
9		i9 & i11 +
10		/i12 & /i13 +
11		i18 & /i19
12
13		o15 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
14		i9 & /i11 +
15		i12 & i13 +
16		/i18 & i19
17
18		o16 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
19		/i9 & i11 +
20		i12 & /i13 +
21		/i18 & /i19
22
23		o17 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
24		i9 & i11 +
25		/i12 & i13 +
26		i18 & i19

trunk/src/regtests/jedutil/eqns/pal12h6/pal12h6.eqn

r19304	r19305
1		chip 2000 PAL12H6
2
3		i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
4		i12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 i19=19 VCC=20
5
6		equations
7
8		o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
9		i9 & i11 +
10		/i19 +
11		i12
12
13		o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
14		/i9 & i11
15
16		o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
17		/i9 & /i11
18
19		o16 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
20		i9 & /i11
21
22		o17 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
23		/i9 & /i11
24
25		o18 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
26		/i9 & i11 +
27		i19 +
28		/i12

trunk/src/regtests/jedutil/eqns/pal14l4/pal14l4.eqn

r19304	r19305
1		chip 2000 PAL14L4
2
3		i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
4		i12=12 i13=13 o14=14 o15=15 o16=16 o17=17 i18=18 i19=19 VCC=20
5
6		equations
7
8		/o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
9		/i9 & i11 +
10		i12 & /i13 +
11		i18 & i19
12
13		/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
14		/i9 & /i11 +
15		/i12 & i13 +
16		/i18 & i19
17
18		/o16 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
19		/i9 & /i11 +
20		i12 & i13 +
21		i18 & /i19
22
23		/o17 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
24		/i9 & i11 +
25		/i12 & /i13 +
26		/i18 & /i19

trunk/src/regtests/jedutil/eqns/pal16l2/pal16l2.eqn

r19304	r19305
1		chip 2000 PAL16L2
2
3		i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
4		i12=12 i13=13 i14=14 o15=15 o16=16 i17=17 i18=18 i19=19 VCC=20
5
6		equations
7
8		/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
9		/i9 +
10		/i11 +
11		/i12 +
12		i13 +
13		i14 +
14		i17 +
15		i18 & i19
16
17		/o16 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
18		i9 +
19		i11 +
20		i12 +
21		/i13 +
22		/i14 +
23		/i17 +
24		/i18 & /i19

trunk/src/regtests/jedutil/eqns/pal10l8/pal10l8.eqn

r19304	r19305
1		chip 2000 PAL10L8
2
3		i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
4		o12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 o19=19 VCC=20
5
6		equations
7
8		/o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
9		i9 & i11
10
11		/o13 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
12		/i9 & i11
13
14		/o14 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
15		i9 & /i11
16
17		/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
18		/i9 & /i11
19
20		/o16 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
21		/i9 & /i11
22
23		/o17 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
24		i9 & /i11
25
26		/o18 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
27		i11
28
29		/o19 = i1 & i2 & i3 & i4 & i5 & i6 & i7 & /i8 +
30		/i9

trunk/src/regtests/jedutil/eqns/pal12l6/pal12l6.eqn

r19304	r19305
1		chip 2000 PAL12L6
2
3		i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
4		i12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 i19=19 VCC=20
5
6		equations
7
8		/o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
9		i9 & i11 +
10		/i19 +
11		i12
12
13		/o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
14		/i9 & i11
15
16		/o15 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
17		i9 & i11
18
19		/o16 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
20		/i9 & /i11
21
22		/o17 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
23		/i9 & /i11
24
25		/o18 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
26		/i9 & i11 +
27		i19 +
28		/i12

trunk/src/regtests/jedutil/eqns/pal20l8/pal20l8.eqn

r19304	r19305
1		chip 2000 PAL20L8
2
3		i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 i10=10 i11=11 GND=12
4		i13=13 i14=14 o15=15 o16=16 o17=17 o18=18 o19=19 o20=20 o21=21 o22=22 i23=23 VCC=24
5
6		equations
7
8		/o15 = /i1 & i2 & /i3 & i4 & i11 +
9		/i1 & i2 & /i3 & /i5 & /i13 +
10		/i1 & i2 & /i3 & i6 & i14 +
11		/i1 & i2 & /i3 & /i7 & /i23 +
12		/i1 & i2 & /i3 & i8 & /i11 +
13		/i1 & i2 & /i3 & /i9 & i13 +
14		/o16
15		o15.oe = o16
16
17		/o16 = i1 & /i2 & /o17 +
18		i3 & /i4 +
19		i5 & /i6 +
20		i7 & /i8 +
21		i3 & i9 & o17 +
22		i1 & /i2 & i3 & /i4 & i5 & /i6 & i7 & /i8 & /i9 +
23		/i8 & /i9
24		o16.oe = vcc
25
26		/o17 = /i23 & /o18 +
27		i10 & o18 +
28		i9 +
29		i8 +
30		/i7 +
31		/i6 +
32		i5
33		o17.oe = i4 & i5
34
35		/o18 = i1 & /i2 & i3 & /i4 & /i8 & i23 +
36		i1 & i2 & i3 & /i4 & /i5 +
37		/i6 & i7 & i8 & i9 & i10 & /o19 +
38		i11 & i13 & i14 & i23 +
39		/i6 & i7 & i8 & i9 & i10 +
40		i3 & i13 & i14 & i23 +
41		i1 & i2 & i3 & /i4 & /i5 & o19
42		o18.oe = i1 & i10 & i23
43
44		/o19 = i9 & /i10 & i11 & i23 +
45		i9 +
46		/i10 +
47		i11 & o20 +
48		i23 +
49		i2 & /i10 & i23 +
50		i9 & i11
51		o19.oe = i8 & /o20
52
53		/o20 = o21 +
54		/i2 +
55		/i3 +
56		/i4 +
57		/i5 +
58		/i6 +
59		/i7 & /o21
60		o20.oe = vcc
61
62		/o21 = i1 & i8 +
63		/i14 +
64		i1 & /i5 & i8 +
65		i23 +
66		i1 & i8 & /i14 +
67		i13 +
68		i1 & i11
69		o21.oe = i5 & i6
70
71		/o22 = i1 & /i8 +
72		/i8 +
73		i1 +
74		/i10 +
75		/i23 +
76		i8 & /i13 +
77		/i11
78		o22.oe = i3 & /i7

trunk/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_bi-directional_io.psf

r0	r19305
	1	Title 'PEEL18CV8 Test Data'
	2	Designer 'MAMEDev'
	3	Date '10-7-2012'
	4
	5	Description
	6	Determine Bi-directional IO fuses.
	7	End_Desc;
	8
	9	PEEL18CV8
	10
	11	I1 PIN 1
	12	I2 PIN 2
	13	I3 PIN 3
	14	I4 PIN 4
	15	I5 PIN 5
	16	I6 PIN 6
	17	I7 PIN 7
	18	I8 PIN 8
	19	I9 PIN 9
	20	I11 PIN 11
	21
	22	IOC (12 'O12'  POS OUTCOM FEED_PIN)
	23	IOC (13 'I13'  POS IN     FEED_PIN)
	24	IOC (14 'RF14' POS REG    FEED_PIN)
	25	IOC (15 'I15'  NEG IN     FEED_PIN)
	26	IOC (16 'RF16' NEG REG    FEED_PIN)
	27	IOC (17 'I17'  POS IN     FEED_PIN)
	28	IOC (18 'O18'  NEG OUTCOM FEED_PIN)
	29	IOC (19 'I19'  POS IN     FEED_PIN)
	30
	31
	32	AR NODE 21; " Asynchronous reset
	33	SP NODE 22; " Synchronous reset
	34
	35	Define
	36
	37	EQUATIONS
	38
	39	AR = 0;
	40	SP = 0;
	41
	42	O12.COM = I1 & /I2 #
	43	I13 & /RF14 & RF16 #
	44	/I3 & /I4 & /I5 & I6 #
	45	I15 & RF14 & /RF16 #
	46	/O18;
	47	O12.OE = O18;
	48
	49	RF14.REG = I11 & /RF14 #
	50	O12 & /RF16 & O18 #
	51	RF16 & /O18;
	52	RF14.OE = /O12;
	53
	54	RF16.REG = I13 & RF16 #
	55	/O12 & /RF14 & /O18 #
	56	O12 & RF14;
	57	RF16.OE = O18;
	58
	59	O18.COM = /I7 & I8 & O12 #
	60	/I9 & /I11 & RF14 #
	61	I19 & /I15 & RF16 #
	62	/O12 #
	63	/RF14 & /RF16;
	64	O18.OE = 1; " output always enabled

Property changes on: trunk/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_bi-directional_io.psf

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_combinatorial_feedback.psf

r0	r19305
	1	Title 'PEEL18CV8 Combinatorial Feedback Test Data'
	2	Designer 'MAMEDev'
	3	Date '11-11-2012'
	4
	5	Description
	6	Determine Combinatorial Feedback fuses.
	7	End_Desc;
	8
	9	PEEL18CV8
	10
	11	I1 PIN 1
	12	I2 PIN 2
	13	I3 PIN 3
	14	I4 PIN 4
	15	I5 PIN 5
	16	I6 PIN 6
	17	I7 PIN 7
	18	I8 PIN 8
	19	I9 PIN 9
	20	I11 PIN 11
	21
	22	IOC (12 'I12'  POS IN  FEED_PIN)
	23	IOC (13 'RF13' NEG REG FEED_OR)
	24	IOC (14 'I14'  POS IN  FEED_PIN)
	25	IOC (15 'RF15' POS REG FEED_OR)
	26	IOC (16 'I16'  NEG IN  FEED_PIN)
	27	IOC (17 'O17'  POS COM FEED_OR)
	28	IOC (18 'I18'  NEG IN  FEED_PIN)
	29	IOC (19 'O19'  NEG COM FEED_OR)
	30
	31
	32	AR NODE 21; " Asynchronous reset
	33	SP NODE 22; " Synchronous reset
	34
	35	Define
	36
	37	EQUATIONS
	38
	39	AR = 0;
	40	SP = 0;
	41
	42	RF13.REG = I1 & /I2 & O19 #
	43	I12 & /RF15 #
	44	/I3 & /I4 & /I5 & I6 #
	45	I14 & RF15 #
	46	/O17 & /O19;
	47	RF13.OE = O17;
	48
	49	RF15.REG = I11 & /I12 & RF13 & /O17 #
	50	/O19 #
	51	O17 & O19;
	52	RF15.OE = /RF13;
	53
	54	O17.COM = /RF13 & RF15 & I16 & O19 #
	55	RF13 & /RF15 #
	56	/O19;
	57	O17.OE = 1;
	58
	59	O19.COM = /I7 & I8 & /RF13 & /RF15 #
	60	/I9 & /I11 & RF15 #
	61	RF13 & I16 & /O17 & /I18;
	62	O19.OE = O17;

Property changes on: trunk/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_combinatorial_feedback.psf

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_register_feedback.psf

r0	r19305
	1	Title 'PEEL18CV8 Register Feedback Test Data'
	2	Designer 'MAMEDev'
	3	Date '11-25-2012'
	4
	5	Description
	6	Determine Register Feedback fuses.
	7	End_Desc;
	8
	9	PEEL18CV8
	10
	11	I1 PIN 1
	12	I2 PIN 2
	13	I3 PIN 3
	14	I4 PIN 4
	15	I5 PIN 5
	16	I6 PIN 6
	17	I7 PIN 7
	18	I8 PIN 8
	19	I9 PIN 9
	20	I11 PIN 11
	21
	22	IOC (12 'I12'  POS IN  FEED_PIN)
	23	IOC (13 'O13'  POS COM FEED_REG)
	24	IOC (14 'I14'  POS IN  FEED_PIN)
	25	IOC (15 'RF15' NEG REG FEED_REG)
	26	IOC (16 'I16'  NEG IN  FEED_PIN)
	27	IOC (17 'O17'  NEG COM FEED_REG)
	28	IOC (18 'I18'  NEG IN  FEED_PIN)
	29	IOC (19 'RF19' POS REG FEED_REG)
	30
	31
	32	AR NODE 21; " Asynchronous reset
	33	SP NODE 22; " Synchronous reset
	34
	35	Define
	36
	37	EQUATIONS
	38
	39	AR = 0;
	40	SP = 0;
	41
	42	O13.COM = I3 & O17 #
	43	/I9 & /RF19 #
	44	I7 & RF19 #
	45	/I12 & RF15 #
	46	/RF15 & /O17;
	47	O13.OE = 1;
	48
	49	RF15.REG = /O13 & RF19 #
	50	/O17 #
	51	O13 & O17 & /RF19;
	52	RF15.OE = O17;
	53
	54	O17.COM = I1 & /O13 & I16 & /RF15 #
	55	RF15 & RF19 #
	56	O13;
	57	O17.OE = /RF19;
	58
	59	RF19.REG = I8 & RF15 & O17 #
	60	I1 & I2 & /RF15 #
	61	O13 & /O17;
	62	RF19.OE = /O13;

Property changes on: trunk/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_register_feedback.psf

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/eqns/ICT_Place/readme.txt

r0	r19305
	1	These files are for use with the utilities place and plcom which are included with ICT Place.  The place tool was used to configure the pins and the plcom tool was used to create the jed files.  (Under Windows 7 64-bit the place tool will not run under the Windows XP VM downloadable for free with Windows 7, but will run under DOSBox.)

Property changes on: trunk/src/regtests/jedutil/eqns/ICT_Place/readme.txt

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/eqns/pal20r4/pal20r4.eqn

r19304	r19305
1		chip pal20r4 PAL20R4
2
3		CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 i10=10 i11=11 GND=12
4		/OE=13 i14=14 o15=15 o16=16 rf17=17 rf18=18 rf19=19 rf20=20 o21=21 o22=22 i23=23 VCC=24
5
6		equations
7
8		/o15 = i2 & i6 & i7 +
9		i6 & o16 +
10		i3 & /o16 +
11		i7 +
12		/i4 +
13		i6 & i7 +
14		i4 & i7
15		o15.oe = /i23
16
17		/o16 = /i3 & /rf17 +
18		/i4 +
19		/i3 +
20		/i3 & i4 +
21		/i7 & rf17 +
22		/i7 +
23		i4
24		o16.oe = i23
25
26		/rf17 := /i2 +
27		/rf18 +
28		i5 +
29		i6 +
30		rf18 +
31		i4 +
32		/i10 +
33		/i23
34		rf17.oe = OE
35
36		/rf18 := /i2 & i5 & i6 & /i7 +
37		i3 & i6 & i7 +
38		i3 & rf19 +
39		/i2 & /i7 +
40		/i3 & /rf19 +
41		i5 & i6 & /i7 +
42		i7 +
43		/i11
44		rf18.oe = OE
45
46		/rf19 := i5 & i6 & /i7 +
47		i3 & i6 & i7 +
48		i5 & rf20 +
49		i6 +
50		i7 +
51		/i4 & /rf20 +
52		/i7 +
53		i10
54		rf19.oe = OE
55
56		/rf20 := i10 & rf17 +
57		/i11 +
58		i4 & /rf17 +
59		i2 +
60		/i6 & /i7 +
61		i8 +
62		/i9 +
63		o22
64		rf20.oe = OE
65
66		/o21 = /i8 +
67		/i2 & rf17 +
68		i11 +
69		/i10 +
70		o15 +
71		/i14 +
72		/i3
73		o21.oe = i8 & i9 & /o22
74
75		/o22 = i14 +
76		/o15 +
77		i3 & /o21 +
78		i7 +
79		/i8 & o21 +
80		i10 +
81		/i9
82		o22.oe = i14 & /o15
		No newline at end of file

trunk/src/regtests/jedutil/eqns/pal20r6/pal20r6.eqn

r19304	r19305
1		chip pal20r6 PAL20R6
2
3		CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 i10=10 i11=11 GND=12
4		/OE=13 i14=14 o15=15 rf16=16 rf17=17 rf18=18 rf19=19 rf20=20 rf21=21 o22=22 i23=23 VCC=24
5
6		equations
7
8		/o15 = i2 & i6 & i7 +
9		i6 & rf16 +
10		i3 & /rf16 +
11		i7 +
12		/i4 +
13		i6 & i7 +
14		i4 & i7
15		o15.oe = /i23
16
17		/rf16 := /i3 & /rf17 +
18		/i4 & /i23 +
19		/i3 +
20		/i3 & i4 +
21		/i7 & rf17 +
22		/i7 +
23		i4 +
24		i23
25		rf16.oe = OE
26
27		/rf17 := /i2 +
28		/rf18 +
29		i5 +
30		i6 +
31		rf18 +
32		i4 +
33		/i10 +
34		/i23
35		rf17.oe = OE
36
37		/rf18 := /i2 & i5 & i6 & /i7 +
38		i3 & i6 & i7 +
39		i3 & rf19 +
40		/i2 & /i7 +
41		/i3 & /rf19 +
42		i5 & i6 & /i7 +
43		i7 +
44		/i11
45		rf18.oe = OE
46
47		/rf19 := i5 & i6 & /i7 +
48		i3 & i6 & i7 +
49		i5 & rf20 +
50		i6 +
51		i7 +
52		/i4 & /rf20 +
53		/i7 +
54		i10
55		rf19.oe = OE
56
57		/rf20 := i10 & rf17 +
58		/i11 +
59		i4 & /rf17 +
60		i2 +
61		/i6 & /i7 +
62		i8 +
63		/i9 +
64		o22
65		rf20.oe = OE
66
67		/rf21 := /i8 +
68		/i2 & rf17 +
69		i11 +
70		/i10 +
71		o15 +
72		/i14 & /o22 +
73		/i3 +
74		/i5
75		rf21.oe = OE
76
77		/o22 = i14 +
78		/o15 +
79		i3 & /rf21 +
80		i7 +
81		/i8 & rf21 +
82		i10 +
83		/i9
84		o22.oe = i14 & /o15
		No newline at end of file

trunk/src/regtests/jedutil/eqns/Opal_Jr/readme.txt

r0	r19305
	1	This files are for use with the utility eqn2jed which is a tool included with Opal Jr.  The tools takes this equation files and automatically creates a jed file.

Property changes on: trunk/src/regtests/jedutil/eqns/Opal_Jr/readme.txt

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/regtests/jedutil/eqns/pal16l8/pal16l8.eqn

r19304	r19305
1		md
2		chip 2000 PAL16L8
3
4		i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10
5		i11=11 o12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 o19=19 VCC=20
6
7		equations
8
9		/o12 = i3 & i7 & /i9 +
10		i1 & o13 +
11		i3 +
12		/i6 +
13		i8 +
14		/i9 +
15		i7 & /o13
16		o12.oe = vcc
17
18		/o13 = i11 & /o14 +
19		/i9 +
20		i8 +
21		/i7 +
22		/i6 & o14 +
23		i5 +
24		i4
25		o13.oe = i2 & o14
26
27		/o14 = i1 & /o15 +
28		/i8 +
29		i1 & /i8 +
30		i1 & /i2 & /o15 +
31		/i2 +
32		i2 & /i8 & o15 +
33		i3
34		o14.oe = vcc
35
36		/o15 = i3 & i6 & i7 & /i11 +
37		i6 & o16 +
38		i3 & /o16 +
39		i7 +
40		/i11 +
41		i6 & i7 +
42		i7 & /i11
43		o15.oe = vcc
44
45		/o16 = /i3 & /o17 +
46		/i4 & /i11 +
47		/i4 & /i3 +
48		/i3 & i4 +
49		/i7 & o17 +
50		/i7 & /i11 +
51		i4
52		o16.oe = vcc
53
54		/o17 = i2 & i5 & i6 & /i7 +
55		i2 & /o18 +
56		i5 +
57		i6 +
58		/i7 & o18 +
59		i2 & /i7 +
60		i5 & i6
61		o17.oe = /o16
62
63		/o18 = /i2 & i5 & i6 & /i7 +
64		i3 & i6 & i7 & i11 +
65		i3 +
66		/i2 & /i7 +
67		i3 & i11 +
68		i5 & i6 & /i7 +
69		i7 & i11
70		o18.oe = vcc
71
72		/o19 = i5 & i6 & /i7 & i11 +
73		i3 & i6 & i7 +
74		i5 +
75		i6 +
76		i7 +
77		i11 +
78		/i7
79		o19.oe = vcc

trunk/src/regtests/jedutil/eqns/pal20r8/pal20r8.eqn

r19304	r19305
1		chip pal20r8 PAL20R8
2
3		CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 i10=10 i11=11 GND=12
4		/OE=13 i14=14 rf15=15 rf16=16 rf17=17 rf18=18 rf19=19 rf20=20 rf21=21 rf22=22 i23=23 VCC=24
5
6		equations
7
8		/rf15 := i2 & i6 & i7 +
9		i6 & rf16 +
10		i3 & /rf16 +
11		i7 +
12		/i4 +
13		i6 & i7 +
14		i4 & i7 +
15		/i23
16		rf15.oe = OE
17
18		/rf16 := /i3 & /rf17 +
19		/i4 +
20		/i3 +
21		/i3 & i4 +
22		/i7 & rf17 +
23		/i7 +
24		i4 +
25		i23
26		rf16.oe = OE
27
28		/rf17 := /i2 +
29		/rf18 +
30		i5 +
31		i6 +
32		rf18 +
33		i4 +
34		/i10 +
35		/i23
36		rf17.oe = OE
37
38		/rf18 := /i2 & i5 & i6 & /i7 +
39		i3 & i6 & i7 +
40		i3 & rf19 +
41		/i2 & /i7 +
42		/i3 & /rf19 +
43		i5 & i6 & /i7 +
44		i7 +
45		/i11
46		rf18.oe = OE
47
48		/rf19 := i5 & i6 & /i7 +
49		i3 & i6 & i7 +
50		i5 & rf20 +
51		i6 +
52		i7 +
53		/i4 & /rf20 +
54		/i7 +
55		i10
56		rf19.oe = OE
57
58		/rf20 := i10 & rf17 +
59		/i11 +
60		i4 & /rf17 +
61		i2 +
62		/i6 & /i7 +
63		i8 +
64		/i9 +
65		rf22
66		rf20.oe = OE
67
68		/rf21 := /i8 +
69		/i2 & rf17 +
70		i11 +
71		/i10 +
72		rf15 +
73		/i14 +
74		/i3 +
75		i8 & i9 & /rf22
76		rf21.oe = OE
77
78		/rf22 := i14 +
79		/rf15 +
80		i3 & /rf21 +
81		i7 +
82		/i8 & rf21 +
83		i10 +
84		/i9 +
85		i14 & /rf15
86		rf22.oe = OE
		No newline at end of file

trunk/src/regtests/jedutil/eqns/pal16r4/pal16r4.eqn

r19304	r19305
1		chip pal16r4 PAL16R4
2
3		CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10
4		/OE=11 o12=12 o13=13 rf14=14 rf15=15 rf16=16 rf17=17 o18=18 o19=19 VCC=20
5
6		equations
7
8		/o12 = /i2 & /i3 +
9		i4 & o13 +
10		i3 +
11		/i6 +
12		i8 +
13		/i9 +
14		i7 & /o13
15		o12.oe = rf14
16
17		/o13 = /rf14 +
18		/i9 +
19		i8 +
20		/i7 +
21		/i6 & /rf14 +
22		i5 +
23		i4
24		o13.oe = i2 & rf14
25
26		/rf14 := /rf15 +
27		/i8 +
28		i8 +
29		/i2 & /rf15 +
30		/i2 +
31		i2 & /i8 & rf15 +
32		/i4 +
33		i3
34		rf14.oe = OE
35
36		/rf15 := i3 & i6 & i7 +
37		i6 & rf16 +
38		i3 & /rf16 +
39		i7 +
40		/i4 +
41		i6 & i7 +
42		i4 & i7 +
43		/i2 & /i7
44		rf15.oe = OE
45
46		/rf16 := /i3 & /rf17 +
47		/i4 +
48		/i3 & /i3 +
49		/i3 & i4 +
50		/i7 & rf17 +
51		/i7 +
52		i4 +
53		i2 & i3
54		rf16.oe = OE
55
56		/rf17 := i2 & i5 & i6 & /i7 +
57		i2 & /o18 +
58		i5 +
59		i6 +
60		/i7 & o18 +
61		i2 & /i7 +
62		i5 & i6 +
63		/i3
64		rf17.oe = OE
65
66		/o18 = /i2 & i5 & i6 & /i7 +
67		i3 & i6 & i7 +
68		i3 +
69		/i2 & /i7 +
70		/i3 +
71		i5 & i6 & /i7 +
72		i7
73		o18.oe = vcc
74
75		/o19 = i5 & i6 & /i7 +
76		i3 & i6 & i7 +
77		i5 +
78		i6 +
79		i7 +
80		/i4 +
81		/i7
82		o19.oe = vcc

trunk/src/regtests/jedutil/eqns/pal16r6/pal16r6.eqn

r19304	r19305
1		chip pal16r6 PAL16R6
2
3		CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10
4		/OE=11 o12=12 rf13=13 rf14=14 rf15=15 rf16=16 rf17=17 rf18=18 o19=19 VCC=20
5
6		equations
7
8		/o12 = /i2 & /i3 +
9		i4 & rf13 +
10		i3 +
11		/i6 +
12		i8 +
13		/i9 +
14		i7 & /rf13
15		o12.oe = rf14
16
17		/rf13 := /rf14 +
18		/i9 +
19		i8 +
20		/i7 +
21		/i6 & /rf14 +
22		i5 & rf14 +
23		i4 +
24		/i2
25		rf13.oe = OE
26
27		/rf14 := /rf15 +
28		/i8 +
29		i8 +
30		/i2 & /rf15 +
31		/i2 +
32		i2 & /i8 & rf15 +
33		/i4 +
34		i3
35		rf14.oe = OE
36
37		/rf15 := i3 & i6 & i7 +
38		i6 & rf16 +
39		i3 & /rf16 +
40		i7 +
41		/i4 +
42		i6 & i7 +
43		i4 & i7 +
44		/i2 & /i7
45		rf15.oe = OE
46
47		/rf16 := /i3 & /rf17 +
48		/i4 +
49		/i3 +
50		/i3 & i4 +
51		/i7 & rf17 +
52		/i7 +
53		i4 +
54		i2 & i3
55		rf16.oe = OE
56
57		/rf17 := i2 & i5 & i6 & /i7 +
58		i2 & /rf18 +
59		i5 +
60		i6 +
61		/i7 & rf18 +
62		i2 & /i7 +
63		i5 & i6 +
64		/i3
65		rf17.oe = OE
66
67		/rf18 := /i2 & i5 & i6 & /i7 +
68		i3 & i6 & i7 +
69		i3 +
70		/i2 & /i7 +
71		/i3 +
72		i5 & i6 & /i7 +
73		i7 +
74		i4
75		rf18.oe = OE
76
77		/o19 = i5 & i6 & /i7 +
78		i3 & i6 & i7 +
79		i5 +
80		i6 +
81		i7 +
82		/i4 +
83		/i7
84		o19.oe = vcc

trunk/src/regtests/jedutil/eqns/pal20l10/pal20l10.eqn

r19304	r19305
1		chip 2000 PAL20L10
2
3		i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 i10=10 i11=11 GND=12
4		i13=13 o14=14 o15=15 o16=16 o17=17 o18=18 o19=19 o20=20 o21=21 o22=22 o23=23 VCC=24
5
6		equations
7
8		/o14 = /i11 +
9		i10 +
10		i9 & /o15
11		o14.oe = o15
12
13		/o15 = /i1 & i2 & /i3 & i4 & i11 +
14		/i1 & i2 & /i3 & /i5 & /i13 & o16 +
15		/i1 & i2 & /i3 & i6
16		o15.oe = /o16
17
18		/o16 = i1 & /i2 & /o17 +
19		i3 & /i4 +
20		i3 & i9 & o17
21		o16.oe = vcc
22
23		/o17 = /o18 +
24		i10 & o18 +
25		i9
26		o17.oe = i4 & i5
27
28		/o18 = i1 & /i2 & i3 & /i4 & /i8 +
29		/i6 & i7 & i8 & i9 & i10 & /o19 +
30		i1 & i2 & i3 & /i4 & /i5 & o19
31		o18.oe = i1 & i10
32
33		/o19 = i11 & o20 +
34		i2 & /i10 +
35		i9 & i11
36		o19.oe = i8 & /o20
37
38		/o20 = o21 +
39		/i6 +
40		/i7 & /o21
41		o20.oe = vcc
42
43		/o21 = i1 & i8 +
44		/i4 & /o22 +
45		o22
46		o21.oe = i5 & i6
47
48		/o22 = i1 & /i8 +
49		/i8 +
50		i1
51		o22.oe = i3 & /i7
52
53		/o23 = i7 +
54		i11 +
55		/i13
56		o23.oe = vcc

trunk/src/regtests/jedutil/eqns/pal16r8/pal16r8.eqn

r19304	r19305
1		chip pal16r8 PAL16R8
2
3		CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10
4		/OE=11 rf12=12 rf13=13 rf14=14 rf15=15 rf16=16 rf17=17 rf18=18 rf19=19 VCC=20
5
6		equations
7
8		/rf12 := /i2 & /i3 +
9		i4 & rf13 +
10		i3 +
11		/i6 +
12		i8 +
13		/i9 +
14		i7 & /rf13 +
15		i5
16		rf12.oe = OE
17
18		/rf13 := /rf14 +
19		/i9 +
20		i8 +
21		/i7 +
22		/i6 & rf14 +
23		i5 +
24		i4 +
25		/i3
26		rf13.oe = OE
27
28		/rf14 := /rf15 +
29		/i8 +
30		i8 +
31		/i2 & /rf15 +
32		/i2 +
33		i2 & /i8 & rf15 +
34		/i4 +
35		i3
36		rf14.oe = OE
37
38		/rf15 := i3 & i6 & i7 +
39		i6 & rf16 +
40		i3 & /rf16 +
41		i7 +
42		/i4 +
43		i6 & i7 +
44		i4 & i7 +
45		/i2 & /i7
46		rf15.oe = OE
47
48		/rf16 := /i3 & /rf17 +
49		/i4 +
50		/i3 +
51		/i3 & i4 +
52		/i7 & rf17 +
53		/i7 +
54		i4 +
55		i2 & i3
56		rf16.oe = OE
57
58		/rf17 := i2 & i5 & i6 & /i7 +
59		i2 & /rf18 +
60		i5 +
61		i6 +
62		/i7 & rf18 +
63		i2 & /i7 +
64		i5 & i6 +
65		/i3
66		rf17.oe = OE
67
68		/rf18 := /i2 & i5 & i6 & /i7 +
69		i3 & i6 & i7 +
70		i3 & rf19 +
71		/i2 & /i7 +
72		/i3 & /rf19 +
73		i5 & i6 & /i7 +
74		i7 +
75		/i4
76		rf18.oe = OE
77
78		/rf19 := i5 & i6 & /i7 +
79		i3 & i6 & i7 +
80		i5 & rf12 +
81		i6 +
82		i7 +
83		/i4 & /rf12 +
84		/i7 +
85		i2
86		rf19.oe = OE

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