trunk/src/mess/drivers/ymmu100.c
| r0 | r19259 | |
| 1 | /************************************************************************************* |
| 2 | |
| 3 | Yamaha MU-100 : 32-voice polyphonic/multitimbral General MIDI/GS/XG tone module |
| 4 | Preliminary driver by R. Belmont |
| 5 | |
| 6 | CPU: Hitachi H8S/2655 (HD6432655F), strapped for mode 4 (24-bit address, 16-bit data, no internal ROM) |
| 7 | Sound ASIC: Yamaha XS725A0 |
| 8 | RAM: 1 MSM51008 (1 meg * 1 bit = 128KBytes) |
| 9 | |
| 10 | I/O ports from service manual: |
| 11 | |
| 12 | Port 1: |
| 13 | 0 - LCD data, SW data, LED 1 |
| 14 | 1 - LCD data, SW data, LED 2 |
| 15 | 2 - LCD data, SW data, LED 3 |
| 16 | 3 - LCD data, SW data, LED 4 |
| 17 | 4 - LCD data, SW data, LED 5 |
| 18 | 5 - LCD data, SW strobe data |
| 19 | 6 - LCD data, SW strobe data |
| 20 | 7 - LCD data, SW data, LED 6 |
| 21 | |
| 22 | Port 2: |
| 23 | 0 - (out) LCD control RS |
| 24 | 1 - (out) LCD control R/W |
| 25 | 2 - (out) LCD control E |
| 26 | 3 - (out) LCD contrast A |
| 27 | 4 - (out) LCD contrast B |
| 28 | 5 - (out) LCD contrast C |
| 29 | 6 - (out) 1 MHz clock for serial |
| 30 | 7 - NC |
| 31 | |
| 32 | Port 3: |
| 33 | 4 - (out) A/D gain control 1 |
| 34 | 5 - (out) A/D gain control 2 |
| 35 | |
| 36 | Port 5: |
| 37 | 3 - (out) Reset signal for rotary encoder |
| 38 | |
| 39 | Port 6: |
| 40 | 1 - NC |
| 41 | 2 - (out) PB select (SW1) |
| 42 | 3 - (out) PB select (SW2) |
| 43 | 4 - (out) reset PB |
| 44 | 5 - (out) reset SWP30 (sound chip) |
| 45 | 6 - NC |
| 46 | 7 - (in) Plug detection for A/D input |
| 47 | |
| 48 | Port A: |
| 49 | 5 - (in) Off Line Detection |
| 50 | 6 - (out) Signal for rotary encoder (REB) |
| 51 | 7 - (out) Signal for rotary encoder (REA) |
| 52 | |
| 53 | Port F: |
| 54 | 0 - (out) LED,SW Strobe data latch |
| 55 | 1 - (out) SW data read control |
| 56 | 2 - (out) PB select (SW4) |
| 57 | |
| 58 | Port G: |
| 59 | 0 - (out) PB select (SW3) |
| 60 | |
| 61 | Analog input channels: |
| 62 | 0 - level input R |
| 63 | 2 - level output L |
| 64 | 4 - host SW type switch position |
| 65 | 6 - battery voltage |
| 66 | 7 - model check (GND for MU100) |
| 67 | |
| 68 | **************************************************************************************/ |
| 69 | |
| 70 | #include "emu.h" |
| 71 | #include "cpu/h83002/h8.h" |
| 72 | |
| 73 | static INPUT_PORTS_START( mu100 ) |
| 74 | INPUT_PORTS_END |
| 75 | |
| 76 | class mu100_state : public driver_device |
| 77 | { |
| 78 | public: |
| 79 | mu100_state(const machine_config &mconfig, device_type type, const char *tag) |
| 80 | : driver_device(mconfig, type, tag), |
| 81 | m_maincpu(*this, "maincpu") |
| 82 | { } |
| 83 | |
| 84 | required_device<cpu_device> m_maincpu; |
| 85 | |
| 86 | DECLARE_READ8_MEMBER(adc7_r); |
| 87 | }; |
| 88 | |
| 89 | static ADDRESS_MAP_START( mu100_map, AS_PROGRAM, 16, mu100_state ) |
| 90 | AM_RANGE(0x000000, 0x1fffff) AM_ROM AM_REGION("maincpu", 0) |
| 91 | AM_RANGE(0x200000, 0x21ffff) AM_RAM // 128K work RAM |
| 92 | ADDRESS_MAP_END |
| 93 | |
| 94 | // model detect. pulled to GND (0) on MU100. |
| 95 | READ8_MEMBER(mu100_state::adc7_r) |
| 96 | { |
| 97 | return 0; |
| 98 | } |
| 99 | |
| 100 | static ADDRESS_MAP_START( mu100_iomap, AS_IO, 8, mu100_state ) |
| 101 | AM_RANGE(H8_ADC_7_H, H8_ADC_7_L) AM_READ(adc7_r) |
| 102 | ADDRESS_MAP_END |
| 103 | |
| 104 | static MACHINE_CONFIG_START( mu100, mu100_state ) |
| 105 | MCFG_CPU_ADD( "maincpu", H8S2655, XTAL_16MHz ) |
| 106 | MCFG_CPU_PROGRAM_MAP( mu100_map ) |
| 107 | MCFG_CPU_IO_MAP( mu100_iomap ) |
| 108 | |
| 109 | MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") |
| 110 | MACHINE_CONFIG_END |
| 111 | |
| 112 | ROM_START( mu100 ) |
| 113 | ROM_REGION( 0x200000, "maincpu", 0 ) |
| 114 | ROM_LOAD16_WORD_SWAP( "xu50720.ic11", 0x000000, 0x200000, CRC(1126a8a4) SHA1(e90b8bd9d14297da26ba12f4d9a4f2d22cd7d34a) ) |
| 115 | |
| 116 | ROM_REGION( 0x2800000, "waverom", 0 ) |
| 117 | ROM_LOAD32_WORD( "sx518b0.ic34", 0x000000, 0x400000, CRC(2550d44f) SHA1(fd3cce228c7d389a2fde25c808a5b26080588cba) ) |
| 118 | ROM_LOAD32_WORD( "sx743b0.ic35", 0x000002, 0x400000, CRC(a9109a6c) SHA1(a67bb49378a38a2d809bd717d286e18bc6496db0) ) |
| 119 | ROM_LOAD32_WORD( "xt445a0-828.ic36", 0x800000, 0x1000000, CRC(d4483a43) SHA1(5bfd0762dea8598eda19db20251dac20e31fa02c) ) |
| 120 | ROM_LOAD32_WORD( "xt461a0-829.ic37", 0x800002, 0x1000000, CRC(c5af4501) SHA1(1c88de197c36382311053add8b19a5740802cb78) ) |
| 121 | ROM_END |
| 122 | |
| 123 | CONS( 1997, mu100, 0, 0, mu100, mu100, driver_device, 0, "Yamaha", "MU100", GAME_NOT_WORKING ) |
| 124 | |
trunk/src/mess/drivers/mirage.c
| r19258 | r19259 | |
| 17 | 17 | e800-e803: WD1770 FDC |
| 18 | 18 | ec00-ecef: ES5503 "DOC" sound chip |
| 19 | 19 | f000-ffff: boot ROM |
| 20 | | |
| 21 | | LED patterns |
| 22 | | |
| 23 | | 80 |
| 24 | | _____ |
| 25 | | | | 40 |
| 26 | | 04 | 02 | |
| 27 | | _____ |
| 28 | | | | 20 |
| 29 | | 08 | | |
| 30 | | _____ |
| 31 | | 10 |
| 32 | | 76543210 |
| 33 | | PORT A: 111xyzzz |
| 34 | | |
| 35 | | PA4/PA5 are the "enable" for the two LEDs |
| 36 | | |
| 37 | | 7seg Display Bits |
| 38 | | '0' %11111100 $FC |
| 39 | | '1' %01100000 $60 |
| 40 | | '2' %11011010 $DA |
| 41 | | '3' %11110010 $F2 |
| 42 | | '4' %01100110 $66 |
| 43 | | '5' %10110110 $B6 |
| 44 | | '6' %10111110 $BE |
| 45 | | '7' %11100000 $E0 |
| 46 | | '8' %11111110 $FE |
| 47 | | '9' %11100110 $E6 |
| 48 | | 'A' %11101110 $EE |
| 49 | | 'b' %00111110 $3E |
| 50 | | 'C' %10011100 $9C |
| 51 | | 'd' %01111010 $7A |
| 52 | | 'E' %10011110 $9E |
| 53 | | 'F' %10001110 $8E |
| 54 | | 'L' %00011100 $1C |
| 55 | | 'n' %00101010 $2A |
| 56 | | 'o' %00111010 $3A |
| 57 | | 'P' %11001110 $CE |
| 58 | | 'r' %00001010 $0A |
| 59 | | 'U' %01111100 $7C |
| 60 | | 'c' %00011010 $1A |
| 61 | | 'u' %01111000 $38 |
| 62 | | |
| 20 | |
| 21 | NMI: IRQ from WD1772 |
| 22 | IRQ: DRQ from WD1772 wire-ORed with IRQ from ES5503 wire-ORed with IRQ from VIA6522 |
| 23 | FIRQ: IRQ from 6850 UART |
| 24 | |
| 25 | LED / switch matrix: |
| 26 | |
| 27 | A B C D E F G DP |
| 28 | ROW 0: LOAD UPPER LOAD LOWER SAMPLE UPPER PLAY SEQ LOAD SEQ SAVE SEQ REC SEQ SAMPLE LOWER |
| 29 | ROW 1: 3 6 9 5 8 0 2 Enter |
| 30 | ROW 2: 1 4 7 up arrow PARAM dn arrow VALUE CANCEL |
| 31 | L. AN: SEG A SEG B SEG C SEG D SEG E SEG F SEG G SEG DP (decimal point) |
| 32 | R. AN: SEG A SEG B SEG C SEG D SEG E SEG F SEG G SEG DP |
| 33 | |
| 34 | Column number in VIA port A bits 0-2 is converted to discrete lines by a 74LS145. |
| 35 | Port A bit 3 is right anode, bit 4 is left anode |
| 36 | ROW 0 is read on VIA port A bit 5, ROW 1 in port A bit 6, and ROW 2 in port A bit 7. |
| 37 | |
| 38 | Keyboard models talk to the R6500 through the VIA shifter: CA2 is handshake, CB1 is shift clock, CB2 is shift data. |
| 39 | This is unconnected on the rackmount version. |
| 40 | |
| 63 | 41 | ***************************************************************************/ |
| 64 | 42 | |
| 65 | 43 | |
| r19258 | r19259 | |
| 74 | 52 | #include "formats/ipf_dsk.h" |
| 75 | 53 | #include "sound/es5503.h" |
| 76 | 54 | |
| 55 | #include "mirage.lh" |
| 56 | |
| 77 | 57 | class mirage_state : public driver_device |
| 78 | 58 | { |
| 79 | 59 | public: |
| r19258 | r19259 | |
| 105 | 85 | DECLARE_READ8_MEMBER(mirage_via_read_cb1); |
| 106 | 86 | DECLARE_READ8_MEMBER(mirage_via_read_ca2); |
| 107 | 87 | DECLARE_READ8_MEMBER(mirage_via_read_cb2); |
| 88 | |
| 89 | DECLARE_WRITE_LINE_MEMBER(acia_irq_w); |
| 90 | |
| 91 | UINT8 m_l_segs, m_r_segs; |
| 92 | int m_l_hi, m_r_hi; |
| 108 | 93 | }; |
| 109 | 94 | |
| 110 | 95 | FLOPPY_FORMATS_MEMBER( mirage_state::floppy_formats ) |
| r19258 | r19259 | |
| 115 | 100 | SLOT_INTERFACE( "35dd", FLOPPY_35_DD ) |
| 116 | 101 | SLOT_INTERFACE_END |
| 117 | 102 | |
| 103 | WRITE_LINE_MEMBER(mirage_state::acia_irq_w) |
| 104 | { |
| 105 | m_maincpu->set_input_line(M6809_FIRQ_LINE, state ? CLEAR_LINE : ASSERT_LINE); |
| 106 | } |
| 107 | |
| 118 | 108 | void mirage_state::fdc_intrq_w(bool state) |
| 119 | 109 | { |
| 120 | 110 | m_maincpu->set_input_line(INPUT_LINE_NMI, state); |
| r19258 | r19259 | |
| 122 | 112 | |
| 123 | 113 | void mirage_state::fdc_drq_w(bool state) |
| 124 | 114 | { |
| 125 | | m_maincpu->set_input_line(M6809_FIRQ_LINE, state); |
| 115 | m_maincpu->set_input_line(M6809_IRQ_LINE, state); |
| 126 | 116 | } |
| 127 | 117 | |
| 128 | 118 | static void mirage_doc_irq(device_t *device, int state) |
| 129 | 119 | { |
| 120 | // m_maincpu->set_input_line(M6809_IRQ_LINE, state); |
| 130 | 121 | } |
| 131 | 122 | |
| 132 | 123 | static UINT8 mirage_adc_read(device_t *device) |
| 133 | 124 | { |
| 134 | | return 0x80; |
| 125 | return 0x00; |
| 135 | 126 | } |
| 136 | 127 | |
| 137 | 128 | void mirage_state::video_start() |
| r19258 | r19259 | |
| 163 | 154 | ADDRESS_MAP_END |
| 164 | 155 | |
| 165 | 156 | // port A: front panel |
| 157 | // bits 0-2: column select from 0-7 |
| 158 | // bits 3/4 = right and left LED enable |
| 159 | // bits 5/6/7 keypad rows 0/1/2 return |
| 166 | 160 | WRITE8_MEMBER(mirage_state::mirage_via_write_porta) |
| 167 | 161 | { |
| 168 | | // printf("PORT A: %02x\n", data); |
| 162 | UINT8 seg = data & 7; |
| 163 | static const int segconv[8] = |
| 164 | { |
| 165 | 16, 8, 32, 2, 1, 64, 128, 4 |
| 166 | }; |
| 167 | |
| 168 | // printf("PA: %02x (PC=%x)\n", data, m_maincpu->pc()); |
| 169 | |
| 170 | // left LED selected? |
| 171 | if ((data & 0x10) == 0x10) |
| 172 | { |
| 173 | // if the segment number is lower than last time, we've |
| 174 | // started a new refresh cycle |
| 175 | if ((seg < m_l_hi) || (seg == 0)) |
| 176 | { |
| 177 | m_l_segs = segconv[seg]; |
| 178 | } |
| 179 | else |
| 180 | { |
| 181 | m_l_segs |= segconv[seg]; |
| 182 | } |
| 183 | |
| 184 | m_l_hi = seg; |
| 185 | output_set_digit_value(0, m_l_segs); |
| 186 | // printf("L LED: seg %d (hi %d conv %02x, %02x)\n", seg, m_l_hi, segconv[seg], m_l_segs); |
| 187 | } |
| 188 | // right LED selected? |
| 189 | if ((data & 0x08) == 0x08) |
| 190 | { |
| 191 | // if the segment number is lower than last time, we've |
| 192 | // started a new refresh cycle |
| 193 | if ((seg < m_r_hi) || (seg == 0)) |
| 194 | { |
| 195 | m_r_segs = segconv[seg]; |
| 196 | } |
| 197 | else |
| 198 | { |
| 199 | m_r_segs |= segconv[seg]; |
| 200 | } |
| 201 | |
| 202 | m_r_hi = seg; |
| 203 | output_set_digit_value(1, m_r_segs); |
| 204 | // printf("R LED: seg %d (hi %d conv %02x, %02x)\n", seg, m_r_hi, segconv[seg], m_r_segs); |
| 205 | } |
| 169 | 206 | } |
| 170 | 207 | |
| 171 | 208 | // port B: |
| r19258 | r19259 | |
| 197 | 234 | } |
| 198 | 235 | |
| 199 | 236 | // port B: |
| 200 | | // bit 6: IN FDC disk loaded |
| 237 | // bit 6: IN FDC disk ready |
| 201 | 238 | // bit 5: IN 5503 sync (?) |
| 202 | 239 | READ8_MEMBER(mirage_state::mirage_via_read_portb) |
| 203 | 240 | { |
| r19258 | r19259 | |
| 231 | 268 | |
| 232 | 269 | const via6522_interface mirage_via = |
| 233 | 270 | { |
| 234 | | DEVCB_DRIVER_MEMBER(mirage_state,mirage_via_read_porta), |
| 235 | | DEVCB_DRIVER_MEMBER(mirage_state,mirage_via_read_portb), |
| 236 | | DEVCB_DRIVER_MEMBER(mirage_state,mirage_via_read_ca1), |
| 237 | | DEVCB_DRIVER_MEMBER(mirage_state,mirage_via_read_cb1), |
| 238 | | DEVCB_DRIVER_MEMBER(mirage_state,mirage_via_read_ca2), |
| 239 | | DEVCB_DRIVER_MEMBER(mirage_state,mirage_via_read_cb2), |
| 240 | | DEVCB_DRIVER_MEMBER(mirage_state,mirage_via_write_porta), |
| 241 | | DEVCB_DRIVER_MEMBER(mirage_state,mirage_via_write_portb), |
| 271 | DEVCB_DRIVER_MEMBER(mirage_state, mirage_via_read_porta), |
| 272 | DEVCB_DRIVER_MEMBER(mirage_state, mirage_via_read_portb), |
| 273 | DEVCB_DRIVER_MEMBER(mirage_state, mirage_via_read_ca1), |
| 274 | DEVCB_DRIVER_MEMBER(mirage_state, mirage_via_read_cb1), |
| 275 | DEVCB_DRIVER_MEMBER(mirage_state, mirage_via_read_ca2), |
| 276 | DEVCB_DRIVER_MEMBER(mirage_state, mirage_via_read_cb2), |
| 277 | DEVCB_DRIVER_MEMBER(mirage_state, mirage_via_write_porta), |
| 278 | DEVCB_DRIVER_MEMBER(mirage_state, mirage_via_write_portb), |
| 242 | 279 | DEVCB_NULL, |
| 243 | 280 | DEVCB_NULL, |
| 244 | 281 | DEVCB_NULL, |
| r19258 | r19259 | |
| 255 | 292 | DEVCB_NULL, // cts in |
| 256 | 293 | DEVCB_NULL, // rts out |
| 257 | 294 | DEVCB_NULL, // dcd in |
| 258 | | DEVCB_NULL |
| 259 | | // DEVCB_CPU_INPUT_LINE("maincpu", M6809_FIRQ_LINE) |
| 295 | DEVCB_DRIVER_LINE_MEMBER(mirage_state, acia_irq_w) |
| 260 | 296 | }; |
| 261 | 297 | |
| 262 | 298 | static MACHINE_CONFIG_START( mirage, mirage_state ) |
| 263 | 299 | MCFG_CPU_ADD("maincpu", M6809E, 4000000) |
| 264 | 300 | MCFG_CPU_PROGRAM_MAP(mirage_map) |
| 265 | 301 | |
| 266 | | MCFG_SCREEN_ADD("screen", RASTER) |
| 267 | | MCFG_SCREEN_REFRESH_RATE(60) |
| 268 | | MCFG_SCREEN_UPDATE_DRIVER(mirage_state, screen_update_mirage) |
| 269 | | MCFG_SCREEN_SIZE(320, 240) |
| 270 | | MCFG_SCREEN_VISIBLE_AREA(0, 319, 1, 239) |
| 302 | MCFG_DEFAULT_LAYOUT( layout_mirage ) |
| 271 | 303 | |
| 272 | 304 | MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") |
| 273 | 305 | MCFG_ES5503_ADD("es5503", 7000000, 2, mirage_doc_irq, mirage_adc_read) |
| r19258 | r19259 | |
| 305 | 337 | |
| 306 | 338 | floppy->ss_w(0); |
| 307 | 339 | } |
| 340 | |
| 341 | m_l_hi = m_r_hi = 9; |
| 342 | m_l_segs = m_r_segs = 0; |
| 308 | 343 | } |
| 309 | 344 | |
| 310 | 345 | CONS( 1984, enmirage, 0, 0, mirage, mirage, mirage_state, mirage, "Ensoniq", "Ensoniq Mirage", GAME_NOT_WORKING ) |
| 311 | | |