Previous 199869 Revisions Next

r19234 Friday 30th November, 2012 at 19:35:49 UTC by Angelo Salese
Added FDC DRQ signals for PC-9821
[src/mess/drivers]pc9801.c

trunk/src/mess/drivers/pc9801.c
r19233r19234
260260      : driver_device(mconfig, type, tag),
261261      m_maincpu(*this, "maincpu"),
262262      m_dmac(*this, "i8237"),
263      m_fdc_2hd(*this, "upd765_2hd"),
264      m_fdc_2dd(*this, "upd765_2dd"),
263265      m_rtc(*this, UPD1990A_TAG),
264266      m_sio(*this, UPD8251_TAG),
265267      m_hgdc1(*this, "upd7220_chr"),
r19233r19234
269271
270272   required_device<cpu_device> m_maincpu;
271273   required_device<am9517a_device> m_dmac;
274   required_device<upd765a_device> m_fdc_2hd;
275   optional_device<upd765a_device> m_fdc_2dd;
272276   required_device<upd1990a_device> m_rtc;
273277   required_device<i8251_device> m_sio;
274278   required_device<upd7220_device> m_hgdc1;
r19233r19234
441445   void fdc_2dd_drq(bool state);
442446
443447   void pc9801rs_fdc_irq(bool state);
448   void pc9801rs_fdc_drq(bool state);
444449
445450private:
446451   UINT8 m_sdip_read(UINT16 port, UINT8 sdip_offset);
r19233r19234
484489   DECLARE_WRITE_LINE_MEMBER(fdc_2hd_drq);
485490   DECLARE_WRITE_LINE_MEMBER(fdc_2dd_irq);
486491   DECLARE_WRITE_LINE_MEMBER(fdc_2dd_drq);
487   DECLARE_WRITE_LINE_MEMBER(pc9801rs_fdc_irq);
492//   DECLARE_WRITE_LINE_MEMBER(pc9801rs_fdc_irq);
488493};
489494
490495
r19233r19234
771776   }
772777   else // odd
773778   {
774      printf("Write to DMA bank register %d %02x\n",(offset >> 1) & 3,data);
775      m_dma_offset[(offset >> 1) & 3] = data & 0x0f; // TODO: old was +1? Why?
779      printf("Write to DMA bank register %d %02x\n",((offset >> 1)+1) & 3,data);
780      m_dma_offset[((offset >> 1)+1) & 3] = data & 0x0f;
776781   }
777782}
778783
r19233r19234
16201625
16211626static ADDRESS_MAP_START( pc9801rs_io, AS_IO, 32, pc9801_state )
16221627   AM_RANGE(0x0000, 0x001f) AM_READWRITE8(pc9801_00_r,        pc9801_00_w,        0xffffffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
1623
1628   AM_RANGE(0x0020, 0x0027) AM_READWRITE8(pc9801_20_r,        pc9801_20_w,        0xffffffff) // RTC / DMA registers (LS244)
16241629   AM_RANGE(0x0030, 0x0037) AM_READWRITE8(pc9801rs_30_r,      pc9801_30_w,        0xffffffff) //i8251 RS232c / i8255 system port
16251630   AM_RANGE(0x0040, 0x0047) AM_READWRITE8(pc9801_40_r,        pc9801_40_w,        0xffffffff) //i8255 printer port / i8251 keyboard
16261631   AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r,        pc9801_60_w,        0xffffffff) //upd7220 character ports / <undefined>
r19233r19234
16761681
16771682static ADDRESS_MAP_START( pc9801ux_io, AS_IO, 16, pc9801_state )
16781683   AM_RANGE(0x0000, 0x001f) AM_READWRITE8(pc9801_00_r,        pc9801_00_w,        0xffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
1679
1684   AM_RANGE(0x0020, 0x0027) AM_READWRITE8(pc9801_20_r,        pc9801_20_w,        0xffff) // RTC / DMA registers (LS244)
16801685   AM_RANGE(0x0030, 0x0037) AM_READWRITE8(pc9801rs_30_r,      pc9801_30_w,        0xffff) //i8251 RS232c / i8255 system port
16811686   AM_RANGE(0x0040, 0x0047) AM_READWRITE8(pc9801_40_r,        pc9801_40_w,        0xffff) //i8255 printer port / i8251 keyboard
16821687   AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r,        pc9801_60_w,        0xffff) //upd7220 character ports / <undefined>
r19233r19234
19451950
19461951static ADDRESS_MAP_START( pc9821_io, AS_IO, 32, pc9801_state )
19471952   AM_RANGE(0x0000, 0x001f) AM_READWRITE8(pc9801_00_r,        pc9801_00_w,        0xffffffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
1948
1953   AM_RANGE(0x0020, 0x0027) AM_READWRITE8(pc9801_20_r,        pc9801_20_w,        0xffffffff) // RTC / DMA registers (LS244)
19491954   AM_RANGE(0x0030, 0x0037) AM_READWRITE8(pc9801rs_30_r,      pc9801_30_w,        0xffffffff) //i8251 RS232c / i8255 system port
19501955   AM_RANGE(0x0040, 0x0047) AM_READWRITE8(pc9801_40_r,        pc9801_40_w,        0xffffffff) //i8255 printer port / i8251 keyboard
19511956   AM_RANGE(0x005c, 0x005f) AM_READ(pc9821_timestamp_r) AM_WRITENOP
r19233r19234
24762481WRITE_LINE_MEMBER(pc9801_state::pc9801_tc_w )
24772482{
24782483   /* floppy terminal count */
2479//   m_fdc->tc_w(state);
2484   m_fdc_2hd->tc_w(state);
24802485
24812486//   printf("TC %02x\n",state);
24822487}
r19233r19234
25132518WRITE_LINE_MEMBER(pc9801_state::pc9801_dack2_w){ /*printf("%02x 2\n",state);*/ set_dma_channel(machine(), 2, state); }
25142519WRITE_LINE_MEMBER(pc9801_state::pc9801_dack3_w){ /*printf("%02x 3\n",state);*/ set_dma_channel(machine(), 3, state); }
25152520
2516/* TODO: double check channel for this one */
25172521READ8_MEMBER(pc9801_state::fdc_r)
25182522{
2519   printf("2dd DACK R\n");
2520
2521   return 0xff;
2523   return m_fdc_2hd->dma_r();
25222524}
25232525
25242526WRITE8_MEMBER(pc9801_state::fdc_w)
25252527{
2526   printf("2dd DACK W\n");
2528   m_fdc_2hd->dma_w(data);
25272529}
25282530
2531/* TODO: check channels for this */
25292532static I8237_INTERFACE( dmac_intf )
25302533{
25312534   DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dma_hrq_changed),
r19233r19234
25372540   { DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack0_w), DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack1_w), DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack2_w), DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack3_w) }
25382541};
25392542
2543
2544/*
2545ch1 cs-4231a
2546ch2 FDC
2547ch3 SCSI
2548*/
2549static I8237_INTERFACE( pc9801rs_dmac_intf )
2550{
2551   DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dma_hrq_changed),
2552   DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_tc_w),
2553   DEVCB_DRIVER_MEMBER(pc9801_state, pc9801_dma_read_byte),
2554   DEVCB_DRIVER_MEMBER(pc9801_state, pc9801_dma_write_byte),
2555   { DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(pc9801_state,fdc_r), DEVCB_NULL },
2556   { DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(pc9801_state,fdc_w), DEVCB_NULL },
2557   { DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack0_w), DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack1_w), DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack2_w), DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack3_w) }
2558};
2559
25402560/****************************************
25412561*
25422562* PPI interfaces
r19233r19234
26502670      pic8259_ir2_w(machine().device("pic8259_slave"), state);
26512671}
26522672
2673void pc9801_state::pc9801rs_fdc_drq(bool state)
2674{
2675   if(m_fdc_ctrl & 1)
2676      m_dmac->dreq2_w(state);
2677   else
2678      printf("DRQ %02x %d\n",m_fdc_ctrl,state);
2679}
2680
26532681static UPD1990A_INTERFACE( pc9801_upd1990a_intf )
26542682{
26552683   DEVCB_NULL,
r19233r19234
27362764   upd765a_device *fdc;
27372765   fdc = machine().device<upd765a_device>(":upd765_2hd");
27382766   fdc->setup_intrq_cb(upd765a_device::line_cb(FUNC(pc9801_state::pc9801rs_fdc_irq), this));
2739   fdc->setup_drq_cb(upd765a_device::line_cb(FUNC(pc9801_state::fdc_2hd_drq), this));
2767   fdc->setup_drq_cb(upd765a_device::line_cb(FUNC(pc9801_state::pc9801rs_fdc_drq), this));
27402768}
27412769
27422770MACHINE_START_MEMBER(pc9801_state,pc9821)
r19233r19234
29202948   MCFG_MACHINE_RESET_OVERRIDE(pc9801_state,pc9801rs)
29212949
29222950   MCFG_PIT8253_ADD( "pit8253", pc9801rs_pit8253_config )
2923   MCFG_I8237_ADD("i8237", 16000000, dmac_intf) // unknown clock
2951   MCFG_I8237_ADD("i8237", 16000000, pc9801rs_dmac_intf) // unknown clock
29242952   MCFG_PIC8259_ADD( "pic8259_master", pic8259_master_config )
29252953   MCFG_PIC8259_ADD( "pic8259_slave", pic8259_slave_config )
29262954   MCFG_I8255_ADD( "ppi8255_sys", ppi_system_intf )
r19233r19234
29813009   MCFG_MACHINE_RESET_OVERRIDE(pc9801_state,pc9821)
29823010
29833011   MCFG_PIT8253_ADD( "pit8253", pc9801rs_pit8253_config )
2984   MCFG_I8237_ADD("i8237", 16000000, dmac_intf) // unknown clock
3012   MCFG_I8237_ADD("i8237", 16000000, pc9801rs_dmac_intf) // unknown clock
29853013   MCFG_PIC8259_ADD( "pic8259_master", pic8259_master_config )
29863014   MCFG_PIC8259_ADD( "pic8259_slave", pic8259_slave_config )
29873015   MCFG_I8255_ADD( "ppi8255_sys", ppi_system_intf )

Previous 199869 Revisions Next

© 1997-2024 The MAME Team