trunk/src/mame/machine/archimds.c
| r19200 | r19201 | |
|---|
| 44 | 44 | { |
| 45 | 45 | m_ioc_regs[IRQ_STATUS_A] |= mask; |
| 46 | 46 | |
| 47 | | if (m_ioc_regs[IRQ_MASK_A] & mask) |
| 48 | | { |
| 47 | if (m_ioc_regs[IRQ_STATUS_A] & m_ioc_regs[IRQ_MASK_A]) |
| 49 | 48 | machine().device("maincpu")->execute().set_input_line(ARM_IRQ_LINE, ASSERT_LINE); |
| 50 | | } |
| 49 | |
| 50 | if ((m_ioc_regs[IRQ_STATUS_A] & m_ioc_regs[IRQ_MASK_A]) == 0) |
| 51 | machine().device("maincpu")->execute().set_input_line(ARM_IRQ_LINE, CLEAR_LINE); |
| 52 | |
| 51 | 53 | } |
| 52 | 54 | |
| 53 | 55 | void archimedes_state::archimedes_request_irq_b(int mask) |
| 54 | 56 | { |
| 55 | 57 | m_ioc_regs[IRQ_STATUS_B] |= mask; |
| 56 | 58 | |
| 57 | | if (m_ioc_regs[IRQ_MASK_B] & mask) |
| 59 | if (m_ioc_regs[IRQ_STATUS_B] & m_ioc_regs[IRQ_MASK_B]) |
| 58 | 60 | { |
| 59 | 61 | generic_pulse_irq_line(machine().device("maincpu")->execute(), ARM_IRQ_LINE, 1); |
| 60 | 62 | } |
| r19200 | r19201 | |
|---|
| 64 | 66 | { |
| 65 | 67 | m_ioc_regs[FIQ_STATUS] |= mask; |
| 66 | 68 | |
| 67 | | if (m_ioc_regs[FIQ_MASK] & mask) |
| 69 | if (m_ioc_regs[FIQ_STATUS] & m_ioc_regs[FIQ_MASK]) |
| 68 | 70 | { |
| 69 | 71 | generic_pulse_irq_line(machine().device("maincpu")->execute(), ARM_FIRQ_LINE, 1); |
| 70 | 72 | } |
| r19200 | r19201 | |
|---|
| 78 | 80 | void archimedes_state::archimedes_clear_irq_b(int mask) |
| 79 | 81 | { |
| 80 | 82 | m_ioc_regs[IRQ_STATUS_B] &= ~mask; |
| 83 | archimedes_request_irq_b(0); |
| 81 | 84 | } |
| 82 | 85 | |
| 83 | 86 | void archimedes_state::archimedes_clear_fiq(int mask) |
| 84 | 87 | { |
| 85 | 88 | m_ioc_regs[FIQ_STATUS] &= ~mask; |
| 89 | archimedes_request_fiq(0); |
| 86 | 90 | } |
| 87 | 91 | |
| 88 | 92 | void archimedes_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) |
| r19200 | r19201 | |
|---|
| 533 | 537 | case IRQ_MASK_A: |
| 534 | 538 | m_ioc_regs[IRQ_MASK_A] = data & 0xff; |
| 535 | 539 | |
| 536 | | if(data & 0x80) //force an IRQ |
| 537 | | archimedes_request_irq_a(ARCHIMEDES_IRQA_FORCE); |
| 540 | /* bit 7 forces an IRQ trap */ |
| 541 | archimedes_request_irq_a((data & 0x80) ? ARCHIMEDES_IRQA_FORCE : 0); |
| 538 | 542 | |
| 539 | 543 | if(data & 0x08) //set up the VBLANK timer |
| 540 | 544 | m_vbl_timer->adjust(machine().primary_screen->time_until_pos(m_vidc_regs[0xb4])); |
| 541 | 545 | |
| 542 | 546 | break; |
| 543 | 547 | |
| 548 | case IRQ_MASK_B: |
| 549 | m_ioc_regs[IRQ_MASK_B] = data & 0xff; |
| 550 | |
| 551 | archimedes_request_irq_b(0); |
| 552 | break; |
| 553 | |
| 544 | 554 | case FIQ_MASK: |
| 545 | 555 | m_ioc_regs[FIQ_MASK] = data & 0xff; |
| 546 | 556 | |
| 547 | | if(data & 0x80) //force a FIRQ |
| 548 | | archimedes_request_fiq(ARCHIMEDES_FIQ_FORCE); |
| 549 | | |
| 557 | /* bit 7 forces a FIRQ trap */ |
| 558 | archimedes_request_fiq((data & 0x80) ? ARCHIMEDES_FIQ_FORCE : 0); |
| 550 | 559 | break; |
| 551 | 560 | |
| 552 | 561 | case IRQ_REQUEST_A: // IRQ clear A |
| 553 | 562 | m_ioc_regs[IRQ_STATUS_A] &= ~(data&0xff); |
| 554 | 563 | |
| 555 | | // if that did it, clear the IRQ |
| 556 | | //if (ioc_regs[IRQ_STATUS_A] == 0) |
| 557 | | { |
| 558 | | //printf("IRQ clear A\n"); |
| 559 | | machine().device("maincpu")->execute().set_input_line(ARM_IRQ_LINE, CLEAR_LINE); |
| 560 | | } |
| 564 | // check pending irqs |
| 565 | archimedes_request_irq_a(0); |
| 561 | 566 | break; |
| 562 | 567 | |
| 563 | 568 | case T0_LATCH_LO: |
| r19200 | r19201 | |
|---|
| 929 | 934 | |
| 930 | 935 | case 4: /* sound start */ |
| 931 | 936 | //logerror("MEMC: SNDSTART %08x\n",data); |
| 937 | archimedes_clear_irq_b(ARCHIMEDES_IRQB_SOUND_EMPTY); |
| 932 | 938 | m_vidc_sndstart = 0x2000000 | ((data>>2)&0x7fff)*16; |
| 933 | | m_ioc_regs[IRQ_STATUS_B] &= ~ARCHIMEDES_IRQB_SOUND_EMPTY; |
| 934 | 939 | break; |
| 935 | 940 | |
| 936 | 941 | case 5: /* sound end */ |