Previous

199869 Revisions

Next

r19186 Wednesday 28th November, 2012 at 13:22:44 UTC by O. Galibert
wd_fdc: Change the feature functions into bools, and use the correct pll for each chip [O. Galibert]

[src/emu/machine]

wd_fdc.c wd_fdc.h

trunk/src/emu/machine/wd_fdc.c

r19185	r19186
36	36	#include "debugger.h"
37	37
38	38	const device_type FD1771x = &device_creator<fd1771_t>;
	39	const device_type FD1781x = &device_creator<fd1781_t>;
	40	const device_type FD1791x = &device_creator<fd1791_t>;
	41	const device_type FD1792x = &device_creator<fd1792_t>;
39	42	const device_type FD1793x = &device_creator<fd1793_t>;
	43	const device_type FD1794x = &device_creator<fd1794_t>;
	44	const device_type FD1795x = &device_creator<fd1795_t>;
40	45	const device_type FD1797x = &device_creator<fd1797_t>;
	46	const device_type MB8866x = &device_creator<mb8866_t>;
	47	const device_type MB8876x = &device_creator<mb8876_t>;
	48	const device_type MB8877x = &device_creator<mb8877_t>;
	49	const device_type FD1761x = &device_creator<fd1761_t>;
	50	const device_type FD1763x = &device_creator<fd1763_t>;
	51	const device_type FD1765x = &device_creator<fd1765_t>;
	52	const device_type FD1767x = &device_creator<fd1767_t>;
	53	const device_type WD2791x = &device_creator<wd2791_t>;
41	54	const device_type WD2793x = &device_creator<wd2793_t>;
	55	const device_type WD2795x = &device_creator<wd2795_t>;
42	56	const device_type WD2797x = &device_creator<wd2797_t>;
43	57	const device_type WD1770x = &device_creator<wd1770_t>;
44	58	const device_type WD1772x = &device_creator<wd1772_t>;
r19185	r19186
106	120	floppy = _floppy;
107	121
108	122	if(floppy) {
109		if(has_motor())
	123	if(motor_control)
110	124	floppy->mon_w(status & S_MON ? 0 : 1);
111	125	floppy->setup_index_pulse_cb(floppy_image_device::index_pulse_cb(FUNC(wd_fdc_t::index_callback), this));
112	126	}
r19185	r19186
178	192	{
179	193	main_state = state;
180	194	status = (status & ~(S_CRC|S_RNF|S_SPIN)) | S_BUSY;
181		if(has_head_load()) {
	195	if(head_control) {
182	196	// TODO get value from HLT callback
183		if (command & 8)
	197	if(command & 8)
184	198	status |= S_HLD;
185	199	else
186	200	status &= ~S_HLD;
187	201	}
188		sub_state = has_motor() && !has_head_load() ? SPINUP : SPINUP_DONE;
	202	sub_state = motor_control ? SPINUP : SPINUP_DONE;
189	203	status_type_1 = true;
190	204	seek_continue();
191	205	}
r19185	r19186
259	273
260	274	if(command & 0x04) {
261	275	sub_state = SEEK_WAIT_STABILIZATION_TIME;
262		delay_cycles(t_gen, 120000);
	276	delay_cycles(t_gen, 30000);
263	277	return;
264	278	} else
265	279	sub_state = SEEK_DONE;
r19185	r19186
279	293
280	294	case SEEK_DONE:
281	295	if(command & 0x04) {
282		if(has_ready() && !is_ready()) {
	296	if(!is_ready()) {
283	297	status |= S_RNF;
284	298	command_end();
285	299	return;
r19185	r19186
321	335	{
322	336	if(cur_live.idbuf[0] != track || cur_live.idbuf[2] != sector)
323	337	return false;
324		if(!has_side_check() || (command & 2))
	338	if(!side_compare || (command & 2))
325	339	return true;
326	340	if(command & 8)
327	341	return cur_live.idbuf[1] & 1;
r19185	r19186
331	345
332	346	bool wd_fdc_t::is_ready()
333	347	{
334		return (floppy && !floppy->ready_r());
	348	return !ready_hooked || (floppy && !floppy->ready_r());
335	349	}
336	350
337	351	void wd_fdc_t::read_sector_start()
338	352	{
339		if(has_ready() && !is_ready())
	353	if(!is_ready())
340	354	command_end();
341	355
342	356	main_state = READ_SECTOR;
343	357	status = (status & ~(S_CRC|S_LOST|S_RNF|S_WP|S_DDM)) | S_BUSY;
344	358	drop_drq();
345		if (has_side_select() && floppy)
346		floppy->ss_w(BIT(command, 1));
347		sub_state = has_motor() && !has_head_load() ? SPINUP : SPINUP_DONE;
	359	if(side_control && floppy)
	360	floppy->ss_w(command & 0x02);
	361	sub_state = motor_control ? SPINUP : SPINUP_DONE;
348	362	status_type_1 = false;
349	363	read_sector_continue();
350	364	}
r19185	r19186
426	440
427	441	void wd_fdc_t::read_track_start()
428	442	{
429		if(has_ready() && !is_ready())
	443	if(!is_ready())
430	444	command_end();
431
	445
432	446	main_state = READ_TRACK;
433	447	status = (status & ~(S_LOST|S_RNF)) | S_BUSY;
434	448	drop_drq();
435		if (has_side_select() && floppy)
436		floppy->ss_w(BIT(command, 1));
437		sub_state = has_motor() && !has_head_load()  ? SPINUP : SPINUP_DONE;
	449	if(side_control && floppy)
	450	floppy->ss_w(command & 0x02);
	451	sub_state = motor_control ? SPINUP : SPINUP_DONE;
438	452	status_type_1 = false;
439	453	read_track_continue();
440	454	}
r19185	r19186
493	507
494	508	void wd_fdc_t::read_id_start()
495	509	{
496		if(has_ready() && !is_ready())
	510	if(!is_ready())
497	511	command_end();
498
	512
499	513	main_state = READ_ID;
500	514	status = (status & ~(S_WP|S_DDM|S_LOST|S_RNF)) | S_BUSY;
501	515	drop_drq();
502		if (has_side_select() && floppy)
503		floppy->ss_w(BIT(command, 1));
504		sub_state = has_motor() && !has_head_load()  ? SPINUP : SPINUP_DONE;
	516	if(side_control && floppy)
	517	floppy->ss_w(command & 0x02);
	518	sub_state = motor_control ? SPINUP : SPINUP_DONE;
505	519	status_type_1 = false;
506	520	read_id_continue();
507	521	}
r19185	r19186
558	572
559	573	void wd_fdc_t::write_track_start()
560	574	{
561		if(has_ready() && !is_ready())
	575	if(!is_ready())
562	576	command_end();
563
	577
564	578	main_state = WRITE_TRACK;
565	579	status = (status & ~(S_WP|S_DDM|S_LOST|S_RNF)) | S_BUSY;
566	580	drop_drq();
567		if (has_side_select() && floppy)
568		floppy->ss_w(BIT(command, 1));
569		sub_state = has_motor()  && !has_head_load() ? SPINUP : SPINUP_DONE;
	581	if(side_control && floppy)
	582	floppy->ss_w(command & 0x02);
	583	sub_state = motor_control ? SPINUP : SPINUP_DONE;
570	584	status_type_1 = false;
571	585	write_track_continue();
572	586	}
r19185	r19186
602	616	case SETTLE_DONE:
603	617	set_drq();
604	618	sub_state = DATA_LOAD_WAIT;
605		delay_cycles(t_gen, 768);
	619	delay_cycles(t_gen, 192);
606	620	return;
607	621
608	622	case DATA_LOAD_WAIT:
r19185	r19186
623	637	case WAIT_INDEX_DONE:
624	638	sub_state = TRACK_DONE;
625	639	live_start(WRITE_TRACK_DATA);
626		cur_live.pll.start_writing(machine().time());
	640	pll_start_writing(machine().time());
627	641	return;
628	642
629	643	case TRACK_DONE:
r19185	r19186
640	654
641	655	void wd_fdc_t::write_sector_start()
642	656	{
643		if(has_ready() && !is_ready())
	657	if(!is_ready())
644	658	command_end();
645
	659
646	660	main_state = WRITE_SECTOR;
647	661	status = (status & ~(S_CRC|S_LOST|S_RNF|S_WP|S_DDM)) | S_BUSY;
648	662	drop_drq();
649		if (has_side_select() && floppy)
650		floppy->ss_w(BIT(command, 1));
651		sub_state = has_motor() && !has_head_load()  ? SPINUP : SPINUP_DONE;
	663	if(side_control && floppy)
	664	floppy->ss_w(command & 0x02);
	665	sub_state = motor_control  ? SPINUP : SPINUP_DONE;
652	666	status_type_1 = false;
653	667	write_sector_continue();
654	668	}
r19185	r19186
734	748	drop_drq();
735	749	motor_timeout = 0;
736	750	}
737
	751
738	752	if(!(command & 0x0f)) {
739	753	intrq_cond = 0;
740	754	} else {
r19185	r19186
848	862	void wd_fdc_t::cmd_w(UINT8 val)
849	863	{
850	864	logerror("wd1772 cmd: %02x\n", val);
851
	865
852	866	if(intrq && !(intrq_cond & I_IMM)) {
853	867	intrq = false;
854	868	if(!intrq_cb.isnull())
r19185	r19186
861	875
862	876	cmd_buffer = val;
863	877
864		delay_cycles(t_cmd, dden ? 384 : 184);
	878	delay_cycles(t_cmd, dden ? 192 : 46);
865	879	}
866	880
867	881	UINT8 wd_fdc_t::status_r()
r19185	r19186
894	908	}
895	909	}
896	910
897		if(has_ready()) {
	911	if(ready_hooked) {
898	912	if(!is_ready())
899	913	status |= S_NRDY;
900	914	else
r19185	r19186
917	931	return;
918	932
919	933	track_buffer = val;
920		delay_cycles(t_track, dden ? 256 : 128);
	934	delay_cycles(t_track, dden ? 64 : 32);
921	935	}
922	936
923	937	UINT8 wd_fdc_t::track_r()
r19185	r19186
938	952	return;
939	953
940	954	sector_buffer = val;
941		delay_cycles(t_sector, dden ? 256 : 128);
	955	delay_cycles(t_sector, dden ? 64 : 32);
942	956	}
943	957
944	958	UINT8 wd_fdc_t::sector_r()
r19185	r19186
981	995
982	996	void wd_fdc_t::delay_cycles(emu_timer *tm, int cycles)
983	997	{
984		tm->adjust(clocks_to_attotime(cycles));
	998	tm->adjust(clocks_to_attotime(cycles*clock_ratio));
985	999	}
986	1000
987	1001	void wd_fdc_t::spinup()
r19185	r19186
1016	1030
1017	1031	switch(sub_state) {
1018	1032	case IDLE:
1019		if(has_motor()) {
	1033	if(motor_control) {
1020	1034	motor_timeout ++;
1021	1035	if(motor_timeout >= 5) {
1022	1036	status &= ~S_MON;
r19185	r19186
1117	1131	cur_live.previous_type = live_info::PT_NONE;
1118	1132	cur_live.data_bit_context = false;
1119	1133	cur_live.byte_counter = 0;
1120		cur_live.pll.reset(cur_live.tm);
1121		cur_live.pll.set_clock(clocks_to_attotime(1));
	1134	pll_reset(cur_live.tm);
1122	1135	checkpoint_live = cur_live;
	1136	pll_save_checkpoint();
1123	1137
1124	1138	live_run();
1125	1139	}
1126	1140
1127	1141	void wd_fdc_t::checkpoint()
1128	1142	{
1129		cur_live.pll.commit(floppy, cur_live.tm);
	1143	pll_commit(floppy, cur_live.tm);
1130	1144	checkpoint_live = cur_live;
	1145	pll_save_checkpoint();
1131	1146	}
1132	1147
1133	1148	void wd_fdc_t::rollback()
1134	1149	{
1135	1150	cur_live = checkpoint_live;
	1151	pll_retrieve_checkpoint();
1136	1152	}
1137	1153
1138	1154	void wd_fdc_t::live_delay(int state)
r19185	r19186
1148	1164	//          fprintf(stderr, "%s: Rolling back and replaying (%s)\n", ttsn().cstr(), tts(cur_live.tm).cstr());
1149	1165	rollback();
1150	1166	live_run(machine().time());
1151		cur_live.pll.commit(floppy, cur_live.tm);
	1167	pll_commit(floppy, cur_live.tm);
1152	1168	} else {
1153	1169	//          fprintf(stderr, "%s: Committing (%s)\n", ttsn().cstr(), tts(cur_live.tm).cstr());
1154		cur_live.pll.commit(floppy, cur_live.tm);
	1170	pll_commit(floppy, cur_live.tm);
1155	1171	if(cur_live.next_state != -1) {
1156	1172	cur_live.state = cur_live.next_state;
1157	1173	cur_live.next_state = -1;
1158	1174	}
1159	1175	if(cur_live.state == IDLE) {
1160		cur_live.pll.stop_writing(floppy, cur_live.tm);
	1176	pll_stop_writing(floppy, cur_live.tm);
1161	1177	cur_live.tm = attotime::never;
1162	1178	}
1163	1179	}
r19185	r19186
1173	1189	live_run(machine().time());
1174	1190	}
1175	1191
1176		cur_live.pll.stop_writing(floppy, cur_live.tm);
	1192	pll_stop_writing(floppy, cur_live.tm);
1177	1193	cur_live.tm = attotime::never;
1178	1194	cur_live.state = IDLE;
1179	1195	cur_live.next_state = -1;
r19185	r19186
1181	1197
1182	1198	bool wd_fdc_t::read_one_bit(attotime limit)
1183	1199	{
1184		int bit = cur_live.pll.get_next_bit(cur_live.tm, floppy, limit);
	1200	int bit = pll_get_next_bit(cur_live.tm, floppy, limit);
1185	1201	if(bit < 0)
1186	1202	return true;
1187	1203	cur_live.shift_reg = (cur_live.shift_reg << 1) | bit;
r19185	r19186
1200	1216	bool wd_fdc_t::write_one_bit(attotime limit)
1201	1217	{
1202	1218	bool bit = cur_live.shift_reg & 0x8000;
1203		if(cur_live.pll.write_next_bit(bit, cur_live.tm, floppy, limit))
	1219	if(pll_write_next_bit(bit, cur_live.tm, floppy, limit))
1204	1220	return true;
1205	1221	if(cur_live.bit_counter & 1) {
1206	1222	if((cur_live.crc ^ (bit ? 0x8000 : 0x0000)) & 0x8000)
r19185	r19186
1590	1606	// Is that correct?  It seems required (try ST formatting)
1591	1607	live_write_mfm(0xff);
1592	1608	else {
1593		cur_live.pll.stop_writing(floppy, cur_live.tm);
	1609	pll_stop_writing(floppy, cur_live.tm);
1594	1610	cur_live.state = IDLE;
1595	1611	return;
1596	1612	}
r19185	r19186
1634	1650	cur_live.bit_counter = 16;
1635	1651	cur_live.byte_counter = 0;
1636	1652	cur_live.data_bit_context = cur_live.data_reg & 1;
1637		cur_live.pll.start_writing(cur_live.tm);
	1653	pll_start_writing(cur_live.tm);
1638	1654	live_write_mfm(0x00);
1639	1655	break;
1640	1656	}
r19185	r19186
1667	1683	}
1668	1684	}
1669	1685
1670		void wd_fdc_t::pll_t::set_clock(attotime period)
	1686	int wd_fdc_t::step_time(int mode) const
1671	1687	{
	1688	const static int step_times[4] = { 12000, 24000, 40000, 60000 };
	1689	return step_times[mode];
	1690	}
	1691
	1692	int wd_fdc_t::settle_time() const
	1693	{
	1694	return 60000;
	1695	}
	1696
	1697	wd_fdc_analog_t::wd_fdc_analog_t(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
	1698	wd_fdc_t(mconfig, type, name, tag, owner, clock)
	1699	{
	1700	clock_ratio = 1;
	1701	}
	1702
	1703	void wd_fdc_analog_t::pll_reset(attotime when)
	1704	{
	1705	cur_pll.reset(when);
	1706	cur_pll.set_clock(clocks_to_attotime(4));
	1707	}
	1708
	1709	void wd_fdc_analog_t::pll_start_writing(attotime tm)
	1710	{
	1711	cur_pll.start_writing(tm);
	1712	}
	1713
	1714	void wd_fdc_analog_t::pll_commit(floppy_image_device *floppy, attotime tm)
	1715	{
	1716	cur_pll.commit(floppy, tm);
	1717	}
	1718
	1719	void wd_fdc_analog_t::pll_stop_writing(floppy_image_device *floppy, attotime tm)
	1720	{
	1721	cur_pll.stop_writing(floppy, tm);
	1722	}
	1723
	1724	void wd_fdc_analog_t::pll_save_checkpoint()
	1725	{
	1726	checkpoint_pll = cur_pll;
	1727	}
	1728
	1729	void wd_fdc_analog_t::pll_retrieve_checkpoint()
	1730	{
	1731	cur_pll = checkpoint_pll;
	1732	}
	1733
	1734	int wd_fdc_analog_t::pll_get_next_bit(attotime &tm, floppy_image_device *floppy, attotime limit)
	1735	{
	1736	return cur_pll.get_next_bit(tm, floppy, limit);
	1737	}
	1738
	1739	bool wd_fdc_analog_t::pll_write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, attotime limit)
	1740	{
	1741	return cur_pll.write_next_bit(bit, tm, floppy, limit);
	1742	}
	1743
	1744	wd_fdc_digital_t::wd_fdc_digital_t(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
	1745	wd_fdc_t(mconfig, type, name, tag, owner, clock)
	1746	{
	1747	clock_ratio = 4;
	1748	}
	1749
	1750	void wd_fdc_digital_t::pll_reset(attotime when)
	1751	{
	1752	cur_pll.reset(when);
	1753	cur_pll.set_clock(clocks_to_attotime(1));
	1754	}
	1755
	1756	void wd_fdc_digital_t::pll_start_writing(attotime tm)
	1757	{
	1758	cur_pll.start_writing(tm);
	1759	}
	1760
	1761	void wd_fdc_digital_t::pll_commit(floppy_image_device *floppy, attotime tm)
	1762	{
	1763	cur_pll.commit(floppy, tm);
	1764	}
	1765
	1766	void wd_fdc_digital_t::pll_stop_writing(floppy_image_device *floppy, attotime tm)
	1767	{
	1768	cur_pll.stop_writing(floppy, tm);
	1769	}
	1770
	1771	int wd_fdc_digital_t::pll_get_next_bit(attotime &tm, floppy_image_device *floppy, attotime limit)
	1772	{
	1773	return cur_pll.get_next_bit(tm, floppy, limit);
	1774	}
	1775
	1776	bool wd_fdc_digital_t::pll_write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, attotime limit)
	1777	{
	1778	return cur_pll.write_next_bit(bit, tm, floppy, limit);
	1779	}
	1780
	1781	void wd_fdc_digital_t::pll_save_checkpoint()
	1782	{
	1783	checkpoint_pll = cur_pll;
	1784	}
	1785
	1786	void wd_fdc_digital_t::pll_retrieve_checkpoint()
	1787	{
	1788	cur_pll = checkpoint_pll;
	1789	}
	1790
	1791	void wd_fdc_digital_t::digital_pll_t::set_clock(attotime period)
	1792	{
1672	1793	for(int i=0; i<42; i++)
1673	1794	delays[i] = period*(i+1);
1674	1795	}
1675	1796
1676		void wd_fdc_t::pll_t::reset(attotime when)
	1797	void wd_fdc_digital_t::digital_pll_t::reset(attotime when)
1677	1798	{
1678	1799	counter = 0;
1679	1800	increment = 128;
r19185	r19186
1689	1810	write_start_time = attotime::never;
1690	1811	}
1691	1812
1692		int wd_fdc_t::pll_t::get_next_bit(attotime &tm, floppy_image_device *floppy, attotime limit)
	1813	int wd_fdc_digital_t::digital_pll_t::get_next_bit(attotime &tm, floppy_image_device *floppy, attotime limit)
1693	1814	{
1694	1815	attotime when = floppy ? floppy->get_next_transition(ctime) : attotime::never;
1695	1816	#if 0
r19185	r19186
1769	1890	return bit;
1770	1891	}
1771	1892
1772		void wd_fdc_t::pll_t::start_writing(attotime tm)
	1893	void wd_fdc_digital_t::digital_pll_t::start_writing(attotime tm)
1773	1894	{
1774	1895	write_start_time = tm;
1775	1896	write_position = 0;
1776	1897	}
1777	1898
1778		void wd_fdc_t::pll_t::stop_writing(floppy_image_device *floppy, attotime tm)
	1899	void wd_fdc_digital_t::digital_pll_t::stop_writing(floppy_image_device *floppy, attotime tm)
1779	1900	{
1780	1901	commit(floppy, tm);
1781	1902	write_start_time = attotime::never;
1782	1903	}
1783	1904
1784		bool wd_fdc_t::pll_t::write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, attotime limit)
	1905	bool wd_fdc_digital_t::digital_pll_t::write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, attotime limit)
1785	1906	{
1786	1907	if(write_start_time.is_never()) {
1787	1908	write_start_time = ctime;
r19185	r19186
1811	1932	return false;
1812	1933	}
1813	1934
1814		void wd_fdc_t::pll_t::commit(floppy_image_device *floppy, attotime tm)
	1935	void wd_fdc_digital_t::digital_pll_t::commit(floppy_image_device *floppy, attotime tm)
1815	1936	{
1816	1937	if(write_start_time.is_never() || tm == write_start_time)
1817	1938	return;
r19185	r19186
1822	1943	write_position = 0;
1823	1944	}
1824	1945
1825		int wd_fdc_t::step_time(int mode) const
	1946	fd1771_t::fd1771_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, FD1771x, "FD1771", tag, owner, clock)
1826	1947	{
1827		const static int step_times[4] = { 48000, 96000, 160000, 240000 };
1828		return step_times[mode];
	1948	inverted_bus = true;
	1949	side_control = false;
	1950	side_compare = false;
	1951	head_control = true;
	1952	motor_control = false;
	1953	ready_hooked = true;
1829	1954	}
1830	1955
1831		int wd_fdc_t::settle_time() const
	1956	fd1781_t::fd1781_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, FD1781x, "FD1781", tag, owner, clock)
1832	1957	{
1833		return 240000;
	1958	inverted_bus = true;
	1959	side_control = false;
	1960	side_compare = false;
	1961	head_control = true;
	1962	motor_control = false;
	1963	ready_hooked = true;
1834	1964	}
1835	1965
1836		bool wd_fdc_t::has_ready() const
	1966	fd1791_t::fd1791_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, FD1791x, "FD1791", tag, owner, clock)
1837	1967	{
1838		return false;
	1968	inverted_bus = true;
	1969	side_control = false;
	1970	side_compare = true;
	1971	head_control = true;
	1972	motor_control = false;
	1973	ready_hooked = true;
1839	1974	}
1840	1975
1841		bool wd_fdc_t::has_head_load() const
	1976	fd1792_t::fd1792_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, FD1792x, "FD1792", tag, owner, clock)
1842	1977	{
1843		return false;
	1978	inverted_bus = true;
	1979	side_control = false;
	1980	side_compare = true;
	1981	head_control = true;
	1982	motor_control = false;
	1983	ready_hooked = true;
1844	1984	}
1845	1985
1846		bool wd_fdc_t::has_side_check() const
	1986	fd1793_t::fd1793_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, FD1793x, "FD1793", tag, owner, clock)
1847	1987	{
1848		return false;
	1988	inverted_bus = false;
	1989	side_control = false;
	1990	side_compare = true;
	1991	head_control = true;
	1992	motor_control = false;
	1993	ready_hooked = true;
1849	1994	}
1850	1995
1851		bool wd_fdc_t::has_side_select() const
	1996	fd1794_t::fd1794_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, FD1794x, "FD1794", tag, owner, clock)
1852	1997	{
1853		return false;
	1998	inverted_bus = false;
	1999	side_control = false;
	2000	side_compare = true;
	2001	head_control = true;
	2002	motor_control = false;
	2003	ready_hooked = true;
1854	2004	}
1855	2005
1856		bool wd_fdc_t::has_sector_length_select() const
	2006	fd1795_t::fd1795_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, FD1795x, "FD1795", tag, owner, clock)
1857	2007	{
1858		return false;
	2008	inverted_bus = true;
	2009	side_control = false;
	2010	side_compare = false;
	2011	head_control = true;
	2012	motor_control = false;
	2013	ready_hooked = true;
1859	2014	}
1860	2015
1861		bool wd_fdc_t::has_precompensation() const
	2016	fd1797_t::fd1797_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, FD1797x, "FD1797", tag, owner, clock)
1862	2017	{
1863		return false;
	2018	inverted_bus = false;
	2019	side_control = false;
	2020	side_compare = false;
	2021	head_control = true;
	2022	motor_control = false;
	2023	ready_hooked = true;
1864	2024	}
1865	2025
1866		fd1771_t::fd1771_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_t(mconfig, FD1771x, "FD1771", tag, owner, clock)
	2026	mb8866_t::mb8866_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, MB8866x, "MB8866", tag, owner, clock)
1867	2027	{
	2028	inverted_bus = true;
	2029	side_control = false;
	2030	side_compare = true;
	2031	head_control = true;
	2032	motor_control = false;
	2033	ready_hooked = true;
1868	2034	}
1869	2035
1870		fd1793_t::fd1793_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_t(mconfig, FD1793x, "FD1793", tag, owner, clock)
	2036	mb8876_t::mb8876_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, MB8876x, "MB8876", tag, owner, clock)
1871	2037	{
	2038	inverted_bus = true;
	2039	side_control = false;
	2040	side_compare = true;
	2041	head_control = true;
	2042	motor_control = false;
	2043	ready_hooked = true;
1872	2044	}
1873	2045
1874		fd1797_t::fd1797_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_t(mconfig, FD1797x, "FD1797", tag, owner, clock)
	2046	mb8877_t::mb8877_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, MB8877x, "MB8877", tag, owner, clock)
1875	2047	{
	2048	inverted_bus = false;
	2049	side_control = false;
	2050	side_compare = true;
	2051	head_control = true;
	2052	motor_control = false;
	2053	ready_hooked = true;
1876	2054	}
1877	2055
1878		wd2793_t::wd2793_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_t(mconfig, WD2793x, "WD2793", tag, owner, clock)
	2056	fd1761_t::fd1761_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, FD1761x, "FD1761", tag, owner, clock)
1879	2057	{
	2058	inverted_bus = true;
	2059	side_control = false;
	2060	side_compare = true;
	2061	head_control = true;
	2062	motor_control = false;
	2063	ready_hooked = true;
1880	2064	}
1881	2065
1882		wd2797_t::wd2797_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_t(mconfig, WD2797x, "WD2797", tag, owner, clock)
	2066	fd1763_t::fd1763_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, FD1763x, "FD1763", tag, owner, clock)
1883	2067	{
	2068	inverted_bus = false;
	2069	side_control = false;
	2070	side_compare = true;
	2071	head_control = true;
	2072	motor_control = false;
	2073	ready_hooked = true;
1884	2074	}
1885	2075
1886		wd1770_t::wd1770_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_t(mconfig, WD1770x, "WD1770", tag, owner, clock)
	2076	fd1765_t::fd1765_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, FD1765x, "FD1765", tag, owner, clock)
1887	2077	{
	2078	inverted_bus = true;
	2079	side_control = true;
	2080	side_compare = false;
	2081	head_control = true;
	2082	motor_control = false;
	2083	ready_hooked = true;
1888	2084	}
1889	2085
1890		wd1772_t::wd1772_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_t(mconfig, WD1772x, "WD1772", tag, owner, clock)
	2086	fd1767_t::fd1767_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, FD1767x, "FD1767", tag, owner, clock)
1891	2087	{
	2088	inverted_bus = false;
	2089	side_control = true;
	2090	side_compare = false;
	2091	head_control = true;
	2092	motor_control = false;
	2093	ready_hooked = true;
1892	2094	}
1893	2095
	2096	wd2791_t::wd2791_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, WD2791x, "WD2791", tag, owner, clock)
	2097	{
	2098	inverted_bus = true;
	2099	side_control = false;
	2100	side_compare = true;
	2101	head_control = true;
	2102	motor_control = false;
	2103	ready_hooked = true;
	2104	}
	2105
	2106	wd2793_t::wd2793_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, WD2793x, "WD2793", tag, owner, clock)
	2107	{
	2108	inverted_bus = false;
	2109	side_control = false;
	2110	side_compare = true;
	2111	head_control = true;
	2112	motor_control = false;
	2113	ready_hooked = true;
	2114	}
	2115
	2116	wd2795_t::wd2795_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, WD2795x, "WD2795", tag, owner, clock)
	2117	{
	2118	inverted_bus = true;
	2119	side_control = true;
	2120	side_compare = false;
	2121	head_control = true;
	2122	motor_control = false;
	2123	ready_hooked = true;
	2124	}
	2125
	2126	wd2797_t::wd2797_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_analog_t(mconfig, WD2797x, "WD2797", tag, owner, clock)
	2127	{
	2128	inverted_bus = false;
	2129	side_control = true;
	2130	side_compare = false;
	2131	head_control = true;
	2132	motor_control = false;
	2133	ready_hooked = true;
	2134	}
	2135
	2136	wd1770_t::wd1770_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_digital_t(mconfig, WD1770x, "WD1770", tag, owner, clock)
	2137	{
	2138	inverted_bus = false;
	2139	side_control = false;
	2140	side_compare = false;
	2141	head_control = false;
	2142	motor_control = true;
	2143	ready_hooked = false;
	2144	}
	2145
	2146	wd1772_t::wd1772_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_digital_t(mconfig, WD1772x, "WD1772", tag, owner, clock)
	2147	{
	2148	inverted_bus = false;
	2149	side_control = false;
	2150	side_compare = false;
	2151	head_control = false;
	2152	motor_control = true;
	2153	ready_hooked = false;
	2154	}
	2155
1894	2156	int wd1772_t::step_time(int mode) const
1895	2157	{
1896		const static int step_times[4] = { 48000, 96000, 16000, 24000 };
	2158	const static int step_times[4] = { 12000, 24000, 4000, 6000 };
1897	2159	return step_times[mode];
1898	2160	}
1899	2161
1900	2162	int wd1772_t::settle_time() const
1901	2163	{
1902		return 120000;
	2164	return 30000;
1903	2165	}
1904	2166
1905		wd1773_t::wd1773_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_t(mconfig, WD1773x, "WD1773", tag, owner, clock)
	2167	wd1773_t::wd1773_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : wd_fdc_digital_t(mconfig, WD1773x, "WD1773", tag, owner, clock)
1906	2168	{
	2169	inverted_bus = false;
	2170	side_control = false;
	2171	side_compare = true;
	2172	head_control = false;
	2173	motor_control = false;
	2174	ready_hooked = true;
1907	2175	}

trunk/src/emu/machine/wd_fdc.h

r19185	r19186
3	3
4	4	#include "emu.h"
5	5	#include "imagedev/floppy.h"
	6	#include "fdc_pll.h"
6	7
7	8	/*
8	9	* The Western Digital floppy controller family
r19185	r19186
44	45	#define MCFG_FD1771x_ADD(_tag, _clock)  \
45	46	MCFG_DEVICE_ADD(_tag, FD1771x, _clock)
46	47
	48	#define MCFG_FD1781x_ADD(_tag, _clock)  \
	49	MCFG_DEVICE_ADD(_tag, FD1781x, _clock)
	50
	51	#define MCFG_FD1791x_ADD(_tag, _clock)  \
	52	MCFG_DEVICE_ADD(_tag, FD1791x, _clock)
	53
	54	#define MCFG_FD1792x_ADD(_tag, _clock)  \
	55	MCFG_DEVICE_ADD(_tag, FD1792x, _clock)
	56
47	57	#define MCFG_FD1793x_ADD(_tag, _clock)  \
48	58	MCFG_DEVICE_ADD(_tag, FD1793x, _clock)
49	59
	60	#define MCFG_FD1794x_ADD(_tag, _clock)  \
	61	MCFG_DEVICE_ADD(_tag, FD1794x, _clock)
	62
	63	#define MCFG_FD1795x_ADD(_tag, _clock)  \
	64	MCFG_DEVICE_ADD(_tag, FD1795x, _clock)
	65
50	66	#define MCFG_FD1797x_ADD(_tag, _clock)  \
51	67	MCFG_DEVICE_ADD(_tag, FD1797x, _clock)
52	68
	69	#define MCFG_MB866x_ADD(_tag, _clock)  \
	70	MCFG_DEVICE_ADD(_tag, MB8866x, _clock)
	71
	72	#define MCFG_MB876x_ADD(_tag, _clock)  \
	73	MCFG_DEVICE_ADD(_tag, MB8876x, _clock)
	74
	75	#define MCFG_MB877x_ADD(_tag, _clock)  \
	76	MCFG_DEVICE_ADD(_tag, MB8877x, _clock)
	77
	78	#define MCFG_FD1761x_ADD(_tag, _clock)  \
	79	MCFG_DEVICE_ADD(_tag, FD1761x, _clock)
	80
	81	#define MCFG_FD1763x_ADD(_tag, _clock)  \
	82	MCFG_DEVICE_ADD(_tag, FD1763x, _clock)
	83
	84	#define MCFG_FD1765x_ADD(_tag, _clock)  \
	85	MCFG_DEVICE_ADD(_tag, FD1765x, _clock)
	86
	87	#define MCFG_FD1767x_ADD(_tag, _clock)  \
	88	MCFG_DEVICE_ADD(_tag, FD1767x, _clock)
	89
	90	#define MCFG_WD2791x_ADD(_tag, _clock)  \
	91	MCFG_DEVICE_ADD(_tag, WD2791x, _clock)
	92
53	93	#define MCFG_WD2793x_ADD(_tag, _clock)  \
54	94	MCFG_DEVICE_ADD(_tag, WD2793x, _clock)
55	95
	96	#define MCFG_WD2795x_ADD(_tag, _clock)  \
	97	MCFG_DEVICE_ADD(_tag, WD2795x, _clock)
	98
56	99	#define MCFG_WD2797x_ADD(_tag, _clock)  \
57	100	MCFG_DEVICE_ADD(_tag, WD2797x, _clock)
58	101
r19185	r19186
112	155	bool enp_r();
113	156
114	157	protected:
	158	// Chip-specific configuration flags
	159	bool inverted_bus;
	160	bool side_control;
	161	bool side_compare;
	162	bool head_control;
	163	bool motor_control;
	164	bool ready_hooked;
	165	int clock_ratio;
	166
115	167	virtual void device_start();
116	168	virtual void device_reset();
117	169	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
118	170
119		virtual bool has_ready() const;
120		virtual bool has_motor() const = 0;
121		virtual bool has_head_load() const;
122		virtual bool has_side_check() const;
123		virtual bool has_side_select() const;
124		virtual bool has_sector_length_select() const;
125		virtual bool has_precompensation() const;
126	171	virtual int step_time(int mode) const;
127	172	virtual int settle_time() const;
128	173
	174	virtual void pll_reset(attotime when) = 0;
	175	virtual void pll_start_writing(attotime tm) = 0;
	176	virtual void pll_commit(floppy_image_device *floppy, attotime tm) = 0;
	177	virtual void pll_stop_writing(floppy_image_device *floppy, attotime tm) = 0;
	178	virtual int pll_get_next_bit(attotime &tm, floppy_image_device *floppy, attotime limit) = 0;
	179	virtual bool pll_write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, attotime limit) = 0;
	180	virtual void pll_save_checkpoint() = 0;
	181	virtual void pll_retrieve_checkpoint() = 0;
	182
129	183	private:
130	184	enum { TM_GEN, TM_CMD, TM_TRACK, TM_SECTOR };
131	185
r19185	r19186
233	287	WRITE_SECTOR_PRE_BYTE,
234	288	};
235	289
236		struct pll_t {
237		UINT16 counter;
238		UINT16 increment;
239		UINT16 transition_time;
240		UINT8 history;
241		UINT8 slot;
242		UINT8 phase_add, phase_sub, freq_add, freq_sub;
243		attotime ctime;
244
245		attotime delays[42];
246
247		attotime write_start_time;
248		attotime write_buffer[32];
249		int write_position;
250
251		void set_clock(attotime period);
252		void reset(attotime when);
253		int get_next_bit(attotime &tm, floppy_image_device *floppy, attotime limit);
254		bool write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, attotime limit);
255		void start_writing(attotime tm);
256		void commit(floppy_image_device *floppy, attotime tm);
257		void stop_writing(floppy_image_device *floppy, attotime tm);
258		};
259
260	290	struct live_info {
261	291	enum { PT_NONE, PT_CRC_1, PT_CRC_2 };
262	292
r19185	r19186
268	298	bool data_separator_phase, data_bit_context;
269	299	UINT8 data_reg;
270	300	UINT8 idbuf[6];
271		pll_t pll;
272	301	};
273	302
274	303	enum {
r19185	r19186
295	324	I_IMM = 0x08
296	325	};
297	326
	327
298	328	floppy_image_device *floppy;
299	329
300	330	emu_timer *t_gen, *t_cmd, *t_track, *t_sector;
r19185	r19186
369	399	void set_drq();
370	400	};
371	401
372		class fd1771_t : public wd_fdc_t {
	402	class wd_fdc_analog_t : public wd_fdc_t {
373	403	public:
374		fd1771_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	404	wd_fdc_analog_t(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
375	405
376	406	protected:
377		virtual bool has_ready() const { return true; }
378		virtual bool has_motor() const { return false; }
379		virtual bool has_head_load() const { return true; }
380		virtual bool has_side_check() const { return true; }
	407	virtual void pll_reset(attotime when);
	408	virtual void pll_start_writing(attotime tm);
	409	virtual void pll_commit(floppy_image_device *floppy, attotime tm);
	410	virtual void pll_stop_writing(floppy_image_device *floppy, attotime tm);
	411	virtual int pll_get_next_bit(attotime &tm, floppy_image_device *floppy, attotime limit);
	412	virtual bool pll_write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, attotime limit);
	413	virtual void pll_save_checkpoint();
	414	virtual void pll_retrieve_checkpoint();
	415
	416	private:
	417	fdc_pll_t cur_pll, checkpoint_pll;
381	418	};
382	419
383		class fd1793_t : public wd_fdc_t {
	420	class wd_fdc_digital_t : public wd_fdc_t {
384	421	public:
385		fd1793_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	422	wd_fdc_digital_t(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
386	423
387	424	protected:
388		virtual bool has_ready() const { return true; }
389		virtual bool has_motor() const { return false; }
390		virtual bool has_head_load() const { return true; }
391		virtual bool has_side_check() const { return true; }
	425	virtual void pll_reset(attotime when);
	426	virtual void pll_start_writing(attotime tm);
	427	virtual void pll_commit(floppy_image_device *floppy, attotime tm);
	428	virtual void pll_stop_writing(floppy_image_device *floppy, attotime tm);
	429	virtual int pll_get_next_bit(attotime &tm, floppy_image_device *floppy, attotime limit);
	430	virtual bool pll_write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, attotime limit);
	431	virtual void pll_save_checkpoint();
	432	virtual void pll_retrieve_checkpoint();
	433
	434	private:
	435	struct digital_pll_t {
	436	UINT16 counter;
	437	UINT16 increment;
	438	UINT16 transition_time;
	439	UINT8 history;
	440	UINT8 slot;
	441	UINT8 phase_add, phase_sub, freq_add, freq_sub;
	442	attotime ctime;
	443
	444	attotime delays[42];
	445
	446	attotime write_start_time;
	447	attotime write_buffer[32];
	448	int write_position;
	449
	450	void set_clock(attotime period);
	451	void reset(attotime when);
	452	int get_next_bit(attotime &tm, floppy_image_device *floppy, attotime limit);
	453	bool write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, attotime limit);
	454	void start_writing(attotime tm);
	455	void commit(floppy_image_device *floppy, attotime tm);
	456	void stop_writing(floppy_image_device *floppy, attotime tm);
	457	};
	458
	459	digital_pll_t cur_pll, checkpoint_pll;
392	460	};
393	461
394		class fd1797_t : public wd_fdc_t {
	462	class fd1771_t : public wd_fdc_analog_t {
395	463	public:
	464	fd1771_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	465	};
	466
	467	class fd1781_t : public wd_fdc_analog_t {
	468	public:
	469	fd1781_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	470	};
	471
	472	class fd1791_t : public wd_fdc_analog_t {
	473	public:
	474	fd1791_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	475	};
	476
	477	class fd1792_t : public wd_fdc_analog_t {
	478	public:
	479	fd1792_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	480	};
	481
	482	class fd1793_t : public wd_fdc_analog_t {
	483	public:
	484	fd1793_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	485	};
	486
	487	class fd1794_t : public wd_fdc_analog_t {
	488	public:
	489	fd1794_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	490	};
	491
	492	class fd1795_t : public wd_fdc_analog_t {
	493	public:
	494	fd1795_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	495	};
	496
	497	class fd1797_t : public wd_fdc_analog_t {
	498	public:
396	499	fd1797_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	500	};
397	501
398		protected:
399		virtual bool has_ready() const { return true; }
400		virtual bool has_motor() const { return false; }
401		virtual bool has_head_load() const { return true; }
402		virtual bool has_side_select() const { return true; }
403		virtual bool has_sector_length_select() const { return true; }
	502	class mb8866_t : public wd_fdc_analog_t {
	503	public:
	504	mb8866_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
404	505	};
405	506
406		class wd2793_t : public wd_fdc_t {
	507	class mb8876_t : public wd_fdc_analog_t {
407	508	public:
	509	mb8876_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	510	};
	511
	512	class mb8877_t : public wd_fdc_analog_t {
	513	public:
	514	mb8877_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	515	};
	516
	517	class fd1761_t : public wd_fdc_analog_t {
	518	public:
	519	fd1761_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	520	};
	521
	522	class fd1763_t : public wd_fdc_analog_t {
	523	public:
	524	fd1763_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	525	};
	526
	527	class fd1765_t : public wd_fdc_analog_t {
	528	public:
	529	fd1765_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	530	};
	531
	532	class fd1767_t : public wd_fdc_analog_t {
	533	public:
	534	fd1767_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	535	};
	536
	537	class wd2791_t : public wd_fdc_analog_t {
	538	public:
	539	wd2791_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	540	};
	541
	542	class wd2793_t : public wd_fdc_analog_t {
	543	public:
408	544	wd2793_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	545	};
409	546
410		protected:
411		virtual bool has_ready() const { return true; }
412		virtual bool has_motor() const { return false; }
413		virtual bool has_head_load() const { return true; }
414		virtual bool has_side_check() const { return true; }
	547	class wd2795_t : public wd_fdc_analog_t {
	548	public:
	549	wd2795_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
415	550	};
416	551
417		class wd2797_t : public wd_fdc_t {
	552	class wd2797_t : public wd_fdc_analog_t {
418	553	public:
419	554	wd2797_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
420
421		protected:
422		virtual bool has_ready() const { return true; }
423		virtual bool has_motor() const { return false; }
424		virtual bool has_head_load() const { return true; }
425		virtual bool has_side_select() const { return true; }
426		virtual bool has_sector_length_select() const { return true; }
427	555	};
428	556
429		class wd1770_t : public wd_fdc_t {
	557	class wd1770_t : public wd_fdc_digital_t {
430	558	public:
431	559	wd1770_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
432
433		protected:
434		virtual bool has_motor() const { return true; }
435		virtual bool has_precompensation() const { return true; }
436	560	};
437	561
438		class wd1772_t : public wd_fdc_t {
	562	class wd1772_t : public wd_fdc_digital_t {
439	563	public:
440	564	wd1772_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
441	565
442	566	protected:
443		virtual bool has_motor() const { return true; }
444		virtual bool has_precompensation() const { return true; }
445	567	virtual int step_time(int mode) const;
446	568	virtual int settle_time() const;
447	569	};
448	570
449		class wd1773_t : public wd_fdc_t {
	571	class wd1773_t : public wd_fdc_digital_t {
450	572	public:
451	573	wd1773_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
452
453		protected:
454		virtual bool has_motor() const { return false; }
455		virtual bool has_head_load() const { return true; }
456		virtual bool has_side_check() const { return true; }
457	574	};
458	575
459	576	extern const device_type FD1771x;
	577
	578	extern const device_type FD1781x;
	579
	580	extern const device_type FD1791x;
	581	extern const device_type FD1792x;
460	582	extern const device_type FD1793x;
	583	extern const device_type FD1795x;
461	584	extern const device_type FD1797x;
	585
	586	extern const device_type MB8866x;
	587	extern const device_type MB8876x;
	588	extern const device_type MB8877x;
	589
	590	extern const device_type FD1761x;
	591	extern const device_type FD1763x;
	592	extern const device_type FD1765x;
	593	extern const device_type FD1767x;
	594
	595	extern const device_type WD2791x;
462	596	extern const device_type WD2793x;
	597	extern const device_type WD2795x;
463	598	extern const device_type WD2797x;
	599
464	600	extern const device_type WD1770x;
465	601	extern const device_type WD1772x;
466	602	extern const device_type WD1773x;

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team