trunk/src/emu/cpu/z8000/z8000ops.c
| r19095 | r19096 | |
| 6 | 6 | * |
| 7 | 7 | * Copyright Juergen Buchmueller, all rights reserved. |
| 8 | 8 | * Bug fixes and MSB_FIRST compliance Ernesto Corvi. |
| 9 | * Bug fixes and segmented mode support Christian Groessler. |
| 9 | 10 | * |
| 10 | 11 | * - This source code is released as freeware for non-commercial purposes. |
| 11 | 12 | * - You are free to use and redistribute this code in modified or |
| r19095 | r19096 | |
| 73 | 74 | |
| 74 | 75 | INLINE UINT32 make_segmented_addr(UINT32 addr) |
| 75 | 76 | { |
| 76 | | return ((addr & 0xffff0000) << 8) | (addr & 0xffff); |
| 77 | return ((addr & 0x007f0000) << 8) | 0x80000000 | (addr & 0xffff); |
| 77 | 78 | } |
| 78 | 79 | |
| 79 | 80 | INLINE UINT32 segmented_addr(UINT32 addr) |
| r19095 | r19096 | |
| 91 | 92 | |
| 92 | 93 | INLINE void addr_to_reg(z8000_state *cpustate, int regno, UINT32 addr) |
| 93 | 94 | { |
| 94 | | if (segmented_mode(cpustate)) |
| 95 | | cpustate->RL(regno) = /*(cpustate->RL(regno) & 0x00ff0000) |*/ make_segmented_addr(addr); |
| 95 | if (segmented_mode(cpustate)) { |
| 96 | UINT32 segaddr = make_segmented_addr(addr); |
| 97 | cpustate->RW(regno) = (cpustate->RW(regno) & 0x80ff) | ((segaddr >> 16) & 0x7f00); |
| 98 | cpustate->RW(regno | 1) = segaddr & 0xffff; |
| 99 | } |
| 96 | 100 | else |
| 97 | 101 | cpustate->RW(regno) = addr; |
| 98 | 102 | } |
| 99 | 103 | |
| 104 | INLINE void add_to_addr_reg(z8000_state *cpustate, int regno, UINT16 addend) |
| 105 | { |
| 106 | if (segmented_mode(cpustate)) |
| 107 | regno |= 1; |
| 108 | cpustate->RW(regno) += addend; |
| 109 | } |
| 110 | |
| 111 | INLINE void sub_from_addr_reg(z8000_state *cpustate, int regno, UINT16 subtrahend) |
| 112 | { |
| 113 | if (segmented_mode(cpustate)) |
| 114 | regno |= 1; |
| 115 | cpustate->RW(regno) -= subtrahend; |
| 116 | } |
| 117 | |
| 100 | 118 | INLINE void PUSHW(z8000_state *cpustate, UINT8 dst, UINT16 value) |
| 101 | 119 | { |
| 102 | 120 | if (segmented_mode(cpustate)) |
| r19095 | r19096 | |
| 1437 | 1455 | static void Z0C_ddN0_0000(z8000_state *cpustate) |
| 1438 | 1456 | { |
| 1439 | 1457 | GET_DST(OP0,NIB3); |
| 1440 | | WRMEM_B(cpustate, cpustate->RW(dst), COMB(cpustate, RDMEM_B(cpustate, addr_from_reg(cpustate, dst)))); |
| 1458 | UINT32 addr = addr_from_reg(cpustate, dst); |
| 1459 | WRMEM_B(cpustate, addr, COMB(cpustate, RDMEM_B(cpustate, addr))); |
| 1441 | 1460 | } |
| 1442 | 1461 | |
| 1443 | 1462 | /****************************************** |
| r19095 | r19096 | |
| 1480 | 1499 | { |
| 1481 | 1500 | GET_DST(OP0,NIB2); |
| 1482 | 1501 | GET_IMM8(OP1); |
| 1483 | | WRMEM_B(cpustate, addr_from_reg(cpustate, dst), imm8); |
| 1502 | WRMEM_B(cpustate, addr_from_reg(cpustate, dst), imm8); |
| 1484 | 1503 | } |
| 1485 | 1504 | |
| 1486 | 1505 | /****************************************** |
| r19095 | r19096 | |
| 1535 | 1554 | { |
| 1536 | 1555 | GET_DST(OP0,NIB2); |
| 1537 | 1556 | UINT32 addr = addr_from_reg(cpustate, dst); |
| 1538 | | WRMEM_W(cpustate, addr, NEGW(cpustate, RDMEM_W(cpustate, addr))); |
| 1557 | WRMEM_W(cpustate, addr, NEGW(cpustate, RDMEM_W(cpustate, addr))); |
| 1539 | 1558 | } |
| 1540 | 1559 | |
| 1541 | 1560 | /****************************************** |
| r19095 | r19096 | |
| 1578 | 1597 | static void Z0D_ddN0_1000(z8000_state *cpustate) |
| 1579 | 1598 | { |
| 1580 | 1599 | GET_DST(OP0,NIB2); |
| 1581 | | WRMEM_W(cpustate, addr_from_reg(cpustate, dst), 0); |
| 1600 | WRMEM_W(cpustate, addr_from_reg(cpustate, dst), 0); |
| 1582 | 1601 | } |
| 1583 | 1602 | |
| 1584 | 1603 | /****************************************** |
| r19095 | r19096 | |
| 1711 | 1730 | } |
| 1712 | 1731 | |
| 1713 | 1732 | /****************************************** |
| 1714 | | popl @rd,@rs |
| 1733 | popl rd,@rs |
| 1715 | 1734 | flags: ------ |
| 1716 | 1735 | ******************************************/ |
| 1717 | 1736 | static void Z15_ssN0_ddN0(z8000_state *cpustate) |
| r19095 | r19096 | |
| 1751 | 1770 | { |
| 1752 | 1771 | GET_DST(OP0,NIB3); |
| 1753 | 1772 | GET_SRC(OP0,NIB2); |
| 1754 | | cpustate->RW(dst) = POPW(cpustate, src); |
| 1773 | WRMEM_W(cpustate, addr_from_reg(cpustate, dst), POPW(cpustate, src)); |
| 1755 | 1774 | } |
| 1756 | 1775 | |
| 1757 | 1776 | /****************************************** |
| r19095 | r19096 | |
| 1861 | 1880 | GET_DST(OP0,NIB2); |
| 1862 | 1881 | GET_CNT(OP1,NIB3); |
| 1863 | 1882 | GET_SRC(OP1,NIB1); |
| 1864 | | UINT16 idx = cpustate->RW(dst); |
| 1883 | UINT32 addr = addr_from_reg(cpustate, dst); |
| 1865 | 1884 | while (cnt-- >= 0) { |
| 1866 | | WRMEM_W(cpustate, idx, cpustate->RW(src)); |
| 1867 | | idx = (idx + 2) & 0xffff; |
| 1885 | WRMEM_W(cpustate, addr, cpustate->RW(src)); |
| 1886 | addr = addr_add(cpustate, addr, 2); |
| 1868 | 1887 | src = (src+1) & 15; |
| 1869 | 1888 | } |
| 1870 | 1889 | } |
| r19095 | r19096 | |
| 1878 | 1897 | GET_SRC(OP0,NIB2); |
| 1879 | 1898 | GET_CNT(OP1,NIB3); |
| 1880 | 1899 | GET_DST(OP1,NIB1); |
| 1881 | | UINT16 idx = cpustate->RW(src); |
| 1900 | UINT32 addr = addr_from_reg(cpustate, src); |
| 1882 | 1901 | while (cnt-- >= 0) { |
| 1883 | | cpustate->RW(dst) = RDMEM_W(cpustate, idx); |
| 1884 | | idx = (idx + 2) & 0xffff; |
| 1902 | cpustate->RW(dst) = RDMEM_W(cpustate, addr); |
| 1903 | addr = addr_add(cpustate, addr, 2); |
| 1885 | 1904 | dst = (dst+1) & 15; |
| 1886 | 1905 | } |
| 1887 | 1906 | } |
| r19095 | r19096 | |
| 2322 | 2341 | GET_DST(OP0,NIB3); |
| 2323 | 2342 | GET_SRC(OP0,NIB2); |
| 2324 | 2343 | GET_IDX16(OP1); |
| 2325 | | idx16 = addr_add(cpustate, addr_from_reg(cpustate, src), idx16); |
| 2326 | | addr_to_reg(cpustate, dst, idx16); |
| 2344 | if (segmented_mode(cpustate)) { |
| 2345 | cpustate->RL(dst) = cpustate->RL(src); |
| 2346 | } |
| 2347 | else { |
| 2348 | cpustate->RW(dst) = cpustate->RW(src); |
| 2349 | } |
| 2350 | add_to_addr_reg(cpustate, dst, idx16); |
| 2327 | 2351 | } |
| 2328 | 2352 | |
| 2329 | 2353 | /****************************************** |
| r19095 | r19096 | |
| 2445 | 2469 | GET_DST(OP1,NIB2); |
| 2446 | 2470 | GET_CCC(OP1,NIB3); |
| 2447 | 2471 | WRMEM_B(cpustate, addr_from_reg(cpustate, dst), RDPORT_B(cpustate, 0, cpustate->RW(src))); |
| 2448 | | addr_to_reg(cpustate, dst, addr_add(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 2472 | add_to_addr_reg(cpustate, dst, 1); |
| 2449 | 2473 | if (--cpustate->RW(cnt)) { CLR_V; if (cc == 0) cpustate->pc -= 4; } else SET_V; |
| 2450 | 2474 | } |
| 2451 | 2475 | |
| r19095 | r19096 | |
| 2480 | 2504 | GET_DST(OP1,NIB2); |
| 2481 | 2505 | GET_CCC(OP1,NIB3); |
| 2482 | 2506 | WRPORT_B(cpustate, 0, cpustate->RW(dst), RDMEM_B(cpustate, addr_from_reg(cpustate, src))); |
| 2483 | | addr_to_reg(cpustate, src, addr_add(cpustate, addr_from_reg(cpustate, src), 1)); |
| 2507 | add_to_addr_reg(cpustate, src, 1); |
| 2484 | 2508 | if (--cpustate->RW(cnt)) { CLR_V; if (cc == 0) cpustate->pc -= 4; } else SET_V; |
| 2485 | 2509 | } |
| 2486 | 2510 | |
| r19095 | r19096 | |
| 4424 | 4448 | GET_DST(OP0,NIB3); |
| 4425 | 4449 | GET_SRC(OP0,NIB2); |
| 4426 | 4450 | GET_IDX(OP1,NIB1); |
| 4427 | | addr_to_reg(cpustate, dst, addr_add(cpustate, addr_from_reg(cpustate, src), cpustate->RW(idx))); |
| 4451 | if (segmented_mode(cpustate)) { |
| 4452 | cpustate->RL(dst) = cpustate->RL(src); |
| 4453 | } |
| 4454 | else { |
| 4455 | cpustate->RW(dst) = cpustate->RW(src); |
| 4456 | } |
| 4457 | add_to_addr_reg(cpustate, dst, cpustate->RW(idx)); |
| 4428 | 4458 | } |
| 4429 | 4459 | |
| 4430 | 4460 | /****************************************** |
| r19095 | r19096 | |
| 4446 | 4476 | static void Z76_0000_dddd_addr(z8000_state *cpustate) |
| 4447 | 4477 | { |
| 4448 | 4478 | GET_DST(OP0,NIB3); |
| 4449 | | GET_ADDR(OP1); |
| 4450 | | addr_to_reg(cpustate, dst, addr); |
| 4479 | GET_ADDR_RAW(OP1); |
| 4480 | if (segmented_mode(cpustate)) { |
| 4481 | cpustate->RL(dst) = addr; |
| 4482 | } |
| 4483 | else { |
| 4484 | cpustate->RW(dst) = addr; |
| 4485 | } |
| 4451 | 4486 | } |
| 4452 | 4487 | |
| 4453 | 4488 | /****************************************** |
| r19095 | r19096 | |
| 4455 | 4490 | flags: ------ |
| 4456 | 4491 | ******************************************/ |
| 4457 | 4492 | static void Z76_ssN0_dddd_addr(z8000_state *cpustate) |
| 4458 | | { |
| 4493 | {//@@@ |
| 4459 | 4494 | GET_DST(OP0,NIB3); |
| 4460 | 4495 | GET_SRC(OP0,NIB2); |
| 4461 | | GET_ADDR(OP1); |
| 4462 | | addr = addr_add(cpustate, addr, cpustate->RW(src)); |
| 4463 | | addr_to_reg(cpustate, dst, addr); |
| 4496 | GET_ADDR_RAW(OP1); |
| 4497 | if (segmented_mode(cpustate)) { |
| 4498 | cpustate->RL(dst) = addr; |
| 4499 | } |
| 4500 | else { |
| 4501 | cpustate->RW(dst) = addr; |
| 4502 | } |
| 4503 | add_to_addr_reg(cpustate, dst, cpustate->RW(src)); |
| 4464 | 4504 | } |
| 4465 | 4505 | |
| 4466 | 4506 | /****************************************** |
| r19095 | r19096 | |
| 5543 | 5583 | static void ZB2_dddd_0001_imm8(z8000_state *cpustate) |
| 5544 | 5584 | { |
| 5545 | 5585 | GET_DST(OP0,NIB2); |
| 5546 | | GET_IMM16(OP1); |
| 5547 | | if (imm16 & S16) |
| 5548 | | cpustate->RB(dst) = SRLB(cpustate, cpustate->RB(dst), -(INT16)imm16); |
| 5586 | GET_IMM8(OP1); |
| 5587 | if (imm8 & S08) |
| 5588 | cpustate->RB(dst) = SRLB(cpustate, cpustate->RB(dst), -(INT8)imm8); |
| 5549 | 5589 | else |
| 5550 | | cpustate->RB(dst) = SLLB(cpustate, cpustate->RB(dst), imm16); |
| 5590 | cpustate->RB(dst) = SLLB(cpustate, cpustate->RB(dst), imm8); |
| 5551 | 5591 | } |
| 5552 | 5592 | |
| 5553 | 5593 | /****************************************** |
| r19095 | r19096 | |
| 5592 | 5632 | static void ZB2_dddd_1001_imm8(z8000_state *cpustate) |
| 5593 | 5633 | { |
| 5594 | 5634 | GET_DST(OP0,NIB2); |
| 5595 | | GET_IMM16(OP1); |
| 5596 | | if (imm16 & S16) |
| 5597 | | cpustate->RB(dst) = SRAB(cpustate, cpustate->RB(dst), -(INT16)imm16); |
| 5635 | GET_IMM8(OP1); |
| 5636 | if (imm8 & S08) |
| 5637 | cpustate->RB(dst) = SRAB(cpustate, cpustate->RB(dst), -(INT8)imm8); |
| 5598 | 5638 | else |
| 5599 | | cpustate->RB(dst) = SLAB(cpustate, cpustate->RB(dst), imm16); |
| 5639 | cpustate->RB(dst) = SLAB(cpustate, cpustate->RB(dst), imm8); |
| 5600 | 5640 | } |
| 5601 | 5641 | |
| 5602 | 5642 | /****************************************** |
| r19095 | r19096 | |
| 5840 | 5880 | UINT8 xlt = RDMEM_B(cpustate, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, addr_from_reg(cpustate, dst))); |
| 5841 | 5881 | cpustate->RB(1) = xlt; /* load RH1 */ |
| 5842 | 5882 | if (xlt) CLR_Z; else SET_Z; |
| 5843 | | addr_to_reg(cpustate, dst, addr_add(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 5883 | add_to_addr_reg(cpustate, dst, 1); |
| 5844 | 5884 | if (--cpustate->RW(cnt)) CLR_V; else SET_V; |
| 5845 | 5885 | } |
| 5846 | 5886 | |
| r19095 | r19096 | |
| 5856 | 5896 | UINT8 xlt = RDMEM_B(cpustate, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, addr_from_reg(cpustate, dst))); |
| 5857 | 5897 | cpustate->RB(1) = xlt; /* load RH1 */ |
| 5858 | 5898 | if (xlt) CLR_Z; else SET_Z; |
| 5859 | | addr_to_reg(cpustate, dst, addr_add(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 5899 | add_to_addr_reg(cpustate, dst, 1); |
| 5860 | 5900 | if (--cpustate->RW(cnt)) { |
| 5861 | 5901 | CLR_V; |
| 5862 | 5902 | if (!xlt) |
| r19095 | r19096 | |
| 5877 | 5917 | UINT8 xlt = RDMEM_B(cpustate, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, addr_from_reg(cpustate, dst))); |
| 5878 | 5918 | cpustate->RB(1) = xlt; /* load RH1 */ |
| 5879 | 5919 | if (xlt) CLR_Z; else SET_Z; |
| 5880 | | addr_to_reg(cpustate, dst, addr_sub(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 5920 | sub_from_addr_reg(cpustate, dst, 1); |
| 5881 | 5921 | if (--cpustate->RW(cnt)) CLR_V; else SET_V; |
| 5882 | 5922 | } |
| 5883 | 5923 | |
| r19095 | r19096 | |
| 5893 | 5933 | UINT8 xlt = RDMEM_B(cpustate, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, addr_from_reg(cpustate, dst))); |
| 5894 | 5934 | cpustate->RB(1) = xlt; /* load RH1 */ |
| 5895 | 5935 | if (xlt) CLR_Z; else SET_Z; |
| 5896 | | addr_to_reg(cpustate, dst, addr_sub(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 5936 | sub_from_addr_reg(cpustate, dst, 1); |
| 5897 | 5937 | if (--cpustate->RW(cnt)) { |
| 5898 | 5938 | CLR_V; |
| 5899 | 5939 | if (!xlt) |
| r19095 | r19096 | |
| 5914 | 5954 | UINT8 xlt = RDMEM_B(cpustate, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, addr_from_reg(cpustate, dst))); |
| 5915 | 5955 | WRMEM_B(cpustate, addr_from_reg(cpustate, dst), xlt); |
| 5916 | 5956 | cpustate->RB(1) = xlt; /* destroy RH1 */ |
| 5917 | | addr_to_reg(cpustate, dst, addr_add(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 5957 | add_to_addr_reg(cpustate, dst, 1); |
| 5918 | 5958 | if (--cpustate->RW(cnt)) CLR_V; else SET_V; |
| 5919 | 5959 | } |
| 5920 | 5960 | |
| r19095 | r19096 | |
| 5930 | 5970 | UINT8 xlt = RDMEM_B(cpustate, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, addr_from_reg(cpustate, dst))); |
| 5931 | 5971 | WRMEM_B(cpustate, addr_from_reg(cpustate, dst), xlt); |
| 5932 | 5972 | cpustate->RB(1) = xlt; /* destroy RH1 */ |
| 5933 | | addr_to_reg(cpustate, dst, addr_add(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 5973 | add_to_addr_reg(cpustate, dst, 1); |
| 5934 | 5974 | if (--cpustate->RW(cnt)) { CLR_V; cpustate->pc -= 4; } else SET_V; |
| 5935 | 5975 | } |
| 5936 | 5976 | |
| r19095 | r19096 | |
| 5946 | 5986 | UINT8 xlt = RDMEM_B(cpustate, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, addr_from_reg(cpustate, dst))); |
| 5947 | 5987 | WRMEM_B(cpustate, addr_from_reg(cpustate, dst), xlt); |
| 5948 | 5988 | cpustate->RB(1) = xlt; /* destroy RH1 */ |
| 5949 | | addr_to_reg(cpustate, dst, addr_sub(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 5989 | sub_from_addr_reg(cpustate, dst, 1); |
| 5950 | 5990 | if (--cpustate->RW(cnt)) CLR_V; else SET_V; |
| 5951 | 5991 | } |
| 5952 | 5992 | |
| r19095 | r19096 | |
| 5962 | 6002 | UINT8 xlt = RDMEM_B(cpustate, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, addr_from_reg(cpustate, dst))); |
| 5963 | 6003 | WRMEM_B(cpustate, addr_from_reg(cpustate, dst), xlt); |
| 5964 | 6004 | cpustate->RB(1) = xlt; /* destroy RH1 */ |
| 5965 | | addr_to_reg(cpustate, dst, addr_sub(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 6005 | sub_from_addr_reg(cpustate, dst, 1); |
| 5966 | 6006 | if (--cpustate->RW(cnt)) { CLR_V; cpustate->pc -= 4; } else SET_V; |
| 5967 | 6007 | } |
| 5968 | 6008 | |
| r19095 | r19096 | |
| 6010 | 6050 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6011 | 6051 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6012 | 6052 | } |
| 6013 | | addr_to_reg(cpustate, src, addr_add(cpustate, addr_from_reg(cpustate, src), 1)); |
| 6053 | add_to_addr_reg(cpustate, src, 1); |
| 6014 | 6054 | if (--cpustate->RW(cnt)) CLR_V; else SET_V; |
| 6015 | 6055 | } |
| 6016 | 6056 | |
| r19095 | r19096 | |
| 6026 | 6066 | GET_DST(OP1,NIB2); |
| 6027 | 6067 | GET_CCC(OP1,NIB3); /* repeat? */ |
| 6028 | 6068 | WRMEM_B(cpustate, addr_from_reg(cpustate, dst), RDMEM_B(cpustate, addr_from_reg(cpustate, src))); |
| 6029 | | addr_to_reg(cpustate, dst, addr_add(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 6030 | | addr_to_reg(cpustate, src, addr_add(cpustate, addr_from_reg(cpustate, src), 1)); |
| 6069 | add_to_addr_reg(cpustate, src, 1); |
| 6070 | add_to_addr_reg(cpustate, dst, 1); |
| 6031 | 6071 | if (--cpustate->RW(cnt)) { CLR_V; if (cc == 0) cpustate->pc -= 4; } else SET_V; |
| 6032 | 6072 | } |
| 6033 | 6073 | |
| r19095 | r19096 | |
| 6060 | 6100 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6061 | 6101 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6062 | 6102 | } |
| 6063 | | addr_to_reg(cpustate, dst, addr_add(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 6064 | | addr_to_reg(cpustate, src, addr_add(cpustate, addr_from_reg(cpustate, src), 1)); |
| 6103 | add_to_addr_reg(cpustate, src, 1); |
| 6104 | add_to_addr_reg(cpustate, dst, 1); |
| 6065 | 6105 | if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; |
| 6066 | 6106 | } |
| 6067 | 6107 | |
| r19095 | r19096 | |
| 6094 | 6134 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6095 | 6135 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6096 | 6136 | } |
| 6097 | | addr_to_reg(cpustate, src, addr_add(cpustate, addr_from_reg(cpustate, src), 1)); |
| 6137 | add_to_addr_reg(cpustate, src, 1); |
| 6098 | 6138 | if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; |
| 6099 | 6139 | } |
| 6100 | 6140 | |
| r19095 | r19096 | |
| 6127 | 6167 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6128 | 6168 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6129 | 6169 | } |
| 6130 | | addr_to_reg(cpustate, dst, addr_add(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 6131 | | addr_to_reg(cpustate, src, addr_add(cpustate, addr_from_reg(cpustate, src), 1)); |
| 6170 | add_to_addr_reg(cpustate, src, 1); |
| 6171 | add_to_addr_reg(cpustate, dst, 1); |
| 6132 | 6172 | if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; |
| 6133 | 6173 | } |
| 6134 | 6174 | |
| r19095 | r19096 | |
| 6161 | 6201 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6162 | 6202 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6163 | 6203 | } |
| 6164 | | addr_to_reg(cpustate, src, addr_sub(cpustate, addr_from_reg(cpustate, src), 1)); |
| 6204 | sub_from_addr_reg(cpustate, src, 1); |
| 6165 | 6205 | if (--cpustate->RW(cnt)) CLR_V; else SET_V; |
| 6166 | 6206 | } |
| 6167 | 6207 | |
| r19095 | r19096 | |
| 6177 | 6217 | GET_DST(OP1,NIB2); |
| 6178 | 6218 | GET_CCC(OP1,NIB3); |
| 6179 | 6219 | WRMEM_B(cpustate, addr_from_reg(cpustate, dst), RDMEM_B(cpustate, addr_from_reg(cpustate, src))); |
| 6180 | | addr_to_reg(cpustate, dst, addr_sub(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 6181 | | addr_to_reg(cpustate, src, addr_sub(cpustate, addr_from_reg(cpustate, src), 1)); |
| 6220 | sub_from_addr_reg(cpustate, src, 1); |
| 6221 | sub_from_addr_reg(cpustate, dst, 1); |
| 6182 | 6222 | if (--cpustate->RW(cnt)) { CLR_V; if (cc == 0) cpustate->pc -= 4; } else SET_V; |
| 6183 | 6223 | } |
| 6184 | 6224 | |
| r19095 | r19096 | |
| 6211 | 6251 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6212 | 6252 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6213 | 6253 | } |
| 6214 | | addr_to_reg(cpustate, dst, addr_sub(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 6215 | | addr_to_reg(cpustate, src, addr_sub(cpustate, addr_from_reg(cpustate, src), 1)); |
| 6254 | sub_from_addr_reg(cpustate, src, 1); |
| 6255 | sub_from_addr_reg(cpustate, dst, 1); |
| 6216 | 6256 | if (--cpustate->RW(cnt)) CLR_V; else SET_V; |
| 6217 | 6257 | } |
| 6218 | 6258 | |
| r19095 | r19096 | |
| 6245 | 6285 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6246 | 6286 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6247 | 6287 | } |
| 6248 | | addr_to_reg(cpustate, src, addr_sub(cpustate, addr_from_reg(cpustate, src), 1)); |
| 6288 | sub_from_addr_reg(cpustate, src, 1); |
| 6249 | 6289 | if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; |
| 6250 | 6290 | } |
| 6251 | 6291 | |
| r19095 | r19096 | |
| 6278 | 6318 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6279 | 6319 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6280 | 6320 | } |
| 6281 | | addr_to_reg(cpustate, dst, addr_sub(cpustate, addr_from_reg(cpustate, dst), 1)); |
| 6282 | | addr_to_reg(cpustate, src, addr_sub(cpustate, addr_from_reg(cpustate, src), 1)); |
| 6321 | sub_from_addr_reg(cpustate, src, 1); |
| 6322 | sub_from_addr_reg(cpustate, dst, 1); |
| 6283 | 6323 | if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; |
| 6284 | 6324 | } |
| 6285 | 6325 | |
| r19095 | r19096 | |
| 6312 | 6352 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6313 | 6353 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6314 | 6354 | } |
| 6315 | | addr_to_reg(cpustate, src, addr_add(cpustate, addr_from_reg(cpustate, src), 2)); |
| 6355 | add_to_addr_reg(cpustate, src, 2); |
| 6316 | 6356 | if (--cpustate->RW(cnt)) CLR_V; else SET_V; |
| 6317 | 6357 | } |
| 6318 | 6358 | |
| r19095 | r19096 | |
| 6328 | 6368 | GET_DST(OP1,NIB2); |
| 6329 | 6369 | GET_CCC(OP1,NIB3); |
| 6330 | 6370 | WRMEM_W(cpustate, addr_from_reg(cpustate, dst), RDMEM_W(cpustate, addr_from_reg(cpustate, src))); |
| 6331 | | addr_to_reg(cpustate, src, addr_add(cpustate, addr_from_reg(cpustate, src), 2)); |
| 6332 | | addr_to_reg(cpustate, dst, addr_add(cpustate, addr_from_reg(cpustate, dst), 2)); |
| 6371 | add_to_addr_reg(cpustate, src, 2); |
| 6372 | add_to_addr_reg(cpustate, dst, 2); |
| 6333 | 6373 | if (--cpustate->RW(cnt)) { CLR_V; if (cc == 0) cpustate->pc -= 4; } else SET_V; |
| 6334 | 6374 | } |
| 6335 | 6375 | |
| r19095 | r19096 | |
| 6362 | 6402 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6363 | 6403 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6364 | 6404 | } |
| 6365 | | addr_to_reg(cpustate, src, addr_add(cpustate, addr_from_reg(cpustate, src), 2)); |
| 6366 | | addr_to_reg(cpustate, dst, addr_add(cpustate, addr_from_reg(cpustate, dst), 2)); |
| 6405 | add_to_addr_reg(cpustate, src, 2); |
| 6406 | add_to_addr_reg(cpustate, dst, 2); |
| 6367 | 6407 | if (--cpustate->RW(cnt)) CLR_V; else SET_V; |
| 6368 | 6408 | } |
| 6369 | 6409 | |
| r19095 | r19096 | |
| 6396 | 6436 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6397 | 6437 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6398 | 6438 | } |
| 6399 | | addr_to_reg(cpustate, src, addr_add(cpustate, addr_from_reg(cpustate, src), 2)); |
| 6439 | add_to_addr_reg(cpustate, src, 2); |
| 6400 | 6440 | if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; |
| 6401 | 6441 | } |
| 6402 | 6442 | |
| r19095 | r19096 | |
| 6429 | 6469 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6430 | 6470 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6431 | 6471 | } |
| 6432 | | addr_to_reg(cpustate, src, addr_add(cpustate, addr_from_reg(cpustate, src), 2)); |
| 6433 | | addr_to_reg(cpustate, dst, addr_add(cpustate, addr_from_reg(cpustate, dst), 2)); |
| 6472 | add_to_addr_reg(cpustate, src, 2); |
| 6473 | add_to_addr_reg(cpustate, dst, 2); |
| 6434 | 6474 | if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; |
| 6435 | 6475 | } |
| 6436 | 6476 | |
| r19095 | r19096 | |
| 6463 | 6503 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6464 | 6504 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6465 | 6505 | } |
| 6466 | | addr_to_reg(cpustate, src, addr_sub(cpustate, addr_from_reg(cpustate, src), 2)); |
| 6506 | sub_from_addr_reg(cpustate, src, 2); |
| 6467 | 6507 | if (--cpustate->RW(cnt)) CLR_V; else SET_V; |
| 6468 | 6508 | } |
| 6469 | 6509 | |
| r19095 | r19096 | |
| 6479 | 6519 | GET_DST(OP1,NIB2); |
| 6480 | 6520 | GET_CCC(OP1,NIB3); |
| 6481 | 6521 | WRMEM_W(cpustate, addr_from_reg(cpustate, dst), RDMEM_W(cpustate, addr_from_reg(cpustate, src))); |
| 6482 | | addr_to_reg(cpustate, dst, addr_sub(cpustate, addr_from_reg(cpustate, dst), 2)); |
| 6483 | | addr_to_reg(cpustate, src, addr_sub(cpustate, addr_from_reg(cpustate, src), 2)); |
| 6522 | sub_from_addr_reg(cpustate, src, 2); |
| 6523 | sub_from_addr_reg(cpustate, dst, 2); |
| 6484 | 6524 | if (--cpustate->RW(cnt)) { CLR_V; if (cc == 0) cpustate->pc -= 4; } else SET_V; |
| 6485 | 6525 | } |
| 6486 | 6526 | |
| r19095 | r19096 | |
| 6513 | 6553 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6514 | 6554 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6515 | 6555 | } |
| 6516 | | addr_to_reg(cpustate, dst, addr_sub(cpustate, addr_from_reg(cpustate, dst), 2)); |
| 6517 | | addr_to_reg(cpustate, src, addr_sub(cpustate, addr_from_reg(cpustate, src), 2)); |
| 6556 | sub_from_addr_reg(cpustate, src, 2); |
| 6557 | sub_from_addr_reg(cpustate, dst, 2); |
| 6518 | 6558 | if (--cpustate->RW(cnt)) CLR_V; else SET_V; |
| 6519 | 6559 | } |
| 6520 | 6560 | |
| r19095 | r19096 | |
| 6547 | 6587 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6548 | 6588 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6549 | 6589 | } |
| 6550 | | addr_to_reg(cpustate, src, addr_sub(cpustate, addr_from_reg(cpustate, src), 2)); |
| 6590 | sub_from_addr_reg(cpustate, src, 2); |
| 6551 | 6591 | if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; |
| 6552 | 6592 | } |
| 6553 | 6593 | |
| r19095 | r19096 | |
| 6580 | 6620 | case 14: if (CCE) SET_Z; else CLR_Z; break; |
| 6581 | 6621 | case 15: if (CCF) SET_Z; else CLR_Z; break; |
| 6582 | 6622 | } |
| 6583 | | addr_to_reg(cpustate, dst, addr_sub(cpustate, addr_from_reg(cpustate, dst), 2)); |
| 6584 | | addr_to_reg(cpustate, src, addr_sub(cpustate, addr_from_reg(cpustate, src), 2)); |
| 6623 | sub_from_addr_reg(cpustate, src, 2); |
| 6624 | sub_from_addr_reg(cpustate, dst, 2); |
| 6585 | 6625 | if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; |
| 6586 | 6626 | } |
| 6587 | 6627 | |