MAME SVN History

199869 Revisions

r19031 Monday 19th November, 2012 at 08:40:08 UTC by Miodrag Milanović
Cleanups and version bump (nw)

[hash]	cd32.xml neocd.xml
[src]	version.c
[src/emu/cpu/avr8]	avr8.c avr8.h
[src/emu/cpu/i386]	i386.c
[src/emu/cpu/m6502]	m4510.c m6502make.c m6510.c om6502.lst om65c02.lst om65ce02.lst
[src/emu/cpu/z8000]	z8000ops.c
[src/emu/machine]	scsicd.c
[src/emu/sound]	tms5110r.c tms5220.c
[src/emu/video]	pc_vga.c
[src/mame]	mame.lst
[src/mame/audio]	8080bw.c
[src/mame/drivers]	aerofgt.c btime.c cntsteer.c cps1.c ddenlovr.c dec8.c firebeat.c funworld.c goldstar.c naomi.c s6a.c scramble.c supercrd.c vastar.c zn.c
[src/mame/machine]	pgmcrypt.c scramble.c zndip.c znsec.c
[src/mame/video]	f1gp.c galaxold.c konicdev.c vastar.c vsystem_spr2.c
[src/mess/drivers]	a7800.c adam.c alphasma.c altos5.c apc.c apple3.c bw2.c ng_aes.c pc100.c pc9801.c
[src/mess/machine]	adam_ddp.c adam_fdc.c adam_ide.c adam_kb.c adam_prn.c adam_spi.c adamlink.c
[src/mess/video]	isa_cga.c isa_cga.h

trunk/hash/cd32.xml
r19030	r19031
4	4
5	5	<!--- Preliminary List -->
6	6
7
8		<!-- playable but there's a scrolling glitch every few frames -->
	7
	8	<!-- playable but there's a scrolling glitch every few frames -->
9	9	<software name="morph" supported="partial">
10	10	<description>Morph</description>
11	11	<year>1993</year>
r19030	r19031
137	137	</diskarea>
138	138	</part>
139	139	</software>
140
141
142	140
	141
	142
143	143	</softwarelist>

trunk/hash/neocd.xml
r19030	r19031
1161	1161	</software>
1162	1162
1163	1163	-->
1164
	1164
1165	1165	</softwarelist>

trunk/src/mame/mame.lst
r19030	r19031
5042	5042	ggxxsla // 2005.09 Guilty Gear XX Slash (Rev A)
5043	5043	radirgy // 2005.10 Radirgy
5044	5044	undefeat // 2005.10 Under Defeat
5045		radirgya // 2005.12 Radirgy (Rev A)
	5045	radirgya // 2005.12 Radirgy (Rev A)
5046	5046	// 2005.?? Dragon Treasure 3 (Rev A)
5047	5047	// 2005.?? ExZeus
5048	5048	// 2005.?? Mushiking The King Of Beetles II ENG

trunk/src/mame/audio/8080bw.c
r19030	r19031
1107	1107	UINT8 rising_bits = data & ~m_port_2_last_extra;
1108	1108
1109	1109	if (rising_bits & 0x01) m_samples->start(0, 6); /* Lands on top of building, wife kicks man */
1110		//if (rising_bits & 0x02) m_samples->start(3, 7); /* deposit money, start intermission, end game */
1111		//if (rising_bits & 0x04) m_samples->start(4, 7); /* deposit money, start intermission, Slides down rope */
1112		//if (rising_bits & 0x08) m_samples->start(5, 7); /* start intermission, end game */
	1110	//if (rising_bits & 0x02) m_samples->start(3, 7); /* deposit money, start intermission, end game */
	1111	//if (rising_bits & 0x04) m_samples->start(4, 7); /* deposit money, start intermission, Slides down rope */
	1112	//if (rising_bits & 0x08) m_samples->start(5, 7); /* start intermission, end game */
1113	1113	if (rising_bits & 0x10) m_samples->start(3, 1); /* Dog barking */
1114	1114
1115	1115	m_color_map = data & 0x40;

trunk/src/mame/machine/pgmcrypt.c
r19030	r19031
161	161	for(i=0; i<rom_size/2; i++) {
162	162	UINT16 x = src[i];
163	163
164		IGS27_CRYPT1_ALT
	164	IGS27_CRYPT1_ALT
165	165	IGS27_CRYPT2_ALT2
166		IGS27_CRYPT3_ALT2
167		IGS27_CRYPT4
168		IGS27_CRYPT5
169		IGS27_CRYPT6
170		IGS27_CRYPT7
171		IGS27_CRYPT8_ALT
	166	IGS27_CRYPT3_ALT2
	167	IGS27_CRYPT4
	168	IGS27_CRYPT5
	169	IGS27_CRYPT6
	170	IGS27_CRYPT7
	171	IGS27_CRYPT8_ALT
172	172
173	173	x ^= kovsh_tab[i & 0xff] << 8;
174	174
r19030	r19031
209	209
210	210	IGS27_CRYPT1_ALT
211	211	IGS27_CRYPT2_ALT3
212		IGS27_CRYPT3_ALT2
213		IGS27_CRYPT4
	212	IGS27_CRYPT3_ALT2
	213	IGS27_CRYPT4
214	214	IGS27_CRYPT5_ALT
215		IGS27_CRYPT6
	215	IGS27_CRYPT6
216	216	IGS27_CRYPT7_ALT
217		IGS27_CRYPT8
	217	IGS27_CRYPT8
218	218
219	219	x ^= photoy2k_tab[i & 0xff] << 8;
220	220
r19030	r19031
252	252	for(i=0; i<rom_size/2; i++) {
253	253	UINT16 x = src[i];
254	254
255		IGS27_CRYPT1
256		IGS27_CRYPT3_ALT2
257		IGS27_CRYPT4
258		IGS27_CRYPT5
259		IGS27_CRYPT6_ALT
260		IGS27_CRYPT7
261		IGS27_CRYPT8
	255	IGS27_CRYPT1
	256	IGS27_CRYPT3_ALT2
	257	IGS27_CRYPT4
	258	IGS27_CRYPT5
	259	IGS27_CRYPT6_ALT
	260	IGS27_CRYPT7
	261	IGS27_CRYPT8
262	262
263	263	x = x ^ pstar[(i & 255)] << 8;
264	264	src[i] = x ;
r19030	r19031
294	294	for(i=0; i<rom_size/2; i++) {
295	295	UINT16 x = src[i];
296	296
297		IGS27_CRYPT1_ALT
298		IGS27_CRYPT2
299		IGS27_CRYPT3
	297	IGS27_CRYPT1_ALT
	298	IGS27_CRYPT2
	299	IGS27_CRYPT3
300	300	IGS27_CRYPT4_ALT
301		IGS27_CRYPT5
302		IGS27_CRYPT6
303		IGS27_CRYPT7
304		IGS27_CRYPT8
	301	IGS27_CRYPT5
	302	IGS27_CRYPT6
	303	IGS27_CRYPT7
	304	IGS27_CRYPT8
305	305
306	306	x ^= dfront_tab[(i>> 1) & 0xff] << 8;
307	307
r19030	r19031
343	343	// NO CRYPT2
344	344	// NO CRYPT3
345	345	IGS27_CRYPT4_ALT
346		IGS27_CRYPT5
347		IGS27_CRYPT6
348		IGS27_CRYPT7_ALT
349		IGS27_CRYPT8_ALT
	346	IGS27_CRYPT5
	347	IGS27_CRYPT6
	348	IGS27_CRYPT7_ALT
	349	IGS27_CRYPT8_ALT
350	350
351	351	x ^= ddp2_tab[(i>> 1) & 0xff] << 8;
352	352
r19030	r19031
384	384	for(i=0; i<rom_size/2; i++) {
385	385	UINT16 x = src[i];
386	386
387		IGS27_CRYPT1
388		IGS27_CRYPT2_ALT
389		IGS27_CRYPT3_ALT2
390		IGS27_CRYPT4
391		IGS27_CRYPT5
392		IGS27_CRYPT6_ALT
393		IGS27_CRYPT7
394		IGS27_CRYPT8_ALT
	387	IGS27_CRYPT1
	388	IGS27_CRYPT2_ALT
	389	IGS27_CRYPT3_ALT2
	390	IGS27_CRYPT4
	391	IGS27_CRYPT5
	392	IGS27_CRYPT6_ALT
	393	IGS27_CRYPT7
	394	IGS27_CRYPT8_ALT
395	395
396	396	x ^= mm_tab[(i>> 1) & 0xff] << 8;
397	397
r19030	r19031
428	428	for(i=0; i<rom_size/2; i++) {
429	429	UINT16 x = src[i];
430	430
431		IGS27_CRYPT1_ALT
	431	IGS27_CRYPT1_ALT
432	432	// NO CRYPT2
433		IGS27_CRYPT3
	433	IGS27_CRYPT3
434	434	IGS27_CRYPT4_ALT
435	435	IGS27_CRYPT5_ALT
436	436	IGS27_CRYPT6_ALT
437		IGS27_CRYPT7_ALT
	437	IGS27_CRYPT7_ALT
438	438	IGS27_CRYPT8_ALT
439	439
440	440	x ^= kov2_tab[(i >> 1) & 0xff] << 8;
r19030	r19031
472	472	for(i=0; i<rom_size/2; i++) {
473	473	UINT16 x = src[i];
474	474
475		IGS27_CRYPT1_ALT
476		IGS27_CRYPT2_ALT
477		IGS27_CRYPT3
478		IGS27_CRYPT4
479		IGS27_CRYPT5
480		IGS27_CRYPT6
481		IGS27_CRYPT7
482		IGS27_CRYPT8_ALT
	475	IGS27_CRYPT1_ALT
	476	IGS27_CRYPT2_ALT
	477	IGS27_CRYPT3
	478	IGS27_CRYPT4
	479	IGS27_CRYPT5
	480	IGS27_CRYPT6
	481	IGS27_CRYPT7
	482	IGS27_CRYPT8_ALT
483	483
484	484	x ^= kov2p_tab[(i >> 1) & 0xff] << 8;
485	485
r19030	r19031
516	516	for(i=0; i<rom_size/2; i++) {
517	517	UINT16 x = src[i];
518	518
519		IGS27_CRYPT1_ALT
520		IGS27_CRYPT2_ALT
521		IGS27_CRYPT3_ALT2
522		IGS27_CRYPT4
523		IGS27_CRYPT5
524		IGS27_CRYPT6_ALT
525		IGS27_CRYPT7
526		IGS27_CRYPT8
	519	IGS27_CRYPT1_ALT
	520	IGS27_CRYPT2_ALT
	521	IGS27_CRYPT3_ALT2
	522	IGS27_CRYPT4
	523	IGS27_CRYPT5
	524	IGS27_CRYPT6_ALT
	525	IGS27_CRYPT7
	526	IGS27_CRYPT8
527	527
528	528	x ^= puzzli2_tab[i & 0xff] << 8;
529	529	src[i] = x;
r19030	r19031
560	560	for(i=0; i<rom_size/2; i++) {
561	561	UINT16 x = src[i];
562	562
563		IGS27_CRYPT1_ALT
564		IGS27_CRYPT2
565		IGS27_CRYPT3
566		IGS27_CRYPT4_ALT
567		IGS27_CRYPT5
568		IGS27_CRYPT6_ALT
569		IGS27_CRYPT7
570		IGS27_CRYPT8_ALT
	563	IGS27_CRYPT1_ALT
	564	IGS27_CRYPT2
	565	IGS27_CRYPT3
	566	IGS27_CRYPT4_ALT
	567	IGS27_CRYPT5
	568	IGS27_CRYPT6_ALT
	569	IGS27_CRYPT7
	570	IGS27_CRYPT8_ALT
571	571
572	572	x ^= theglad_tab[(i >> 1) & 0xff] << 8;
573	573
r19030	r19031
605	605	for(i=0; i<rom_size/2; i++) {
606	606	unsigned short x = src[i];
607	607
608		IGS27_CRYPT1
609		IGS27_CRYPT2_ALT
610		IGS27_CRYPT3_ALT2
611		IGS27_CRYPT4
612		IGS27_CRYPT5_ALT
613		IGS27_CRYPT6
614		IGS27_CRYPT7
615		IGS27_CRYPT8_ALT
	608	IGS27_CRYPT1
	609	IGS27_CRYPT2_ALT
	610	IGS27_CRYPT3_ALT2
	611	IGS27_CRYPT4
	612	IGS27_CRYPT5_ALT
	613	IGS27_CRYPT6
	614	IGS27_CRYPT7
	615	IGS27_CRYPT8_ALT
616	616
617	617	x ^= oldsplus_tab[i & 0xff] << 8;
618	618
r19030	r19031
650	650	for(i=0; i<rom_size/2; i++) {
651	651	unsigned short x = src[i];
652	652
653		IGS27_CRYPT1_ALT
654		IGS27_CRYPT2_ALT2
655		IGS27_CRYPT3_ALT2
656		IGS27_CRYPT4_ALT
657		IGS27_CRYPT5
658		IGS27_CRYPT6_ALT
659		IGS27_CRYPT7
660		IGS27_CRYPT8_ALT
	653	IGS27_CRYPT1_ALT
	654	IGS27_CRYPT2_ALT2
	655	IGS27_CRYPT3_ALT2
	656	IGS27_CRYPT4_ALT
	657	IGS27_CRYPT5
	658	IGS27_CRYPT6_ALT
	659	IGS27_CRYPT7
	660	IGS27_CRYPT8_ALT
661	661
662	662	x ^= kovshp_tab[i & 0xff] << 8;
663	663
r19030	r19031
695	695	for(i=0; i<rom_size/2; i++) {
696	696	UINT16 x = src[i];
697	697
698		IGS27_CRYPT1
699		IGS27_CRYPT2
700		IGS27_CRYPT3
701		IGS27_CRYPT4
702		IGS27_CRYPT5
703		IGS27_CRYPT6
704		IGS27_CRYPT7
705		IGS27_CRYPT8_ALT
	698	IGS27_CRYPT1
	699	IGS27_CRYPT2
	700	IGS27_CRYPT3
	701	IGS27_CRYPT4
	702	IGS27_CRYPT5
	703	IGS27_CRYPT6
	704	IGS27_CRYPT7
	705	IGS27_CRYPT8_ALT
706	706
707	707	x ^= killbldp_tab[(i >> 1) & 0xff] << 8;
708	708
r19030	r19031
721	721	for(i=0; i<rom_size/2; i++) {
722	722	UINT16 x = src[i];
723	723
724		IGS27_CRYPT1_ALT
725		IGS27_CRYPT2_ALT
726		IGS27_CRYPT3
727		IGS27_CRYPT4_ALT
728		IGS27_CRYPT5_ALT
729		IGS27_CRYPT6
730		IGS27_CRYPT7
731		IGS27_CRYPT8_ALT
	724	IGS27_CRYPT1_ALT
	725	IGS27_CRYPT2_ALT
	726	IGS27_CRYPT3
	727	IGS27_CRYPT4_ALT
	728	IGS27_CRYPT5_ALT
	729	IGS27_CRYPT6
	730	IGS27_CRYPT7
	731	IGS27_CRYPT8_ALT
732	732
733	733	src[i] = x;
734	734	}
r19030	r19031
765	765
766	766	// preliminary!
767	767	IGS27_CRYPT1_ALT; // ok?
768		IGS27_CRYPT2_ALT3
	768	IGS27_CRYPT2_ALT3
769	769	IGS27_CRYPT3
770	770	IGS27_CRYPT4 // ok?
771	771	IGS27_CRYPT5_ALT //
772	772	IGS27_CRYPT6_ALT // ok?
773	773	IGS27_CRYPT7
774		IGS27_CRYPT8_ALT
	774	IGS27_CRYPT8_ALT
775	775
776	776	x ^= svgpcb_tab[(i >> 1) & 0xff] << 8;
777	777
r19030	r19031
811	811	UINT16 x = src[i];
812	812
813	813	IGS27_CRYPT1
814		IGS27_CRYPT2_ALT3
815		IGS27_CRYPT3_ALT
816		IGS27_CRYPT4_ALT
	814	IGS27_CRYPT2_ALT3
	815	IGS27_CRYPT3_ALT
	816	IGS27_CRYPT4_ALT
817	817	IGS27_CRYPT5
818	818	IGS27_CRYPT6_ALT
819	819	IGS27_CRYPT7
r19030	r19031
859	859	IGS27_CRYPT1
860	860	IGS27_CRYPT2_ALT
861	861	IGS27_CRYPT3_ALT3
862		IGS27_CRYPT4_ALT
	862	IGS27_CRYPT4_ALT
863	863	IGS27_CRYPT5
864	864	IGS27_CRYPT6
865	865	IGS27_CRYPT7
866		IGS27_CRYPT8_ALT
	866	IGS27_CRYPT8_ALT
867	867
868	868
869	869	x ^= ket_tab[i & 0xff] << 8;
r19030	r19031
903	903	UINT16 x = src[i];
904	904
905	905	IGS27_CRYPT1
906		IGS27_CRYPT2_ALT3
907		IGS27_CRYPT3_ALT2
908		IGS27_CRYPT4_ALT
909		IGS27_CRYPT5_ALT
	906	IGS27_CRYPT2_ALT3
	907	IGS27_CRYPT3_ALT2
	908	IGS27_CRYPT4_ALT
	909	IGS27_CRYPT5_ALT
910	910	IGS27_CRYPT6_ALT
911	911	IGS27_CRYPT7
912		IGS27_CRYPT8_ALT
	912	IGS27_CRYPT8_ALT
913	913
914	914	x ^= espgal_tab[i & 0xff] << 8;
915	915
r19030	r19031
953	953	IGS27_CRYPT2
954	954	IGS27_CRYPT3
955	955	IGS27_CRYPT4
956		IGS27_CRYPT5_ALT
	956	IGS27_CRYPT5_ALT
957	957	IGS27_CRYPT6
958	958	IGS27_CRYPT7
959		IGS27_CRYPT8_ALT
	959	IGS27_CRYPT8_ALT
960	960
961	961	x ^= happy6in1_tab[(i >> 1) & 0xff] << 8;
962	962
r19030	r19031
997	997	{
998	998	UINT16 x = src[i];
999	999
1000		IGS27_CRYPT1_ALT2
1001		IGS27_CRYPT2_ALT
1002		IGS27_CRYPT3_ALT2
1003		IGS27_CRYPT4
1004		IGS27_CRYPT5
1005		IGS27_CRYPT6_ALT
1006		IGS27_CRYPT7
1007		IGS27_CRYPT8
	1000	IGS27_CRYPT1_ALT2
	1001	IGS27_CRYPT2_ALT
	1002	IGS27_CRYPT3_ALT2
	1003	IGS27_CRYPT4
	1004	IGS27_CRYPT5
	1005	IGS27_CRYPT6_ALT
	1006	IGS27_CRYPT7
	1007	IGS27_CRYPT8
1008	1008
1009	1009	x ^= sdwx_tab[(i >> 1) & 0xff] << 8;
1010	1010
r19030	r19031
1045	1045	IGS27_CRYPT1
1046	1046	// IGS27_CRYPT2
1047	1047	// IGS27_CRYPT3
1048		IGS27_CRYPT4_ALT
	1048	IGS27_CRYPT4_ALT
1049	1049	// IGS27_CRYPT5
1050	1050	IGS27_CRYPT6
1051		IGS27_CRYPT7_ALT
	1051	IGS27_CRYPT7_ALT
1052	1052	IGS27_CRYPT8
1053	1053
1054	1054	x ^= hauntedh_tab[(i>> 1) & 0xff] << 8;
r19030	r19031
1399	1399	IGS27_CRYPT1
1400	1400	// IGS27_CRYPT2
1401	1401	// IGS27_CRYPT3
1402		IGS27_CRYPT4_ALT
	1402	IGS27_CRYPT4_ALT
1403	1403	// IGS27_CRYPT5
1404	1404	IGS27_CRYPT6_ALT
1405	1405	IGS27_CRYPT7
1406		IGS27_CRYPT8_ALT
	1406	IGS27_CRYPT8_ALT
1407	1407
1408	1408	x ^= lhzb4_tab[(i>> 1) & 0xff] << 8;
1409	1409
r19030	r19031
1443	1443	UINT16 x = src[i];
1444	1444
1445	1445	// might not be 100% correct...
1446		IGS27_CRYPT1
	1446	IGS27_CRYPT1
1447	1447	// IGS27_CRYPT2
1448		IGS27_CRYPT3_ALT2
1449		IGS27_CRYPT4
	1448	IGS27_CRYPT3_ALT2
	1449	IGS27_CRYPT4
1450	1450	// IGS27_CRYPT5
1451		IGS27_CRYPT6_ALT
1452		IGS27_CRYPT7
1453		IGS27_CRYPT8
	1451	IGS27_CRYPT6_ALT
	1452	IGS27_CRYPT7
	1453	IGS27_CRYPT8
1454	1454
1455	1455	x ^= fearless_tab[(i>> 1) & 0xff] << 8;
1456	1456

trunk/src/mame/machine/zndip.c
r19030	r19031
30	30	{
31	31	data_out(0, PSX_SIO_IN_DATA \| PSX_SIO_IN_DSR);
32	32	}
33
	33
34	34	m_select = select;
35	35	}
36	36	}
r19030	r19031
41	41	{
42	42	int dip = m_data_handler();
43	43	int bit = ( ( dip >> m_bit ) & 1 );
44		// verboselog( machine, 2, "read dip %02x -> %02x\n", n_data, bit * PSX_SIO_IN_DATA );
	44	// verboselog( machine, 2, "read dip %02x -> %02x\n", n_data, bit * PSX_SIO_IN_DATA );
45	45	data_out( bit * PSX_SIO_IN_DATA, PSX_SIO_IN_DATA );
46	46	m_bit++;
47	47	m_bit &= 7;

trunk/src/mame/machine/scramble.c
r19030	r19031
637	637	m_harem_decrypt_mode = ((m_harem_decrypt_mode >> 1) \| ((m_harem_decrypt_bit & 1) << 3)) & 0x0f;
638	638	m_harem_decrypt_count++;
639	639
640		// logerror("%s: decrypt mode = %02x, count = %x\n", machine().describe_context(), m_harem_decrypt_mode, m_harem_decrypt_count);
	640	// logerror("%s: decrypt mode = %02x, count = %x\n", machine().describe_context(), m_harem_decrypt_mode, m_harem_decrypt_count);
641	641	}
642	642
643	643	m_harem_decrypt_clk = data;
r19030	r19031
654	654	logerror("%s: warning, unknown decrypt mode = %02x\n", machine().describe_context(), m_harem_decrypt_mode);
655	655	bank = 0;
656	656	}
657
	657
658	658	membank("rombank")->set_base (m_harem_decrypted_data + 0x2000 * bank);
659	659	membank("rombank")->set_base_decrypted (m_harem_decrypted_opcodes + 0x2000 * bank);
660	660
661		// logerror("%s: decrypt mode = %02x (bank %x) active\n", machine().describe_context(), m_harem_decrypt_mode, bank);
	661	// logerror("%s: decrypt mode = %02x (bank %x) active\n", machine().describe_context(), m_harem_decrypt_mode, bank);
662	662
663	663	m_harem_decrypt_mode = 0;
664	664	m_harem_decrypt_count = 0;
r19030	r19031
670	670	m_harem_decrypt_mode = 0;
671	671	m_harem_decrypt_count = 0;
672	672
673		// logerror("%s: decrypt mode reset\n", machine().describe_context());
	673	// logerror("%s: decrypt mode reset\n", machine().describe_context());
674	674	}
675	675
676	676	DRIVER_INIT_MEMBER(scramble_state,harem)

trunk/src/mame/machine/znsec.c
r19030	r19031
172	172	{
173	173	data_out(0, PSX_SIO_IN_DATA);
174	174	}
175
	175
176	176	m_select = select;
177	177	}
178	178	}

trunk/src/mame/video/konicdev.c
r19030	r19031
10321	10321
10322	10322	x = (x + 320) * 256;
10323	10323	y = (y + 208) * 256;
10324		// xx = (xx);
	10324	// xx = (xx);
10325	10325	xy = (-xy);
10326	10326	yx = (-yx);
10327		// yy = (yy);
	10327	// yy = (yy);
10328	10328
10329	10329	if ((k001604->reg[0x6c / 4] & (0x08 >> layer)) != 0)
10330	10330	{

trunk/src/mame/video/f1gp.c
r19030	r19031
82	82	UINT32 f1gp_state::f1gp_old_tile_callback( UINT32 code )
83	83	{
84	84	return m_spr1cgram[code % (m_spr1cgram.bytes()/2)];
85		}
	85	}
86	86
87	87	UINT32 f1gp_state::f1gp_ol2_tile_callback( UINT32 code )
88	88	{

trunk/src/mame/video/vastar.c
r19030	r19031
130	130	UINT8 *spriteram_3 = state->m_spriteram3;
131	131	int offs;
132	132
133		// for (offs = 0; offs < 0x40; offs += 2)
	133	// for (offs = 0; offs < 0x40; offs += 2)
134	134	for (offs = 0x40-2; offs >=0; offs -= 2)
135	135	{
136	136	int code, sx, sy, color, flipx, flipy;

trunk/src/mame/video/galaxold.c
r19030	r19031
790	790	{
791	791	video_start_common(machine());
792	792	m_bg_tilemap = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(galaxold_state::harem_get_tile_info),this),TILEMAP_SCAN_ROWS,8,8,32,32);
793		// m_bg_tilemap->set_transparent_pen(0); // opaque tilemap to get sky and sand colors
	793	// m_bg_tilemap->set_transparent_pen(0); // opaque tilemap to get sky and sand colors
794	794
795	795	m_bg_tilemap->set_scroll_cols(32);
796	796

trunk/src/mame/video/vsystem_spr2.c
r19030	r19031
16	16	// Pipe Dream
17	17
18	18	// there were lots of comments saying drivers using the
19		// static const UINT8 zoomtable[16] = { 0,7,14,20,25,30,34,38,42,46,49,52,54,57,59,61 };
	19	// static const UINT8 zoomtable[16] = { 0,7,14,20,25,30,34,38,42,46,49,52,54,57,59,61 };
20	20	// table for zooming needed upgrading, are we sure this isn't one of the
21	21	// differences between this sprite chip and the one in vsystem_spr.c, pspikes zooming is very rough
22	22
r19030	r19031
159	159	continue;
160	160	}
161	161
162
	162
163	163	if (m_pritype == 0) // turbo force etc.
164	164	{
165	165	usepri = curr_sprite.pri ? 0 : 2;

trunk/src/mame/drivers/funworld.c
r19030	r19031
5165	5165
5166	5166	CTUNK: Rare board with blue TAB board encryption scheme
5167	5167	plus a daughterboard for program encryption.
5168
	5168
5169	5169	*********************************************************/
5170	5170	{
5171	5171	UINT8 *rom = machine().root_device().memregion("maincpu")->base();

trunk/src/mame/drivers/btime.c
r19030	r19031
208	208	void deco_cpu7_device::mi_decrypt::write(UINT16 adr, UINT8 val)
209	209	{
210	210	program->write_byte(adr, val);
211		had_written = true;
	211	had_written = true;
212	212	}
213	213
214	214
r19030	r19031
2008	2008	UINT8 *rom = memregion("maincpu")->base();
2009	2009
2010	2010	/* At location 0xa2b6 there's a strange RLA followed by a BPL that reads from an
2011		unmapped area that causes the game to fail in several circumstances.On the Cassette
2012		version the RLA (33) is in reality a BIT (24),so I'm guessing that there's something
2013		wrong going on in the encryption scheme.*/
	2011	unmapped area that causes the game to fail in several circumstances.On the Cassette
	2012	version the RLA (33) is in reality a BIT (24),so I'm guessing that there's something
	2013	wrong going on in the encryption scheme.*/
2014	2014	memset(&rom[0xa2b6],0x24,1);
2015	2015
2016	2016	m_audio_nmi_enable_type = AUDIO_ENABLE_DIRECT;

trunk/src/mame/drivers/vastar.c
r19030	r19031
199	199	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
200	200
201	201	PORT_START("DSW1")
202		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) ) PORT_DIPLOCATION("DSW1:1,2")
	202	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) ) PORT_DIPLOCATION("DSW1:1,2")
203	203	PORT_DIPSETTING( 0x03, "3" )
204	204	PORT_DIPSETTING( 0x02, "4" )
205	205	PORT_DIPSETTING( 0x01, "5" )
206	206	PORT_DIPSETTING( 0x00, "6" )
207		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:3")
	207	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:3")
208	208	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
209	209	PORT_DIPSETTING( 0x04, DEF_STR( On ) )
210	210	PORT_DIPNAME( 0x08, 0x08, "Show Author Credits" ) PORT_DIPLOCATION("DSW1:4")

trunk/src/mame/drivers/cntsteer.c
r19030	r19031
887	887
888	888	MCFG_CPU_ADD("subcpu", M6809, 2000000) /* ? */
889	889	MCFG_CPU_PROGRAM_MAP(cntsteer_cpu2_map)
890		// MCFG_DEVICE_DISABLE()
	890	// MCFG_DEVICE_DISABLE()
891	891	MCFG_CPU_VBLANK_INT_DRIVER("screen", cntsteer_state, nmi_line_pulse) /* ? */
892	892
893	893	MCFG_CPU_ADD("audiocpu", M6502, 1500000) /* ? */

trunk/src/mame/drivers/ddenlovr.c
r19030	r19031
445	445	arg_size = fetch_word(src_data, src_len, &bit_addr, 4) + 1;
446	446
447	447	#ifdef MAME_DEBUG
448		// if (pen_size > 4 \|\| arg_size > 8)
449		// popmessage("warning: pen_size %d arg_size %d", pen_size, arg_size);
	448	// if (pen_size > 4 \|\| arg_size > 8)
	449	// popmessage("warning: pen_size %d arg_size %d", pen_size, arg_size);
450	450	#endif
451	451
452	452	// sryudens game bug
r19030	r19031
2513	2513	AM_RANGE(0x83, 0x84) AM_READ(hanakanz_gfxrom_r)
2514	2514	AM_RANGE(0xa0, 0xa1) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w)
2515	2515	AM_RANGE(0xb0, 0xb0) AM_READ_PORT("SYSTEM")
2516		// AM_RANGE(0xb1, 0xb2) AM_READ(hanakanz_keyb_r)
	2516	// AM_RANGE(0xb1, 0xb2) AM_READ(hanakanz_keyb_r)
2517	2517	AM_RANGE(0xb1, 0xb1) AM_READ_PORT("KEYB0")
2518	2518	AM_RANGE(0xb2, 0xb2) AM_READ_PORT("KEYB1")
2519	2519	AM_RANGE(0xb3, 0xb3) AM_WRITE(hanakanz_coincounter_w)
2520		// AM_RANGE(0xb4, 0xb4) AM_WRITE(hanakanz_keyb_w)
	2520	// AM_RANGE(0xb4, 0xb4) AM_WRITE(hanakanz_keyb_w)
2521	2521	AM_RANGE(0xb6, 0xb6) AM_READ(hanakanz_rand_r)
2522	2522	AM_RANGE(0xc0, 0xc0) AM_DEVREADWRITE("oki", okim6295_device, read, write)
2523		// AM_RANGE(0xe0, 0xef) AM_DEVREADWRITE("rtc", msm6242_device, read, write)
	2523	// AM_RANGE(0xe0, 0xef) AM_DEVREADWRITE("rtc", msm6242_device, read, write)
2524	2524	ADDRESS_MAP_END
2525	2525
2526	2526
r19030	r19031
2537	2537	AM_RANGE(0x83, 0x84) AM_READ(hanakanz_gfxrom_r)
2538	2538	AM_RANGE(0xa0, 0xa1) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w)
2539	2539	AM_RANGE(0x90, 0x90) AM_READ_PORT("SYSTEM")
2540		// AM_RANGE(0x91, 0x91) AM_READ(hanakanz_keyb_r)
	2540	// AM_RANGE(0x91, 0x91) AM_READ(hanakanz_keyb_r)
2541	2541	AM_RANGE(0x91, 0x91) AM_READ_PORT("KEYB0")
2542	2542	AM_RANGE(0x92, 0x92) AM_READ_PORT("KEYB1")
2543	2543	AM_RANGE(0x93, 0x93) AM_WRITE(hanakanz_coincounter_w)
2544		// AM_RANGE(0x94, 0x94) AM_WRITE(hanakanz_keyb_w)
	2544	// AM_RANGE(0x94, 0x94) AM_WRITE(hanakanz_keyb_w)
2545	2545	AM_RANGE(0x96, 0x96) AM_READ(hanakanz_rand_r)
2546	2546	AM_RANGE(0xc0, 0xc0) AM_DEVREADWRITE("oki", okim6295_device, read, write)
2547		// AM_RANGE(0xe0, 0xef) AM_DEVREADWRITE("rtc", msm6242_device, read, write)
	2547	// AM_RANGE(0xe0, 0xef) AM_DEVREADWRITE("rtc", msm6242_device, read, write)
2548	2548	ADDRESS_MAP_END
2549	2549
2550	2550
r19030	r19031
5178	5178	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
5179	5179	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
5180	5180	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
5181
	5181
5182	5182	PORT_START("KEYB0")
5183	5183	// Forced Joystick mode wrt kotbinyo:
5184	5184	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 ) // * press at boot for service mode
r19030	r19031
9133	9133	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80)
9134	9134
9135	9135	/* devices */
9136		// MCFG_MSM6242_ADD("rtc", hanakanz_rtc_intf)
	9136	// MCFG_MSM6242_ADD("rtc", hanakanz_rtc_intf)
9137	9137	MACHINE_CONFIG_END
9138	9138
9139	9139	static MACHINE_CONFIG_DERIVED( kotbinsp, kotbinyo )
r19030	r19031
10531	10531	DIPs - 10-Position (x2)
10532	10532	HSync - 15.1015kHz
10533	10533	VSync - 60.1656Hz
10534
	10534
10535	10535	no RTC nor battery (unpopulated)
10536	10536
10537	10537	***************************************************************************/
r19030	r19031
10579	10579	ROM_LOAD16_BYTE( "909035.8c", 0x000001, 0x100000, CRC(cea4dbfa) SHA1(581bbcfcb0c900667002b7b744197d039d586833) )
10580	10580	ROM_LOAD16_BYTE( "909034.6b", 0x200000, 0x080000, CRC(9f366a2a) SHA1(2199cf640b665bd1ba3eac081bde288dec521383) )
10581	10581	ROM_LOAD16_BYTE( "909033.6c", 0x200001, 0x080000, CRC(9388b85d) SHA1(a35fe0b585cba256bb5575f7b539b33dd0ca3aa0) )
10582		ROM_FILL( 0x300000, 0x100000, 0xff )
	10582	ROM_FILL( 0x300000, 0x100000, 0xff )
10583	10583	// mirror the whole address space (25 bits)
10584	10584	ROM_COPY( "blitter", 0, 0x0400000, 0x400000 )
10585	10585	ROM_COPY( "blitter", 0, 0x0800000, 0x400000 )

trunk/src/mame/drivers/dec8.c
r19030	r19031
2079	2079	deco_karnovsprites_device::set_gfx_region(*device, 1);
2080	2080
2081	2081	MCFG_SCREEN_ADD("screen", RASTER)
2082		// MCFG_SCREEN_REFRESH_RATE(58)
2083		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
2084		// MCFG_SCREEN_SIZE(328, 328)
2085		// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
	2082	// MCFG_SCREEN_REFRESH_RATE(58)
	2083	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
	2084	// MCFG_SCREEN_SIZE(328, 328)
	2085	// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
2086	2086	MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
2087	2087	MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_lastmisn)
2088	2088
r19030	r19031
2118	2118	MCFG_CPU_PROGRAM_MAP(ym3526_s_map)
2119	2119	/* NMIs are caused by the main CPU */
2120	2120
2121		// MCFG_QUANTUM_TIME(attotime::from_hz(100000))
	2121	// MCFG_QUANTUM_TIME(attotime::from_hz(100000))
2122	2122	MCFG_QUANTUM_PERFECT_CPU("maincpu") // needs heavy sync, otherwise one of the two CPUs will miss an irq and makes the game to hang
2123	2123
2124	2124	/* video hardware */
r19030	r19031
2128	2128	deco_karnovsprites_device::set_gfx_region(*device, 1);
2129	2129
2130	2130	MCFG_SCREEN_ADD("screen", RASTER)
2131		// MCFG_SCREEN_REFRESH_RATE(58)
2132		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
2133		// MCFG_SCREEN_SIZE(328, 328)
2134		// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
	2131	// MCFG_SCREEN_REFRESH_RATE(58)
	2132	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
	2133	// MCFG_SCREEN_SIZE(328, 328)
	2134	// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
2135	2135	MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
2136	2136	MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_shackled)
2137	2137
r19030	r19031
2176	2176	deco_karnovsprites_device::set_gfx_region(*device, 1);
2177	2177
2178	2178	MCFG_SCREEN_ADD("screen", RASTER)
2179		// MCFG_SCREEN_REFRESH_RATE(58)
2180		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
2181		// MCFG_SCREEN_SIZE(328, 328)
2182		// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
	2179	// MCFG_SCREEN_REFRESH_RATE(58)
	2180	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
	2181	// MCFG_SCREEN_SIZE(328, 328)
	2182	// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
2183	2183	MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
2184	2184	MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_gondo)
2185	2185	MCFG_SCREEN_VBLANK_DRIVER(dec8_state, screen_eof_dec8)
r19030	r19031
2225	2225	deco_karnovsprites_device::set_gfx_region(*device, 1);
2226	2226
2227	2227	MCFG_SCREEN_ADD("screen", RASTER)
2228		// MCFG_SCREEN_REFRESH_RATE(58)
2229		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
2230		// MCFG_SCREEN_SIZE(328, 328)
2231		// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
	2228	// MCFG_SCREEN_REFRESH_RATE(58)
	2229	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
	2230	// MCFG_SCREEN_SIZE(328, 328)
	2231	// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
2232	2232	MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
2233	2233	MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_garyoret)
2234	2234	MCFG_SCREEN_VBLANK_DRIVER(dec8_state, screen_eof_dec8)
r19030	r19031
2277	2277	deco_karnovsprites_device::set_gfx_region(*device, 1);
2278	2278
2279	2279	MCFG_SCREEN_ADD("screen", RASTER)
2280		// MCFG_SCREEN_REFRESH_RATE(58)
2281		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
2282		// MCFG_SCREEN_SIZE(328, 328)
2283		// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
	2280	// MCFG_SCREEN_REFRESH_RATE(58)
	2281	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
	2282	// MCFG_SCREEN_SIZE(328, 328)
	2283	// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
2284	2284	MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
2285	2285	MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_ghostb)
2286	2286	MCFG_SCREEN_VBLANK_DRIVER(dec8_state, screen_eof_dec8)
r19030	r19031
2328	2328	deco_karnovsprites_device::set_gfx_region(*device, 1);
2329	2329
2330	2330	MCFG_SCREEN_ADD("screen", RASTER)
2331		// MCFG_SCREEN_REFRESH_RATE(58)
2332		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
2333		// MCFG_SCREEN_SIZE(328, 328)
2334		// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
	2331	// MCFG_SCREEN_REFRESH_RATE(58)
	2332	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
	2333	// MCFG_SCREEN_SIZE(328, 328)
	2334	// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
2335	2335	MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
2336	2336	MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_lastmisn)
2337	2337
r19030	r19031
2384	2384	deco_mxc06_device::set_gfx_region(*device, 1);
2385	2385
2386	2386	MCFG_SCREEN_ADD("screen", RASTER)
2387		// MCFG_SCREEN_REFRESH_RATE(58)
2388		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
2389		// MCFG_SCREEN_SIZE(328, 328)
2390		// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
	2387	// MCFG_SCREEN_REFRESH_RATE(58)
	2388	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
	2389	// MCFG_SCREEN_SIZE(328, 328)
	2390	// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
2391	2391	MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
2392	2392	MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_oscar)
2393	2393
r19030	r19031
2426	2426	MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
2427	2427
2428	2428	MCFG_SCREEN_ADD("screen", RASTER)
2429		// MCFG_SCREEN_REFRESH_RATE(58)
2430		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
2431		// MCFG_SCREEN_SIZE(328, 328)
2432		// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
	2429	// MCFG_SCREEN_REFRESH_RATE(58)
	2430	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
	2431	// MCFG_SCREEN_SIZE(328, 328)
	2432	// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
2433	2433	MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
2434	2434	MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_srdarwin)
2435	2435
r19030	r19031
2477	2477
2478	2478
2479	2479	MCFG_SCREEN_ADD("screen", RASTER)
2480		// MCFG_SCREEN_REFRESH_RATE(58)
2481		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
2482		// MCFG_SCREEN_SIZE(328, 328)
2483		// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
	2480	// MCFG_SCREEN_REFRESH_RATE(58)
	2481	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
	2482	// MCFG_SCREEN_SIZE(328, 328)
	2483	// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
2484	2484	MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
2485	2485	MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_cobracom)
2486	2486

trunk/src/mame/drivers/naomi.c
r19030	r19031
5617	5617	NAOMI_DEFAULT_EEPROM
5618	5618
5619	5619	ROM_REGION( 0xb000000, "rom_board", ROMREGION_ERASEFF)
5620		ROM_LOAD( "nja1_fl1.2d", 0x0800000, 0x0800000, CRC(a57c0576) SHA1(0c99a3e648798bf6a100512d682c08a3d4f05958) )
5621		ROM_LOAD( "nja1_fl2.2c", 0x1000000, 0x0800000, CRC(1f81f46b) SHA1(7677f881b84233f3f95a792f9be6f618cba6d586) )
5622		ROM_LOAD( "nja1_fl3.2b", 0x1800000, 0x0800000, CRC(24974c3d) SHA1(cd64dec682688e26fca91873e5e7b6e0d931d1ce) )
	5620	ROM_LOAD( "nja1_fl1.2d", 0x0800000, 0x0800000, CRC(a57c0576) SHA1(0c99a3e648798bf6a100512d682c08a3d4f05958) )
	5621	ROM_LOAD( "nja1_fl2.2c", 0x1000000, 0x0800000, CRC(1f81f46b) SHA1(7677f881b84233f3f95a792f9be6f618cba6d586) )
	5622	ROM_LOAD( "nja1_fl3.2b", 0x1800000, 0x0800000, CRC(24974c3d) SHA1(cd64dec682688e26fca91873e5e7b6e0d931d1ce) )
5623	5623	ROM_LOAD( "nja1ma2.4l", 0x2000000, 0x1000000, CRC(5af34ea0) SHA1(b49a50e995cb6682782b0643d40001b9bffe0118) )
5624	5624	ROM_LOAD( "nja1ma3.4k", 0x3000000, 0x1000000, CRC(504a89b3) SHA1(e0b90542f80527e998db7ee3bb75e36c375cacba) )
5625	5625	ROM_LOAD( "nja1ma4.4j", 0x4000000, 0x1000000, CRC(d5c2799a) SHA1(ce46c1aa38479d9e5e350573bc6b214979b88dbc) )

trunk/src/mame/drivers/scramble.c
r19030	r19031
1789	1789	Triple Punch
1790	1790	(C)1982 KKI
1791	1791
1792		board silkscreend PCO-008-01
	1792	board silkscreend PCO-008-01
1793	1793
1794	1794	Empty 24 pin socket at 2E
1795	1795	Empty 40 pin socket at 0A
1796	1796
1797		.2h 2732 stickered TD4
1798		.2k 2732 stickered TC3
1799		.2l 2732 stickered TE2
1800		.2m 2732 stickered TD1
1801		.5h 2716 stickered TA7
1802		.5f 2716 stickered TA6
1803		.6e 82s123 stickered TA
	1797	.2h 2732 stickered TD4
	1798	.2k 2732 stickered TC3
	1799	.2l 2732 stickered TE2
	1800	.2m 2732 stickered TD1
	1801	.5h 2716 stickered TA7
	1802	.5f 2716 stickered TA6
	1803	.6e 82s123 stickered TA
1804	1804	***************************************************************************/
1805	1805
1806	1806	ROM_START( triplepa )

trunk/src/mame/drivers/s6a.c
r19030	r19031
261	261
262	262	WRITE8_MEMBER( s6a_state::sol0_w )
263	263	{
264		// if (BIT(data, 4))
265		// m_samples->start(2, 5); // outhole
	264	// if (BIT(data, 4))
	265	// m_samples->start(2, 5); // outhole
266	266	}
267	267
268	268	WRITE8_MEMBER( s6a_state::sol1_w )
r19030	r19031
287	287
288	288	m_pias->cb1_w(m_cb1);
289	289
290		// if (BIT(data, 5))
291		// m_samples->start(0, 6); // knocker
	290	// if (BIT(data, 5))
	291	// m_samples->start(0, 6); // knocker
292	292	}
293	293
294	294	static const pia6821_interface pia22_intf =

trunk/src/mame/drivers/goldstar.c
r19030	r19031
634	634	AM_RANGE(0xe0, 0xe0) AM_DEVWRITE("sn3", sn76489_device, write) /* SN76489 #3 */
635	635	AM_RANGE(0x60, 0x60) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w) /* AY8910 control? */
636	636	AM_RANGE(0x80, 0x80) AM_DEVREADWRITE_LEGACY("aysnd", ay8910_r, ay8910_data_w) /* AY8910 Input? */
637		// AM_RANGE(0x01, 0x01) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
638		// AM_RANGE(0x02, 0x03) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
	637	// AM_RANGE(0x01, 0x01) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
	638	// AM_RANGE(0x02, 0x03) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
639	639	ADDRESS_MAP_END
640	640
641	641
r19030	r19031
7012	7012	MCFG_CPU_VBLANK_INT_DRIVER("screen", goldstar_state, nmi_line_pulse)
7013	7013
7014	7014	/* 3x 8255 */
7015		// MCFG_I8255A_ADD( "ppi8255_0", lucky8_ppi8255_0_intf )
7016		// MCFG_I8255A_ADD( "ppi8255_1", lucky8_ppi8255_1_intf )
7017		// MCFG_I8255A_ADD( "ppi8255_2", lucky8_ppi8255_2_intf )
	7015	// MCFG_I8255A_ADD( "ppi8255_0", lucky8_ppi8255_0_intf )
	7016	// MCFG_I8255A_ADD( "ppi8255_1", lucky8_ppi8255_1_intf )
	7017	// MCFG_I8255A_ADD( "ppi8255_2", lucky8_ppi8255_2_intf )
7018	7018
7019	7019	/* video hardware */
7020	7020	MCFG_SCREEN_ADD("screen", RASTER)
r19030	r19031
7027	7027
7028	7028	MCFG_GFXDECODE(megaline)
7029	7029	MCFG_PALETTE_LENGTH(256)
7030		// MCFG_NVRAM_ADD_1FILL("nvram")
	7030	// MCFG_NVRAM_ADD_1FILL("nvram")
7031	7031
7032	7032	MCFG_VIDEO_START_OVERRIDE(goldstar_state,goldstar)
7033	7033
r19030	r19031
10499	10499
10500	10500
10501	10501	==========================
10502		Custom 06B53P 9G1 - DIP 28
	10502	Custom 06B53P 9G1 - DIP 28
10503	10503	==========================
10504	10504	Pinout
10505	10505	======
r19030	r19031
10555	10555	08 -> M2(16)
10556	10556	09 -> M2(15)
10557	10557	10 -> M2(12)
10558		11 -> N2(19) -> 10k -> +5V
	10558	11 -> N2(19) -> 10k -> +5V
10559	10559	12 -> GND
10560	10560	13 -> GND
10561	10561	14 -> M2(06)
r19030	r19031
10632	10632	========
10633	10633	BPROMS:
10634	10634	========
10635
	10635
10636	10636	GND-------------+ +----------N3(10)
10637	10637	GND-----------+ \| \| +--------N3(06)
10638	10638	K5(06)------+ \| \| \| \| +------(N/C)
r19030	r19031
10643	10643	\|>## 24S10 @M3 ###\|
10644	10644	\|#################\|
10645	10645	+-+-+-+-+-+-+-+-+-+
10646		\| \| \| \| \| \| \| \|
	10646	\| \| \| \| \| \| \| \|
10647	10647	K5(15)----+ \| \| \| \| \| \| +----GND
10648	10648	K3(12)------+ \| \| \| \| +------D3(03)
10649	10649	K3(14)--------+ \| \| +--------D3(11)
r19030	r19031
10654	10654	J3(10)---+ +----J3(11)
10655	10655	K5(05)---+ \| \| +----J3(12)
10656	10656	H3(05)----+ \| \| \| \| +-----J3(13)
10657		+5V-------+ \| \| \| \| \| \|
	10657	+5V-------+ \| \| \| \| \| \|
10658	10658	\| \| \| \| \| \| \| +-------------------+
10659	10659	\| \| \| \| \| \| \| \| \|
10660	10660	+-----------------+ \|
r19030	r19031
10778	10778	\| \| \| \| \| \| +--------------\|-\|-+
10779	10779	\| \| \| \| \| \| \| +------------\|-+
10780	10780	\| \| \| \| \| \| \| \| +----------+
10781		\| \| \| \| \| \| \| \| \|
	10781	\| \| \| \| \| \| \| \| \|
10782	10782	\| +---+-+-+-+-+-+-+-+---+
10783	10783	\| \| 1+---------------+8 \|
10784	10784	\| \| \| \| \| \| \| \| \| \| \| \|

trunk/src/mame/drivers/firebeat.c
r19030	r19031
106	106	The display list objects seem to be there, but the address is wrong (0x14c400, instead of the correct address)
107	107
108	108	- The external Yamaha MIDI sound board is not emulated (no keyboard sounds).
109
110
111		- Notes on how the video is supposed to work from Ville / Ian Patterson:
112
113		There are four "display contexts" that are set up via registers 20-4E. They are
114		basically just raw framebuffers. 40-4E sets the base framebuffer pointer, 30-3E
115		sets the size, 20-2E may set the minimum x and y coordinates but I haven't seen
116		them set to something other than 0 yet. One context is set as the one the RAMDAC
117		outputs to the monitor (not sure how this is selected yet, probably the lower
118		bits of register 12). Thestartup test in the popn BIOS checks all of VRAM, so
119		it moves the currentdisplay address around so you don't see crazy colors, which
120		is very helpful in figuring out how this part works.
121	109
122		The other new part is that there are two VRAM write ports, managed by registers
123		60+68+70 and 64+6A+74, with status read from the lower bits of reg 7A. Each context
124		can either write to VRAM as currently emulated, or the port can be switched in to
125		"immediate mode" via registers 68/6A. Immedate mode can be used to run GCU commands
126		at any point during the frame. It's mainly used to call display lists, which is where
127		the display list addresses come from. Some games use it to send other commands, so
128		it appears to be a 4-dword FIFO or something along those lines.
	110
	111	- Notes on how the video is supposed to work from Ville / Ian Patterson:
	112
	113	There are four "display contexts" that are set up via registers 20-4E. They are
	114	basically just raw framebuffers. 40-4E sets the base framebuffer pointer, 30-3E
	115	sets the size, 20-2E may set the minimum x and y coordinates but I haven't seen
	116	them set to something other than 0 yet. One context is set as the one the RAMDAC
	117	outputs to the monitor (not sure how this is selected yet, probably the lower
	118	bits of register 12). Thestartup test in the popn BIOS checks all of VRAM, so
	119	it moves the currentdisplay address around so you don't see crazy colors, which
	120	is very helpful in figuring out how this part works.
	121
	122	The other new part is that there are two VRAM write ports, managed by registers
	123	60+68+70 and 64+6A+74, with status read from the lower bits of reg 7A. Each context
	124	can either write to VRAM as currently emulated, or the port can be switched in to
	125	"immediate mode" via registers 68/6A. Immedate mode can be used to run GCU commands
	126	at any point during the frame. It's mainly used to call display lists, which is where
	127	the display list addresses come from. Some games use it to send other commands, so
	128	it appears to be a 4-dword FIFO or something along those lines.
129	129	*/
130	130
131	131	#include "emu.h"
r19030	r19031
730	730	}
731	731
732	732	case 0x40: /* framebuffer config */
733		// HACK: switch display lists at the right times for the ParaParaParadise games until we
	733	// HACK: switch display lists at the right times for the ParaParaParadise games until we
734	734	// do the video emulation properly
735	735	if (mame_strnicmp(machine.system().name, "pp", 2) == 0)
736	736	{
r19030	r19031
1190	1190	//if (state->m_atapi_drivesel==1) logerror("!!!ATAPI COMMAND %x\n", state->m_atapi_data[0]&0xff);
1191	1191	switch (state->m_atapi_data[0]&0xff)
1192	1192	{
1193
	1193
1194	1194	case 0x55: // MODE SELECT
1195	1195	state->m_atapi_cdata_wait = state->m_atapi_data[4]/2;
1196	1196	state->m_atapi_data_ptr = 0;
1197	1197	logerror("ATAPI: Waiting for %x bytes of MODE SELECT data\n", state->m_atapi_cdata_wait);
1198	1198	break;
1199	1199
1200
	1200
1201	1201	case 0xa8: // READ (12)
1202	1202	// indicate data ready: set DRQ and DMA ready, and IO in INTREASON
1203	1203	state->m_atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ \| ATAPI_STAT_SERVDSC;
r19030	r19031
1209	1209	case 0x00: // BUS RESET / TEST UNIT READY
1210	1210	case 0xbb: // SET CD SPEED
1211	1211	case 0xa5: // PLAY AUDIO
1212		case 0x1b: // START_STOP_UNIT
1213		case 0x4e: // STOPPLAY_SCAN
	1212	case 0x1b: // START_STOP_UNIT
	1213	case 0x4e: // STOPPLAY_SCAN
1214	1214	state->m_atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
1215	1215	break;
1216	1216	}
r19030	r19031
2394	2394	ROM_REGION(0x400000, "ymz", ROMREGION_ERASE00)
2395	2395
2396	2396	ROM_REGION(0xc0, "user2", 0) // Security dongle
2397		ROM_LOAD( "gqa11-ja", 0x000000, 0x0000c0, CRC(2ed8e2ae) SHA1(b8c3410dab643111b2d2027068175ba018a0a67e) )
	2397	ROM_LOAD( "gqa11-ja", 0x000000, 0x0000c0, CRC(2ed8e2ae) SHA1(b8c3410dab643111b2d2027068175ba018a0a67e) )
2398	2398
2399	2399	DISK_REGION( "scsi0" )
2400	2400	DISK_IMAGE_READONLY( "a11jaa01", 0, SHA1(539ec6f1c1d198b0d6ce5543eadcbb4d9917fa42) )

trunk/src/mame/drivers/zn.c
r19030	r19031
422	422	{
423	423	state->m_znsec0->init( zn_config_table[ n_game ].p_n_mainsec );
424	424	state->m_znsec1->init( zn_config_table[ n_game ].p_n_gamesec );
425		// psx_sio_install_handler( machine, 0, sio_pad_handler );
	425	// psx_sio_install_handler( machine, 0, sio_pad_handler );
426	426	break;
427	427	}
428	428	n_game++;

trunk/src/mame/drivers/cps1.c
r19030	r19031
1813	1813
1814	1814	/* To-Do sf2amf dipswitch SW(B):4 + SW(B):5 + SW(B):6
1815	1815	static INPUT_PORTS_START( sf2amf )
1816		PORT_INCLUDE( )
	1816	PORT_INCLUDE( )
1817	1817
1818		PORT_MODIFY("DSWB")
1819		PORT_DIPNAME( 0x08, 0x00, "Turbo Switch 1 of 3" ) PORT_DIPLOCATION("SW(B):4")
1820		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1821		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1822		PORT_DIPNAME( 0x10, 0x00, "Turbo Switch 2 of 3" ) PORT_DIPLOCATION("SW(B):5")
1823		PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1824		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1825		PORT_DIPNAME( 0x20, 0x00, "Turbo Switch 3 of 3" ) PORT_DIPLOCATION("SW(B):6")
1826		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1827		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1818	PORT_MODIFY("DSWB")
	1819	PORT_DIPNAME( 0x08, 0x00, "Turbo Switch 1 of 3" ) PORT_DIPLOCATION("SW(B):4")
	1820	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	1821	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1822	PORT_DIPNAME( 0x10, 0x00, "Turbo Switch 2 of 3" ) PORT_DIPLOCATION("SW(B):5")
	1823	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	1824	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1825	PORT_DIPNAME( 0x20, 0x00, "Turbo Switch 3 of 3" ) PORT_DIPLOCATION("SW(B):6")
	1826	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	1827	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1828	1828	INPUT_PORTS_END
1829	1829	*/
1830	1830
r19030	r19031
6576	6576	ROM_START( sf2stt )
6577	6577	ROM_REGION( CODE_SIZE, "maincpu", 0 ) /* 68000 code */
6578	6578	/* do not comment this out, this is only for testing purpose
6579		ROM_LOAD16_BYTE( "12.bin", 0x00000, 0x40000, CRC(a258b4d5) SHA1(3433b6493794c98bb35c1b27cc65bb5f13d52e9b) )
6580		ROM_LOAD16_BYTE( "09.bin", 0x00001, 0x40000, CRC(59ccd474) SHA1(7bb28c28ee722435fdbb18eb73e52bd65b419103) )
6581		*/
	6579	ROM_LOAD16_BYTE( "12.bin", 0x00000, 0x40000, CRC(a258b4d5) SHA1(3433b6493794c98bb35c1b27cc65bb5f13d52e9b) )
	6580	ROM_LOAD16_BYTE( "09.bin", 0x00001, 0x40000, CRC(59ccd474) SHA1(7bb28c28ee722435fdbb18eb73e52bd65b419103) )
	6581	*/
6582	6582	ROM_LOAD16_BYTE( "prg part 1.stt", 0x00000, 0x40000, NO_DUMP )
6583	6583	ROM_LOAD16_BYTE( "prg part 2.stt", 0x00001, 0x40000, NO_DUMP )
6584	6584	/* there are two empty sockets next to the two following program roms,
6585		these roms may be missing and this PCB is not working on real hardware */
	6585	these roms may be missing and this PCB is not working on real hardware */
6586	6586	ROM_LOAD16_BYTE( "ce91e-b", 0x80000, 0x40000, CRC(0862386e) SHA1(9fcfbcbbc17529de75d5419018e7b1dd90b397c0) )
6587	6587	ROM_LOAD16_BYTE( "ce91e-a", 0x80001, 0x40000, CRC(0c83844d) SHA1(4c25ba4a50d62c62789d026e3d304ed1dfb3c248) )
6588	6588
r19030	r19031
6625	6625	ROM_START( sf2unkb )
6626	6626	ROM_REGION( CODE_SIZE, "maincpu", 0 ) /* 68000 code */
6627	6627	/* do not comment this out, this is only for testing purpose
6628		ROM_LOAD16_BYTE( "12.bin", 0x000000, 0x40000, CRC(a258b4d5) SHA1(3433b6493794c98bb35c1b27cc65bb5f13d52e9b) )
6629		ROM_LOAD16_BYTE( "09.bin", 0x000001, 0x40000, CRC(59ccd474) SHA1(7bb28c28ee722435fdbb18eb73e52bd65b419103) )
6630		ROM_LOAD16_BYTE( "11.bin", 0x080000, 0x40000, CRC(82097d63) SHA1(881e7ffb78197f6794b5d41f5c2c87da35e8cb15) )
6631		ROM_LOAD16_BYTE( "10.bin", 0x080001, 0x40000, CRC(0c83844d) SHA1(4c25ba4a50d62c62789d026e3d304ed1dfb3c248) )
6632		*/
	6628	ROM_LOAD16_BYTE( "12.bin", 0x000000, 0x40000, CRC(a258b4d5) SHA1(3433b6493794c98bb35c1b27cc65bb5f13d52e9b) )
	6629	ROM_LOAD16_BYTE( "09.bin", 0x000001, 0x40000, CRC(59ccd474) SHA1(7bb28c28ee722435fdbb18eb73e52bd65b419103) )
	6630	ROM_LOAD16_BYTE( "11.bin", 0x080000, 0x40000, CRC(82097d63) SHA1(881e7ffb78197f6794b5d41f5c2c87da35e8cb15) )
	6631	ROM_LOAD16_BYTE( "10.bin", 0x080001, 0x40000, CRC(0c83844d) SHA1(4c25ba4a50d62c62789d026e3d304ed1dfb3c248) )
	6632	*/
6633	6633	ROM_LOAD16_BYTE( "prg part 1.sf2unkb", 0x00000, 0x80000, NO_DUMP )
6634	6634	ROM_LOAD16_BYTE( "prg part 2.sf2unkb", 0x00001, 0x80000, NO_DUMP )
6635	6635	/* there are two empty sockets next to the two following program roms,
6636		these roms may be missing and this PCB is not working on real hardware */
	6636	these roms may be missing and this PCB is not working on real hardware */
6637	6637	ROM_LOAD16_BYTE( "w-6", 0x100000, 0x20000, CRC(bb4af315) SHA1(75f0827f4f7e9f292add46467f8d4fe19b2514c9) )
6638	6638	ROM_LOAD16_BYTE( "w-5", 0x100001, 0x20000, CRC(c02a13eb) SHA1(b807cc495bff3f95d03b061fc629c95f965cb6d8) )
6639	6639
r19030	r19031
6671	6671	ROM_REGION( 0x40000, "oki", 0 ) /* Samples */
6672	6672	ROM_LOAD( "sample part 1.unkb", 0x20000, 0x20000, NO_DUMP )
6673	6673	/* do not comment this out, this is only for testing purpose
6674		ROM_LOAD( "sf2_18.11c", 0x00000, 0x20000, CRC(7f162009) SHA1(346bf42992b4c36c593e21901e22c87ae4a7d86d) )
6675		*/
	6674	ROM_LOAD( "sf2_18.11c", 0x00000, 0x20000, CRC(7f162009) SHA1(346bf42992b4c36c593e21901e22c87ae4a7d86d) )
	6675	*/
6676	6676	ROM_LOAD( "w-7", 0x20000, 0x20000, CRC(beade53f) SHA1(277c397dc12752719ec6b47d2224750bd1c07f79) )
6677	6677	ROM_END
6678	6678
r19030	r19031
8323	8323	ROM_LOAD16_BYTE( "5.amf", 0x000000, 0x80000, CRC(03991fba) SHA1(6c42bf15248640fdb3e98fb01b0a870649deb410) )
8324	8324	ROM_LOAD16_BYTE( "4.amf", 0x000001, 0x80000, CRC(39f15a1e) SHA1(901c4fea76bf5bff7330ed07ffde54cdccdaa680) )
8325	8325	/* there are two empty sockets next to the two former program roms,
8326		these roms may be missing and this PCB is not working on real hardware */
	8326	these roms may be missing and this PCB is not working on real hardware */
8327	8327	ROM_LOAD16_BYTE( "prg part 3.amf", 0x100000, 0x40000, NO_DUMP )
8328	8328	ROM_LOAD16_BYTE( "prg part 4.amf", 0x100001, 0x40000, NO_DUMP )
8329	8329	/* do not comment this out, this is only for testing purpose
8330		ROM_LOAD16_BYTE( "u221.rom", 0x100000, 0x20000, CRC(64e6e091) SHA1(32ec05db955e538d4ada26d19ee50926f74b684f) )
8331		ROM_LOAD16_BYTE( "u195.rom", 0x100001, 0x20000, CRC(c95e4443) SHA1(28417dee9ccdfa65b0f4a92aa29b90279fe8cd85) )
8332		*/
8333
	8330	ROM_LOAD16_BYTE( "u221.rom", 0x100000, 0x20000, CRC(64e6e091) SHA1(32ec05db955e538d4ada26d19ee50926f74b684f) )
	8331	ROM_LOAD16_BYTE( "u195.rom", 0x100001, 0x20000, CRC(c95e4443) SHA1(28417dee9ccdfa65b0f4a92aa29b90279fe8cd85) )
	8332	*/
	8333
8334	8334	ROM_REGION( 0x600000, "gfx", 0 )
8335	8335	ROMX_LOAD( "y.c.e.c m.k.r-001", 0x000000, 0x80000, CRC(a258de13) SHA1(2e477948c4c8a2fb7cfdc4a739766bc4a4e01c49), ROM_GROUPWORD \| ROM_SKIP(6) )
8336	8336	ROM_CONTINUE( 0x000002, 0x80000)

trunk/src/mame/drivers/supercrd.c
r19030	r19031
34	34
35	35	ROMs: PRG: 2x 27C512 (IC37, IC51)
36	36	GFX: 2x 27C512 (IC10, IC11)
37		BP: 1x N82S147N
	37	BP: 1x N82S147N
38	38
39	39	1x Xtal 16 MHz.
40	40	1x 8 DIP switches bank.
r19030	r19031
276	276	AM_RANGE(0x0000, 0xbfff) AM_ROM
277	277	AM_RANGE(0xc000, 0xcfff) AM_RAM_WRITE(supercrd_videoram_w) AM_SHARE("videoram") // wrong
278	278	AM_RANGE(0xd000, 0xdfff) AM_RAM_WRITE(supercrd_colorram_w) AM_SHARE("colorram") // wrong
279		// AM_RANGE(0x0000, 0x0000) AM_RAM AM_SHARE("nvram")
280		// AM_RANGE(0xe000, 0xe000) AM_DEVWRITE("crtc", mc6845_device, address_w)
281		// AM_RANGE(0xe001, 0xe001) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
	279	// AM_RANGE(0x0000, 0x0000) AM_RAM AM_SHARE("nvram")
	280	// AM_RANGE(0xe000, 0xe000) AM_DEVWRITE("crtc", mc6845_device, address_w)
	281	// AM_RANGE(0xe001, 0xe001) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
282	282	ADDRESS_MAP_END
283	283
284	284
r19030	r19031
401	401
402	402	//static const mc6845_interface mc6845_intf =
403	403	//{
404		// "screen", /* screen we are acting on */
405		// 4, /* number of pixels per video memory address */
406		// NULL, /* before pixel update callback */
407		// NULL, /* row update callback */
408		// NULL, /* after pixel update callback */
409		// DEVCB_NULL, /* callback for display state changes */
410		// DEVCB_NULL, /* callback for cursor state changes */
411		// DEVCB_NULL, /* HSYNC callback */
412		// DEVCB_NULL, /* VSYNC callback */
413		// NULL /* update address callback */
	404	// "screen", /* screen we are acting on */
	405	// 4, /* number of pixels per video memory address */
	406	// NULL, /* before pixel update callback */
	407	// NULL, /* row update callback */
	408	// NULL, /* after pixel update callback */
	409	// DEVCB_NULL, /* callback for display state changes */
	410	// DEVCB_NULL, /* callback for cursor state changes */
	411	// DEVCB_NULL, /* HSYNC callback */
	412	// DEVCB_NULL, /* VSYNC callback */
	413	// NULL /* update address callback */
414	414	//};
415	415
416	416
r19030	r19031
420	420
421	421	//static I8255_INTERFACE (ppi8255_intf_0)
422	422	//{
423		// /* (port) Mode X - description */
424		// DEVCB_UNMAPPED, /* Port A read */
425		// DEVCB_UNMAPPED, /* Port A write */
426		// DEVCB_UNMAPPED, /* Port B read */
427		// DEVCB_UNMAPPED, /* Port B write */
428		// DEVCB_UNMAPPED, /* Port C read */
429		// DEVCB_UNMAPPED /* Port C write */
	423	// /* (port) Mode X - description */
	424	// DEVCB_UNMAPPED, /* Port A read */
	425	// DEVCB_UNMAPPED, /* Port A write */
	426	// DEVCB_UNMAPPED, /* Port B read */
	427	// DEVCB_UNMAPPED, /* Port B write */
	428	// DEVCB_UNMAPPED, /* Port C read */
	429	// DEVCB_UNMAPPED /* Port C write */
430	430	//};
431	431
432	432	//static I8255_INTERFACE (ppi8255_intf_1)
433	433	//{
434		// /* (port) Mode X - description */
435		// DEVCB_UNMAPPED, /* Port A read */
436		// DEVCB_UNMAPPED, /* Port A write */
437		// DEVCB_UNMAPPED, /* Port B read */
438		// DEVCB_UNMAPPED, /* Port B write */
439		// DEVCB_UNMAPPED, /* Port C read */
440		// DEVCB_UNMAPPED /* Port C write */
	434	// /* (port) Mode X - description */
	435	// DEVCB_UNMAPPED, /* Port A read */
	436	// DEVCB_UNMAPPED, /* Port A write */
	437	// DEVCB_UNMAPPED, /* Port B read */
	438	// DEVCB_UNMAPPED, /* Port B write */
	439	// DEVCB_UNMAPPED, /* Port C read */
	440	// DEVCB_UNMAPPED /* Port C write */
441	441	//};
442	442
443	443	/**************************
r19030	r19031
449	449	MCFG_CPU_ADD("maincpu", Z80, MASTER_CLOCK/8) /* 2MHz, guess */
450	450	MCFG_CPU_PROGRAM_MAP(supercrd_map)
451	451
452		// MCFG_NVRAM_ADD_0FILL("nvram")
	452	// MCFG_NVRAM_ADD_0FILL("nvram")
453	453
454		// MCFG_I8255_ADD( "ppi8255_0", ppi8255_intf_0 )
455		// MCFG_I8255_ADD( "ppi8255_1", ppi8255_intf_1 )
	454	// MCFG_I8255_ADD( "ppi8255_0", ppi8255_intf_0 )
	455	// MCFG_I8255_ADD( "ppi8255_1", ppi8255_intf_1 )
456	456
457	457	/* video hardware */
458	458
r19030	r19031
469	469	MCFG_PALETTE_INIT_OVERRIDE(supercrd_state, supercrd)
470	470	MCFG_VIDEO_START_OVERRIDE(supercrd_state, supercrd)
471	471
472		// MCFG_MC6845_ADD("crtc", MC6845, MASTER_CLOCK/8, mc6845_intf)
	472	// MCFG_MC6845_ADD("crtc", MC6845, MASTER_CLOCK/8, mc6845_intf)
473	473
474	474	/* sound hardware */
475	475	MCFG_SPEAKER_STANDARD_MONO("mono")
476	476
477		// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.75)
	477	// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.75)
478	478	MACHINE_CONFIG_END
479	479
480	480
r19030	r19031
488	488	ROM_LOAD( "supca_417_ce2.ic51", 0x10000, 0x08000, CRC(36415f73) SHA1(9881b88991f034d79260502289432a7318aa1647) ) // wrong
489	489	ROM_IGNORE( 0x8000)
490	490
491		// ROM_LOAD( "supca_417_ce1.ic37", 0x0000, 0x8000, CRC(b67f7d38) SHA1(eaf8f24d476185d4744858afcbf0005362f49cab) )
492		// ROM_CONTINUE( 0x0000, 0x8000)
493		// ROM_LOAD( "supca_417_ce2.ic51", 0x8000, 0x8000, CRC(36415f73) SHA1(9881b88991f034d79260502289432a7318aa1647) )
494		// ROM_IGNORE( 0x8000)
	491	// ROM_LOAD( "supca_417_ce1.ic37", 0x0000, 0x8000, CRC(b67f7d38) SHA1(eaf8f24d476185d4744858afcbf0005362f49cab) )
	492	// ROM_CONTINUE( 0x0000, 0x8000)
	493	// ROM_LOAD( "supca_417_ce2.ic51", 0x8000, 0x8000, CRC(36415f73) SHA1(9881b88991f034d79260502289432a7318aa1647) )
	494	// ROM_IGNORE( 0x8000)
495	495
496	496	ROM_REGION( 0x20000, "gfxtemp", 0 )
497	497	ROM_LOAD( "supca_410_zg2.ic11", 0x00000, 0x10000, CRC(a4646dc6) SHA1(638ad334bb4f1430381474ddfaa1029cb4d13916) )

trunk/src/mame/drivers/aerofgt.c
r19030	r19031
1634	1634	MCFG_DEVICE_ADD("vsystem_spr_ol2", VSYSTEM_SPR2, 0)
1635	1635	MCFG_VSYSTEM_SPR2_SET_TILE_INDIRECT( aerofgt_state, aerofgt_ol2_tile_callback )
1636	1636	MCFG_VSYSTEM_SPR2_SET_GFXREGION(3)
1637
	1637
1638	1638	MCFG_VIDEO_START_OVERRIDE(aerofgt_state,turbofrc)
1639	1639
1640	1640	/* sound hardware */

trunk/src/version.c
r19030	r19031
38	38	***************************************************************************/
39	39
40	40	extern const char build_version[];
41		const char build_version[] = "0.147u2 ("__DATE__")";
	41	const char build_version[] = "0.147u3 ("__DATE__")";

trunk/src/emu/sound/tms5110r.c
r19030	r19031
383	383	},
384	384	/* Chirp table */
385	385	/*
386		{ 0, 42, -44, 50, -78, 18, 37, 20,
387		2, -31, -59, 2, 95, 90, 5, 15,
388		38, -4, -91,-91, -42,-35,-36, -4,
389		37, 43, 34, 33, 15, -1, -8,-18,
390		-19,-17, -9,-10, -6, 0, 3, 2,
391		1, 0, 0, 0, 0, 0, 0, 0,
392		0, 0, 0, 0 },*/
	386	{ 0, 42, -44, 50, -78, 18, 37, 20,
	387	2, -31, -59, 2, 95, 90, 5, 15,
	388	38, -4, -91,-91, -42,-35,-36, -4,
	389	37, 43, 34, 33, 15, -1, -8,-18,
	390	-19,-17, -9,-10, -6, 0, 3, 2,
	391	1, 0, 0, 0, 0, 0, 0, 0,
	392	0, 0, 0, 0 },*/
393	393	{ 0,127,127, 0, 0, 0, 0, 0,
394	394	0, 0, 0, 0, 0, 0, 0, 0,
395	395	0, 0, 0, 0, 0, 0, 0, 0,
r19030	r19031
460	460	},
461	461	/* Chirp table */
462	462	/*
463		{ 0, 42, -44, 50, -78, 18, 37, 20,
464		2, -31, -59, 2, 95, 90, 5, 15,
465		38, -4, -91,-91, -42,-35,-36, -4,
466		37, 43, 34, 33, 15, -1, -8,-18,
467		-19,-17, -9,-10, -6, 0, 3, 2,
468		1, 0, 0, 0, 0, 0, 0, 0,
469		0, 0, 0, 0 },*/
	463	{ 0, 42, -44, 50, -78, 18, 37, 20,
	464	2, -31, -59, 2, 95, 90, 5, 15,
	465	38, -4, -91,-91, -42,-35,-36, -4,
	466	37, 43, 34, 33, 15, -1, -8,-18,
	467	-19,-17, -9,-10, -6, 0, 3, 2,
	468	1, 0, 0, 0, 0, 0, 0, 0,
	469	0, 0, 0, 0 },*/
470	470	{ 0,127,127, 0, 0, 0, 0, 0,
471	471	0, 0, 0, 0, 0, 0, 0, 0,
472	472	0, 0, 0, 0, 0, 0, 0, 0,
r19030	r19031
541	541	},
542	542	/* Chirp table */
543	543	/*
544		{ 0, 42, -44, 50, -78, 18, 37, 20,
545		2, -31, -59, 2, 95, 90, 5, 15,
546		38, -4, -91,-91, -42,-35,-36, -4,
547		37, 43, 34, 33, 15, -1, -8,-18,
548		-19,-17, -9,-10, -6, 0, 3, 2,
549		1, 0, 0, 0, 0, 0, 0, 0,
550		0, 0, 0, 0 },*/
	544	{ 0, 42, -44, 50, -78, 18, 37, 20,
	545	2, -31, -59, 2, 95, 90, 5, 15,
	546	38, -4, -91,-91, -42,-35,-36, -4,
	547	37, 43, 34, 33, 15, -1, -8,-18,
	548	-19,-17, -9,-10, -6, 0, 3, 2,
	549	1, 0, 0, 0, 0, 0, 0, 0,
	550	0, 0, 0, 0 },*/
551	551	{ 0,127,127, 0, 0, 0, 0, 0,
552	552	0, 0, 0, 0, 0, 0, 0, 0,
553	553	0, 0, 0, 0, 0, 0, 0, 0,

trunk/src/emu/sound/tms5220.c
r19030	r19031
418	418	UINT8 RDB_flag; /* whether we should read data register or status register */
419	419
420	420	/* io_ready: page 3 of the datasheet specifies that READY will be asserted until
421		* data is available or processed by the system.
422		*/
	421	* data is available or processed by the system.
	422	*/
423	423	UINT8 io_ready;
424	424
425	425	/* flag for "true" timing involving rs/ws */
r19030	r19031
431	431	UINT8 write_latch;
432	432
433	433	/* The TMS52xx has two different ways of providing output data: the
434		analog speaker pin (which was usually used) and the Digital I/O pin.
435		The internal DAC used to feed the analog pin is only 8 bits, and has the
436		funny clipping/clamping logic, while the digital pin gives full 12? bit
437		resolution of the output data.
438		TODO: add a way to set/reset this other than the FORCE_DIGITAL define
439		*/
	434	analog speaker pin (which was usually used) and the Digital I/O pin.
	435	The internal DAC used to feed the analog pin is only 8 bits, and has the
	436	funny clipping/clamping logic, while the digital pin gives full 12? bit
	437	resolution of the output data.
	438	TODO: add a way to set/reset this other than the FORCE_DIGITAL define
	439	*/
440	440	UINT8 digital_select;
441	441	device_t *device;
442	442
r19030	r19031
554	554
555	555	/**********************************************************************************************
556	556
557		printbits helper function: takes a long int input and prints the resulting bits to stderr
	557	printbits helper function: takes a long int input and prints the resulting bits to stderr
558	558
559	559	***********************************************************************************************/
560	560
r19030	r19031
592	592
593	593	/**********************************************************************************************
594	594
595		tms5220_data_write -- handle a write to the TMS5220
	595	tms5220_data_write -- handle a write to the TMS5220
596	596
597	597	***********************************************************************************************/
598	598
r19030	r19031
652	652
653	653	/**********************************************************************************************
654	654
655		update_status_and_ints -- check to see if the various flags should be on or off
656		Description of flags, and their position in the status register:
657		From the data sheet:
658		bit D0(bit 7) = TS - Talk Status is active (high) when the VSP is processing speech data.
659		Talk Status goes active at the initiation of a Speak command or after nine
660		bytes of data are loaded into the FIFO following a Speak External command. It
661		goes inactive (low) when the stop code (Energy=1111) is processed, or
662		immediately by a buffer empty condition or a reset command.
663		bit D1(bit 6) = BL - Buffer Low is active (high) when the FIFO buffer is more than half empty.
664		Buffer Low is set when the "Last-In" byte is shifted down past the half-full
665		boundary of the stack. Buffer Low is cleared when data is loaded to the stack
666		so that the "Last-In" byte lies above the half-full boundary and becomes the
667		eighth data byte of the stack.
668		bit D2(bit 5) = BE - Buffer Empty is active (high) when the FIFO buffer has run out of data
669		while executing a Speak External command. Buffer Empty is set when the last bit
670		of the "Last-In" byte is shifted out to the Synthesis Section. This causes
671		Talk Status to be cleared. Speech is terminated at some abnormal point and the
672		Speak External command execution is terminated.
	655	update_status_and_ints -- check to see if the various flags should be on or off
	656	Description of flags, and their position in the status register:
	657	From the data sheet:
	658	bit D0(bit 7) = TS - Talk Status is active (high) when the VSP is processing speech data.
	659	Talk Status goes active at the initiation of a Speak command or after nine
	660	bytes of data are loaded into the FIFO following a Speak External command. It
	661	goes inactive (low) when the stop code (Energy=1111) is processed, or
	662	immediately by a buffer empty condition or a reset command.
	663	bit D1(bit 6) = BL - Buffer Low is active (high) when the FIFO buffer is more than half empty.
	664	Buffer Low is set when the "Last-In" byte is shifted down past the half-full
	665	boundary of the stack. Buffer Low is cleared when data is loaded to the stack
	666	so that the "Last-In" byte lies above the half-full boundary and becomes the
	667	eighth data byte of the stack.
	668	bit D2(bit 5) = BE - Buffer Empty is active (high) when the FIFO buffer has run out of data
	669	while executing a Speak External command. Buffer Empty is set when the last bit
	670	of the "Last-In" byte is shifted out to the Synthesis Section. This causes
	671	Talk Status to be cleared. Speech is terminated at some abnormal point and the
	672	Speak External command execution is terminated.
673	673
674	674	***********************************************************************************************/
675	675
r19030	r19031
680	680	update_ready_state(tms);
681	681
682	682	/* BL is set if neither byte 9 nor 8 of the fifo are in use; this
683		translates to having fifo_count (which ranges from 0 bytes in use to 16
684		bytes used) being less than or equal to 8. Victory/Victorba depends on this. */
	683	translates to having fifo_count (which ranges from 0 bytes in use to 16
	684	bytes used) being less than or equal to 8. Victory/Victorba depends on this. */
685	685	if (tms->fifo_count <= 8)
686	686	{
687	687	// generate an interrupt if necessary; if /BL was inactive and is now active, set int.
r19030	r19031
693	693	tms->buffer_low = 0;
694	694
695	695	/* BE is set if neither byte 15 nor 14 of the fifo are in use; this
696		translates to having fifo_count equal to exactly 0 */
	696	translates to having fifo_count equal to exactly 0 */
697	697	if (tms->fifo_count == 0)
698	698	{
699	699	// generate an interrupt if necessary; if /BE was inactive and is now active, set int.
r19030	r19031
705	705	tms->buffer_empty = 0;
706	706
707	707	/* TS is talk status and is set elsewhere in the fifo parser and in
708		the SPEAK command handler; however, if /BE is true during speak external
709		mode, it is immediately unset here. */
	708	the SPEAK command handler; however, if /BE is true during speak external
	709	mode, it is immediately unset here. */
710	710	if ((tms->speak_external == 1) && (tms->buffer_empty == 1))
711	711	{
712	712	// generate an interrupt: /TS was active, and is now inactive.
r19030	r19031
717	717	}
718	718	}
719	719	/* Note that TS being unset will also generate an interrupt when a STOP
720		frame is encountered; this is handled in the sample generator code and not here */
	720	frame is encountered; this is handled in the sample generator code and not here */
721	721	}
722	722
723	723	/**********************************************************************************************
724	724
725		extract_bits -- extract a specific number of bits from the current input stream (FIFO or VSM)
	725	extract_bits -- extract a specific number of bits from the current input stream (FIFO or VSM)
726	726
727	727	***********************************************************************************************/
728	728
r19030	r19031
759	759
760	760	/**********************************************************************************************
761	761
762		tms5220_status_read -- read status or data from the TMS5220
	762	tms5220_status_read -- read status or data from the TMS5220
763	763
764	764	***********************************************************************************************/
765	765
r19030	r19031
801	801
802	802	/**********************************************************************************************
803	803
804		tms5220_cycles_to_ready -- returns the number of cycles until ready is asserted
805		NOTE: this function is deprecated and is known to be VERY inaccurate.
806		Use at your own peril!
	804	tms5220_cycles_to_ready -- returns the number of cycles until ready is asserted
	805	NOTE: this function is deprecated and is known to be VERY inaccurate.
	806	Use at your own peril!
807	807
808	808	***********************************************************************************************/
809	809
r19030	r19031
829	829	val = (tms->fifo[tms->fifo_head] >> tms->fifo_bits_taken) & 0xf;
830	830	if (val == 0)
831	831	/* 0 -> silence frame: we will only read 4 bits, and we will
832		* therefore need to read another frame before the FIFO is not
833		* full any more */
	832	* therefore need to read another frame before the FIFO is not
	833	* full any more */
834	834	answer += tms->subc_reload?200:304;
835	835	/* 15 -> stop frame, we will only read 4 bits, but the FIFO will
836		* we cleared; otherwise, we need to parse the repeat flag (1 bit)
837		* and the pitch (6 bits), so everything will be OK. */
	836	* we cleared; otherwise, we need to parse the repeat flag (1 bit)
	837	* and the pitch (6 bits), so everything will be OK. */
838	838	}
839	839	}
840	840
r19030	r19031
844	844
845	845	/**********************************************************************************************
846	846
847		tms5220_int_read -- returns the interrupt state of the TMS5220
	847	tms5220_int_read -- returns the interrupt state of the TMS5220
848	848
849	849	***********************************************************************************************/
850	850
r19030	r19031
859	859
860	860	/**********************************************************************************************
861	861
862		tms5220_process -- fill the buffer with a specific number of samples
	862	tms5220_process -- fill the buffer with a specific number of samples
863	863
864	864	***********************************************************************************************/
865	865
r19030	r19031
875	875	goto empty;
876	876
877	877	/* if speak external is set, but talk status is not (yet) set,
878		wait for buffer low to clear */
	878	wait for buffer low to clear */
879	879	if (!tms->talk_status && tms->speak_external && tms->buffer_low)
880	880	goto empty;
881	881
r19030	r19031
883	883	while ((size > 0) && tms->speaking_now)
884	884	{
885	885	/* if it is the appropriate time to update the old energy/pitch idxes,
886		* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
887		* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
888		* which happens 4 T-cycles later), we change on the latter.*/
	886	* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
	887	* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
	888	* which happens 4 T-cycles later), we change on the latter.*/
889	889	if ((tms->interp_period == 0) && (tms->PC == 0) && (tms->subcycle < 2))
890	890	{
891	891	tms->OLDE = (tms->new_frame_energy_idx == 0);
r19030	r19031
893	893	}
894	894
895	895	/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
896		* (In reality, the frame was really loaded incrementally during the entire IP=0
897		* PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
898		*/
	896	* (In reality, the frame was really loaded incrementally during the entire IP=0
	897	* PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
	898	*/
899	899	if ((tms->interp_period == 0) && (tms->PC == 12) && (tms->subcycle == 1))
900	900	{
901	901	// HACK for regression testing, be sure to comment out before release!
r19030	r19031
939	939	}
940	940
941	941	/* in all cases where interpolation would be inhibited, set the inhibit flag; otherwise clear it.
942		Interpolation inhibit cases:
943		* Old frame was voiced, new is unvoiced
944		* Old frame was silence/zero energy, new has nonzero energy
945		* Old frame was unvoiced, new is voiced
946		*/
	942	Interpolation inhibit cases:
	943	* Old frame was voiced, new is unvoiced
	944	* Old frame was silence/zero energy, new has nonzero energy
	945	* Old frame was unvoiced, new is voiced
	946	*/
947	947	if ( ((OLD_FRAME_UNVOICED_FLAG == 0) && (NEW_FRAME_UNVOICED_FLAG == 1))
948	948	\|\| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_UNVOICED_FLAG == 0))
949	949	\|\| ((OLD_FRAME_SILENCE_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 0)) )
r19030	r19031
1056	1056	{
1057	1057	// generate voiced samples here
1058	1058	/* US patent 4331836 Figure 14B shows, and logic would hold, that a pitch based chirp
1059		* function has a chirp/peak and then a long chain of zeroes.
1060		* The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample,
1061		* and if the address reaches that point the ADDRESS incrementer is
1062		* disabled, forcing all samples beyond 51d to be == 51d
1063		* (address 51d holds zeroes, which may or may not be inverted to -1)
1064		*/
	1059	* function has a chirp/peak and then a long chain of zeroes.
	1060	* The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample,
	1061	* and if the address reaches that point the ADDRESS incrementer is
	1062	* disabled, forcing all samples beyond 51d to be == 51d
	1063	* (address 51d holds zeroes, which may or may not be inverted to -1)
	1064	*/
1065	1065	if (tms->pitch_count >= 51)
1066	1066	tms->excitation_data = tms->coeff->chirptable[51];
1067	1067	else /tms->pitch_count < 51/
r19030	r19031
1124	1124	tms->PC++;
1125	1125	}
1126	1126	/* Circuit 412 in the patent ensures that when INHIBIT is true,
1127		* during the period from IP=7 PC=12 T12, to IP=0 PC=12 T12, the pitch
1128		* count is forced to 0; since the initial stop happens right before
1129		* the switch to IP=0 PC=0 and this code is located after the switch would
1130		* happen, we check for ip=0 inhibit=1, which covers that whole range.
1131		* The purpose of Circuit 412 is to prevent a spurious click caused by
1132		* the voiced source being fed to the filter before all the values have
1133		* been updated during ip=0 when interpolation was inhibited.
1134		*/
	1127	* during the period from IP=7 PC=12 T12, to IP=0 PC=12 T12, the pitch
	1128	* count is forced to 0; since the initial stop happens right before
	1129	* the switch to IP=0 PC=0 and this code is located after the switch would
	1130	* happen, we check for ip=0 inhibit=1, which covers that whole range.
	1131	* The purpose of Circuit 412 is to prevent a spurious click caused by
	1132	* the voiced source being fed to the filter before all the values have
	1133	* been updated during ip=0 when interpolation was inhibited.
	1134	*/
1135	1135	tms->pitch_count++;
1136	1136	if (tms->pitch_count >= tms->current_pitch) tms->pitch_count = 0;
1137	1137	if ((tms->interp_period == 0)&&(tms->inhibit==1)) tms->pitch_count = 0;
r19030	r19031
1165	1165
1166	1166	/**********************************************************************************************
1167	1167
1168		clip_analog -- clips the 14 bit return value from the lattice filter to its final 10 bit value (-512 to 511), and upshifts/range extends this to 16 bits
	1168	clip_analog -- clips the 14 bit return value from the lattice filter to its final 10 bit value (-512 to 511), and upshifts/range extends this to 16 bits
1169	1169
1170	1170	***********************************************************************************************/
1171	1171
1172	1172	static INT16 clip_analog(INT16 cliptemp)
1173	1173	{
1174	1174	/* clipping, just like the patent shows:
1175		* the top 10 bits of this result are visible on the digital output IO pin.
1176		* next, if the top 3 bits of the 14 bit result are all the same, the lowest of those 3 bits plus the next 7 bits are the signed analog output, otherwise the low bits are all forced to match the inverse of the topmost bit, i.e.:
1177		* 1x xxxx xxxx xxxx -> 0b10000000
1178		* 11 1bcd efgh xxxx -> 0b1bcdefgh
1179		* 00 0bcd efgh xxxx -> 0b0bcdefgh
1180		* 0x xxxx xxxx xxxx -> 0b01111111
1181		*/
	1175	* the top 10 bits of this result are visible on the digital output IO pin.
	1176	* next, if the top 3 bits of the 14 bit result are all the same, the lowest of those 3 bits plus the next 7 bits are the signed analog output, otherwise the low bits are all forced to match the inverse of the topmost bit, i.e.:
	1177	* 1x xxxx xxxx xxxx -> 0b10000000
	1178	* 11 1bcd efgh xxxx -> 0b1bcdefgh
	1179	* 00 0bcd efgh xxxx -> 0b0bcdefgh
	1180	* 0x xxxx xxxx xxxx -> 0b01111111
	1181	*/
1182	1182	#ifdef DEBUG_CLIP
1183	1183	if ((cliptemp > 2047) \|\| (cliptemp < -2048)) fprintf(stderr,"clipping cliptemp to range; was %d\n", cliptemp);
1184	1184	#endif
r19030	r19031
1203	1203
1204	1204	/**********************************************************************************************
1205	1205
1206		matrix_multiply -- does the proper multiply and shift
1207		a is the k coefficient and is clamped to 10 bits (9 bits plus a sign)
1208		b is the running result and is clamped to 14 bits.
1209		output is 14 bits, but note the result LSB bit is always 1.
1210		Because the low 4 bits of the result are trimmed off before
1211		output, this makes almost no difference in the computation.
	1206	matrix_multiply -- does the proper multiply and shift
	1207	a is the k coefficient and is clamped to 10 bits (9 bits plus a sign)
	1208	b is the running result and is clamped to 14 bits.
	1209	output is 14 bits, but note the result LSB bit is always 1.
	1210	Because the low 4 bits of the result are trimmed off before
	1211	output, this makes almost no difference in the computation.
1212	1212
1213	1213	**********************************************************************************************/
1214	1214	static INT32 matrix_multiply(INT32 a, INT32 b)
r19030	r19031
1228	1228
1229	1229	/**********************************************************************************************
1230	1230
1231		lattice_filter -- executes one 'full run' of the lattice filter on a specific byte of
1232		excitation data, and specific values of all the current k constants, and returns the
1233		resulting sample.
	1231	lattice_filter -- executes one 'full run' of the lattice filter on a specific byte of
	1232	excitation data, and specific values of all the current k constants, and returns the
	1233	resulting sample.
1234	1234
1235	1235	***********************************************************************************************/
1236	1236
r19030	r19031
1239	1239	// Lattice filter here
1240	1240	// Aug/05/07: redone as unrolled loop, for clarity - LN
1241	1241	/* Originally Copied verbatim from table I in US patent 4,209,804, now updated to be in same order as the actual chip does it, not that it matters.
1242		notation equivalencies from table:
1243		Yn(i) == tms->u[n-1]
1244		Kn = tms->current_k[n-1]
1245		bn = tms->x[n-1]
1246		*/
	1242	notation equivalencies from table:
	1243	Yn(i) == tms->u[n-1]
	1244	Kn = tms->current_k[n-1]
	1245	bn = tms->x[n-1]
	1246	*/
1247	1247	tms->u[10] = matrix_multiply(tms->previous_energy, (tms->excitation_data<<6)); //Y(11)
1248	1248	tms->u[9] = tms->u[10] - matrix_multiply(tms->current_k[9], tms->x[9]);
1249	1249	tms->u[8] = tms->u[9] - matrix_multiply(tms->current_k[8], tms->x[8]);
r19030	r19031
1282	1282
1283	1283	/**********************************************************************************************
1284	1284
1285		process_command -- extract a byte from the FIFO and interpret it as a command
	1285	process_command -- extract a byte from the FIFO and interpret it as a command
1286	1286
1287	1287	***********************************************************************************************/
1288	1288
r19030	r19031
1332	1332	if (tms->talk_status == 0) /* TALKST must be clear for LA */
1333	1333	{
1334	1334	/* tms5220 data sheet says that if we load only one 4-bit nibble, it won't work.
1335		This code does not care about this. */
	1335	This code does not care about this. */
1336	1336	if (tms->intf->load_address)
1337	1337	(*tms->intf->load_address)(tms->device, cmd & 0x0f);
1338	1338	tms->schedule_dummy_read = TRUE;
r19030	r19031
1403	1403	// We actually don't care how many bits are left in the fifo here; the frame subpart will be processed normally, and any bits extracted 'past the end' of the fifo will be read as zeroes; the fifo being emptied will set the /BE latch which will halt speech exactly as if a stop frame had been encountered (instead of whatever partial frame was read); the same exact circuitry is used for both on the real chip, see us patent 4335277 sheet 16, gates 232a (decode stop frame) and 232b (decode /BE plus DDIS (decode disable) which is active during speak external).
1404	1404
1405	1405	/* if the chip is a tms5220C, and the rate mode is set to that each frame (0x04 bit set)
1406		has a 2 bit rate preceding it, grab two bits here and store them as the rate; */
	1406	has a 2 bit rate preceding it, grab two bits here and store them as the rate; */
1407	1407	if ((tms->variant == SUBTYPE_TMS5220C) && (tms->tms5220c_rate & 0x04))
1408	1408	{
1409	1409	indx = extract_bits(tms, 2);
r19030	r19031
2177	2177
2178	2178	// initialize the chip state
2179	2179	/* Note that we do not actually clear IRQ on start-up: IRQ is even raised
2180		* if m_buffer_empty or m_buffer_low are 0 */
	2180	* if m_buffer_empty or m_buffer_low are 0 */
2181	2181	m_speaking_now = false;
2182	2182	m_speak_external = false;
2183	2183	m_talk_status = false;
r19030	r19031
2314	2314	while ((size > 0) && m_speaking_now)
2315	2315	{
2316	2316	/* if it is the appropriate time to update the old energy/pitch idxes,
2317		* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
2318		* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
2319		* which happens 4 T-cycles later), we change on the latter.
2320		*/
	2317	* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
	2318	* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
	2319	* which happens 4 T-cycles later), we change on the latter.
	2320	*/
2321	2321	if ((m_interp_period == 0) && (m_PC == 0) && (m_subcycle < 2))
2322	2322	{
2323	2323	m_OLDE = (m_new_frame_energy_idx == 0);
r19030	r19031
2325	2325	}
2326	2326
2327	2327	/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
2328		* (In reality, the frame was really loaded incrementally during the
2329		* entire IP=0 PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
2330		*/
	2328	* (In reality, the frame was really loaded incrementally during the
	2329	* entire IP=0 PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
	2330	*/
2331	2331	if ((m_interp_period == 0) && (m_PC == 12) && (m_subcycle == 1))
2332	2332	{
2333	2333	// HACK for regression testing, be sure to comment out before release!
r19030	r19031
2573	2573	m_PC++;
2574	2574	}
2575	2575	/* Circuit 412 in the patent ensures that when INHIBIT is true,
2576		* during the period from IP=7 PC=12 T12, to IP=0 PC=12 T12, the pitch
2577		* count is forced to 0; since the initial stop happens right before
2578		* the switch to IP=0 PC=0 and this code is located after the switch would
2579		* happen, we check for ip=0 inhibit=1, which covers that whole range.
2580		* The purpose of Circuit 412 is to prevent a spurious click caused by
2581		* the voiced source being fed to the filter before all the values have
2582		* been updated during ip=0 when interpolation was inhibited.
2583		*/
	2576	* during the period from IP=7 PC=12 T12, to IP=0 PC=12 T12, the pitch
	2577	* count is forced to 0; since the initial stop happens right before
	2578	* the switch to IP=0 PC=0 and this code is located after the switch would
	2579	* happen, we check for ip=0 inhibit=1, which covers that whole range.
	2580	* The purpose of Circuit 412 is to prevent a spurious click caused by
	2581	* the voiced source being fed to the filter before all the values have
	2582	* been updated during ip=0 when interpolation was inhibited.
	2583	*/
2584	2584	m_pitch_count++;
2585	2585	if (m_pitch_count >= m_current_pitch) m_pitch_count = 0;
2586	2586	if ((m_interp_period == 0) && m_inhibit) m_pitch_count = 0;
r19030	r19031
2622	2622	{
2623	2623	/* Lattice filter here */
2624	2624	/* Aug/05/07: redone as unrolled loop, for clarity - LN
2625		* Originally Copied verbatim from table I in US patent 4,209,804, now updated
2626		* to be in same order as the actual chip does it, not that it matters.
2627		* notation equivalencies from table:
2628		* Yn(i) == m_u[n-1]
2629		* Kn = m_current_k[n-1]
2630		* bn = m_x[n-1]
2631		*/
	2625	* Originally Copied verbatim from table I in US patent 4,209,804, now updated
	2626	* to be in same order as the actual chip does it, not that it matters.
	2627	* notation equivalencies from table:
	2628	* Yn(i) == m_u[n-1]
	2629	* Kn = m_current_k[n-1]
	2630	* bn = m_x[n-1]
	2631	*/
2632	2632
2633	2633	m_u[10] = matrix_multiply(m_previous_energy, (m_excitation_data<<6)); //Y(11)
2634	2634	m_u[9] = m_u[10] - matrix_multiply(m_current_k[9], m_x[9]);
r19030	r19031
2694	2694	logerror("tms52xx: data_write triggered talk status to go active!\n");
2695	2695	#endif
2696	2696	/* ...then we now have enough bytes to start talking; clear out
2697		* the new frame parameters (it will become old frame just before the first call to parse_frame())
2698		* TODO: the 3 lines below (and others) are needed for victory
2699		* to not fail its selftest due to a sample ending too late, may require additional investigation */
	2697	* the new frame parameters (it will become old frame just before the first call to parse_frame())
	2698	* TODO: the 3 lines below (and others) are needed for victory
	2699	* to not fail its selftest due to a sample ending too late, may require additional investigation */
2700	2700	m_subcycle = m_subc_reload;
2701	2701	m_PC = 0;
2702	2702	m_interp_period = reload_table[m_tms5220c_rate & 0x3]; // is this correct? should this be always 7 instead, so that the new frame is loaded quickly?
r19030	r19031
2842	2842	int indx, i, rep_flag;
2843	2843
2844	2844	/* We actually don't care how many bits are left in the fifo here; the
2845		* frame subpart will be processed normally, and any bits extracted 'past
2846		* the end' of the fifo will be read as zeroes; the fifo being emptied will
2847		* set the /BE latch which will halt speech exactly as if a stop frame had
2848		* been encountered (instead of whatever partial frame was read); the same
2849		* exact circuitry is used for both on the real chip, see us patent 4335277
2850		* sheet 16, gates 232a (decode stop frame) and 232b (decode /BE plus DDIS
2851		* (decode disable) which is active during speak external). */
	2845	* frame subpart will be processed normally, and any bits extracted 'past
	2846	* the end' of the fifo will be read as zeroes; the fifo being emptied will
	2847	* set the /BE latch which will halt speech exactly as if a stop frame had
	2848	* been encountered (instead of whatever partial frame was read); the same
	2849	* exact circuitry is used for both on the real chip, see us patent 4335277
	2850	* sheet 16, gates 232a (decode stop frame) and 232b (decode /BE plus DDIS
	2851	* (decode disable) which is active during speak external). */
2852	2852
2853	2853	/* if the chip is a tms5220C, and the rate mode is set to that each frame (0x04 bit set)
2854		* has a 2 bit rate preceding it, grab two bits here and store them as the rate; */
	2854	* has a 2 bit rate preceding it, grab two bits here and store them as the rate; */
2855	2855	if ((m_variant == SUBTYPE_TMS5220C) && (m_tms5220c_rate & 0x04))
2856	2856	{
2857	2857	indx = extract_bits(2);
r19030	r19031
2895	2895	update_status_and_ints();
2896	2896	if (!m_talk_status) goto ranout;
2897	2897	/* if this is a repeat frame, just do nothing, it will reuse the
2898		* old coefficients */
	2898	* old coefficients */
2899	2899	if (rep_flag) return;
2900	2900
2901	2901	// extract first 4 K coefficients
r19030	r19031
2972	2972	update_ready_state();
2973	2973
2974	2974	/* BL is set if neither byte 9 nor 8 of the fifo are in use; this
2975		* translates to having fifo_count (which ranges from 0 bytes in use to 16
2976		* bytes used) being less than or equal to 8. Victory/Victorba depends on this. */
	2975	* translates to having fifo_count (which ranges from 0 bytes in use to 16
	2976	* bytes used) being less than or equal to 8. Victory/Victorba depends on this. */
2977	2977	if (m_fifo_count <= 8)
2978	2978	{
2979	2979	// generate an interrupt if necessary; if /BL was inactive and is now active, set int.
r19030	r19031
2984	2984	m_buffer_low = false;
2985	2985
2986	2986	/* BE is set if neither byte 15 nor 14 of the fifo are in use; this
2987		* translates to having fifo_count equal to exactly 0 */
	2987	* translates to having fifo_count equal to exactly 0 */
2988	2988	if (m_fifo_count == 0)
2989	2989	{
2990	2990	// generate an interrupt if necessary; if /BE was inactive and is now active, set int.
r19030	r19031
2995	2995	m_buffer_empty = false;
2996	2996
2997	2997	/* TS is talk status and is set elsewhere in the fifo parser and in
2998		* the SPEAK command handler; however, if /BE is true during speak external
2999		* mode, it is immediately unset here. */
	2998	* the SPEAK command handler; however, if /BE is true during speak external
	2999	* mode, it is immediately unset here. */
3000	3000	if (m_speak_external && m_buffer_empty)
3001	3001	{
3002	3002	// generate an interrupt: /TS was active, and is now inactive.
r19030	r19031
3007	3007	}
3008	3008	}
3009	3009	/* Note that TS being unset will also generate an interrupt when a STOP
3010		* frame is encountered; this is handled in the sample generator code and not here */
	3010	* frame is encountered; this is handled in the sample generator code and not here */
3011	3011	}
3012	3012
3013	3013	/******************************************************************************
r19030	r19031
3214	3214	logerror("tms52xx: Scheduling ready cycle for /RS...\n");
3215	3215	#endif
3216	3216	/* upon /RS being activated, /READY goes inactive after 100 nsec from
3217		* data sheet, through 3 asynchronous gates on patent. This is effectively
3218		* within one clock, so we immediately set io_ready to 0 and activate the callback. */
	3217	* data sheet, through 3 asynchronous gates on patent. This is effectively
	3218	* within one clock, so we immediately set io_ready to 0 and activate the callback. */
3219	3219	m_io_ready = 0;
3220	3220	update_ready_state();
3221	3221	/* How long does /READY stay inactive, when /RS is pulled low?
3222		* I believe its almost always ~16 clocks (25 usec at 800khz as shown on the datasheet) */
	3222	* I believe its almost always ~16 clocks (25 usec at 800khz as shown on the datasheet) */
3223	3223	m_ready_timer->adjust(attotime::from_hz(clock()/16));
3224	3224	}
3225	3225	}
r19030	r19031
3270	3270	logerror("tms52xx: Scheduling ready cycle for /WS...\n");
3271	3271	#endif
3272	3272	/* upon /WS being activated, /READY goes inactive after 100 nsec
3273		* from data sheet, through 3 asynchronous gates on patent.
3274		* This is effectively within one clock, so we immediately set
3275		* io_ready to 0 and activate the callback. */
	3273	* from data sheet, through 3 asynchronous gates on patent.
	3274	* This is effectively within one clock, so we immediately set
	3275	* io_ready to 0 and activate the callback. */
3276	3276	m_io_ready = 0;
3277	3277	update_ready_state();
3278	3278	/* Now comes the complicated part: long does /READY stay inactive
3279		* when /WS is pulled low? This depends ENTIRELY on the command written,
3280		* or whether the chip is in speak external mode or not...
3281		* Speak external mode: ~16 cycles
3282		* Command Mode:
3283		* SPK: ? cycles
3284		* SPKEXT: ? cycles
3285		* RDBY: between 60 and 140 cycles
3286		* RB: ? cycles (80?)
3287		* RST: between 60 and 140 cycles
3288		* SET RATE (5220C only): ? cycles (probably ~16) */
	3279	* when /WS is pulled low? This depends ENTIRELY on the command written,
	3280	* or whether the chip is in speak external mode or not...
	3281	* Speak external mode: ~16 cycles
	3282	* Command Mode:
	3283	* SPK: ? cycles
	3284	* SPKEXT: ? cycles
	3285	* RDBY: between 60 and 140 cycles
	3286	* RB: ? cycles (80?)
	3287	* RST: between 60 and 140 cycles
	3288	* SET RATE (5220C only): ? cycles (probably ~16) */
3289	3289
3290	3290	// TODO: actually HANDLE the timing differences! currently just assuming always 16 cycles
3291	3291	m_ready_timer->adjust(attotime::from_hz(clock()/16));

trunk/src/emu/machine/scsicd.c
r19030	r19031
272	272	SetPhase( SCSI_PHASE_STATUS );
273	273	*transferLength = 0;
274	274	break;
275
276		case 0x4e: // STOP
	275
	276	case 0x4e: // STOP
277	277	if (cdrom)
278	278	{
279	279	cdda = cdda_from_cdrom(machine(), cdrom);

trunk/src/emu/cpu/m6502/m4510.c
r19030	r19031
57	57
58	58	void m4510_device::device_start()
59	59	{
60		if(direct_disabled)
	60	if(direct_disabled)
61	61	mintf = new mi_4510_nd(this);
62	62	else
63	63	mintf = new mi_4510_normal(this);

trunk/src/emu/cpu/m6502/m6502make.c
r19030	r19031
211	211	opc = string(opcode.begin(), k);
212	212	fullopc = string(opcode.begin(), ke-1);
213	213	mode = string(ke, opcode.end());
214
	214
215	215	bool step_over = opc == "jsr" \|\| opc == "bsr";
216	216	bool step_out = opc == "rts" \|\| opc == "rti" \|\| opc == "rtn";
217	217	fprintf(f, "\t{ \"%s\", DASM_%s, %s },\n",

trunk/src/emu/cpu/m6502/m6510.c
r19030	r19031
76	76	read_port.resolve_safe(0);
77	77	write_port.resolve_safe();
78	78
79		if(direct_disabled)
	79	if(direct_disabled)
80	80	mintf = new mi_6510_nd(this);
81	81	else
82	82	mintf = new mi_6510_normal(this);

trunk/src/emu/cpu/m6502/om65c02.lst
r19030	r19031
533	533	if(A & TMP2)
534	534	P &= ~F_Z;
535	535	else
536		P \|= F_Z;
	536	P \|= F_Z;
537	537	TMP2 &= ~A;
538	538	write(TMP, TMP2);
539	539	prefetch();
r19030	r19031
545	545	if(A & TMP2)
546	546	P &= ~F_Z;
547	547	else
548		P \|= F_Z;
	548	P \|= F_Z;
549	549	TMP2 &= ~A;
550	550	write(TMP, TMP2);
551	551	prefetch();
r19030	r19031
558	558	if(A & TMP2)
559	559	P &= ~F_Z;
560	560	else
561		P \|= F_Z;
	561	P \|= F_Z;
562	562	TMP2 \|= A;
563	563	write(TMP, TMP2);
564	564	prefetch();
r19030	r19031
570	570	if(A & TMP2)
571	571	P &= ~F_Z;
572	572	else
573		P \|= F_Z;
	573	P \|= F_Z;
574	574	TMP2 \|= A;
575	575	write(TMP, TMP2);
576	576	prefetch();

trunk/src/emu/cpu/m6502/om65ce02.lst
r19030	r19031
1459	1459	if(A & TMP2)
1460	1460	P &= ~F_Z;
1461	1461	else
1462		P \|= F_Z;
	1462	P \|= F_Z;
1463	1463	TMP2 &= ~A;
1464	1464	write(TMP, TMP2);
1465	1465	prefetch();
r19030	r19031
1470	1470	if(A & TMP2)
1471	1471	P &= ~F_Z;
1472	1472	else
1473		P \|= F_Z;
	1473	P \|= F_Z;
1474	1474	TMP2 &= ~A;
1475	1475	write(TMP, TMP2);
1476	1476	prefetch();
r19030	r19031
1482	1482	if(A & TMP2)
1483	1483	P &= ~F_Z;
1484	1484	else
1485		P \|= F_Z;
	1485	P \|= F_Z;
1486	1486	TMP2 \|= A;
1487	1487	write(TMP, TMP2);
1488	1488	prefetch();
r19030	r19031
1493	1493	if(A & TMP2)
1494	1494	P &= ~F_Z;
1495	1495	else
1496		P \|= F_Z;
	1496	P \|= F_Z;
1497	1497	TMP2 \|= A;
1498	1498	write(TMP, TMP2);
1499	1499	prefetch();

trunk/src/emu/cpu/m6502/om6502.lst
r19030	r19031
1962	1962	read(0xfffe);
1963	1963	for(;;) {
1964	1964	read(0xffff);
1965		}
	1965	}

trunk/src/emu/cpu/z8000/z8000ops.c
r19030	r19031
5829	5829	}
5830	5830
5831	5831	/******************************************
5832		trtib @rd,@rs,rr
5833		flags: -ZSV--
	5832	trtib @rd,@rs,rr
	5833	flags: -ZSV--
5834	5834	******************************************/
5835	5835	static void ZB8_ddN0_0010_0000_rrrr_ssN0_0000(z8000_state *cpustate)
5836	5836	{
r19030	r19031
5845	5845	}
5846	5846
5847	5847	/******************************************
5848		trtirb @rd,@rs,rbr
5849		flags: -ZSV--
	5848	trtirb @rd,@rs,rbr
	5849	flags: -ZSV--
5850	5850	******************************************/
5851	5851	static void ZB8_ddN0_0110_0000_rrrr_ssN0_1110(z8000_state *cpustate)
5852	5852	{
r19030	r19031
5866	5866	}
5867	5867
5868	5868	/******************************************
5869		trtdb @rd,@rs,rbr
5870		flags: -ZSV--
	5869	trtdb @rd,@rs,rbr
	5870	flags: -ZSV--
5871	5871	******************************************/
5872	5872	static void ZB8_ddN0_1010_0000_rrrr_ssN0_0000(z8000_state *cpustate)
5873	5873	{
r19030	r19031
5882	5882	}
5883	5883
5884	5884	/******************************************
5885		trtdrb @rd,@rs,rbr
5886		flags: -ZSV--
	5885	trtdrb @rd,@rs,rbr
	5886	flags: -ZSV--
5887	5887	******************************************/
5888	5888	static void ZB8_ddN0_1110_0000_rrrr_ssN0_1110(z8000_state *cpustate)
5889	5889	{
r19030	r19031
5903	5903	}
5904	5904
5905	5905	/******************************************
5906		trib @rd,@rs,rbr
5907		flags: -ZSV--
	5906	trib @rd,@rs,rbr
	5907	flags: -ZSV--
5908	5908	******************************************/
5909	5909	static void ZB8_ddN0_0000_0000_rrrr_ssN0_0000(z8000_state *cpustate)
5910	5910	{
r19030	r19031
5919	5919	}
5920	5920
5921	5921	/******************************************
5922		trirb @rd,@rs,rbr
5923		flags: -ZSV--
	5922	trirb @rd,@rs,rbr
	5923	flags: -ZSV--
5924	5924	******************************************/
5925	5925	static void ZB8_ddN0_0100_0000_rrrr_ssN0_0000(z8000_state *cpustate)
5926	5926	{
r19030	r19031
5935	5935	}
5936	5936
5937	5937	/******************************************
5938		trdb @rd,@rs,rbr
5939		flags: -ZSV--
	5938	trdb @rd,@rs,rbr
	5939	flags: -ZSV--
5940	5940	******************************************/
5941	5941	static void ZB8_ddN0_1000_0000_rrrr_ssN0_0000(z8000_state *cpustate)
5942	5942	{
r19030	r19031
5951	5951	}
5952	5952
5953	5953	/******************************************
5954		trdrb @rd,@rs,rbr
5955		flags: -ZSV--
	5954	trdrb @rd,@rs,rbr
	5955	flags: -ZSV--
5956	5956	******************************************/
5957	5957	static void ZB8_ddN0_1100_0000_rrrr_ssN0_0000(z8000_state *cpustate)
5958	5958	{

trunk/src/emu/cpu/avr8/avr8.c
r19030	r19031
9	9	the existing opcodes has been shown to wildly corrupt the video output in Craft, so one can assume that the
10	10	existing timing is 100% correct.
11	11
12		Unimplemented opcodes: CPSR, LD Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL, EICALL,
13		JMP, CALL
	12	Unimplemented opcodes: CPSR, LD Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL, EICALL,
	13	JMP, CALL
14	14
15		- Changelist -
16		30 Oct. 2012
17		- Added FMUL, FMULS, FMULSU opcodes [MooglyGuy]
18		- Fixed incorrect flag calculation in ROR opcode [MooglyGuy]
19		- Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy]
	15	- Changelist -
	16	30 Oct. 2012
	17	- Added FMUL, FMULS, FMULSU opcodes [MooglyGuy]
	18	- Fixed incorrect flag calculation in ROR opcode [MooglyGuy]
	19	- Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy]
20	20
21		25 Oct. 2012
22		- Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy]
23		- Corrected cycle counts for LD and ST opcodes [MooglyGuy]
24		- Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing
25		all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy]
26		- Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy]
	21	25 Oct. 2012
	22	- Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy]
	23	- Corrected cycle counts for LD and ST opcodes [MooglyGuy]
	24	- Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing
	25	all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy]
	26	- Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy]
27	27
28		18 Oct. 2012
29		- Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy]
30		- Fixed COM, NEG, LSR opcodes [MooglyGuy]
	28	18 Oct. 2012
	29	- Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy]
	30	- Fixed COM, NEG, LSR opcodes [MooglyGuy]
31	31
32	32	*/
33	33
r19030	r19031
783	783	//UINT8 compare_mode[2] = { (m_r[AVR8_REGIDX_TCCR0A] & AVR8_TCCR0A_COM0A_MASK) >> AVR8_TCCR0A_COM0A_SHIFT,
784	784	//(m_r[AVR8_REGIDX_TCCR0A] & AVR8_TCCR0A_COM0B_MASK) >> AVR8_TCCR0A_COM0B_SHIFT };
785	785	UINT8 ocr0[2] = { m_r[AVR8_REGIDX_OCR0A], m_r[AVR8_REGIDX_OCR0B] };
786		UINT8 ocf0[2] = { (1 << AVR8_TIFR0_OCF0A_SHIFT), (1 << AVR8_TIFR0_OCF0B_SHIFT) };
	786	UINT8 ocf0[2] = { (1 << AVR8_TIFR0_OCF0A_SHIFT), (1 << AVR8_TIFR0_OCF0B_SHIFT) };
787	787	INT32 increment = m_timer0_increment;
788	788
789	789	for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++)
r19030	r19031
854	854
855	855	m_r[AVR8_REGIDX_TCNT0] = count + increment;
856	856
857		update_interrupt(AVR8_INTIDX_OCF0A);
858		update_interrupt(AVR8_INTIDX_OCF0B);
859		update_interrupt(AVR8_INTIDX_TOV0);
	857	update_interrupt(AVR8_INTIDX_OCF0A);
	858	update_interrupt(AVR8_INTIDX_OCF0B);
	859	update_interrupt(AVR8_INTIDX_TOV0);
860	860	*/
861	861	}
862	862
r19030	r19031
1054	1054	break;
1055	1055
1056	1056	default:
1057		verboselog(m_pc, 0, "update_timer1_compare_mode: Unknown waveform generation mode: %02x\n", wgm1);
	1057	verboselog(m_pc, 0, "update_timer1_compare_mode: Unknown waveform generation mode: %02x\n", wgm1);
1058	1058	break;
1059	1059	}
1060	1060	/*

trunk/src/emu/cpu/avr8/avr8.h
r19030	r19031
9	9	the existing opcodes has been shown to wildly corrupt the video output in Craft, so one can assume that the
10	10	existing timing is 100% correct.
11	11
12		Unimplemented opcodes: CPSR, LD Z+, ST Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL,
13		EICALL, JMP, CALL, SBIW
	12	Unimplemented opcodes: CPSR, LD Z+, ST Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL,
	13	EICALL, JMP, CALL, SBIW
14	14
15		- Changelist -
16		30 Oct. 2012
17		- Added FMUL, FMULS, FMULSU opcodes [MooglyGuy]
18		- Fixed incorrect flag calculation in ROR opcode [MooglyGuy]
19		- Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy]
	15	- Changelist -
	16	30 Oct. 2012
	17	- Added FMUL, FMULS, FMULSU opcodes [MooglyGuy]
	18	- Fixed incorrect flag calculation in ROR opcode [MooglyGuy]
	19	- Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy]
20	20
21		25 Oct. 2012
22		- Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy]
23		- Corrected cycle counts for LD and ST opcodes [MooglyGuy]
24		- Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing
25		all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy]
26		- Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy]
	21	25 Oct. 2012
	22	- Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy]
	23	- Corrected cycle counts for LD and ST opcodes [MooglyGuy]
	24	- Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing
	25	all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy]
	26	- Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy]
27	27
28		18 Oct. 2012
29		- Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy]
30		- Fixed COM, NEG, LSR opcodes [MooglyGuy]
	28	18 Oct. 2012
	29	- Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy]
	30	- Fixed COM, NEG, LSR opcodes [MooglyGuy]
31	31
32	32	*/
33	33

trunk/src/emu/cpu/i386/i386.c
r19030	r19031
2831	2831	entry = seg->selector & ~0x7;
2832	2832	if (limit == 0 \|\| entry + 7 > limit)
2833	2833	return 0;
2834
	2834
2835	2835	address = entry + base;
2836	2836
2837	2837	// todo: bigendian
r19030	r19031
2910	2910
2911	2911	if(param[0] > 65535)
2912	2912	return 0;
2913
	2913
2914	2914	if (PROTECTED_MODE && !V8086_MODE)
2915	2915	{
2916	2916	memset(&seg, 0, sizeof(seg));

trunk/src/emu/video/pc_vga.c
r19030	r19031
2994	2994	/*
2995	2995	3d4h index 5Eh (R/W): Extended Vertical Overflow Register (80x +)
2996	2996	bit 0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h
2997		index 6). Bits 8 and 9 are in 3d4h index 7 bit 0 and 5.
2998		1 Vertical Display End bit 10. Bit 10 of the Vertical Display End
2999		register (3d4h index 12h). Bits 8 and 9 are in 3d4h index 7 bit 1
3000		and 6
3001		2 Start Vertical Blank bit 10. Bit 10 of the Vertical Start Blanking
3002		register (3d4h index 15h). Bit 8 is in 3d4h index 7 bit 3 and bit 9
3003		in 3d4h index 9 bit 5
3004		4 Vertical Retrace Start bit 10. Bit 10 of the Vertical Start Retrace
3005		register (3d4h index 10h). Bits 8 and 9 are in 3d4h index 7 bit 2
3006		and 7.
3007		6 Line Compare Position bit 10. Bit 10 of the Line Compare register
3008		(3d4h index 18h). Bit 8 is in 3d4h index 7 bit 4 and bit 9 in 3d4h
3009		index 9 bit 6.
	2997	index 6). Bits 8 and 9 are in 3d4h index 7 bit 0 and 5.
	2998	1 Vertical Display End bit 10. Bit 10 of the Vertical Display End
	2999	register (3d4h index 12h). Bits 8 and 9 are in 3d4h index 7 bit 1
	3000	and 6
	3001	2 Start Vertical Blank bit 10. Bit 10 of the Vertical Start Blanking
	3002	register (3d4h index 15h). Bit 8 is in 3d4h index 7 bit 3 and bit 9
	3003	in 3d4h index 9 bit 5
	3004	4 Vertical Retrace Start bit 10. Bit 10 of the Vertical Start Retrace
	3005	register (3d4h index 10h). Bits 8 and 9 are in 3d4h index 7 bit 2
	3006	and 7.
	3007	6 Line Compare Position bit 10. Bit 10 of the Line Compare register
	3008	(3d4h index 18h). Bit 8 is in 3d4h index 7 bit 4 and bit 9 in 3d4h
	3009	index 9 bit 6.
3010	3010	*/
3011	3011	case 0x5e:
3012	3012	vga.crtc.vert_total = (vga.crtc.vert_total & 0xfbff) \| ((data & 0x01) << 10);

trunk/src/mess/drivers/adam.c
r19030	r19031
626	626	{
627	627	/*
628	628
629		bit description
	629	bit description
630	630
631		0 Lower memory option 0
632		1 Lower memory option 1
633		2 Upper memory option 0
634		3 Upper memory option 1
635		4
636		5
637		6
638		7
	631	0 Lower memory option 0
	632	1 Lower memory option 1
	633	2 Upper memory option 0
	634	3 Upper memory option 1
	635	4
	636	5
	637	6
	638	7
639	639
640		*/
	640	*/
641	641
642	642	m_mioc = data;
643	643	}
r19030	r19031
666	666	{
667	667	/*
668	668
669		bit description
	669	bit description
670	670
671		0 Network reset
672		1 EOS enable
673		2
674		3
675		4
676		5
677		6
678		7
	671	0 Network reset
	672	1 EOS enable
	673	2
	674	3
	675	4
	676	5
	677	6
	678	7
679	679
680		*/
	680	*/
681	681
682	682	if (BIT(m_an, 0) && !BIT(data, 0))
683	683	{
r19030	r19031
698	698	{
699	699	/*
700	700
701		bit description
	701	bit description
702	702
703		0 BA8
704		1 BA9
705		2 BA10
706		3 BA11
707		4 BA12
708		5 BA13
709		6 BA14
710		7 BA15
	703	0 BA8
	704	1 BA9
	705	2 BA10
	706	3 BA11
	707	4 BA12
	708	5 BA13
	709	6 BA14
	710	7 BA15
711	711
712		*/
	712	*/
713	713
714	714	m_ba = (data << 8) \| (m_ba & 0xff);
715	715	}
r19030	r19031
723	723	{
724	724	/*
725	725
726		bit description
	726	bit description
727	727
728		0 M6801 mode bit 0
729		1 M6801 mode bit 1
730		2 M6801 mode bit 2
731		3 NET RXD
732		4
	728	0 M6801 mode bit 0
	729	1 M6801 mode bit 1
	730	2 M6801 mode bit 2
	731	3 NET RXD
	732	4
733	733
734		*/
	734	*/
735	735
736	736	UINT8 data = M6801_MODE_7;
737	737
r19030	r19031
750	750	{
751	751	/*
752	752
753		bit description
	753	bit description
754	754
755		0 _DMA
756		1
757		2 _BWR
758		3
759		4 NET TXD
	755	0 _DMA
	756	1
	757	2 _BWR
	758	3
	759	4 NET TXD
760	760
761		*/
	761	*/
762	762
763	763	// DMA
764	764	m_dma = BIT(data, 0);
r19030	r19031
779	779	{
780	780	/*
781	781
782		bit description
	782	bit description
783	783
784		0 BD0
785		1 BD1
786		2 BD2
787		3 BD3
788		4 BD4
789		5 BD5
790		6 BD6
791		7 BD7
	784	0 BD0
	785	1 BD1
	786	2 BD2
	787	3 BD3
	788	4 BD4
	789	5 BD5
	790	6 BD6
	791	7 BD7
792	792
793		*/
	793	*/
794	794
795	795	return m_data_out;
796	796	}
r19030	r19031
804	804	{
805	805	/*
806	806
807		bit description
	807	bit description
808	808
809		0 BD0
810		1 BD1
811		2 BD2
812		3 BD3
813		4 BD4
814		5 BD5
815		6 BD6
816		7 BD7
	809	0 BD0
	810	1 BD1
	811	2 BD2
	812	3 BD3
	813	4 BD4
	814	5 BD5
	815	6 BD6
	816	7 BD7
817	817
818		*/
	818	*/
819	819
820	820	m_data_in = data;
821	821	}
r19030	r19031
829	829	{
830	830	/*
831	831
832		bit description
	832	bit description
833	833
834		0 BA0
835		1 BA1
836		2 BA2
837		3 BA3
838		4 BA4
839		5 BA5
840		6 BA6
841		7 BA7
	834	0 BA0
	835	1 BA1
	836	2 BA2
	837	3 BA3
	838	4 BA4
	839	5 BA5
	840	6 BA6
	841	7 BA7
842	842
843		*/
	843	*/
844	844
845	845	m_ba = (m_ba & 0xff00) \| data;
846	846	}
r19030	r19031
1168	1168	MCFG_ADAM_EXPANSION_SLOT_ADD(ADAM_LEFT_EXPANSION_SLOT_TAG, XTAL_7_15909MHz/2, slot1_intf, adam_slot1_devices, "adamlink", NULL)
1169	1169	MCFG_ADAM_EXPANSION_SLOT_ADD(ADAM_CENTER_EXPANSION_SLOT_TAG, XTAL_7_15909MHz/2, slot2_intf, adam_slot2_devices, NULL, NULL)
1170	1170	MCFG_ADAM_EXPANSION_SLOT_ADD(ADAM_RIGHT_EXPANSION_SLOT_TAG, XTAL_7_15909MHz/2, slot3_intf, adam_slot3_devices, "ram", NULL)
1171
	1171
1172	1172	// internal ram
1173	1173	MCFG_RAM_ADD(RAM_TAG)
1174	1174	MCFG_RAM_DEFAULT_SIZE("64K")

trunk/src/mess/drivers/pc100.c
r19030	r19031
2	2
3	3	NEC PC-100
4	4
5		preliminary driver by Angelo Salese
6		Thanks to Carl for the i8259 tip;
	5	preliminary driver by Angelo Salese
	6	Thanks to Carl for the i8259 tip;
7	7
8	8	TODO:
9	9	- floppy support (no images available right now);
r19030	r19031
20	20	F8216: FA cli
21	21	F8217: 0A E9 or ch,cl
22	22	F8219: 74 15 je 0F8230h
23		- Second one is for the vblank irq timing:
24		F8238: 8B D3 mov dx,bx
25		F823A: 8B D9 mov bx,cx
26		F823C: CF iret
27		F824D: E4 02 in al,2h
28		F824F: 8A E0 mov ah,al
29		F8251: B0 EF mov al,0EFh
30		F8253: E6 02 out 2h,al
31		F8255: BB 00 00 mov bx,0h
32		F8258: BA 00 00 mov dx,0h
33		F825B: B9 20 4E mov cx,4E20h
34		F825E: FB sti
35		F825F: E2 FE loop 0F825Fh ;calculates the vblank here
36		F8261: FA cli
37		F8262: 8A C4 mov al,ah
38		F8264: E6 02 out 2h,al
39		F8266: 2B D3 sub dx,bx
40		F8268: 81 FA 58 1B cmp dx,1B58h
41		F826C: 78 06 js 0F8274h ;error if DX is smaller than 0x1b58
42		F826E: 81 FA 40 1F cmp dx,1F40h
43		F8272: 78 0A js 0F827Eh ;error if DX is greater than 0x1f40
44		F8274: B1 05 mov cl,5h
45		F8276: E8 CB 03 call 0F8644h
46		F8279: E8 79 FF call 0F81F5h
47		F827C: EB FE jmp 0F827Ch
48		F827E: B0 FF mov al,0FFh
49		fwiw with current timings, we get DX=0x1f09, enough for passing the test;
	23	- Second one is for the vblank irq timing:
	24	F8238: 8B D3 mov dx,bx
	25	F823A: 8B D9 mov bx,cx
	26	F823C: CF iret
	27	F824D: E4 02 in al,2h
	28	F824F: 8A E0 mov ah,al
	29	F8251: B0 EF mov al,0EFh
	30	F8253: E6 02 out 2h,al
	31	F8255: BB 00 00 mov bx,0h
	32	F8258: BA 00 00 mov dx,0h
	33	F825B: B9 20 4E mov cx,4E20h
	34	F825E: FB sti
	35	F825F: E2 FE loop 0F825Fh ;calculates the vblank here
	36	F8261: FA cli
	37	F8262: 8A C4 mov al,ah
	38	F8264: E6 02 out 2h,al
	39	F8266: 2B D3 sub dx,bx
	40	F8268: 81 FA 58 1B cmp dx,1B58h
	41	F826C: 78 06 js 0F8274h ;error if DX is smaller than 0x1b58
	42	F826E: 81 FA 40 1F cmp dx,1F40h
	43	F8272: 78 0A js 0F827Eh ;error if DX is greater than 0x1f40
	44	F8274: B1 05 mov cl,5h
	45	F8276: E8 CB 03 call 0F8644h
	46	F8279: E8 79 FF call 0F81F5h
	47	F827C: EB FE jmp 0F827Ch
	48	F827E: B0 FF mov al,0FFh
	49	fwiw with current timings, we get DX=0x1f09, enough for passing the test;
50	50
51	51	****************************************************************************/
52	52
r19030	r19031
352	352	WRITE8_MEMBER( pc100_state::rtc_porta_w )
353	353	{
354	354	/*
355		---- -x-- chip select
356		---- --x- read
357		---- ---x write
	355	---- -x-- chip select
	356	---- --x- read
	357	---- ---x write
358	358	*/
359	359
360	360	m_rtc->write_w(data & 1);

trunk/src/mess/drivers/apple3.c
r19030	r19031
72	72	/* basic machine hardware */
73	73	MCFG_CPU_ADD("maincpu", M6502, 2000000) /* 2 MHz */
74	74	MCFG_CPU_PROGRAM_MAP(apple3_map)
75		// MCFG_CPU_CONFIG( apple3_m6502_interface )
	75	// MCFG_CPU_CONFIG( apple3_m6502_interface )
76	76	MCFG_CPU_PERIODIC_INT_DRIVER(apple3_state, apple3_interrupt, 192)
77	77	MCFG_QUANTUM_TIME(attotime::from_hz(60))
78	78

trunk/src/mess/drivers/pc9801.c
r19030	r19031
9	9	- proper 8251 uart hook-up on keyboard
10	10	- boot is too slow right now, might be due of the floppy / HDD devices
11	11	- investigate on POR bit
12		- Write a PC80S31K device (also used on PC-8801 and PC-88VA, it's the FDC + Z80 sub-system);
	12	- Write a PC80S31K device (also used on PC-8801 and PC-88VA, it's the FDC + Z80 sub-system);
13	13
14	14	TODO (PC-9801RS):
15	15	- floppy disk hook-up;

trunk/src/mess/drivers/alphasma.c
r19030	r19031
4	4
5	5	08/28/2012 Skeleton driver
6	6
7		TODO:
8		- define video HW capabilities
9		- "Addr. Bus RAM error" string read, presumably memory mapped RAM at 0x8000
10		is actually a r/w bank register.
	7	TODO:
	8	- define video HW capabilities
	9	- "Addr. Bus RAM error" string read, presumably memory mapped RAM at 0x8000
	10	is actually a r/w bank register.
11	11
12	12	****************************************************************************/
13	13
r19030	r19031
30	30
31	31	virtual void machine_start();
32	32	virtual void palette_init();
33		// virtual UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	33	// virtual UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
34	34	};
35	35
36	36
r19030	r19031
41	41	ADDRESS_MAP_END
42	42
43	43	static ADDRESS_MAP_START(alphasmart_io, AS_IO, 8, alphasmart_state)
44		// AM_RANGE(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA) AM_DEVREADWRITE("hd44780", hd44780_device, control_read, control_write)
45		// AM_RANGE(MC68HC11_IO_PORTD, MC68HC11_IO_PORTD) AM_DEVREADWRITE("hd44780", hd44780_device, data_read, data_write)
	44	// AM_RANGE(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA) AM_DEVREADWRITE("hd44780", hd44780_device, control_read, control_write)
	45	// AM_RANGE(MC68HC11_IO_PORTD, MC68HC11_IO_PORTD) AM_DEVREADWRITE("hd44780", hd44780_device, data_read, data_write)
46	46	ADDRESS_MAP_END
47	47
48	48	/* Input ports */
r19030	r19031
79	79	MCFG_CPU_PROGRAM_MAP(alphasmart_mem)
80	80	MCFG_CPU_IO_MAP(alphasmart_io)
81	81	MCFG_CPU_CONFIG(alphasmart_hc11_config)
82		// MCFG_CPU_PERIODIC_INT_DRIVER(alphasmart_state, irq0_line_hold, 50)
	82	// MCFG_CPU_PERIODIC_INT_DRIVER(alphasmart_state, irq0_line_hold, 50)
83	83
84	84	MCFG_HD44780_ADD("hd44780", alphasmart_4line_display)
85	85

trunk/src/mess/drivers/apc.c
r19030	r19031
1	1	/***************************************************************************
2	2
3		Advanced Personal Computer (c) 1982 NEC
	3	Advanced Personal Computer (c) 1982 NEC
4	4
5		preliminary driver by Angelo Salese
	5	preliminary driver by Angelo Salese
6	6
7		TODO:
8		- video emulation
9		- Floppy device
10		- keyboard
11		- Understand interrupt sources
12		- NMI seems valid, dumps a x86 stack to vram?
13		- Unknown RTC device type;
14		- What are exactly APU and MPU devices? They sounds scary ...
15		- DMA hook-ups
16		- serial ports
17		- parallel ports
18		- Extract info regarding Hard Disk functionality
19		- Various unknown ports
20		- What kind of external ROM actually maps at 0xa****?
	7	TODO:
	8	- video emulation
	9	- Floppy device
	10	- keyboard
	11	- Understand interrupt sources
	12	- NMI seems valid, dumps a x86 stack to vram?
	13	- Unknown RTC device type;
	14	- What are exactly APU and MPU devices? They sounds scary ...
	15	- DMA hook-ups
	16	- serial ports
	17	- parallel ports
	18	- Extract info regarding Hard Disk functionality
	19	- Various unknown ports
	20	- What kind of external ROM actually maps at 0xa****?
21	21
22	22	============================================================================
23		front ^
24		\|
25		card
26		----
27		69PFCU 7220 PFCU1R 2764
28		69PTS 7220
29		-
30		69PFB2 8086/8087 DFBU2J PFBU2L 2732
31		69SNB RAM
	23	front ^
	24	\|
	25	card
	26	----
	27	69PFCU 7220 PFCU1R 2764
	28	69PTS 7220
	29	-
	30	69PFB2 8086/8087 DFBU2J PFBU2L 2732
	31	69SNB RAM
32	32
33	33	----------------------------------------------------------------------------
34		i/o memory map (preliminary):
35		0x00 - 0x1f DMA
36		0x20 - 0x23 i8259 master
37		0x28 - 0x2f i8259 slave (even), pit8253 (odd)
38		0x30 - 0x37 serial i8251, even #1 / odd #2
39		0x38 - 0x3f DMA segments
40		0x40 - 0x43 upd7220, even chr / odd bitmap
41		0x48 - 0x4f keyboard
42		0x50 - 0x53 upd765
43		0x58 rtc
44		0x5a - 0x5e APU
45		0x60 MPU (melody)
46		0x61 - 0x67 (Mirror of pit8253?)
47		0x68 - 0x6f parallel port
	34	i/o memory map (preliminary):
	35	0x00 - 0x1f DMA
	36	0x20 - 0x23 i8259 master
	37	0x28 - 0x2f i8259 slave (even), pit8253 (odd)
	38	0x30 - 0x37 serial i8251, even #1 / odd #2
	39	0x38 - 0x3f DMA segments
	40	0x40 - 0x43 upd7220, even chr / odd bitmap
	41	0x48 - 0x4f keyboard
	42	0x50 - 0x53 upd765
	43	0x58 rtc
	44	0x5a - 0x5e APU
	45	0x60 MPU (melody)
	46	0x61 - 0x67 (Mirror of pit8253?)
	47	0x68 - 0x6f parallel port
48	48
49	49	----------------------------------------------------------------------------
50	50	0xfe3c2: checks if the floppy has a valid string for booting (either "CP/M-86"
r19030	r19031
172	172	int xi,yi;
173	173	int x;
174	174	UINT8 char_size;
175		// UINT8 interlace_on;
	175	// UINT8 interlace_on;
176	176
177		// if(state->m_video_ff[DISPLAY_REG] == 0) //screen is off
178		// return;
	177	// if(state->m_video_ff[DISPLAY_REG] == 0) //screen is off
	178	// return;
179	179
180		// interlace_on = state->m_video_reg[2] == 0x10; /* TODO: correct? */
	180	// interlace_on = state->m_video_reg[2] == 0x10; /* TODO: correct? */
181	181	char_size = 16;
182	182
183	183	for(x=0;x<pitch;x++)
184	184	{
185	185	UINT8 tile_data;
186		// UINT8 secret,reverse,u_line,v_line;
	186	// UINT8 secret,reverse,u_line,v_line;
187	187	UINT8 color;
188	188	UINT8 tile,attr,pen;
189	189	UINT32 tile_addr;
190	190
191		// tile_addr = addr+(x*(state->m_video_ff[WIDTH40_REG]+1));
	191	// tile_addr = addr+(x*(state->m_video_ff[WIDTH40_REG]+1));
192	192	tile_addr = addr+(x*(1));
193	193
194	194	tile = state->m_video_ram_1[(tile_addr*2+1) & 0x1fff] & 0x007f;
195	195	attr = (state->m_video_ram_1[(tile_addr*2 & 0x1fff) \| 0x2000] & 0x00ff);
196	196
197		// secret = (attr & 1) ^ 1;
	197	// secret = (attr & 1) ^ 1;
198	198	//blink = attr & 2;
199		// reverse = attr & 4;
200		// u_line = attr & 8;
201		// v_line = attr & 0x10;
	199	// reverse = attr & 4;
	200	// u_line = attr & 8;
	201	// v_line = attr & 0x10;
202	202	color = (attr & 0xe0) >> 5;
203	203
204	204	for(yi=0;yi<lr;yi++)
r19030	r19031
207	207	{
208	208	int res_x,res_y;
209	209
210		// res_x = (x8+xi) (state->m_video_ff[WIDTH40_REG]+1);
	210	// res_x = (x8+xi) (state->m_video_ff[WIDTH40_REG]+1);
211	211	res_x = (x8+xi) (1);
212	212	res_y = y*lr+yi;
213	213
214	214	if(res_x > 640 \|\| res_y > char_size*25) //TODO
215	215	continue;
216	216
217		// tile_data = secret ? 0 : (state->m_char_rom[tilechar_size+interlace_on0x800+yi]);
	217	// tile_data = secret ? 0 : (state->m_char_rom[tilechar_size+interlace_on0x800+yi]);
218	218	tile_data = (state->m_char_rom[tile+yi*0x80]);
219	219
220		// if(reverse) { tile_data^=0xff; }
221		// if(u_line && yi == 7) { tile_data = 0xff; }
222		// if(v_line) { tile_data\|=8; }
	220	// if(reverse) { tile_data^=0xff; }
	221	// if(u_line && yi == 7) { tile_data = 0xff; }
	222	// if(v_line) { tile_data\|=8; }
223	223
224	224	if(cursor_on && cursor_addr == tile_addr)
225	225	tile_data^=0xff;
r19030	r19031
232	232	if(pen)
233	233	bitmap.pix16(res_y, res_x) = pen;
234	234
235		// if(state->m_video_ff[WIDTH40_REG])
236		// {
237		// if(res_x+1 > 640 \|\| res_y > char_size*25) //TODO
238		// continue;
	235	// if(state->m_video_ff[WIDTH40_REG])
	236	// {
	237	// if(res_x+1 > 640 \|\| res_y > char_size*25) //TODO
	238	// continue;
239	239
240		// bitmap.pix16(res_y, res_x+1) = pen;
241		// }
	240	// bitmap.pix16(res_y, res_x+1) = pen;
	241	// }
242	242	}
243	243	}
244	244	}
r19030	r19031
387	387
388	388	static ADDRESS_MAP_START( apc_map, AS_PROGRAM, 16, apc_state )
389	389	AM_RANGE(0x00000, 0x9ffff) AM_RAM
390		// AM_RANGE(0xa0000, 0xaffff) space for an external ROM
	390	// AM_RANGE(0xa0000, 0xaffff) space for an external ROM
391	391	AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION("ipl", 0)
392	392	ADDRESS_MAP_END
393	393
r19030	r19031
396	396	AM_RANGE(0x00, 0x1f) AM_READWRITE8(apc_dma_r, apc_dma_w,0xff00)
397	397	AM_RANGE(0x20, 0x23) AM_DEVREADWRITE8_LEGACY("pic8259_master", pic8259_r, pic8259_w, 0x00ff) // i8259
398	398	AM_RANGE(0x28, 0x2f) AM_READWRITE8(apc_port_28_r, apc_port_28_w, 0xffff)
399		// 0x30, 0x37 serial port 0/1 (i8251) (even/odd)
	399	// 0x30, 0x37 serial port 0/1 (i8251) (even/odd)
400	400	AM_RANGE(0x38, 0x3f) AM_WRITE8(apc_dma_segments_w,0x00ff)
401	401	AM_RANGE(0x40, 0x43) AM_READWRITE8(apc_gdc_r, apc_gdc_w, 0xffff)
402	402	// 0x46 UPD7220 reset interrupt
403	403	AM_RANGE(0x48, 0x4f) AM_READWRITE8(apc_kbd_r, apc_kbd_w, 0x00ff)
404	404	AM_RANGE(0x50, 0x53) AM_DEVICE8("upd765", upd765a_device, map, 0x00ff ) // upd765
405		// 0x5a APU data (Arithmetic Processing Unit!)
406		// 0x5e APU status/command
	405	// 0x5a APU data (Arithmetic Processing Unit!)
	406	// 0x5e APU status/command
407	407	AM_RANGE(0x60, 0x67) AM_READWRITE8(apc_port_60_r, apc_port_60_w, 0xffff)
408		// 0x60 Melody Processing Unit
409		// AM_RANGE(0x68, 0x6f) i8255 , printer port (A: status (R) B: data (W) C: command (W))
410		// AM_DEVREADWRITE8("upd7220_btm", upd7220_device, read, write, 0x00ff)
	408	// 0x60 Melody Processing Unit
	409	// AM_RANGE(0x68, 0x6f) i8255 , printer port (A: status (R) B: data (W) C: command (W))
	410	// AM_DEVREADWRITE8("upd7220_btm", upd7220_device, read, write, 0x00ff)
411	411	ADDRESS_MAP_END
412	412
413	413	static INPUT_PORTS_START( apc )
r19030	r19031
468	468
469	469	void apc_state::fdc_drq(bool state)
470	470	{
471		// printf("%02x DRQ\n",state);
472		// i8237_dreq0_w(m_dma, state);
	471	// printf("%02x DRQ\n",state);
	472	// i8237_dreq0_w(m_dma, state);
473	473	m_dmac->dreq1_w(state);
474	474
475	475	}
476	476
477	477	void apc_state::fdc_irq(bool state)
478	478	{
479		// printf("IRQ %d\n",state);
	479	// printf("IRQ %d\n",state);
480	480	pic8259_ir3_w(machine().device("pic8259_slave"), state);
481	481	}
482	482
r19030	r19031
628	628
629	629	m_dmac->hack_w(state);
630	630
631		// printf("%02x HLDA\n",state);
	631	// printf("%02x HLDA\n",state);
632	632	}
633	633
634	634	WRITE_LINE_MEMBER( apc_state::apc_tc_w )
r19030	r19031
655	655	address_space &program = m_maincpu->space(AS_PROGRAM);
656	656	offs_t addr = (m_dma_offset[m_dack] << 16) \| offset;
657	657
658		// printf("%08x %02x\n",addr,data);
	658	// printf("%08x %02x\n",addr,data);
659	659
660	660	program.write_byte(addr, data);
661	661	}
r19030	r19031
673	673
674	674	READ8_MEMBER(apc_state::test_r)
675	675	{
676		// printf("2dd DACK R\n");
	676	// printf("2dd DACK R\n");
677	677
678	678	return m_fdc->dma_r();
679	679	}
r19030	r19031
767	767	ROM_LOAD16_BYTE( "pfbu2j.bin", 0x00000, 0x001000, CRC(86970df5) SHA1(be59c5dad3bd8afc21e9f2f1404553d4371978be) )
768	768	ROM_LOAD16_BYTE( "pfbu2l.bin", 0x00001, 0x001000, CRC(38df2e70) SHA1(a37ccaea00c2b290610d354de08b489fa897ec48) )
769	769
770		// ROM_REGION( 0x10000, "file", ROMREGION_ERASE00 )
771		// ROM_LOAD( "sioapc.o", 0, 0x10000, CRC(1) SHA1(1) )
	770	// ROM_REGION( 0x10000, "file", ROMREGION_ERASE00 )
	771	// ROM_LOAD( "sioapc.o", 0, 0x10000, CRC(1) SHA1(1) )
772	772
773	773	ROM_REGION( 0x2000, "gfx", ROMREGION_ERASE00 )
774	774	ROM_LOAD("pfcu1r.bin", 0x000000, 0x002000, CRC(683efa94) SHA1(43157984a1746b2e448f3236f571011af9a3aa73) )

trunk/src/mess/drivers/a7800.c
r19030	r19031
9	9	2002/05/13 kubecj added more banks for bankswitching
10	10	added PAL machine description
11	11	changed clock to be precise
12
13		2012/10/25 Robert Tuccitto NTSC Color Generator utilized for
14		color palette with hue shift/start
15		based on observation of several
16		systems across multiple displays
17	12
	13	2012/10/25 Robert Tuccitto NTSC Color Generator utilized for
	14	color palette with hue shift/start
	15	based on observation of several
	16	systems across multiple displays
	17
18	18	2012/11/09 Robert Tuccitto Fixed 3 degree hue begin point
19		miscalculation of color palette
	19	miscalculation of color palette
20	20
21	21	***************************************************************************/
22	22

trunk/src/mess/drivers/ng_aes.c
r19030	r19031
92	92	if(neocd.cd == NULL) // no cd is there, bail out
93	93	return QChannelData;
94	94
95		// NeoCDSectorLBA
	95	// NeoCDSectorLBA
96	96	switch (CDEmuStatus) {
97	97	case reading:
98	98	case playing: {
99
	99
100	100	UINT32 msf;
101	101	msf = lba_to_msf_alt(NeoCDSectorLBA+150);
102	102
103	103
104	104
105	105	QChannelData[0] = cdrom_get_track(neocd.cd, NeoCDSectorLBA);
106
	106
107	107	QChannelData[1] = (msf >> 16)&0xff;
108	108	QChannelData[2] = (msf >> 8)&0xff;
109	109	QChannelData[3] = (msf >> 0)&0xff;
110
	110
111	111	int elapsedlba;
112	112	elapsedlba = NeoCDSectorLBA - neocd.toc->tracks[ cdrom_get_track(neocd.cd, NeoCDSectorLBA) ].physframeofs;
113	113	msf = lba_to_msf_alt (elapsedlba);
r19030	r19031
115	115	QChannelData[4] = (msf >> 16)&0xff;
116	116	QChannelData[5] = (msf >> 8)&0xff;
117	117	QChannelData[6] = (msf >> 0)&0xff;
118
	118
119	119	if (QChannelData[0]==1)
120	120	QChannelData[7] = 0x4;
121	121	else
r19030	r19031
140	140
141	141	static unsigned char TOCEntry[4];
142	142
143		if(neocd.cd == NULL)
	143	if(neocd.cd == NULL)
144	144	return TOCEntry;
145	145
146	146
r19030	r19031
252	252	static void MapVectorTable(bool bMapBoardROM)
253	253	{
254	254	/*
255		if (!bMapBoardROM && Neo68KROMActive) {
256		SekMapMemory(Neo68KFix[nNeoActiveSlot], 0x000000, 0x0003FF, SM_ROM);
257		} else {
258		SekMapMemory(NeoVectorActive, 0x000000, 0x0003FF, SM_ROM);
259		}
260		*/
	255	if (!bMapBoardROM && Neo68KROMActive) {
	256	SekMapMemory(Neo68KFix[nNeoActiveSlot], 0x000000, 0x0003FF, SM_ROM);
	257	} else {
	258	SekMapMemory(NeoVectorActive, 0x000000, 0x0003FF, SM_ROM);
	259	}
	260	*/
261	261	}
262	262
263	263
r19030	r19031
404	404
405	405	void ng_aes_state::SekWriteWord(UINT32 a, UINT16 d)
406	406	{
407		// printf("write word %08x %04x\n", a, d);
	407	// printf("write word %08x %04x\n", a, d);
408	408	curr_space->write_word(a,d);
409	409	}
410	410
411	411	void ng_aes_state::SekWriteByte(UINT32 a, UINT8 d)
412	412	{
413		// printf("write byte %08x %02x\n", a, d);
	413	// printf("write byte %08x %02x\n", a, d);
414	414	curr_space->write_byte(a,d);
415	415	}
416	416
417	417	UINT32 ng_aes_state::SekReadByte(UINT32 a)
418	418	{
419		// printf("read byte %08x\n", a);
	419	// printf("read byte %08x\n", a);
420	420	return curr_space->read_byte(a);
421	421	}
422	422
423	423
424	424	UINT32 ng_aes_state::SekReadWord(UINT32 a)
425	425	{
426		// printf("read WORD %08x\n", a);
	426	// printf("read WORD %08x\n", a);
427	427	return curr_space->read_word(a);
428	428	}
429	429
r19030	r19031
947	947	if ((nff0002 & 0x0500)) {
948	948	if (NeoCDAssyStatus == 1 && bNeoCDLoadSector) {
949	949
950		// if (LC8951RegistersW[10] & 0x80) {
	950	// if (LC8951RegistersW[10] & 0x80) {
951	951	NeoCDSectorLBA++;
952	952	NeoCDSectorLBA = CDEmuLoadSector(NeoCDSectorLBA, NeoCDSectorData + 4) -1;
953		// }
	953	// }
954	954
955	955	if (LC8951RegistersW[10] & 0x80) {
956	956	LC8951UpdateHeader();
957
	957
958	958	LC8951RegistersR[12] = 0x80; // STAT0
959	959	LC8951RegistersR[13] = 0; // STAT1
960	960	LC8951RegistersR[14] = 0x10; // STAT2
961	961	LC8951RegistersR[15] = 0; // STAT3
962
963		// bprintf(PRINT_IMPORTANT, _T(" Sector %08i (%02i:%02i:%02i) read\n"), NeoCDSectorLBA, NeoCDSectorMin, NeoCDSectorSec, NeoCDSectorFrm);
964	962
	963	// bprintf(PRINT_IMPORTANT, _T(" Sector %08i (%02i:%02i:%02i) read\n"), NeoCDSectorLBA, NeoCDSectorMin, NeoCDSectorSec, NeoCDSectorFrm);
	964
965	965	// CDZ protection hack? (error correction on the CDC should correct this?)
966	966	#if 1
967	967	if (NeoCDSectorData[4 + 64] == 'g' && !strncmp(NeoCDSectorData + 4, "Copyright by SNK", 16)) {
968		// printf(PRINT_ERROR, _T(" simulated CDZ protection error\n"));
969		// bprintf(PRINT_ERROR, _T(" %.70hs\n"), NeoCDSectorData + 4);
970
	968	// printf(PRINT_ERROR, _T(" simulated CDZ protection error\n"));
	969	// bprintf(PRINT_ERROR, _T(" %.70hs\n"), NeoCDSectorData + 4);
	970
971	971	NeoCDSectorData[4 + 64] = 'f';
972
973		// LC8951RegistersR[12] = 0x00; // STAT0
	972
	973	// LC8951RegistersR[12] = 0x00; // STAT0
974	974	}
975	975	#endif
976	976
977	977	nIRQAcknowledge &= ~0x20;
978	978	NeoCDIRQUpdate(0);
979
	979
980	980	LC8951RegistersR[1] &= ~0x20;
981	981
982		// bprintf(PRINT_IMPORTANT, _T(" DECI interrupt triggered\n"));
	982	// bprintf(PRINT_IMPORTANT, _T(" DECI interrupt triggered\n"));
983	983	}
984	984	}
985	985
986	986	bNeoCDLoadSector = true;
987		// bNeoCDLoadSector = false;
	987	// bNeoCDLoadSector = false;
988	988	}
989	989	}
990	990
r19030	r19031
992	992
993	993	UINT8 ng_aes_state::neogeoReadTransfer(UINT32 sekAddress, int is_byte_transfer)
994	994	{
995		// if ((sekAddress & 0x0FFFFF) < 16)
996		// printf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (byte, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
997
	995	// if ((sekAddress & 0x0FFFFF) < 16)
	996	// printf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (byte, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
	997
998	998	sekAddress ^= 1;
999	999
1000	1000	switch (nActiveTransferArea) {
r19030	r19031
1012	1012	return NeoTextRAM[(sekAddress & 0x3FFFF) >> 1];
1013	1013	break;
1014	1014	}
1015
	1015
1016	1016	return ~0;
1017	1017	}
1018	1018
1019	1019
1020	1020	void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int is_byte_transfer)
1021	1021	{
1022		// if ((sekAddress & 0x0FFFFF) < 16)
1023		// bprintf(PRINT_NORMAL, _T(" - Transfer: 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
	1022	// if ((sekAddress & 0x0FFFFF) < 16)
	1023	// bprintf(PRINT_NORMAL, _T(" - Transfer: 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
1024	1024
1025	1025	if (!nTransferWriteEnable) {
1026		// return;
	1026	// return;
1027	1027	}
1028	1028	int address;
1029	1029
r19030	r19031
1033	1033	switch (nActiveTransferArea) {
1034	1034	case 0: // Sprites
1035	1035	address = (nSpriteTransferBank + (sekAddress & 0x0FFFFF));
1036
	1036
1037	1037	// wtf? is this just due to how we decode the sprite gfx or is something bad happening?
1038	1038	if ((address&3)==0) NeoSpriteRAM[address] = byteValue;
1039	1039	if ((address&3)==1) NeoSpriteRAM[address^3] = byteValue;
1040	1040	if ((address&3)==2) NeoSpriteRAM[address^3] = byteValue;
1041	1041	if ((address&3)==3) NeoSpriteRAM[address] = byteValue;
1042	1042
1043		// NeoCDOBJBankUpdate[nSpriteTransferBank >> 20] = true;
	1043	// NeoCDOBJBankUpdate[nSpriteTransferBank >> 20] = true;
1044	1044	break;
1045	1045	case 1: // ADPCM
1046	1046	YM2610ADPCMAROM[nNeoActiveSlot][nADPCMTransferBank + ((sekAddress & 0x0FFFFF) >> 1)] = byteValue;
r19030	r19031
1058	1058	break;
1059	1059	case 5: // Text
1060	1060	NeoTextRAM[(sekAddress & 0x3FFFF) >> 1] = byteValue;
1061		// NeoUpdateTextOne((sekAddress & 0x3FFFF) >> 1, byteValue);
	1061	// NeoUpdateTextOne((sekAddress & 0x3FFFF) >> 1, byteValue);
1062	1062	break;
1063	1063	}
1064	1064	}
r19030	r19031
1067	1067
1068	1068	UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress)
1069	1069	{
1070		// bprintf(PRINT_NORMAL, _T(" - CDROM: 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
	1070	// bprintf(PRINT_NORMAL, _T(" - CDROM: 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
1071	1071
1072	1072
1073	1073	switch (sekAddress & 0xFFFF) {
r19030	r19031
1077	1077
1078	1078	// LC8951 registers
1079	1079	case 0x0100:
1080		// bprintf(PRINT_NORMAL, _T(" - LC8951 register read (PC: 0x%06X)\n"), SekGetPC(-1));
	1080	// bprintf(PRINT_NORMAL, _T(" - LC8951 register read (PC: 0x%06X)\n"), SekGetPC(-1));
1081	1081	return nLC8951Register;
1082	1082	case 0x0102: {
1083		// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X read (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
	1083	// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X read (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
1084	1084
1085	1085	INT32 reg = LC8951RegistersR[nLC8951Register];
1086	1086
r19030	r19031
1101	1101
1102	1102	// CD mechanism communication
1103	1103	case 0x0160:
1104		return NeoCDCommsread();
	1104	return NeoCDCommsread();
1105	1105
1106	1106	case 0x011C: // region
1107	1107	return ~((0x10 \| (NeoSystem & 3)) << 8);
1108	1108	}
1109	1109
1110	1110
1111		// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
	1111	// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
1112	1112
1113	1113	return ~0;
1114	1114	}
r19030	r19031
1116	1116
1117	1117	void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
1118	1118	{
1119		// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
	1119	// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
1120	1120	int byteValue = wordValue & 0xff;
1121	1121
1122	1122	switch (sekAddress & 0xFFFE) {
1123	1123	case 0x0002:
1124		// bprintf(PRINT_IMPORTANT, _T(" - NGCD Interrupt mask -> 0x%04X (PC: 0x%06X)\n"), wordValue, SekGetPC(-1));
1125		nff0002 = wordValue;
	1124	// bprintf(PRINT_IMPORTANT, _T(" - NGCD Interrupt mask -> 0x%04X (PC: 0x%06X)\n"), wordValue, SekGetPC(-1));
	1125	nff0002 = wordValue;
1126	1126
1127	1127	// LC8951RegistersR[1] \|= 0x20;
1128	1128
1129	1129	//if (nff0002 & 0x0500)
1130		// nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
	1130	// nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
1131	1131	//else
1132		// nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
	1132	// nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
1133	1133
1134	1134	break;
1135	1135
r19030	r19031
1182	1182
1183	1183	case 0x007E:
1184	1184	NeoCDDMAMode = wordValue;
1185		// bprintf(PRINT_NORMAL, _T(" - DMA controller 0x%2X -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0xFF, wordValue, SekGetPC(-1));
	1185	// bprintf(PRINT_NORMAL, _T(" - DMA controller 0x%2X -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0xFF, wordValue, SekGetPC(-1));
1186	1186	break;
1187	1187
1188	1188	// upload DMA controller program
r19030	r19031
1195	1195	case 0x008A:
1196	1196	case 0x008C:
1197	1197	case 0x008E:
1198		// bprintf(PRINT_NORMAL, _T(" - DMA controller program[%02i] -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0x0F, wordValue, SekGetPC(-1));
	1198	// bprintf(PRINT_NORMAL, _T(" - DMA controller program[%02i] -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0x0F, wordValue, SekGetPC(-1));
1199	1199	break;
1200	1200
1201	1201	// LC8951 registers
1202	1202	case 0x0100:
1203	1203	nLC8951Register = byteValue & 0x0F;
1204		// bprintf(PRINT_NORMAL, _T(" - LC8951 register -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
	1204	// bprintf(PRINT_NORMAL, _T(" - LC8951 register -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
1205	1205	break;
1206	1206	case 0x0102:
1207		// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, byteValue, SekGetPC(-1));
	1207	// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, byteValue, SekGetPC(-1));
1208	1208	switch (nLC8951Register) {
1209	1209	case 3: // DBCH
1210	1210	LC8951RegistersW[ 3] = byteValue & 0x0F;
r19030	r19031
1217	1217	LC8951RegistersW[ 7] = ~0x00;
1218	1218	LC8951RegistersR[ 1] &= ~0x40;
1219	1219	break;
1220		// case 10:
1221		// LC8951RegistersW[nLC8951Register] = byteValue;
1222		// bprintf(PRINT_NORMAL, _T(" - CTRL0 -> %02X (PC: 0x%06X)\n"), LC8951RegistersW[nLC8951Register], byteValue, SekGetPC(-1));
1223		// break;
	1220	// case 10:
	1221	// LC8951RegistersW[nLC8951Register] = byteValue;
	1222	// bprintf(PRINT_NORMAL, _T(" - CTRL0 -> %02X (PC: 0x%06X)\n"), LC8951RegistersW[nLC8951Register], byteValue, SekGetPC(-1));
	1223	// break;
1224	1224	case 11:
1225	1225	LC8951RegistersW[11] = byteValue; // CTRL1
1226	1226	LC8951UpdateHeader();
r19030	r19031
1235	1235	break;
1236	1236
1237	1237	case 0x0104:
1238		// bprintf(PRINT_NORMAL, _T(" - NGCD 0xE00000 area -> 0x%02X (PC: 0x%06X)\n"), byteValue, SekGetPC(-1));
	1238	// bprintf(PRINT_NORMAL, _T(" - NGCD 0xE00000 area -> 0x%02X (PC: 0x%06X)\n"), byteValue, SekGetPC(-1));
1239	1239	nActiveTransferArea = byteValue;
1240	1240	break;
1241	1241
1242	1242	case 0x0120:
1243		// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
	1243	// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
1244	1244	NeoSetSpriteSlot(1);
1245	1245	memset(NeoCDOBJBankUpdate, 0, sizeof(NeoCDOBJBankUpdate));
1246	1246	break;
1247	1247	case 0x0122:
1248		// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 1 (PC: 0x%06X) %x\n"), SekGetPC(-1), byteValue);
	1248	// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 1 (PC: 0x%06X) %x\n"), SekGetPC(-1), byteValue);
1249	1249	break;
1250	1250	case 0x0126:
1251		// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
	1251	// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
1252	1252	curr_space->machine().scheduler().synchronize();
1253	1253	curr_space->machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
1254	1254
1255	1255	break;
1256	1256	case 0x0128:
1257		// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
	1257	// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
1258	1258	NeoSetTextSlot(1);
1259	1259	break;
1260	1260
1261	1261	case 0x0140:
1262		// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
	1262	// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
1263	1263	video_reset();
1264	1264	break;
1265	1265	case 0x0142:
1266		// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
	1266	// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
1267	1267	break;
1268	1268	case 0x0146:
1269		// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
	1269	// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
1270	1270	curr_space->machine().scheduler().synchronize();
1271	1271	curr_space->machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
1272	1272	break;
1273	1273	case 0x0148:
1274		// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
	1274	// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
1275	1275	video_reset();
1276	1276	break;
1277	1277
r19030	r19031
1284	1284	break;
1285	1285
1286	1286	case 0x016c:
1287		// bprintf(PRINT_ERROR, _T(" - NGCD port 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
	1287	// bprintf(PRINT_ERROR, _T(" - NGCD port 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
1288	1288
1289	1289	MapVectorTable(!(byteValue == 0xFF));
1290	1290
r19030	r19031
1293	1293	break;
1294	1294
1295	1295	case 0x016e:
1296		// bprintf(PRINT_IMPORTANT, _T(" - NGCD 0xE00000 area write access %s (0x%02X, PC: 0x%06X)\n"), byteValue ? _T("enabled") : _T("disabled"), byteValue, SekGetPC(-1));
	1296	// bprintf(PRINT_IMPORTANT, _T(" - NGCD 0xE00000 area write access %s (0x%02X, PC: 0x%06X)\n"), byteValue ? _T("enabled") : _T("disabled"), byteValue, SekGetPC(-1));
1297	1297
1298	1298	nTransferWriteEnable = byteValue;
1299	1299	break;
r19030	r19031
1301	1301	case 0x0180: {
1302	1302	static UINT8 clara = 0;
1303	1303	if (!byteValue && clara) {
1304		// bprintf(PRINT_IMPORTANT, _T(" - NGCD CD communication reset (PC: 0x%06X)\n"), SekGetPC(-1));
1305		// NeoCDCommsReset();
	1304	// bprintf(PRINT_IMPORTANT, _T(" - NGCD CD communication reset (PC: 0x%06X)\n"), SekGetPC(-1));
	1305	// NeoCDCommsReset();
1306	1306	}
1307		clara = byteValue;
	1307	clara = byteValue;
1308	1308	break;
1309	1309	}
1310	1310	case 0x0182: {
1311	1311	static UINT8 clara = 0;
1312	1312	if (!byteValue && clara) {
1313		// bprintf(PRINT_IMPORTANT, _T(" - NGCD Z80 reset (PC: 0x%06X)\n"), SekGetPC(-1));
	1313	// bprintf(PRINT_IMPORTANT, _T(" - NGCD Z80 reset (PC: 0x%06X)\n"), SekGetPC(-1));
1314	1314	//ZetReset();
1315	1315	}
1316		clara = byteValue;
	1316	clara = byteValue;
1317	1317	break;
1318	1318	}
1319	1319	case 0x01A0:
r19030	r19031
1325	1325
1326	1326
1327	1327	default: {
1328		// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
	1328	// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
1329	1329	}
1330	1330	}
1331
	1331
1332	1332	}
1333	1333
1334	1334
r19030	r19031
1394	1394	// Here, only bus access is used to get a rough approximation --
1395	1395	// each read/write takes a single cycle, setup and everything else is ignored.
1396	1396
1397		// bprintf(PRINT_IMPORTANT, _T(" - DMA controller transfer started (PC: 0x%06X)\n"), SekGetPC(-1));
	1397	// bprintf(PRINT_IMPORTANT, _T(" - DMA controller transfer started (PC: 0x%06X)\n"), SekGetPC(-1));
1398	1398
1399	1399	switch (NeoCDDMAMode) {
1400	1400
1401	1401	case 0xCFFD: {
1402		// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 8);
	1402	// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 8);
1403	1403
1404	1404	// - DMA controller 0x7E -> 0xCFFD (PC: 0xC07CE2)
1405	1405	// - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8)
r19030	r19031
1425	1425	}
1426	1426
1427	1427	case 0xE2DD: {
1428		// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X, skip odd bytes\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
	1428	// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X, skip odd bytes\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
1429	1429
1430	1430	// - DMA controller 0x7E -> 0xE2DD (PC: 0xC0A190)
1431	1431	// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192)
r19030	r19031
1450	1450	}
1451	1451
1452	1452	case 0xFC2D: {
1453		// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
	1453	// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
1454	1454
1455	1455	// - DMA controller 0x7E -> 0xFC2D (PC: 0xC0A190)
1456	1456	// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192)
r19030	r19031
1494	1494	// - DMA controller program[14] -> 0xFCF5 (PC: 0xC0A1A0)
1495	1495
1496	1496	case 0xFE6D: {
1497		// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
	1497	// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
1498	1498
1499	1499	// - DMA controller 0x7E -> 0xFE6D (PC: 0xC0FD7A)
1500	1500	// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0FD7C)
r19030	r19031
1516	1516
1517	1517	if (NeoCDDMAAddress2 == 0x0800) {
1518	1518	// MapVectorTable(false);
1519		// bprintf(PRINT_ERROR, _T(" RAM vectors mapped (PC = 0x%08X\n"), SekGetPC(0));
1520		// extern INT32 bRunPause;
1521		// bRunPause = 1;
	1519	// bprintf(PRINT_ERROR, _T(" RAM vectors mapped (PC = 0x%08X\n"), SekGetPC(0));
	1520	// extern INT32 bRunPause;
	1521	// bRunPause = 1;
1522	1522	}
1523	1523	break;
1524	1524	}
1525	1525
1526	1526	case 0xFEF5: {
1527		// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
	1527	// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
1528	1528
1529	1529	// - DMA controller 0x7E -> 0xFEF5 (PC: 0xC07CE2)
1530	1530	// - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8)
r19030	r19031
1548	1548	}
1549	1549
1550	1550	case 0xFFC5: {
1551		// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
	1551	// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
1552	1552
1553	1553	// - DMA controller 0x7E -> 0xFFC5 (PC: 0xC0A190)
1554	1554	// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192)
r19030	r19031
1592	1592	// - DMA controller program[14] -> 0x13FC (PC: 0xC0A1A0)
1593	1593
1594	1594	case 0xFFDD: {
1595		// bprintf(PRINT_NORMAL, _T(" Fill: 0x%08X - 0x%08X <- 0x%04X\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2, NeoCDDMAValue1);
	1595	// bprintf(PRINT_NORMAL, _T(" Fill: 0x%08X - 0x%08X <- 0x%04X\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2, NeoCDDMAValue1);
1596	1596
1597	1597	// - DMA controller 0x7E -> 0xFFDD (PC: 0xC07CE2)
1598	1598	// - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8)
r19030	r19031
1637	1637	case 0:
1638	1638	break;
1639	1639	case 1:
1640		// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
	1640	// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
1641	1641	CDEmuStop();
1642	1642
1643	1643	NeoCDAssyStatus = 0x0E;
1644	1644	bNeoCDLoadSector = false;
1645	1645	break;
1646	1646	case 2:
1647		// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
	1647	// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
1648	1648	NeoCDCommsStatusFIFO[1] = NeoCDCommsCommandFIFO[3];
1649	1649	switch (NeoCDCommsCommandFIFO[3]) {
1650	1650
r19030	r19031
1659	1659
1660	1660	NeoCDCommsStatusFIFO[6] = ChannelData[3] / 10;
1661	1661	NeoCDCommsStatusFIFO[7] = ChannelData[3] % 10;
1662
	1662
1663	1663	NeoCDCommsStatusFIFO[8] = ChannelData[7];
1664	1664
1665	1665	// //bprintf(PRINT_ERROR, _T(" %02i %02i:%02i:%02i %02i:%02i:%02i %02i\n"), ChannelData[0], ChannelData[1], ChannelData[2], ChannelData[3], ChannelData[4], ChannelData[5], ChannelData[6], ChannelData[7]);
r19030	r19031
1786	1786	NeoCDSectorLBA -= CD_FRAMES_PREGAP;
1787	1787
1788	1788	CDEmuStartRead();
1789		// LC8951RegistersR[1] \|= 0x20;
	1789	// LC8951RegistersR[1] \|= 0x20;
1790	1790	} else {
1791	1791
1792	1792	if (CDEmuGetStatus() == reading) {
r19030	r19031
1802	1802	break;
1803	1803	}
1804	1804	case 4:
1805		// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
	1805	// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
1806	1806	CDEmuPause();
1807	1807	break;
1808	1808	case 5:
1809		// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
1810		// NeoCDAssyStatus = 9;
1811		// bNeoCDLoadSector = false;
	1809	// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
	1810	// NeoCDAssyStatus = 9;
	1811	// bNeoCDLoadSector = false;
1812	1812	break;
1813	1813
1814	1814	case 6:
1815		// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
	1815	// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
1816	1816	NeoCDAssyStatus = 4;
1817	1817	bNeoCDLoadSector = false;
1818	1818	break;
1819	1819	case 7:
1820		// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
	1820	// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
1821	1821	NeoCDAssyStatus = 1;
1822	1822	bNeoCDLoadSector = true;
1823	1823	break;
r19030	r19031
1830	1830	case 13:
1831	1831	case 14:
1832	1832	case 15:
1833		// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
	1833	// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
1834	1834	NeoCDAssyStatus = 9;
1835	1835	bNeoCDLoadSector = false;
1836	1836	break;
r19030	r19031
1853	1853
1854	1854	printf("has command %02x\n", NeoCDCommsCommandFIFO[0]);
1855	1855
1856		// bprintf(PRINT_NORMAL, _T(" - CD mechanism command receive completed : 0x"));
	1856	// bprintf(PRINT_NORMAL, _T(" - CD mechanism command receive completed : 0x"));
1857	1857	for (INT32 i = 0; i < 9; i++) {
1858		// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsCommandFIFO[i]);
	1858	// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsCommandFIFO[i]);
1859	1859	sum += NeoCDCommsCommandFIFO[i];
1860	1860	}
1861	1861	sum = ~(sum + 5) & 0x0F;
1862		// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsCommandFIFO[9], (sum == NeoCDCommsCommandFIFO[9]) ? _T("OK") : _T("NG"));
	1862	// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsCommandFIFO[9], (sum == NeoCDCommsCommandFIFO[9]) ? _T("OK") : _T("NG"));
1863	1863	if (sum == NeoCDCommsCommandFIFO[9]) {
1864	1864
1865	1865	printf("request to process command %02x\n", NeoCDCommsCommandFIFO[0]);
r19030	r19031
1892	1892
1893	1893	// status send complete
1894	1894
1895		// if (NeoCDCommsStatusFIFO[0] \|\| NeoCDCommsStatusFIFO[1]) {
1896		// INT32 sum = 0;
	1895	// if (NeoCDCommsStatusFIFO[0] \|\| NeoCDCommsStatusFIFO[1]) {
	1896	// INT32 sum = 0;
1897	1897	//
1898		// bprintf(PRINT_NORMAL, _T(" - CD mechanism status send completed : 0x"));
1899		// for (INT32 i = 0; i < 9; i++) {
1900		// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsStatusFIFO[i]);
1901		// sum += NeoCDCommsStatusFIFO[i];
1902		// }
1903		// sum = ~(sum + 5) & 0x0F;
1904		// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsStatusFIFO[9], (sum == NeoCDCommsStatusFIFO[9]) ? _T("OK") : _T("NG"));
1905		// }
	1898	// bprintf(PRINT_NORMAL, _T(" - CD mechanism status send completed : 0x"));
	1899	// for (INT32 i = 0; i < 9; i++) {
	1900	// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsStatusFIFO[i]);
	1901	// sum += NeoCDCommsStatusFIFO[i];
	1902	// }
	1903	// sum = ~(sum + 5) & 0x0F;
	1904	// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsStatusFIFO[9], (sum == NeoCDCommsStatusFIFO[9]) ? _T("OK") : _T("NG"));
	1905	// }
1906	1906
1907		// if (NeoCDAssyStatus == 0xE) {
1908		// NeoCDAssyStatus = 9;
1909		// }
	1907	// if (NeoCDAssyStatus == 0xE) {
	1908	// NeoCDAssyStatus = 9;
	1909	// }
1910	1910	}
1911	1911
1912	1912	}
r19030	r19031
1956	1956	}
1957	1957
1958	1958	return NeoCDSectorData + ((LC8951RegistersW[5] << 8) \| LC8951RegistersW[4]);
1959		}
	1959	}
1960	1960
1961	1961	void ng_aes_state::LC8915EndTransfer()
1962	1962	{
r19030	r19031
2014	2014	UINT16 ret = 0x0000;
2015	2015
2016	2016
2017
	2017
2018	2018	if (mem_mask & 0x00ff)
2019	2019	{
2020	2020	ret \|= neogeoReadTransfer(0xe00000+ (offset*2)+1, is_byte_transfer) & 0xff;
r19030	r19031
2038	2038	{
2039	2039	neogeoWriteTransfer(0xe00000+ (offset*2), data>>8, is_byte_transfer);
2040	2040	}
2041
	2041
2042	2042	if (mem_mask & 0x00ff)
2043	2043	{
2044	2044	neogeoWriteTransfer(0xe00000+ (offset*2)+1, data&0xff, is_byte_transfer);
r19030	r19031
2426	2426	AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_READ(audio_command_r)
2427	2427	AM_RANGE(0x04, 0x07) AM_MIRROR(0xff00) AM_DEVREADWRITE_LEGACY("ymsnd", ym2610_r, ym2610_w)
2428	2428	AM_RANGE(0x08, 0x08) AM_MIRROR(0xff00) /* write - NMI enable / acknowledge? (the data written doesn't matter) */
2429		// AM_RANGE(0x08, 0x08) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_f000_f7ff_r)
2430		// AM_RANGE(0x09, 0x09) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_e000_efff_r)
2431		// AM_RANGE(0x0a, 0x0a) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_c000_dfff_r)
2432		// AM_RANGE(0x0b, 0x0b) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_8000_bfff_r)
	2429	// AM_RANGE(0x08, 0x08) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_f000_f7ff_r)
	2430	// AM_RANGE(0x09, 0x09) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_e000_efff_r)
	2431	// AM_RANGE(0x0a, 0x0a) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_c000_dfff_r)
	2432	// AM_RANGE(0x0b, 0x0b) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_8000_bfff_r)
2433	2433	AM_RANGE(0x0c, 0x0c) AM_MIRROR(0xff00) AM_WRITE(audio_result_w)
2434	2434	AM_RANGE(0x18, 0x18) AM_MIRROR(0xff00) /* write - NMI disable? (the data written doesn't matter) */
2435	2435	ADDRESS_MAP_END

trunk/src/mess/drivers/altos5.c
r19030	r19031
1	1	/***************************************************************************
2	2
3		Altos 5-15
	3	Altos 5-15
4	4
5	5	****************************************************************************/
6	6
r19030	r19031
19	19
20	20	DECLARE_READ8_MEMBER(altos_2f_r);
21	21	DECLARE_WRITE8_MEMBER( kbd_put );
22		UINT8 m_term_data;
	22	UINT8 m_term_data;
23	23	required_device<cpu_device> m_maincpu;
24	24	virtual void machine_reset();
25	25	};
r19030	r19031
48	48	static ADDRESS_MAP_START(altos5_io, AS_IO, 8, altos5_state)
49	49	ADDRESS_MAP_GLOBAL_MASK(0xff)
50	50	AM_RANGE(0x2e, 0x2e) AM_DEVWRITE(TERMINAL_TAG, generic_terminal_device, write)
51		AM_RANGE(0x2f, 0x2f) AM_READ(altos_2f_r)
	51	AM_RANGE(0x2f, 0x2f) AM_READ(altos_2f_r)
52	52	ADDRESS_MAP_END
53	53
54	54	/* Input ports */
r19030	r19031
67	67	MCFG_CPU_ADD("maincpu", Z80, XTAL_16MHz / 4)
68	68	MCFG_CPU_PROGRAM_MAP(altos5_mem)
69	69	MCFG_CPU_IO_MAP(altos5_io)
70
	70
71	71	/* video hardware */
72		MCFG_GENERIC_TERMINAL_ADD(TERMINAL_TAG, terminal_intf)
	72	MCFG_GENERIC_TERMINAL_ADD(TERMINAL_TAG, terminal_intf)
73	73	MACHINE_CONFIG_END
74	74
75	75

trunk/src/mess/drivers/bw2.c
r19030	r19031
367	367	{
368	368	/*
369	369
370		PA0 KB0 Keyboard line select 0
371		PA1 KB1 Keyboard line select 1
372		PA2 KB2 Keyboard line select 2
373		PA3 KB3 Keyboard line select 3
374		PA4 /DS0 Drive select 0
375		PA5 /DS1 Drive select 1
376		PA6 Select RS232 connector
377		PA7 /STROBE to centronics printer
	370	PA0 KB0 Keyboard line select 0
	371	PA1 KB1 Keyboard line select 1
	372	PA2 KB2 Keyboard line select 2
	373	PA3 KB3 Keyboard line select 3
	374	PA4 /DS0 Drive select 0
	375	PA5 /DS1 Drive select 1
	376	PA6 Select RS232 connector
	377	PA7 /STROBE to centronics printer
378	378
379		*/
	379	*/
380	380
381	381	// keyboard
382	382	m_kb = data & 0x0f;
r19030	r19031
398	398	{
399	399	/*
400	400
401		PB0 Keyboard column status of selected line
402		PB1 Keyboard column status of selected line
403		PB2 Keyboard column status of selected line
404		PB3 Keyboard column status of selected line
405		PB4 Keyboard column status of selected line
406		PB5 Keyboard column status of selected line
407		PB6 Keyboard column status of selected line
408		PB7 Keyboard column status of selected line
	401	PB0 Keyboard column status of selected line
	402	PB1 Keyboard column status of selected line
	403	PB2 Keyboard column status of selected line
	404	PB3 Keyboard column status of selected line
	405	PB4 Keyboard column status of selected line
	406	PB5 Keyboard column status of selected line
	407	PB6 Keyboard column status of selected line
	408	PB7 Keyboard column status of selected line
409	409
410		*/
	410	*/
411	411
412	412	static const char *const rownames[] = { "Y0", "Y1", "Y2", "Y3", "Y4", "Y5", "Y6", "Y7", "Y8", "Y9" };
413	413
r19030	r19031
425	425	{
426	426	/*
427	427
428		PC0 Memory bank select
429		PC1 Memory bank select
430		PC2 Memory bank select
431		PC3 Not connected
	428	PC0 Memory bank select
	429	PC1 Memory bank select
	430	PC2 Memory bank select
	431	PC3 Not connected
432	432
433		*/
	433	*/
434	434
435	435	m_bank = data & 0x07;
436	436	}
r19030	r19031
439	439	{
440	440	/*
441	441
442		PC4 BUSY from centronics printer
443		PC5 M/FDBK motor feedback
444		PC6 RLSD Carrier detect from RS232
445		PC7 /PROT Write protected disk
	442	PC4 BUSY from centronics printer
	443	PC5 M/FDBK motor feedback
	444	PC6 RLSD Carrier detect from RS232
	445	PC7 /PROT Write protected disk
446	446
447		*/
	447	*/
448	448
449	449	UINT8 data = 0;
450	450

trunk/src/mess/machine/adam_prn.c
r19030	r19031
136	136	{
137	137	/*
138	138
139		bit description
	139	bit description
140	140
141		0 M2 phase D
142		1 M2 phase B
143		2 M2 phase C
144		3 M2 phase A
145		4 M3 phase B
146		5 M3 phase D
147		6 M3 phase A
148		7 M3 phase C
	141	0 M2 phase D
	142	1 M2 phase B
	143	2 M2 phase C
	144	3 M2 phase A
	145	4 M3 phase B
	146	5 M3 phase D
	147	6 M3 phase A
	148	7 M3 phase C
149	149
150		*/
	150	*/
151	151	}
152	152
153	153
r19030	r19031
159	159	{
160	160	/*
161	161
162		bit description
	162	bit description
163	163
164		0 mode bit 0
165		1 mode bit 1
166		2 mode bit 2
167		3 NET RXD
168		4 NET TXD
	164	0 mode bit 0
	165	1 mode bit 1
	166	2 mode bit 2
	167	3 NET RXD
	168	4 NET TXD
169	169
170		*/
	170	*/
171	171
172	172	UINT8 data = M6801_MODE_7;
173	173
r19030	r19031
186	186	{
187	187	/*
188	188
189		bit description
	189	bit description
190	190
191		0 mode bit 0
192		1 mode bit 1
193		2 mode bit 2
194		3 NET RXD
195		4 NET TXD
	191	0 mode bit 0
	192	1 mode bit 1
	193	2 mode bit 2
	194	3 NET RXD
	195	4 NET TXD
196	196
197		*/
	197	*/
198	198
199	199	m_bus->txd_w(this, BIT(data, 4));
200	200	}
r19030	r19031
218	218	{
219	219	/*
220	220
221		bit description
	221	bit description
222	222
223		0
224		1
225		2
226		3
227		4 left margin
228		5 platen detent
229		6 wheel home
230		7 self-test
	223	0
	224	1
	225	2
	226	3
	227	4 left margin
	228	5 platen detent
	229	6 wheel home
	230	7 self-test
231	231
232		*/
	232	*/
233	233
234	234	return 0x80;
235	235	}
r19030	r19031
243	243	{
244	244	/*
245	245
246		bit description
	246	bit description
247	247
248		0 print hammer solenoid
249		1 ribbon advance solenoid
250		2 platen motor advance
251		3 platen motor break
252		4
253		5
254		6
255		7
	248	0 print hammer solenoid
	249	1 ribbon advance solenoid
	250	2 platen motor advance
	251	3 platen motor break
	252	4
	253	5
	254	6
	255	7
256	256
257		*/
	257	*/
258	258	}

trunk/src/mess/machine/adam_ide.c
r19030	r19031
9	9
10	10	/*
11	11
12		TODO:
	12	TODO:
13	13
14		- parallel status port
15		- memory bank switching port
16		- boot ROM
	14	- parallel status port
	15	- memory bank switching port
	16	- boot ROM
17	17
18	18	*/
19	19
r19030	r19031
126	126
127	127	case 0x40: // Printer status
128	128	/*
129
130		bit description
131
132		0
133		1
134		2
135		3
136		4
137		5
138		6
139		7
140
141		*/
	129
	130	bit description
	131
	132	0
	133	1
	134	2
	135	3
	136	4
	137	5
	138	6
	139	7
	140
	141	*/
142	142	break;
143
	143
144	144	case 0x58:
145	145	m_ide_data = ide_bus_r(m_ide, 0, 0);
146	146
147	147	data = m_ide_data & 0xff;
148	148	break;
149
	149
150	150	case 0x59:
151	151	data = m_ide_data >> 8;
152	152	break;
153
	153
154	154	case 0x5a:
155	155	data = ide_bus_r(m_ide, 1, 6) & 0xff;
156	156	break;
157
	157
158	158	case 0x5b: // Digital Input Register
159	159	data = 0xff;
160	160	break;
r19030	r19031
190	190
191	191	case 0x42: // Bank Number
192	192	break;
193
	193
194	194	case 0x58:
195	195	m_ide_data \|= data;
196	196	ide_bus_w(m_ide, 0, 0, m_ide_data);
197	197	break;
198
	198
199	199	case 0x59:
200	200	m_ide_data = data << 8;
201	201	break;
202
	202
203	203	case 0x5a: // Fixed Disk Control Register
204	204	break;
205	205	}

trunk/src/mess/machine/adam_ddp.c
r19030	r19031
166	166	{
167	167	/*
168	168
169		bit description
	169	bit description
170	170
171		0 SPD SEL (0=20 ips, 1=80ips)
172		1 STOP0
173		2 STOP1
174		3 _GO FWD
175		4 _GO REV
176		5 BRAKE
177		6 _WR0
178		7 _WR1
	171	0 SPD SEL (0=20 ips, 1=80ips)
	172	1 STOP0
	173	2 STOP1
	174	3 _GO FWD
	175	4 _GO REV
	176	5 BRAKE
	177	6 _WR0
	178	7 _WR1
179	179
180		*/
	180	*/
181	181
182	182	if (m_ddp0->exists())
183	183	{
r19030	r19031
211	211	{
212	212	/*
213	213
214		bit description
	214	bit description
215	215
216		0 mode bit 0
217		1 mode bit 1 / CIP1
218		2 mode bit 2
219		3 NET RXD
220		4
	216	0 mode bit 0
	217	1 mode bit 1 / CIP1
	218	2 mode bit 2
	219	3 NET RXD
	220	4
221	221
222		*/
	222	*/
223	223
224	224	UINT8 data = 0;
225	225
r19030	r19031
243	243	{
244	244	/*
245	245
246		bit description
	246	bit description
247	247
248		0 WRT DATA
249		1
250		2 TRACK A/B (0=B, 1=A)
251		3
252		4 NET TXD
	248	0 WRT DATA
	249	1
	250	2 TRACK A/B (0=B, 1=A)
	251	3
	252	4 NET TXD
253	253
254		*/
	254	*/
255	255
256	256	if (m_ddp0->exists())
257	257	{
r19030	r19031
278	278	{
279	279	/*
280	280
281		bit description
	281	bit description
282	282
283		0 A8
284		1 A9
285		2 A10 (2114 _S)
286		3 MSENSE 0
287		4 MSENSE 1
288		5 CIP0
289		6 RD DATA 0 (always 1)
290		7 RD DATA 1 (data from drives ORed together)
	283	0 A8
	284	1 A9
	285	2 A10 (2114 _S)
	286	3 MSENSE 0
	287	4 MSENSE 1
	288	5 CIP0
	289	6 RD DATA 0 (always 1)
	290	7 RD DATA 1 (data from drives ORed together)
291	291
292		*/
	292	*/
293	293
294	294	UINT8 data = 0;
295	295

trunk/src/mess/machine/adamlink.c
r19030	r19031
77	77	{
78	78	case 0x5e:
79	79	break;
80
	80
81	81	case 0x5f:
82	82	break;
83	83	}

trunk/src/mess/machine/adam_fdc.c
r19030	r19031
215	215	{
216	216	/*
217	217
218		bit description
	218	bit description
219	219
220		0 disk in place
221		1
222		2 FDC DRQ
223		3
224		4
225		5
226		6
227		7 SW3 (0=DS1, 1=DS2)
	220	0 disk in place
	221	1
	222	2 FDC DRQ
	223	3
	224	4
	225	5
	226	6
	227	7 SW3 (0=DS1, 1=DS2)
228	228
229		*/
	229	*/
230	230
231	231	UINT8 data = 0;
232	232
r19030	r19031
251	251	{
252	252	/*
253	253
254		bit description
	254	bit description
255	255
256		0
257		1 FDC ENP
258		2
259		3 FDC _DDEN
260		4
261		5 DRIVE SELECT
262		6 MOTOR ON
263		7
	256	0
	257	1 FDC ENP
	258	2
	259	3 FDC _DDEN
	260	4
	261	5 DRIVE SELECT
	262	6 MOTOR ON
	263	7
264	264
265		*/
	265	*/
266	266
267	267	// write precompensation
268	268	//m_fdc->enp_w(BIT(data, 1));
r19030	r19031
293	293	{
294	294	/*
295	295
296		bit description
	296	bit description
297	297
298		0 mode bit 0
299		1 mode bit 1
300		2 mode bit 2
301		3 NET RXD
302		4
	298	0 mode bit 0
	299	1 mode bit 1
	300	2 mode bit 2
	301	3 NET RXD
	302	4
303	303
304		*/
	304	*/
305	305
306	306	UINT8 data = M6801_MODE_2;
307	307
r19030	r19031
320	320	{
321	321	/*
322	322
323		bit description
	323	bit description
324	324
325		0
326		1
327		2
328		3
329		4 NET TXD
	325	0
	326	1
	327	2
	328	3
	329	4 NET TXD
330	330
331		*/
	331	*/
332	332
333	333	m_bus->txd_w(this, BIT(data, 4));
334	334	}

trunk/src/mess/machine/adam_kb.c
r19030	r19031
261	261	{
262	262	/*
263	263
264		bit description
	264	bit description
265	265
266		0 X0
267		1 X1
268		2 X2
269		3 X3
270		4 X4
271		5 X5
272		6 X6
273		7 X7
	266	0 X0
	267	1 X1
	268	2 X2
	269	3 X3
	270	4 X4
	271	5 X5
	272	6 X6
	273	7 X7
274	274
275		*/
	275	*/
276	276
277	277	UINT8 data = 0xff;
278	278
r19030	r19031
302	302	{
303	303	/*
304	304
305		bit description
	305	bit description
306	306
307		0 mode bit 0
308		1 mode bit 1
309		2 mode bit 2
310		3 NET RXD
311		4
	307	0 mode bit 0
	308	1 mode bit 1
	309	2 mode bit 2
	310	3 NET RXD
	311	4
312	312
313		*/
	313	*/
314	314
315	315	UINT8 data = M6801_MODE_7;
316	316
r19030	r19031
329	329	{
330	330	/*
331	331
332		bit description
	332	bit description
333	333
334		0
335		1
336		2
337		3
338		4 NET TXD
	334	0
	335	1
	336	2
	337	3
	338	4 NET TXD
339	339
340		*/
	340	*/
341	341
342	342	m_bus->txd_w(this, BIT(data, 4));
343	343	}
r19030	r19031
361	361	{
362	362	/*
363	363
364		bit description
	364	bit description
365	365
366		0 Y0
367		1 Y1
368		2 Y2
369		3 Y3
370		4 Y4
371		5 Y5
372		6 Y6
373		7 Y7
	366	0 Y0
	367	1 Y1
	368	2 Y2
	369	3 Y3
	370	4 Y4
	371	5 Y5
	372	6 Y6
	373	7 Y7
374	374
375		*/
	375	*/
376	376
377	377	m_key_y = (m_key_y & 0x1f00) \| data;
378	378	}
r19030	r19031
396	396	{
397	397	/*
398	398
399		bit description
	399	bit description
400	400
401		0 Y8
402		1 Y9
403		2 Y10
404		3 Y11
405		4 Y12
406		5
407		6
408		7
	401	0 Y8
	402	1 Y9
	403	2 Y10
	404	3 Y11
	405	4 Y12
	406	5
	407	6
	408	7
409	409
410		*/
	410	*/
411	411
412	412	m_key_y = ((data & 0x1f) << 8) \| (m_key_y & 0xff);
413	413	}

trunk/src/mess/machine/adam_spi.c
r19030	r19031
134	134	{
135	135	/*
136	136
137		bit description
	137	bit description
138	138
139		0 mode bit 0
140		1 mode bit 1
141		2 mode bit 2
142		3 NET RXD
143		4
	139	0 mode bit 0
	140	1 mode bit 1
	141	2 mode bit 2
	142	3 NET RXD
	143	4
144	144
145		*/
	145	*/
146	146
147	147	UINT8 data = M6801_MODE_7;
148	148
r19030	r19031
161	161	{
162	162	/*
163	163
164		bit description
	164	bit description
165	165
166		0
167		1
168		2
169		3
170		4 NET TXD
	166	0
	167	1
	168	2
	169	3
	170	4 NET TXD
171	171
172		*/
	172	*/
173	173
174	174	m_bus->txd_w(this, BIT(data, 4));
175	175	}

trunk/src/mess/video/isa_cga.c
r19030	r19031
2044	2044	machine().root_device().membank("bank_wy1")->set_base(m_vram);
2045	2045	}
2046	2046	if ((m_control & 0xf0) == (mode & 0xf0)) return;
2047
	2047
2048	2048	switch(mode & 0xf0) {
2049	2049	case 0xc0: width = 1280; height = 800; break;
2050	2050	case 0xa0: width = 1280; height = 400; break;
2051	2051	case 0x80: width = 640; height = 400; break;
2052	2052	case 0x00: width = 640; height = 400; break; // unhandled
2053	2053	}
2054		rectangle visarea(0, width-1, 0, height-1);
	2054	rectangle visarea(0, width-1, 0, height-1);
2055	2055	subdevice<screen_device>(CGA_SCREEN_NAME)->configure(width, height, visarea, HZ_TO_ATTOSECONDS(60));
2056	2056
2057	2057	}
r19030	r19031
2115	2115	isa8_cga_device( mconfig, ISA8_WYSE700, "Wyse 700", tag, owner, clock )
2116	2116	{
2117	2117	m_vram_size = 0x20000;
2118		m_start_offset = 0x18000;
	2118	m_start_offset = 0x18000;
2119	2119	}
2120	2120
2121	2121

trunk/src/mess/video/isa_cga.h
r19030	r19031
205	205	virtual DECLARE_WRITE8_MEMBER( io_write );
206	206	virtual UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
207	207	void change_resolution(UINT8 mode);
208
	208
209	209	UINT8 m_bank_offset;
210	210	UINT8 m_bank_base;
211	211	UINT8 m_control;

199869 Revisions