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r18994 Friday 16th November, 2012 at 18:39:12 UTC by Curt Coder
(MESS) bw2: Modernized floppy handling and cleaned up driver. [Curt Coder]

[src/mess/drivers]	bw2.c
[src/mess/includes]	bw2.h

trunk/src/mess/includes/bw2.h

r18993	r18994
	1	#pragma once
	2
1	3	#ifndef __BW2__
2	4	#define __BW2__
3	5
4
5	6	#include "emu.h"
6	7	#include "cpu/z80/z80.h"
7		#include "imagedev/flopdrv.h"
8		#include "formats/basicdsk.h"
9		#include "machine/i8255.h"
	8	#include "formats/bw2_dsk.h"
	9	#include "formats/hxcmfm_dsk.h"
	10	#include "formats/imd_dsk.h"
	11	#include "formats/mfi_dsk.h"
	12	#include "machine/bw2exp.h"
10	13	#include "machine/ctronics.h"
11	14	#include "machine/i8251.h"
	15	#include "machine/i8255.h"
12	16	#include "machine/pit8253.h"
13	17	#include "machine/ram.h"
14		#include "machine/wd17xx.h"
	18	#include "machine/serial.h"
	19	#include "machine/wd1772.h"
15	20	#include "video/msm6255.h"
16	21	#include "rendlay.h"
17	22
18
19		#define SCREEN_TAG      "screen"
20	23	#define Z80_TAG         "ic1"
21	24	#define I8255A_TAG      "ic4"
22	25	#define WD2797_TAG      "ic5"
23		#define PIT8253_TAG      "ic6"
	26	#define I8253_TAG      "ic6"
24	27	#define I8251_TAG      "ic7"
25	28	#define MSM6255_TAG      "ic49"
26	29	#define CENTRONICS_TAG   "centronics"
	30	#define RS232_TAG      "rs232"
	31	#define SCREEN_TAG      "screen"
27	32
28		#define BW2_VIDEORAM_SIZE   0x4000
29		#define BW2_RAMCARD_SIZE   0x80000
30
31		enum {
32		BANK_RAM1 = 0,
33		BANK_VRAM,
34		BANK_RAM2, BANK_RAMCARD_ROM = BANK_RAM2,
35		BANK_RAM3,
36		BANK_RAM4,
37		BANK_RAM5, BANK_RAMCARD_RAM = BANK_RAM5,
38		BANK_RAM6,
39		BANK_ROM
40		};
41
42	33	class bw2_state : public driver_device
43	34	{
44	35	public:
r18993	r18994
49	40	m_fdc(*this, WD2797_TAG),
50	41	m_lcdc(*this, MSM6255_TAG),
51	42	m_centronics(*this, CENTRONICS_TAG),
	43	m_exp(*this, BW2_EXPANSION_SLOT_TAG),
52	44	m_ram(*this, RAM_TAG),
53		m_floppy0(*this, FLOPPY_0),
54		m_floppy1(*this, FLOPPY_1)
	45	m_floppy0(*this, WD2797_TAG":0"),
	46	m_floppy1(*this, WD2797_TAG":1"),
	47	m_floppy(NULL),
	48	m_video_ram(*this, "videoram")
55	49	{ }
56	50
57	51	required_device<cpu_device> m_maincpu;
58	52	required_device<i8251_device> m_uart;
59		required_device<device_t> m_fdc;
	53	required_device<wd2797_t> m_fdc;
60	54	required_device<msm6255_device> m_lcdc;
61	55	required_device<centronics_device> m_centronics;
	56	required_device<bw2_expansion_slot_device> m_exp;
62	57	required_device<ram_device> m_ram;
63		required_device<device_t> m_floppy0;
64		required_device<device_t> m_floppy1;
	58	required_device<floppy_connector> m_floppy0;
	59	required_device<floppy_connector> m_floppy1;
	60	floppy_image_device *m_floppy;
65	61
66	62	virtual void machine_start();
67		virtual void machine_reset();
68	63
69		int get_ramdisk_size();
70		void bankswitch(UINT8 data);
71		void ramcard_bankswitch(UINT8 data);
	64	DECLARE_READ8_MEMBER( read );
	65	DECLARE_WRITE8_MEMBER( write );
72	66
73		DECLARE_WRITE8_MEMBER( ramcard_bank_w );
74	67	DECLARE_WRITE8_MEMBER( ppi_pa_w );
75	68	DECLARE_READ8_MEMBER( ppi_pb_r );
76	69	DECLARE_WRITE8_MEMBER( ppi_pc_w );
77	70	DECLARE_READ8_MEMBER( ppi_pc_r );
	71
78	72	DECLARE_WRITE_LINE_MEMBER( pit_out0_w );
79	73	DECLARE_WRITE_LINE_MEMBER( mtron_w );
80		DECLARE_WRITE_LINE_MEMBER( fdc_drq_w );
81	74
	75	void fdc_intrq_w(bool state);
	76	void fdc_drq_w(bool state);
	77	static const floppy_format_type floppy_formats[];
	78
82	79	// keyboard state
83		UINT8 m_kb_row;
	80	UINT8 m_kb;
84	81
85	82	// memory state
86		UINT8 *m_ramcard_ram;
87	83	UINT8 m_bank;
88	84
89	85	// floppy state
90		int m_drive;
91	86	int m_mtron;
92	87	int m_mfdbk;
93	88
94	89	// video state
95		UINT8 *m_video_ram;
	90	optional_shared_ptr<UINT8> m_video_ram;
96	91	virtual void palette_init();
97	92	};
98	93

trunk/src/mess/drivers/bw2.c

r18993	r18994
20	20
21	21	http://www2.okisemi.com/site/productscatalog/displaydrivers/availabledocuments/Intro-7090.html
22	22
	23	***************************************************************************/
23	24
24		TODO:
	25	#include "includes/bw2.h"
25	26
26		- modem card
27	27
28		***************************************************************************/
29	28
30		#include "includes/bw2.h"
	29	//**************************************************************************
	30	//  MACROS / CONSTANTS
	31	//**************************************************************************
31	32
32		int bw2_state::get_ramdisk_size()
	33	enum
33	34	{
34		return ioport("RAMCARD")->read() * 256;
35		}
	35	RAM1 = 0,
	36	VRAM,
	37	RAM2,
	38	RAM3,
	39	RAM4,
	40	RAM5,
	41	RAM6,
	42	ROM
	43	};
36	44
37		/* Memory */
38	45
39		void bw2_state::bankswitch(UINT8 data)
40		{
41		/*
42	46
43		Y0  /RAM1   Memory bank 1
44		Y1  /VRAM   Video memory
45		Y2  /RAM2   Memory bank 2
46		Y3  /RAM3   Memory bank 3
47		Y4  /RAM4   Memory bank 4
48		Y5  /RAM5   Memory bank 5
49		Y6  /RAM6   Memory bank 6
50		Y7  /ROM    ROM
	47	//**************************************************************************
	48	//  ADDRESS DECODING
	49	//**************************************************************************
51	50
52		*/
	51	//-------------------------------------------------
	52	//  read -
	53	//-------------------------------------------------
53	54
54		address_space &program = m_maincpu->space(AS_PROGRAM);
	55	READ8_MEMBER( bw2_state::read )
	56	{
	57	int rom = 1, vram = 1, ram1 = 1, ram2 = 1, ram3 = 1, ram4 = 1, ram5 = 1, ram6 = 1;
55	58
56		int max_ram_bank = 0;
	59	UINT8 data = 0xff;
57	60
58		m_bank = data & 0x07;
	61	switch (m_bank)
	62	{
	63	case RAM1: ram1 = 0; break;
	64	case VRAM: vram = 0; break;
	65	case RAM2: ram2 = 0; break;
	66	case RAM3: ram3 = 0; break;
	67	case RAM4: ram4 = 0; break;
	68	case RAM5: ram5 = 0; break;
	69	case RAM6: ram6 = 0; break;
	70	case ROM: rom = 0; break;
	71	}
59	72
60		switch (m_ram->size())
	73	if (!rom)
61	74	{
62		case 64 * 1024:
63		max_ram_bank = BANK_RAM1;
64		break;
	75	data = memregion(Z80_TAG)->base()[offset & 0x3fff];
	76	}
65	77
66		case 96 * 1024:
67		max_ram_bank = BANK_RAM2;
68		break;
	78	if (!vram)
	79	{
	80	data = m_video_ram[offset & 0x3fff];
	81	}
69	82
70		case 128 * 1024:
71		max_ram_bank = BANK_RAM3;
72		break;
	83	if (!ram1)
	84	{
	85	data = m_ram->pointer()[offset];
	86	}
73	87
74		case 160 * 1024:
75		max_ram_bank = BANK_RAM4;
76		break;
	88	if (!ram2 && (m_ram->size() >= 96 * 1024))
	89	{
	90	data = m_ram->pointer()[0x10000 | offset];
	91	}
77	92
78		case 192 * 1024:
79		max_ram_bank = BANK_RAM5;
80		break;
	93	if (!ram3 && (m_ram->size() >= 128 * 1024))
	94	{
	95	data = m_ram->pointer()[0x18000 | offset];
	96	}
81	97
82		case 224 * 1024:
83		max_ram_bank = BANK_RAM6;
84		break;
	98	if (!ram4 && (m_ram->size() >= 160 * 1024))
	99	{
	100	data = m_ram->pointer()[0x20000 | offset];
85	101	}
86	102
87		switch (m_bank)
	103	if (!ram5 && (m_ram->size() >= 192 * 1024))
88	104	{
89		case BANK_RAM1:
90		program.install_readwrite_bank(0x0000, 0x7fff, "bank1");
91		break;
	105	data = m_ram->pointer()[0x28000 | offset];
	106	}
92	107
93		case BANK_VRAM:
94		program.install_readwrite_bank(0x0000, 0x3fff, 0, 0x4000, "bank1");
95		break;
96
97		case BANK_RAM2:
98		case BANK_RAM3:
99		case BANK_RAM4:
100		case BANK_RAM5:
101		case BANK_RAM6:
102		if (m_bank > max_ram_bank)
103		{
104		program.unmap_readwrite(0x0000, 0x7fff);
105		}
106		else
107		{
108		program.install_readwrite_bank(0x0000, 0x7fff, "bank1");
109		}
110		break;
111
112		case BANK_ROM:
113		program.install_read_bank(0x0000, 0x7fff, "bank1");
114		program.unmap_write(0x0000, 0x7fff);
115		break;
	108	if (!ram6 && (m_ram->size() >= 224 * 1024))
	109	{
	110	data = m_ram->pointer()[0x30000 | offset];
116	111	}
117	112
118		membank("bank1")->set_entry(m_bank);
	113	return m_exp->cd_r(space, offset, data, ram2, ram3, ram4, ram5, ram6);
119	114	}
120	115
121		void bw2_state::ramcard_bankswitch(UINT8 data)
122		{
123		/*
124	116
125		Y0  /RAM1   Memory bank 1
126		Y1  /VRAM   Video memory
127		Y2  /RAM2   RAMCARD ROM
128		Y3  /RAM3   Memory bank 3
129		Y4  /RAM4   Memory bank 4
130		Y5  /RAM5   RAMCARD RAM
131		Y6  /RAM6   Memory bank 6
132		Y7  /ROM    ROM
	117	//-------------------------------------------------
	118	//  write -
	119	//-------------------------------------------------
133	120
134		*/
	121	WRITE8_MEMBER( bw2_state::write )
	122	{
	123	int vram = 1, ram1 = 1, ram2 = 1, ram3 = 1, ram4 = 1, ram5 = 1, ram6 = 1;
135	124
136		address_space &program = m_maincpu->space(AS_PROGRAM);
137
138		int max_ram_bank = BANK_RAM1;
139
140		m_bank = data & 0x07;
141
142		switch (m_ram->size())
	125	switch (m_bank)
143	126	{
144		case 64 * 1024:
145		case 96 * 1024:
146		max_ram_bank = BANK_RAM1;
147		break;
	127	case RAM1: ram1 = 0; break;
	128	case VRAM: vram = 0; break;
	129	case RAM2: ram2 = 0; break;
	130	case RAM3: ram3 = 0; break;
	131	case RAM4: ram4 = 0; break;
	132	case RAM5: ram5 = 0; break;
	133	case RAM6: ram6 = 0; break;
	134	}
148	135
149		case 128 * 1024:
150		max_ram_bank = BANK_RAM3;
151		break;
152
153		case 160 * 1024:
154		max_ram_bank = BANK_RAM4;
155		break;
156
157		case 192 * 1024:
158		case 224 * 1024:
159		max_ram_bank = BANK_RAM6;
160		break;
	136	if (!vram)
	137	{
	138	m_video_ram[offset & 0x3fff] = data;
161	139	}
162	140
163		switch (m_bank)
	141	if (!ram1)
164	142	{
165		case BANK_RAM1:
166		case BANK_RAMCARD_RAM:
167		program.install_readwrite_bank(0x0000, 0x7fff, "bank1");
168		break;
	143	m_ram->pointer()[offset] = data;
	144	}
169	145
170		case BANK_VRAM:
171		program.install_readwrite_bank(0x0000, 0x3fff, 0, 0x4000, "bank1");
172		break;
173
174		case BANK_RAM3:
175		case BANK_RAM4:
176		case BANK_RAM6:
177		if (m_bank > max_ram_bank)
178		{
179		program.unmap_readwrite(0x0000, 0x7fff);
180		}
181		else
182		{
183		program.install_readwrite_bank(0x0000, 0x7fff, "bank1");
184		}
185		break;
186
187		case BANK_RAMCARD_ROM:
188		program.install_read_bank(0x0000, 0x3fff, 0, 0x4000, "bank1");
189		program.unmap_write(0x0000, 0x3fff, 0, 0x4000);
190		break;
191
192		case BANK_ROM:
193		program.install_read_bank(0x0000, 0x7fff, "bank1");
194		program.unmap_write(0x0000, 0x7fff);
195		break;
	146	if (!ram2 && (m_ram->size() >= 96 * 1024))
	147	{
	148	m_ram->pointer()[0x10000 | offset] = data;
196	149	}
197	150
198		membank("bank1")->set_entry(m_bank);
199		}
200
201		WRITE8_MEMBER( bw2_state::ramcard_bank_w )
202		{
203		address_space &program = m_maincpu->space(AS_PROGRAM);
204
205		UINT8 ramcard_bank = data & 0x0f;
206		UINT32 bank_offset = ramcard_bank * 0x8000;
207
208		if ((get_ramdisk_size() == 256) && (ramcard_bank > 7))
	151	if (!ram3 && (m_ram->size() >= 128 * 1024))
209	152	{
210		program.unmap_readwrite(0x0000, 0x7fff);
	153	m_ram->pointer()[0x18000 | offset] = data;
211	154	}
212		else
	155
	156	if (!ram4 && (m_ram->size() >= 160 * 1024))
213	157	{
214		program.install_readwrite_bank(0x0000, 0x7fff, "bank1");
	158	m_ram->pointer()[0x20000 | offset] = data;
215	159	}
216	160
217		membank("bank1")->configure_entry(BANK_RAMCARD_RAM, m_ramcard_ram + bank_offset);
218		membank("bank1")->set_entry(m_bank);
219		}
220
221		/* Floppy */
222
223		WRITE_LINE_MEMBER( bw2_state::fdc_drq_w )
224		{
225		if (state)
	161	if (!ram5 && (m_ram->size() >= 192 * 1024))
226	162	{
227		if (m_maincpu->state_int(Z80_HALT))
228		{
229		m_maincpu->set_input_line(INPUT_LINE_NMI, HOLD_LINE);
230		}
	163	m_ram->pointer()[0x28000 | offset] = data;
231	164	}
232		else
	165
	166	if (!ram6 && (m_ram->size() >= 224 * 1024))
233	167	{
234		m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
	168	m_ram->pointer()[0x30000 | offset] = data;
235	169	}
	170
	171	m_exp->cd_w(space, offset, data, ram2, ram3, ram4, ram5, ram6);
236	172	}
237	173
	174
	175
	176	//**************************************************************************
	177	//  ADDRESS MAPS
	178	//**************************************************************************
	179
	180	//-------------------------------------------------
	181	//  ADDRESS_MAP( bw2_mem )
	182	//-------------------------------------------------
	183
238	184	static ADDRESS_MAP_START( bw2_mem, AS_PROGRAM, 8, bw2_state )
239	185	ADDRESS_MAP_UNMAP_HIGH
240		AM_RANGE(0x0000, 0x7fff) AM_RAMBANK("bank1")
	186	AM_RANGE(0x0000, 0x7fff) AM_READWRITE(read, write)
241	187	AM_RANGE(0x8000, 0xffff) AM_RAM
242	188	ADDRESS_MAP_END
243	189
	190
	191	//-------------------------------------------------
	192	//  ADDRESS_MAP( bw2_io )
	193	//-------------------------------------------------
	194
244	195	static ADDRESS_MAP_START( bw2_io, AS_IO, 8, bw2_state )
245	196	ADDRESS_MAP_UNMAP_HIGH
246	197	ADDRESS_MAP_GLOBAL_MASK(0xff)
247		AM_RANGE( 0x00, 0x03 ) AM_DEVREADWRITE(I8255A_TAG, i8255_device, read, write)
248		AM_RANGE( 0x10, 0x13 ) AM_DEVREADWRITE_LEGACY(PIT8253_TAG, pit8253_r, pit8253_w)
249		AM_RANGE( 0x20, 0x21 ) AM_DEVREADWRITE(MSM6255_TAG, msm6255_device, read, write)
250		//  AM_RANGE( 0x30, 0x3f ) SLOT
251		AM_RANGE( 0x40, 0x40 ) AM_DEVREADWRITE(I8251_TAG, i8251_device, data_r, data_w)
252		AM_RANGE( 0x41, 0x41 ) AM_DEVREADWRITE(I8251_TAG, i8251_device, status_r, control_w)
253		AM_RANGE( 0x50, 0x50 ) AM_DEVWRITE(CENTRONICS_TAG, centronics_device, write)
254		AM_RANGE( 0x60, 0x63 ) AM_DEVREADWRITE_LEGACY(WD2797_TAG, wd17xx_r, wd17xx_w)
255		//  AM_RANGE( 0x70, 0x7f ) MODEMSEL
	198	AM_RANGE(0x00, 0x03) AM_DEVREADWRITE(I8255A_TAG, i8255_device, read, write)
	199	AM_RANGE(0x10, 0x13) AM_DEVREADWRITE_LEGACY(I8253_TAG, pit8253_r, pit8253_w)
	200	AM_RANGE(0x20, 0x21) AM_DEVREADWRITE(MSM6255_TAG, msm6255_device, read, write)
	201	AM_RANGE(0x30, 0x3f) AM_DEVREADWRITE(BW2_EXPANSION_SLOT_TAG, bw2_expansion_slot_device, slot_r, slot_w)
	202	AM_RANGE(0x40, 0x40) AM_DEVREADWRITE(I8251_TAG, i8251_device, data_r, data_w)
	203	AM_RANGE(0x41, 0x41) AM_DEVREADWRITE(I8251_TAG, i8251_device, status_r, control_w)
	204	AM_RANGE(0x50, 0x50) AM_DEVWRITE(CENTRONICS_TAG, centronics_device, write)
	205	AM_RANGE(0x60, 0x63) AM_DEVREADWRITE(WD2797_TAG, wd2797_t, read, write)
	206	AM_RANGE(0x70, 0x7f) AM_DEVREADWRITE(BW2_EXPANSION_SLOT_TAG, bw2_expansion_slot_device, modsel_r, modsel_w)
256	207	ADDRESS_MAP_END
257	208
	209
	210
	211	//**************************************************************************
	212	//  INPUT PORTS
	213	//**************************************************************************
	214
	215	//-------------------------------------------------
	216	//  INPUT_PORTS( bw2 )
	217	//-------------------------------------------------
	218
258	219	/*
259	220	Keyboard matrix
260	221	X0    X1    X2    X3    X4    X5    X6    X7
r18993	r18994
282	243	*/
283	244
284	245	static INPUT_PORTS_START( bw2 )
285		PORT_START("ROW0")
	246	PORT_START("Y0")
286	247	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
287	248	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8)
288	249	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
r18993	r18994
292	253	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR('_')
293	254	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_DEL) PORT_CHAR(UCHAR_MAMEKEY(DEL))
294	255
295		PORT_START("ROW1")
	256	PORT_START("Y1")
296	257	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
297	258	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+')
298	259	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']') PORT_CHAR('}')
r18993	r18994
302	263	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
303	264	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_F8) PORT_CHAR(UCHAR_MAMEKEY(F8))
304	265
305		PORT_START("ROW2")
	266	PORT_START("Y2")
306	267	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))
307	268	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_TILDE) PORT_CHAR('^') PORT_CHAR('~')
308	269	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{')
r18993	r18994
312	273	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
313	274	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_F7) PORT_CHAR(UCHAR_MAMEKEY(F7))
314	275
315		PORT_START("ROW3")
	276	PORT_START("Y3")
316	277	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_TAB) PORT_CHAR(UCHAR_MAMEKEY(TAB))
317	278	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR(':') PORT_CHAR('*')
318	279	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
r18993	r18994
322	283	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'')
323	284	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_F6) PORT_CHAR(UCHAR_MAMEKEY(F6))
324	285
325		PORT_START("ROW4")
	286	PORT_START("Y4")
326	287	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_ESC) PORT_CHAR(27)
327	288	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_UNUSED)
328	289	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_UNUSED)
r18993	r18994
332	293	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
333	294	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_F5) PORT_CHAR(UCHAR_MAMEKEY(F5))
334	295
335		PORT_START("ROW5")
	296	PORT_START("Y5")
336	297	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
337	298	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_UNUSED)
338	299	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_UNUSED)
r18993	r18994
342	303	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
343	304	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_F4) PORT_CHAR(UCHAR_MAMEKEY(F4))
344	305
345		PORT_START("ROW6")
	306	PORT_START("Y6")
346	307	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('@') PORT_CHAR('`')
347	308	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P')
348	309	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP))
r18993	r18994
352	313	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
353	314	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_F3) PORT_CHAR(UCHAR_MAMEKEY(F3))
354	315
355		PORT_START("ROW7")
	316	PORT_START("Y7")
356	317	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_MAMEKEY(LCONTROL))
357	318	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('=')
358	319	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('|')
r18993	r18994
362	323	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
363	324	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_F2) PORT_CHAR(UCHAR_MAMEKEY(F2))
364	325
365		PORT_START("ROW8")
	326	PORT_START("Y8")
366	327	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
367	328	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_UNUSED)
368	329	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
r18993	r18994
372	333	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"')
373	334	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_F1) PORT_CHAR(UCHAR_MAMEKEY(F1))
374	335
375		PORT_START("ROW9")
	336	PORT_START("Y9")
376	337	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_CAPSLOCK) PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK))
377	338	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_UNUSED)
378	339	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_UNUSED)
r18993	r18994
390	351	PORT_CONFSETTING( 0x03, "1200 baud" )
391	352	PORT_CONFSETTING( 0x04, "600 baud" )
392	353	PORT_CONFSETTING( 0x05, "300 baud" )
393
394		PORT_START("RAMCARD")
395		PORT_CONFNAME( 0x03, 0x00, "RAMCARD")
396		PORT_CONFSETTING( 0x00, DEF_STR( None ) )
397		PORT_CONFSETTING( 0x01, "256 KB" )
398		PORT_CONFSETTING( 0x02, "512 KB" )
399	354	INPUT_PORTS_END
400	355
401		/* PPI */
402	356
	357
	358	//**************************************************************************
	359	//  DEVICE CONFIGURATION
	360	//**************************************************************************
	361
	362	//-------------------------------------------------
	363	//  I8255A_INTERFACE( ppi_intf )
	364	//-------------------------------------------------
	365
403	366	WRITE8_MEMBER( bw2_state::ppi_pa_w )
404	367	{
405	368	/*
406	369
407		PA0     KB0 Keyboard line select 0
408		PA1     KB1 Keyboard line select 1
409		PA2     KB2 Keyboard line select 2
410		PA3     KB3 Keyboard line select 3
411		PA4     /DS0 Drive select 0
412		PA5     /DS1 Drive select 1
413		PA6     Select RS232 connector
414		PA7     /STROBE to centronics printer
	370	PA0     KB0 Keyboard line select 0
	371	PA1     KB1 Keyboard line select 1
	372	PA2     KB2 Keyboard line select 2
	373	PA3     KB3 Keyboard line select 3
	374	PA4     /DS0 Drive select 0
	375	PA5     /DS1 Drive select 1
	376	PA6     Select RS232 connector
	377	PA7     /STROBE to centronics printer
415	378
416		*/
	379	*/
417	380
418		m_kb_row = data & 0x0f;
	381	// keyboard
	382	m_kb = data & 0x0f;
419	383
420		if (BIT(data, 4))
421		{
422		m_drive = 0;
	384	// drive select
	385	m_floppy = NULL;
423	386
424		wd17xx_set_drive(m_fdc, m_drive);
425		}
	387	if (BIT(data, 4)) m_floppy = m_floppy0->get_device();
	388	if (BIT(data, 5)) m_floppy = m_floppy1->get_device();
426	389
427		if (BIT(data, 5))
428		{
429		m_drive = 1;
	390	m_fdc->set_floppy(m_floppy);
	391	if (m_floppy) m_floppy->mon_w(m_mtron);
430	392
431		wd17xx_set_drive(m_fdc, m_drive);
432		}
433
	393	// centronics strobe
434	394	m_centronics->strobe_w(BIT(data, 7));
435	395	}
436	396
r18993	r18994
438	398	{
439	399	/*
440	400
441		PB0     Keyboard column status of selected line
442		PB1     Keyboard column status of selected line
443		PB2     Keyboard column status of selected line
444		PB3     Keyboard column status of selected line
445		PB4     Keyboard column status of selected line
446		PB5     Keyboard column status of selected line
447		PB6     Keyboard column status of selected line
448		PB7     Keyboard column status of selected line
	401	PB0     Keyboard column status of selected line
	402	PB1     Keyboard column status of selected line
	403	PB2     Keyboard column status of selected line
	404	PB3     Keyboard column status of selected line
	405	PB4     Keyboard column status of selected line
	406	PB5     Keyboard column status of selected line
	407	PB6     Keyboard column status of selected line
	408	PB7     Keyboard column status of selected line
449	409
450		*/
	410	*/
451	411
452		static const char *const rownames[] = { "ROW0", "ROW1", "ROW2", "ROW3", "ROW4", "ROW5", "ROW6", "ROW7", "ROW8", "ROW9" };
	412	static const char *const rownames[] = { "Y0", "Y1", "Y2", "Y3", "Y4", "Y5", "Y6", "Y7", "Y8", "Y9" };
453	413
454	414	UINT8 data = 0xff;
455	415
456		if (m_kb_row <= 9)
	416	if (m_kb <= 9)
457	417	{
458		data = ioport(rownames[m_kb_row])->read();
	418	data = ioport(rownames[m_kb])->read();
459	419	}
460	420
461	421	return data;
r18993	r18994
465	425	{
466	426	/*
467	427
468		PC0     Memory bank select
469		PC1     Memory bank select
470		PC2     Memory bank select
471		PC3     Not connected
	428	PC0     Memory bank select
	429	PC1     Memory bank select
	430	PC2     Memory bank select
	431	PC3     Not connected
472	432
473		*/
	433	*/
474	434
475		if (get_ramdisk_size() > 0)
476		{
477		ramcard_bankswitch(data & 0x07);
478		}
479		else
480		{
481		bankswitch(data & 0x07);
482		}
	435	m_bank = data & 0x07;
483	436	}
484	437
485	438	READ8_MEMBER( bw2_state::ppi_pc_r )
486	439	{
487	440	/*
488	441
489		PC4     BUSY from centronics printer
490		PC5     M/FDBK motor feedback
491		PC6     RLSD Carrier detect from RS232
492		PC7     /PROT Write protected disk
	442	PC4     BUSY from centronics printer
	443	PC5     M/FDBK motor feedback
	444	PC6     RLSD Carrier detect from RS232
	445	PC7     /PROT Write protected disk
493	446
494		*/
	447	*/
495	448
496	449	UINT8 data = 0;
497	450
	451	// centronics busy
498	452	data |= m_centronics->busy_r() << 4;
	453
	454	// floppy motor
499	455	data |= m_mfdbk << 5;
500	456
501		data |= floppy_wpt_r(m_drive ? m_floppy1 : m_floppy0) << 7;
	457	// write protect
	458	if (m_floppy) data |= m_floppy->wpt_r() << 7;
502	459
503	460	return data;
504	461	}
r18993	r18994
513	470	DEVCB_DRIVER_MEMBER(bw2_state, ppi_pc_w),
514	471	};
515	472
516		/* PIT */
517	473
	474	//-------------------------------------------------
	475	//  pit8253_config pit_intf
	476	//-------------------------------------------------
	477
518	478	WRITE_LINE_MEMBER( bw2_state::pit_out0_w )
519	479	{
520	480	m_uart->transmit_clock();
r18993	r18994
526	486	m_mtron = state;
527	487	m_mfdbk = !state;
528	488
529		floppy_mon_w(m_floppy0, m_mtron);
530		floppy_mon_w(m_floppy1, m_mtron);
531
532		floppy_drive_set_ready_state(m_floppy0, 1, 1);
533		floppy_drive_set_ready_state(m_floppy1, 1, 1);
	489	if (m_floppy) m_floppy->mon_w(m_mtron);
534	490	}
535	491
536	492	static const struct pit8253_config pit_intf =
537	493	{
538	494	{
539	495	{
540		XTAL_16MHz/4,   /* 8251 USART TXC, RXC */
	496	XTAL_16MHz/4,   // 8251 USART TXC, RXC
541	497	DEVCB_LINE_VCC,
542	498	DEVCB_DRIVER_LINE_MEMBER(bw2_state, pit_out0_w)
543	499	},
544	500	{
545		11000,      /* LCD controller */
	501	11000,      // LCD controller
546	502	DEVCB_LINE_VCC,
547		DEVCB_DEVICE_LINE(PIT8253_TAG, pit8253_clk2_w)
	503	DEVCB_DEVICE_LINE(I8253_TAG, pit8253_clk2_w)
548	504	},
549	505	{
550		0,      /* Floppy /MTRON */
	506	0,      // Floppy /MTRON
551	507	DEVCB_LINE_VCC,
552	508	DEVCB_DRIVER_LINE_MEMBER(bw2_state, mtron_w)
553	509	}
r18993	r18994
555	511	};
556	512
557	513
558		/* Video */
	514	//-------------------------------------------------
	515	//  MSM6255_INTERFACE( lcdc_intf )
	516	//-------------------------------------------------
559	517
560	518	void bw2_state::palette_init()
561	519	{
562		palette_set_color_rgb(machine(), 0, 0xa5, 0xad, 0xa5);
563		palette_set_color_rgb(machine(), 1, 0x31, 0x39, 0x10);
	520	palette_set_color_rgb(machine(), 0, 0xa5, 0xad, 0xa5);
	521	palette_set_color_rgb(machine(), 1, 0x31, 0x39, 0x10);
564	522	}
565	523
566	524	static MSM6255_CHAR_RAM_READ( bw2_charram_r )
r18993	r18994
577	535	bw2_charram_r,
578	536	};
579	537
580		static LEGACY_FLOPPY_OPTIONS_START(bw2)
581		LEGACY_FLOPPY_OPTION(bw2, "dsk", "BW2 340K disk image", basicdsk_identify_default, basicdsk_construct_default, NULL,
582		HEADS([1])
583		TRACKS([80])
584		SECTORS([17])
585		SECTOR_LENGTH([256])
586		FIRST_SECTOR_ID([0]))
587		LEGACY_FLOPPY_OPTION(bw2, "dsk", "BW2 360K disk image", basicdsk_identify_default, basicdsk_construct_default, NULL,
588		HEADS([1])
589		TRACKS([80])
590		SECTORS([18])
591		SECTOR_LENGTH([256])
592		FIRST_SECTOR_ID([0]))
593		LEGACY_FLOPPY_OPTIONS_END
594	538
595		static const floppy_interface bw2_floppy_interface =
	539	//-------------------------------------------------
	540	//  floppy_format_type floppy_formats
	541	//-------------------------------------------------
	542
	543	void bw2_state::fdc_intrq_w(bool state)
596	544	{
	545	logerror("intrq %u\n", state?1:0);
	546	m_maincpu->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE);
	547	}
	548
	549	void bw2_state::fdc_drq_w(bool state)
	550	{
	551	logerror("drq %u\n", state?1:0);
	552	if (state)
	553	{
	554	if (m_maincpu->state_int(Z80_HALT))
	555	{
	556	m_maincpu->set_input_line(INPUT_LINE_NMI, HOLD_LINE);
	557	}
	558	}
	559	else
	560	{
	561	m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
	562	}
	563	}
	564
	565	const floppy_format_type bw2_state::floppy_formats[] = {
	566	FLOPPY_BW2_FORMAT,
	567	FLOPPY_IMD_FORMAT,
	568	FLOPPY_MFM_FORMAT,
	569	FLOPPY_MFI_FORMAT,
	570	NULL
	571	};
	572
	573	static SLOT_INTERFACE_START( bw2_floppies )
	574	SLOT_INTERFACE( "35dd", FLOPPY_35_DD ) // Teac FD-35
	575	SLOT_INTERFACE_END
	576
	577
	578	//-------------------------------------------------
	579	//  rs232_port_interface rs232_intf
	580	//-------------------------------------------------
	581
	582	static SLOT_INTERFACE_START( rs232_devices )
	583	SLOT_INTERFACE_END
	584
	585	static const rs232_port_interface rs232_intf =
	586	{
597	587	DEVCB_NULL,
598	588	DEVCB_NULL,
599	589	DEVCB_NULL,
600	590	DEVCB_NULL,
601		DEVCB_NULL,
602		FLOPPY_STANDARD_3_5_SSDD, // Teac FD-35
603		LEGACY_FLOPPY_OPTIONS_NAME(bw2),
604		"floppy_3_5",
605		NULL
	591	DEVCB_NULL
606	592	};
607	593
608		static const wd17xx_interface fdc_intf =
609		{
610		DEVCB_LINE_GND,
611		DEVCB_CPU_INPUT_LINE(Z80_TAG, INPUT_LINE_IRQ0),
612		DEVCB_DRIVER_LINE_MEMBER(bw2_state, fdc_drq_w),
613		{ FLOPPY_0, FLOPPY_1, NULL, NULL }
614		};
615	594
616		/* Machine */
617	595
	596	//**************************************************************************
	597	//  MACHINE INITIALIZATION
	598	//**************************************************************************
	599
	600	//-------------------------------------------------
	601	//  MACHINE_START( bw2 )
	602	//-------------------------------------------------
	603
618	604	void bw2_state::machine_start()
619	605	{
620		/* allocate memory */
621		m_video_ram = auto_alloc_array(machine(), UINT8, BW2_VIDEORAM_SIZE);
622		m_ramcard_ram = auto_alloc_array(machine(), UINT8, BW2_RAMCARD_SIZE);
	606	// allocate memory
	607	m_video_ram.allocate(0x4000);
623	608
624		/* memory banking */
625		membank("bank1")->configure_entry(BANK_RAM1, m_ram->pointer());
626		membank("bank1")->configure_entry(BANK_VRAM, m_video_ram);
627		membank("bank1")->configure_entry(BANK_ROM, memregion("ic1")->base());
	609	// floppy callbacks
	610	m_fdc->setup_intrq_cb(wd2797_t::line_cb(FUNC(bw2_state::fdc_intrq_w), this));
	611	m_fdc->setup_drq_cb(wd2797_t::line_cb(FUNC(bw2_state::fdc_drq_w), this));
628	612
629		/* register for state saving */
630		save_item(NAME(m_kb_row));
631		save_pointer(NAME(m_ramcard_ram), BW2_RAMCARD_SIZE);
	613	// register for state saving
	614	save_item(NAME(m_kb));
632	615	save_item(NAME(m_bank));
633		save_item(NAME(m_drive));
634	616	save_item(NAME(m_mtron));
635	617	save_item(NAME(m_mfdbk));
636		save_pointer(NAME(m_video_ram), BW2_VIDEORAM_SIZE);
637	618	}
638	619
639		void bw2_state::machine_reset()
640		{
641		address_space &io = machine().device(Z80_TAG)->memory().space(AS_IO);
642	620
643		if (get_ramdisk_size() > 0)
644		{
645		// RAMCARD installed
646	621
647		membank("bank1")->configure_entry(BANK_RAMCARD_ROM, memregion("ramcard")->base());
648		membank("bank1")->configure_entries(BANK_RAM3, 2, m_ram->pointer() + 0x8000, 0x8000);
649		membank("bank1")->configure_entry(BANK_RAMCARD_RAM, m_ramcard_ram);
650		membank("bank1")->configure_entry(BANK_RAM6, m_ram->pointer() + 0x18000);
	622	//**************************************************************************
	623	//  MACHINE DRIVERS
	624	//**************************************************************************
651	625
652		io.install_write_handler(0x30, 0x30, 0, 0x0f, write8_delegate(FUNC(bw2_state::ramcard_bank_w), this), 0);
653		}
654		else
655		{
656		// no RAMCARD
	626	//-------------------------------------------------
	627	//  MACHINE_CONFIG( bw2 )
	628	//-------------------------------------------------
657	629
658		membank("bank1")->configure_entries(BANK_RAM2, 5, m_ram->pointer() + 0x8000, 0x8000);
659
660		io.unmap_write(0x30, 0x30, 0, 0x0f);
661		}
662
663		membank("bank1")->set_entry(BANK_ROM);
664		}
665
666	630	static MACHINE_CONFIG_START( bw2, bw2_state )
667	631	// basic machine hardware
668	632	MCFG_CPU_ADD(Z80_TAG, Z80, XTAL_16MHz/4)
r18993	r18994
670	634	MCFG_CPU_IO_MAP(bw2_io)
671	635
672	636	// video hardware
673		MCFG_SCREEN_ADD( SCREEN_TAG, LCD )
674		MCFG_SCREEN_REFRESH_RATE( 60 )
	637	MCFG_DEFAULT_LAYOUT(layout_lcd)
	638	MCFG_SCREEN_ADD(SCREEN_TAG, LCD)
	639	MCFG_SCREEN_REFRESH_RATE(60)
675	640	MCFG_SCREEN_UPDATE_DEVICE( MSM6255_TAG, msm6255_device, screen_update )
676		MCFG_SCREEN_SIZE( 640, 200 )
677		MCFG_SCREEN_VISIBLE_AREA( 0, 640-1, 0, 200-1 )
678		MCFG_DEFAULT_LAYOUT( layout_lcd )
	641	MCFG_SCREEN_SIZE(640, 200)
	642	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 200-1)
	643	MCFG_PALETTE_LENGTH(2)
679	644
680		MCFG_PALETTE_LENGTH( 2 )
681
682	645	// devices
683		MCFG_PIT8253_ADD(PIT8253_TAG, pit_intf)
	646	MCFG_PIT8253_ADD(I8253_TAG, pit_intf)
684	647	MCFG_I8255A_ADD(I8255A_TAG, ppi_intf)
685	648	MCFG_MSM6255_ADD(MSM6255_TAG, XTAL_16MHz, lcdc_intf)
686	649	MCFG_CENTRONICS_PRINTER_ADD(CENTRONICS_TAG, standard_centronics)
687	650	MCFG_I8251_ADD(I8251_TAG, default_i8251_interface)
688		MCFG_WD2797_ADD(WD2797_TAG, fdc_intf)
689		MCFG_LEGACY_FLOPPY_2_DRIVES_ADD(bw2_floppy_interface)
	651	MCFG_WD2797x_ADD(WD2797_TAG, XTAL_16MHz/16)
	652	MCFG_FLOPPY_DRIVE_ADD(WD2797_TAG":0", bw2_floppies, "35dd", NULL, bw2_state::floppy_formats)
	653	MCFG_FLOPPY_DRIVE_ADD(WD2797_TAG":1", bw2_floppies, NULL,   NULL, bw2_state::floppy_formats)
	654	MCFG_BW2_EXPANSION_SLOT_ADD(BW2_EXPANSION_SLOT_TAG, XTAL_16MHz, bw2_expansion_cards, NULL, NULL)
	655	MCFG_RS232_PORT_ADD(RS232_TAG, rs232_intf, rs232_devices, NULL, NULL)
690	656
691	657	// software list
692	658	MCFG_SOFTWARE_LIST_ADD("flop_list","bw2")
r18993	r18994
697	663	MCFG_RAM_EXTRA_OPTIONS("96K,128K,160K,192K,224K")
698	664	MACHINE_CONFIG_END
699	665
700		/***************************************************************************
701	666
702		System driver(s)
703	667
704		***************************************************************************/
	668	//**************************************************************************
	669	//  ROMS
	670	//**************************************************************************
705	671
706		ROM_START( bw2 )
707		ROM_REGION(0x10000, "ic1", 0)
708		ROM_SYSTEM_BIOS(0, "20", "BW 2 v2.0")
709		ROMX_LOAD("bw2-20.ic8", 0x0000, 0x1000, CRC(86f36471) SHA1(a3e2ba4edd50ff8424bb0675bdbb3b9f13c04c9d), ROM_BIOS(1))
710		ROM_SYSTEM_BIOS(1, "12", "BW 2 v1.2")
711		ROMX_LOAD("bw2-12.ic8", 0x0000, 0x1000, CRC(0ab42d10) SHA1(430b232631eee9b715151b8d191b7eb9449ac513), ROM_BIOS(2))
	672	//-------------------------------------------------
	673	//  ROM( bw2 )
	674	//-------------------------------------------------
712	675
713		ROM_REGION(0x4000, "ramcard", 0)
714		ROM_LOAD("ramcard-10.bin", 0x0000, 0x4000, CRC(68cde1ba) SHA1(a776a27d64f7b857565594beb63aa2cd692dcf04))
	676	ROM_START( bw2 )
	677	ROM_REGION( 0x1000, Z80_TAG, 0 )
	678	ROM_DEFAULT_BIOS( "v20" )
	679	ROM_SYSTEM_BIOS( 0, "v12", "BW 2 v1.2" )
	680	ROMX_LOAD( "bw2-12.ic8", 0x0000, 0x1000, CRC(0ab42d10) SHA1(430b232631eee9b715151b8d191b7eb9449ac513), ROM_BIOS(1) )
	681	ROM_SYSTEM_BIOS( 1, "v20", "BW 2 v2.0" )
	682	ROMX_LOAD( "bw2-20.ic8", 0x0000, 0x1000, CRC(86f36471) SHA1(a3e2ba4edd50ff8424bb0675bdbb3b9f13c04c9d), ROM_BIOS(2) )
715	683	ROM_END
716	684
717		/*    YEAR  NAME    PARENT  COMPAT  MACHINE   INPUT   INIT    COMPANY              FULLNAME  FLAGS */
718		COMP( 1985, bw2,    0,      0,      bw2,      bw2, driver_device,    0,   "Bondwell Holding",  "Bondwell Model 2",   GAME_NO_SOUND )
	685
	686
	687	//**************************************************************************
	688	//  SYSTEM DRIVERS
	689	//**************************************************************************
	690
	691	//    YEAR  NAME    PARENT  COMPAT  MACHINE     INPUT   INIT                        COMPANY             FULLNAME            FLAGS
	692	COMP( 1985, bw2,    0,      0,      bw2,        bw2,    driver_device,      0,      "Bondwell Holding", "Bondwell Model 2", GAME_NO_SOUND_HW )

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