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r18984 Friday 16th November, 2012 at 12:23:38 UTC by Michael Zapf
Fixed overflow detection in INC and DEC opcodes (nw)

[src/emu/cpu/tms9900]

tms9900.c tms9995.c

trunk/src/emu/cpu/tms9900/tms9995.c

r18983	r18984
94	94	/* tms9995 ST register bits. */
95	95	enum
96	96	{
97		ST_LH = 0x8000,      // Logical higher (unsigned comparison)
98		ST_AGT = 0x4000,   // Arithmetical greater than (signed comparison)
99		ST_EQ = 0x2000,      // Equal
100		ST_C = 0x1000,      // Carry
101		ST_OV = 0x0800,      // Overflow (when using signed operations)
102		ST_OP = 0x0400,      // Odd parity (used with byte operations)
103		ST_X = 0x0200,      // XOP
104		ST_OE = 0x0020,      // Overflow interrupt enabled
105		ST_IM = 0x000f      // Interrupt mask
	97	ST_LH = 0x8000,     // Logical higher (unsigned comparison)
	98	ST_AGT = 0x4000,    // Arithmetical greater than (signed comparison)
	99	ST_EQ = 0x2000,     // Equal
	100	ST_C = 0x1000,      // Carry
	101	ST_OV = 0x0800,     // Overflow (when using signed operations)
	102	ST_OP = 0x0400,     // Odd parity (used with byte operations)
	103	ST_X = 0x0200,      // XOP
	104	ST_OE = 0x0020,     // Overflow interrupt enabled
	105	ST_IM = 0x000f      // Interrupt mask
106	106	};
107	107
108	108	enum
r18983	r18984
124	124
125	125	tms9995_device::tms9995_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
126	126	: cpu_device(mconfig, TMS9995, "TMS9995", tag, owner, clock),
127		m_program_config("program", ENDIANNESS_BIG, 8, 16),
128		m_io_config("cru", ENDIANNESS_BIG, 8, 16),
129		m_prgspace(NULL),
130		m_cru(NULL)
	127	m_program_config("program", ENDIANNESS_BIG, 8, 16),
	128	m_io_config("cru", ENDIANNESS_BIG, 8, 16),
	129	m_prgspace(NULL),
	130	m_cru(NULL)
131	131	{
132	132	}
133	133
r18983	r18984
148	148
149	149	// TODO: Restore save state suport
150	150
151		m_prgspace = &space(AS_PROGRAM);                  // dimemory.h
	151	m_prgspace = &space(AS_PROGRAM);                        // dimemory.h
152	152	m_cru = &space(AS_IO);
153	153
154	154	// Resolve our external connections
r18983	r18984
207	207	*/
208	208	void tms9995_device::device_reset()
209	209	{
210		m_reset = true;      // for the main loop
	210	m_reset = true;     // for the main loop
211	211	}
212	212
213	213	const char* tms9995_device::s_statename[20] =
r18983	r18984
402	402
403	403	MICROPROGRAM(operand_address_derivation)
404	404	{
405		RETADDR, 0, 0, 0,                     // Register direct                  0
406		WORD_READ, RETADDR, 0, 0,               // Register indirect                1 (1)
407		WORD_READ, RETADDR, 0, 0,               // Symbolic                         1 (1)
408		WORD_READ, INCREG, WORD_WRITE, RETADDR1,   // Reg indirect auto-increment      3 (1) (1)
409		WORD_READ, INDX, WORD_READ, RETADDR         // Indexed                          3 (1) (1)
	405	RETADDR, 0, 0, 0,                           // Register direct                  0
	406	WORD_READ, RETADDR, 0, 0,                   // Register indirect                1 (1)
	407	WORD_READ, RETADDR, 0, 0,                   // Symbolic                         1 (1)
	408	WORD_READ, INCREG, WORD_WRITE, RETADDR1,    // Reg indirect auto-increment      3 (1) (1)
	409	WORD_READ, INDX, WORD_READ, RETADDR         // Indexed                          3 (1) (1)
410	410	};
411	411
412	412	MICROPROGRAM(add_s_sxc_mp)
413	413	{
414		OPERAND_ADDR,         // x
415		MEMORY_READ,         // 1 (1)
416		OPERAND_ADDR,         // y
417		MEMORY_READ,         // 1 (1)
418		ALU_ADD_S_SXC,         // 0
419		PREFETCH,            // 1 (1)
420		MEMORY_WRITE,         // 1 (1)
	414	OPERAND_ADDR,           // x
	415	MEMORY_READ,            // 1 (1)
	416	OPERAND_ADDR,           // y
	417	MEMORY_READ,            // 1 (1)
	418	ALU_ADD_S_SXC,          // 0
	419	PREFETCH,               // 1 (1)
	420	MEMORY_WRITE,           // 1 (1)
421	421	END
422	422	};
423	423
424	424	MICROPROGRAM(b_mp)
425	425	{
426	426	OPERAND_ADDR,
427		ALU_NOP,            // Don't read, just use the address
	427	ALU_NOP,                // Don't read, just use the address
428	428	ALU_B,
429	429	PREFETCH,
430		ALU_NOP,            // Don't save the return address
	430	ALU_NOP,                // Don't save the return address
431	431	END
432	432	};
433	433
434	434	MICROPROGRAM(bl_mp)
435	435	{
436	436	OPERAND_ADDR,
437		ALU_NOP,            // Don't read, just use the address
438		ALU_B,               // Re-use the alu operation from B
	437	ALU_NOP,                // Don't read, just use the address
	438	ALU_B,                  // Re-use the alu operation from B
439	439	PREFETCH,
440	440	ALU_NOP,
441		MEMORY_WRITE,         // Write R11
	441	MEMORY_WRITE,           // Write R11
442	442	ALU_NOP,
443	443	END
444	444	};
445	445
446	446	MICROPROGRAM(blwp_mp)
447	447	{
448		OPERAND_ADDR,         // Determine source address
	448	OPERAND_ADDR,           // Determine source address
449	449	MEMORY_READ,
450		ALU_BLWP,            // Got new WP, save it; increase address, save
451		MEMORY_WRITE,         // save old ST to new R15
	450	ALU_BLWP,               // Got new WP, save it; increase address, save
	451	MEMORY_WRITE,           // save old ST to new R15
452	452	ALU_BLWP,
453		MEMORY_WRITE,         // save old PC to new R14
	453	MEMORY_WRITE,           // save old PC to new R14
454	454	ALU_BLWP,
455		MEMORY_WRITE,         // save old WP to new R13
456		ALU_BLWP,            // retrieve address
457		MEMORY_READ,         // Read new PC
458		ALU_BLWP,            // Set new PC
	455	MEMORY_WRITE,           // save old WP to new R13
	456	ALU_BLWP,               // retrieve address
	457	MEMORY_READ,            // Read new PC
	458	ALU_BLWP,               // Set new PC
459	459	PREFETCH,
460	460	ALU_NOP,
461	461	END
r18983	r18984
463	463
464	464	MICROPROGRAM(c_mp)
465	465	{
466		OPERAND_ADDR,         // x
467		MEMORY_READ,         // 1 (1)
468		OPERAND_ADDR,         // y
469		MEMORY_READ,         // 1 (1)
470		ALU_C,               // 0
471		PREFETCH,            // 1 (1)
472		ALU_NOP,            // 1
	466	OPERAND_ADDR,           // x
	467	MEMORY_READ,            // 1 (1)
	468	OPERAND_ADDR,           // y
	469	MEMORY_READ,            // 1 (1)
	470	ALU_C,                  // 0
	471	PREFETCH,               // 1 (1)
	472	ALU_NOP,                // 1
473	473	END
474	474	};
475	475
476	476	MICROPROGRAM(ci_mp)
477	477	{
478		MEMORY_READ,         // 1 (reg)
479		SET_IMM,            // 0
480		MEMORY_READ,         // 1 (imm)
481		ALU_CI,               // (1) set status
482		PREFETCH,            // 1
483		ALU_NOP,            // 1
	478	MEMORY_READ,            // 1 (reg)
	479	SET_IMM,                // 0
	480	MEMORY_READ,            // 1 (imm)
	481	ALU_CI,                 // (1) set status
	482	PREFETCH,               // 1
	483	ALU_NOP,                // 1
484	484	END
485	485	};
486	486
r18983	r18984
500	500	{
501	501	OPERAND_ADDR,
502	502	ALU_NOP,
503		ALU_CLR_SETO,         // (1)
504		PREFETCH,            // 1
505		MEMORY_WRITE,         // 1
	503	ALU_CLR_SETO,           // (1)
	504	PREFETCH,               // 1
	505	MEMORY_WRITE,           // 1
506	506	END
507	507	};
508	508
509	509	MICROPROGRAM(divide_mp)
510	510	{
511		OPERAND_ADDR,         // Address of divisor S in Q=W1W2/S
512		MEMORY_READ,         // Get S
	511	OPERAND_ADDR,           // Address of divisor S in Q=W1W2/S
	512	MEMORY_READ,            // Get S
513	513	ALU_DIV,
514		MEMORY_READ,         // Get W1
515		ALU_DIV,            // Check for overflow; skip next instruction if not
	514	MEMORY_READ,            // Get W1
	515	ALU_DIV,                // Check for overflow; skip next instruction if not
516	516	ABORT,
517		MEMORY_READ,         // Get W2
518		ALU_DIV,            // Calculate quotient
519		MEMORY_WRITE,         // Write quotient to &W1
	517	MEMORY_READ,            // Get W2
	518	ALU_DIV,                // Calculate quotient
	519	MEMORY_WRITE,           // Write quotient to &W1
520	520	ALU_DIV,
521	521	PREFETCH,
522		MEMORY_WRITE,         // Write remainder to &W2
	522	MEMORY_WRITE,           // Write remainder to &W2
523	523	END
524	524	};
525	525
526	526	MICROPROGRAM(divide_signed_mp)
527	527	{
528		OPERAND_ADDR,         // Address of divisor S in Q=W1W2/S
529		MEMORY_READ,         // Get S
	528	OPERAND_ADDR,           // Address of divisor S in Q=W1W2/S
	529	MEMORY_READ,            // Get S
530	530	ALU_DIV,
531		MEMORY_READ,         // Get W1
532		ALU_DIV,            //
533		MEMORY_READ,         // Get W2
534		ALU_DIV,            // Check for overflow, skip next instruction if not
	531	MEMORY_READ,            // Get W1
	532	ALU_DIV,                //
	533	MEMORY_READ,            // Get W2
	534	ALU_DIV,                // Check for overflow, skip next instruction if not
535	535	ABORT,
536		ALU_DIV,            // Calculate quotient
537		MEMORY_WRITE,         // Write quotient to &W1
	536	ALU_DIV,                // Calculate quotient
	537	MEMORY_WRITE,           // Write quotient to &W1
538	538	ALU_DIV,
539	539	PREFETCH,
540		MEMORY_WRITE,         // Write remainder to &W2
	540	MEMORY_WRITE,           // Write remainder to &W2
541	541	END
542	542	};
543	543
r18983	r18984
557	557	MICROPROGRAM(imm_arithm_mp)
558	558	{
559	559	MEMORY_READ,
560		SET_IMM,            // 0
561		MEMORY_READ,         // 1 (1)
562		ALU_IMM_ARITHM,         // 0
563		PREFETCH,            // 1 (1)
	560	SET_IMM,                // 0
	561	MEMORY_READ,            // 1 (1)
	562	ALU_IMM_ARITHM,         // 0
	563	PREFETCH,               // 1 (1)
564	564	MEMORY_WRITE,
565	565	END
566	566	};
r18983	r18984
577	577	{
578	578	ALU_LDCR,
579	579	OPERAND_ADDR,
580		MEMORY_READ,         // Get source data
581		ALU_LDCR,            // Save it, point to R12
582		WORD_READ,            // Get R12
583		ALU_LDCR,            // Prepare CRU operation
	580	MEMORY_READ,            // Get source data
	581	ALU_LDCR,               // Save it, point to R12
	582	WORD_READ,              // Get R12
	583	ALU_LDCR,               // Prepare CRU operation
584	584	CRU_OUTPUT,
585	585	ALU_NOP,
586	586	PREFETCH,
r18983	r18984
590	590
591	591	MICROPROGRAM(li_mp)
592	592	{
593		SET_IMM,            // 0
594		MEMORY_READ,         // 1 (1)
595		ALU_LI,               // 0
596		PREFETCH,            // 1 (1)
	593	SET_IMM,                // 0
	594	MEMORY_READ,            // 1 (1)
	595	ALU_LI,                 // 0
	596	PREFETCH,               // 1 (1)
597	597	MEMORY_WRITE,
598	598	END
599	599	};
600	600
601	601	MICROPROGRAM(limi_lwpi_mp)
602	602	{
603		SET_IMM,            // 0
604		MEMORY_READ,         // 1 (1)
605		ALU_NOP,            // 1
606		ALU_LIMIWP,            // (1)
607		PREFETCH,            // 1
608		ALU_NOP,            // 1
	603	SET_IMM,                // 0
	604	MEMORY_READ,            // 1 (1)
	605	ALU_NOP,                // 1
	606	ALU_LIMIWP,             // (1)
	607	PREFETCH,               // 1
	608	ALU_NOP,                // 1
609	609	END
610	610	};
611	611
r18983	r18984
621	621
622	622	MICROPROGRAM(mov_mp)
623	623	{
624		OPERAND_ADDR,         // 0
625		MEMORY_READ,         // 1 (1)
626		OPERAND_ADDR,         // 0
627		ALU_MOV,            // 1
	624	OPERAND_ADDR,           // 0
	625	MEMORY_READ,            // 1 (1)
	626	OPERAND_ADDR,           // 0
	627	ALU_MOV,                // 1
628	628	PREFETCH,
629		MEMORY_WRITE,         // 1 (1)
	629	MEMORY_WRITE,           // 1 (1)
630	630	END
631	631	};
632	632
r18983	r18984
660	660
661	661	MICROPROGRAM(sbo_sbz_mp)
662	662	{
663		ALU_SBO_SBZ,         // Set address = &R12
664		WORD_READ,            // Read R12
665		ALU_SBO_SBZ,         // Add offset
666		CRU_OUTPUT,            // output via CRU
	663	ALU_SBO_SBZ,            // Set address = &R12
	664	WORD_READ,              // Read R12
	665	ALU_SBO_SBZ,            // Add offset
	666	CRU_OUTPUT,             // output via CRU
667	667	ALU_NOP,
668	668	PREFETCH,
669	669	ALU_NOP,
r18983	r18984
673	673	MICROPROGRAM(shift_mp)
674	674	{
675	675	MEMORY_READ,
676		ALU_SHIFT,            // skip next operation if count != 0
677		MEMORY_READ,         // if count=0 we must read R0
678		ALU_SHIFT,            // do the shift
	676	ALU_SHIFT,              // skip next operation if count != 0
	677	MEMORY_READ,            // if count=0 we must read R0
	678	ALU_SHIFT,              // do the shift
679	679	PREFETCH,
680	680	MEMORY_WRITE,
681	681	END
r18983	r18984
684	684	MICROPROGRAM(single_arithm_mp)
685	685	{
686	686	OPERAND_ADDR,
687		MEMORY_READ,         // This one is not done for CLR/SETO
	687	MEMORY_READ,            // This one is not done for CLR/SETO
688	688	ALU_SINGLE_ARITHM,
689	689	PREFETCH,
690	690	MEMORY_WRITE,
r18983	r18984
693	693
694	694	MICROPROGRAM(stcr_mp)
695	695	{
696		ALU_STCR,            // Check for byte operation
697		OPERAND_ADDR,         // Source operand
698		ALU_STCR,            // Save, set R12
699		WORD_READ,            // Read R12
	696	ALU_STCR,               // Check for byte operation
	697	OPERAND_ADDR,           // Source operand
	698	ALU_STCR,               // Save, set R12
	699	WORD_READ,              // Read R12
700	700	ALU_STCR,
701	701	CRU_INPUT,
702	702	ALU_STCR,
r18983	r18984
731	731	OPERAND_ADDR,
732	732	MEMORY_READ,
733	733	ALU_X,
734		END                  // should not be reached
	734	END                     // should not be reached
735	735	};
736	736
737	737	MICROPROGRAM(xop_mp)
738	738	{
739		OPERAND_ADDR,         // Determine source address
740		ALU_XOP,            // Save it; determine XOP number
741		MEMORY_READ,         // Read new WP
742		ALU_XOP,            //
743		MEMORY_WRITE,         // save source address to new R11
	739	OPERAND_ADDR,           // Determine source address
	740	ALU_XOP,                // Save it; determine XOP number
	741	MEMORY_READ,            // Read new WP
	742	ALU_XOP,                //
	743	MEMORY_WRITE,           // save source address to new R11
744	744	ALU_XOP,
745		MEMORY_WRITE,         // save old ST to new R15
	745	MEMORY_WRITE,           // save old ST to new R15
746	746	ALU_XOP,
747		MEMORY_WRITE,         // save old PC to new R14
	747	MEMORY_WRITE,           // save old PC to new R14
748	748	ALU_XOP,
749		MEMORY_WRITE,         // save old WP to new R13
	749	MEMORY_WRITE,           // save old WP to new R13
750	750	ALU_XOP,
751		MEMORY_READ,         // Read new PC
752		ALU_XOP,            // set new PC, set X flag
	751	MEMORY_READ,            // Read new PC
	752	ALU_XOP,                // set new PC, set X flag
753	753	PREFETCH,
754	754	ALU_NOP,
755	755	END
r18983	r18984
769	769
770	770	MICROPROGRAM(int_mp)
771	771	{
772		ALU_INT,            // 1
773		MEMORY_READ,         // 1 (1)
774		ALU_INT,            // 2
775		MEMORY_WRITE,         // 1 (1)
776		ALU_INT,            // 1
777		MEMORY_WRITE,         // 1 (1)
778		ALU_INT,            // 1
779		MEMORY_WRITE,         // 1 (1)
780		ALU_INT,            // 1
781		MEMORY_READ,         // 1 (1)
782		ALU_INT,            // 0
783		PREFETCH_NO_INT,      // 1 (1)  (prefetch happens in parallel to the previous operation)
784		ALU_NOP,            // 1 (+decode in parallel; actually performed right after prefetch)
785		ALU_NOP,            // 1
	772	ALU_INT,                // 1
	773	MEMORY_READ,            // 1 (1)
	774	ALU_INT,                // 2
	775	MEMORY_WRITE,           // 1 (1)
	776	ALU_INT,                // 1
	777	MEMORY_WRITE,           // 1 (1)
	778	ALU_INT,                // 1
	779	MEMORY_WRITE,           // 1 (1)
	780	ALU_INT,                // 1
	781	MEMORY_READ,            // 1 (1)
	782	ALU_INT,                // 0
	783	PREFETCH_NO_INT,        // 1 (1)  (prefetch happens in parallel to the previous operation)
	784	ALU_NOP,                // 1 (+decode in parallel; actually performed right after prefetch)
	785	ALU_NOP,                // 1
786	786	END
787	787	};
788	788
r18983	r18984
860	860
861	861	static const char opname[][5] =
862	862	{   "MID ", "A   ", "AB  ", "ABS ", "AI  ", "ANDI", "B   ", "BL  ", "BLWP", "C   ",
863		"CB  ", "CI  ",   "CKOF", "CKON", "CLR ", "COC ", "CZC ", "DEC ", "DECT", "DIV ",
	863	"CB  ", "CI  ", "CKOF", "CKON", "CLR ", "COC ", "CZC ", "DEC ", "DECT", "DIV ",
864	864	"DIVS", "IDLE", "INC ", "INCT", "INV ", "JEQ ", "JGT ", "JH  ", "JHE ", "JL  ",
865	865	"JLE ", "JLT ", "JMP ", "JNC ", "JNE ", "JNO ", "JOC ", "JOP ", "LDCR", "LI  ",
866	866	"LIMI", "LREX", "LST ", "LWP ", "LWPI", "MOV ", "MOVB", "MPY ", "MPYS", "NEG ",
867		"ORI ", "RSET",   "RTWP", "S   ", "SB  ", "SBO ", "SBZ ", "SETO", "SLA ", "SOC ",
868		"SOCB", "SRA ", "SRC ", "SRL ",   "STCR", "STST", "STWP", "SWPB", "SZC ", "SZCB",
	867	"ORI ", "RSET", "RTWP", "S   ", "SB  ", "SBO ", "SBZ ", "SETO", "SLA ", "SOC ",
	868	"SOCB", "SRA ", "SRC ", "SRL ", "STCR", "STST", "STWP", "SWPB", "SZC ", "SZCB",
869	869	"TB  ", "X   ", "XOP ", "XOR ", "*int"
870	870	};
871	871
r18983	r18984
1187	1187	{
1188	1188	m_clock_out_line(ASSERT_LINE);
1189	1189	m_clock_out_line(CLEAR_LINE);
1190		m_icount--;                     // This is the only location where we count down the cycles.
	1190	m_icount--;                         // This is the only location where we count down the cycles.
1191	1191	if (VERBOSE>7) LOG("tms9995: pulse_clock\n");
1192	1192	if (m_flag[0] == false && m_flag[1] == true) trigger_decrementer();
1193	1193	}
r18983	r18984
1309	1309	if (VERBOSE>7) LOG("tms9995: Checking interrupts ... NMI active\n");
1310	1310	m_int_pending |= PENDING_NMI;
1311	1311	m_idle_state = false;
1312		PC = (PC + 2) & 0xfffe;      // we have not prefetched the next instruction
	1312	PC = (PC + 2) & 0xfffe;     // we have not prefetched the next instruction
1313	1313	}
1314	1314	else
1315	1315	{
r18983	r18984
1327	1327	m_idle_state = false;
1328	1328	if (VERBOSE>7) LOG("tms9995: Interrupt occured, terminate IDLE state\n");
1329	1329	}
1330		PC = PC + 2;      // PC must be advanced (see flow chart), but no prefetch
	1330	PC = PC + 2;        // PC must be advanced (see flow chart), but no prefetch
1331	1331	if (VERBOSE>7) LOG("tms9995: Interrupts pending; no prefetch; advance PC to %04x\n", PC);
1332	1332	}
1333	1333	else
r18983	r18984
1362	1362	// Second pass for getting the instruction
1363	1363	if (VERBOSE>6) LOG("tms9995: Prefetch memory access (second pass)\n");
1364	1364	word_read();
1365		decode(m_current_value);         // This is for free; in reality it is in parallel with the next memory operation
1366		m_address = m_address_copy;      // restore m_address
1367		m_current_value = m_value_copy;   // restore m_current_value
1368		PC = (PC + 2) & 0xfffe;      // advance PC
	1365	decode(m_current_value);            // This is for free; in reality it is in parallel with the next memory operation
	1366	m_address = m_address_copy;     // restore m_address
	1367	m_current_value = m_value_copy; // restore m_current_value
	1368	PC = (PC + 2) & 0xfffe;     // advance PC
1369	1369	m_iaq_line(CLEAR_LINE);
1370	1370	if (VERBOSE>5) LOG("tms9995: ++++ Prefetch done ++++\n");
1371	1371	m_lowbyte = false;
r18983	r18984
1383	1383
1384	1384	if (VERBOSE>5) LOG("tms9995: **** Prefetching new instruction at %04x ****\n", PC);
1385	1385
1386		m_lowbyte = false;   // for mem_read
1387		word_read();         // this is where the clock pulses occur
	1386	m_lowbyte = false;  // for mem_read
	1387	word_read();            // this is where the clock pulses occur
1388	1388
1389	1389	if (!m_lowbyte)
1390	1390	{
1391	1391	// Only if we got the word in one pass
1392		decode(m_current_value);   // This is for free; in reality it is in parallel with the next memory operation
	1392	decode(m_current_value);    // This is for free; in reality it is in parallel with the next memory operation
1393	1393
1394		m_address = m_address_copy;         // restore m_address
1395		m_current_value = m_value_copy;      // restore m_current_value
1396		PC = (PC + 2) & 0xfffe;      // advance PC
	1394	m_address = m_address_copy;         // restore m_address
	1395	m_current_value = m_value_copy;     // restore m_current_value
	1396	PC = (PC + 2) & 0xfffe;     // advance PC
1397	1397
1398	1398	m_iaq_line(CLEAR_LINE);
1399	1399	}
r18983	r18984
1470	1470	if (m_reset)
1471	1471	{
1472	1472	vectorpos = 0;
1473		m_intmask = 0;   // clear interrupt mask
	1473	m_intmask = 0;  // clear interrupt mask
1474	1474
1475	1475	m_nmi_state = false;
1476	1476	m_hold_state = false;
r18983	r18984
1565	1565	}
1566	1566	MPC = 0;
1567	1567	m_first_cycle = m_icount;
1568		m_check_ready = false;      // set to default
	1568	m_check_ready = false;      // set to default
1569	1569	}
1570	1570
1571	1571	/*
r18983	r18984
2036	2036	m_regnumber = (ircopy & 0x000f);
2037	2037	m_address = (WP + (m_regnumber<<1)) & 0xffff;
2038	2038
2039		m_source_value = m_current_value;   // will be overwritten when reading the destination
2040		m_current_value = m_address;      // needed for first case
	2039	m_source_value = m_current_value;   // will be overwritten when reading the destination
	2040	m_current_value = m_address;        // needed for first case
2041	2041
2042		if (MPC==8)   // Symbolic
	2042	if (MPC==8) // Symbolic
2043	2043	{
2044	2044	if (m_regnumber != 0)
2045	2045	{
r18983	r18984
2057	2057	m_get_destination = true;
2058	2058	m_lowbyte = false;
2059	2059	m_address_add = 0;
2060		MPC--;      // will be increased in the mail loop
	2060	MPC--;      // will be increased in the mail loop
2061	2061	if (VERBOSE>8) LOG("tms9995: *** Operand address derivation; address=%04x; index=%d\n", m_address, MPC+1);
2062	2062	}
2063	2063
r18983	r18984
2067	2067	*/
2068	2068	void tms9995_device::increment_register()
2069	2069	{
2070		m_address_saved = m_current_value;   // need a special return so we do not lose the value
	2070	m_address_saved = m_current_value;  // need a special return so we do not lose the value
2071	2071	m_current_value += m_instruction->byteop? 1 : 2;
2072	2072	m_address = (WP + (m_regnumber<<1)) & 0xffff;
2073	2073	m_lowbyte = false;
r18983	r18984
2093	2093	// Need to determine the register address
2094	2094	m_address_saved = WP + ((m_instruction->IR & 0x000f)<<1);
2095	2095	m_address = PC;
2096		m_source_value = m_current_value;      // needed for AI, ANDI, ORI
	2096	m_source_value = m_current_value;       // needed for AI, ANDI, ORI
2097	2097	PC = (PC + 2) & 0xfffe;
2098	2098	m_lowbyte = false;
2099	2099	}
r18983	r18984
2238	2238	m_address = m_address - 2;
2239	2239	break;
2240	2240	case 2:
2241		m_current_value = m_value_copy;      // old WP
	2241	m_current_value = m_value_copy;     // old WP
2242	2242	m_address = m_address - 2;
2243	2243	break;
2244	2244	case 3:
r18983	r18984
2323	2323	// or equivalently, dividend / 0x10000 >= divisor
2324	2324
2325	2325	// Check overflow for unsigned DIV
2326		if (m_current_value < m_source_value)   // also if source=0
	2326	if (m_current_value < m_source_value)   // also if source=0
2327	2327	{
2328		MPC++;   // skip the abort
	2328	MPC++;  // skip the abort
2329	2329	overflow = false;
2330	2330	}
2331	2331	set_status_bit(ST_OV, overflow);
2332		m_value_copy = m_current_value;         // Save the high word
	2332	m_value_copy = m_current_value;         // Save the high word
2333	2333	m_address = m_address + 2;
2334	2334	break;
2335	2335	case 2:
r18983	r18984
2412	2412	// requires much less cycles when there is an overflow, so it seems as
2413	2413	// if this is tested before the algorithm starts.
2414	2414
2415		if ((w1 & 0x8000)==0)      // positive dividend
	2415	if ((w1 & 0x8000)==0)       // positive dividend
2416	2416	{
2417		if ((d & 0x8000)==0)   // positive divisor
	2417	if ((d & 0x8000)==0)    // positive divisor
2418	2418	{
2419		if ((d & 1)==0)      // even divisor
	2419	if ((d & 1)==0)     // even divisor
2420	2420	{
2421	2421	if (w1 < d/2) overflow = false;
2422	2422	}
2423		else            // odd divisor
	2423	else                // odd divisor
2424	2424	{
2425	2425	if ((w1 < (d-1)/2) || (w1 == (d-1)/2 && w2 < 0x8000)) overflow = false;
2426	2426	}
2427	2427	}
2428		else               // negative divisor
	2428	else                    // negative divisor
2429	2429	{
2430	2430	d = -d;
2431		if ((d & 1)==0)      // even divisor
	2431	if ((d & 1)==0)     // even divisor
2432	2432	{
2433	2433	if ((w1 < d/2) || (w1 == d/2 && w2 < d)) overflow = false;
2434	2434	}
2435		else            // odd divisor
	2435	else                // odd divisor
2436	2436	{
2437	2437	if ((w1 < (d+1)/2) || (w1 == (d+1)/2 && w2 < 0x8000+d)) overflow = false;
2438	2438	}
2439	2439	}
2440	2440	}
2441		else                  // negative dividend
	2441	else                        // negative dividend
2442	2442	{
2443	2443	w1 = -w1;
2444		if ((d & 0x8000)==0)   // positive divisor
	2444	if ((d & 0x8000)==0)    // positive divisor
2445	2445	{
2446		if ((d & 1)==0)      // even divisor
	2446	if ((d & 1)==0)     // even divisor
2447	2447	{
2448	2448	if ((w1 < d/2+1) || (w1 == d/2+1 && w2 > (-d))) overflow = false;
2449	2449	}
2450		else            // odd divisor
	2450	else                // odd divisor
2451	2451	{
2452	2452	if ((w1 < (d+1)/2) || (w1 == (d+1)/2 && w2 > 0x8000-d)) overflow = false;
2453	2453	}
2454	2454	}
2455		else               // negative divisor
	2455	else                    // negative divisor
2456	2456	{
2457	2457	d = -d;
2458		if ((d & 1)==0)      // even divisor
	2458	if ((d & 1)==0)     // even divisor
2459	2459	{
2460	2460	if ((w1 < d/2) || (w1 == d/2 && w2 > 0)) overflow = false;
2461	2461	}
2462		else            // odd divisor
	2462	else                // odd divisor
2463	2463	{
2464	2464	if ((w1 < (d+1)/2) || (w1 == (d+1)/2 && w2 > 0x8000)) overflow = false;
2465	2465	}
2466	2466	}
2467	2467	}
2468	2468	set_status_bit(ST_OV, overflow);
2469		if (!overflow) MPC++;      // Skip the next microinstruction when there is no overflow
	2469	if (!overflow) MPC++;       // Skip the next microinstruction when there is no overflow
2470	2470	break;
2471	2471	case 3:
2472	2472	// We are here because there was no overflow
2473		w = (m_value_copy << 16) |   m_current_value;
	2473	w = (m_value_copy << 16) |  m_current_value;
2474	2474	// Do the calculation
2475	2475	m_current_value =  (UINT16)(w / (INT16)m_source_value);
2476	2476	m_value_copy = (UINT16)(w % (INT16)m_source_value);
r18983	r18984
2627	2627	case JLT:   // LAECOP == x00xxx
2628	2628	cond = ((ST & (ST_AGT | ST_EQ))==0);
2629	2629	break;
2630		case JLE:   // LAECOP == 0xxxxx
	2630	case JLE:   // LAECOP == 0xxxxx
2631	2631	cond = ((ST & ST_LH)==0);
2632	2632	break;
2633		case JEQ:   // LAECOP == xx1xxx
	2633	case JEQ:   // LAECOP == xx1xxx
2634	2634	cond = ((ST & ST_EQ)!=0);
2635	2635	break;
2636		case JHE:   // LAECOP == 1x0xxx, 0x1xxx
	2636	case JHE:   // LAECOP == 1x0xxx, 0x1xxx
2637	2637	cond = ((ST & (ST_LH | ST_EQ)) != 0);
2638	2638	break;
2639		case JGT:   // LAECOP == x1xxxx
	2639	case JGT:   // LAECOP == x1xxxx
2640	2640	cond = ((ST & ST_AGT)!=0);
2641	2641	break;
2642		case JNE:   // LAECOP == xx0xxx
	2642	case JNE:   // LAECOP == xx0xxx
2643	2643	cond = ((ST & ST_EQ)==0);
2644	2644	break;
2645		case JNC:   // LAECOP == xxx0xx
	2645	case JNC:   // LAECOP == xxx0xx
2646	2646	cond = ((ST & ST_C)==0);
2647	2647	break;
2648		case JOC:   // LAECOP == xxx1xx
	2648	case JOC:   // LAECOP == xxx1xx
2649	2649	cond = ((ST & ST_C)!=0);
2650	2650	break;
2651		case JNO:   // LAECOP == xxxx0x
	2651	case JNO:   // LAECOP == xxxx0x
2652	2652	cond = ((ST & ST_OV)==0);
2653	2653	break;
2654		case JL:   // LAECOP == 0x0xxx
	2654	case JL:    // LAECOP == 0x0xxx
2655	2655	cond = ((ST & (ST_LH | ST_EQ)) == 0);
2656	2656	break;
2657		case JH:   // LAECOP == 1xxxxx
	2657	case JH:    // LAECOP == 1xxxxx
2658	2658	cond = ((ST & ST_LH)!=0);
2659	2659	break;
2660		case JOP:   // LAECOP == xxxxx1
	2660	case JOP:   // LAECOP == xxxxx1
2661	2661	cond = ((ST & ST_OP)!=0);
2662	2662	break;
2663	2663	}
r18983	r18984
2728	2728	{
2729	2729	ST = (ST & 0xfff0) | (m_current_value & 0x000f);
2730	2730	if (VERBOSE>7) LOG("tms9995: ST = %04x\n", ST);
2731		pulse_clock(1);      // needs one more than LWPI
	2731	pulse_clock(1);     // needs one more than LWPI
2732	2732	}
2733	2733	else
2734	2734	{
r18983	r18984
2847	2847	switch (m_instruction->state)
2848	2848	{
2849	2849	case 0:
2850		m_address = WP + 30;      // R15
	2850	m_address = WP + 30;        // R15
2851	2851	break;
2852	2852	case 1:
2853	2853	ST = m_current_value;
2854		m_address -= 2;            // R14
	2854	m_address -= 2;             // R14
2855	2855	break;
2856	2856	case 2:
2857	2857	PC = m_current_value;
2858		m_address -= 2;            // R13
	2858	m_address -= 2;             // R13
2859	2859	break;
2860	2860	case 3:
2861	2861	WP = m_current_value;
r18983	r18984
2956	2956	set_status_bit(ST_C, carry);
2957	2957	set_status_bit(ST_OV, overflow);
2958	2958	compare_and_set_lae(m_current_value, 0);
2959		m_address = m_address_saved;      // Register address
	2959	m_address = m_address_saved;        // Register address
2960	2960	if (VERBOSE>7) LOG("tms9995: ST = %04x (val=%04x)\n", ST, m_current_value);
2961	2961	break;
2962	2962	}
r18983	r18984
3049	3049	return;
3050	3050	}
3051	3051
3052		if (check_ov) set_status_bit(ST_OV, ((src_val & 0x8000)!=sign) && ((dest_new & 0x8000)==sign));
	3052	if (check_ov) set_status_bit(ST_OV, ((src_val & 0x8000)==sign) && ((dest_new & 0x8000)!=sign));
3053	3053	set_status_bit(ST_C, (dest_new & 0x10000) != 0);
3054	3054	m_current_value = dest_new & 0xffff;
3055	3055	compare_and_set_lae(m_current_value, 0);
r18983	r18984
3169	3169	break;
3170	3170	case 1:
3171	3171	// m_current_value is new WP
3172		m_value_copy = WP;   // store this for later
	3172	m_value_copy = WP;  // store this for later
3173	3173	WP = m_current_value;
3174	3174	m_address = WP + 0x0016; // Address of new R11
3175	3175	m_current_value = m_address_saved;
r18983	r18984
3215	3215	if (VERBOSE>7) LOG("tms9995: interrupt service (0): Prepare to read vector\n");
3216	3216	break;
3217	3217	case 1:
3218		pulse = 2;               // two cycles (with the one at the end)
3219		m_source_value = WP;      // old WP
3220		WP = m_current_value;      // new WP
	3218	pulse = 2;                  // two cycles (with the one at the end)
	3219	m_source_value = WP;        // old WP
	3220	WP = m_current_value;       // new WP
3221	3221	m_current_value = ST;
3222	3222	m_address = (WP + 30)&0xfffe;
3223	3223	if (VERBOSE>7) LOG("tms9995: interrupt service (1): Read new WP = %04x, save ST to %04x\n", WP, m_address);
r18983	r18984
3229	3229	break;
3230	3230	case 3:
3231	3231	m_address = (WP + 26)&0xfffe;
3232		m_current_value = m_source_value;   // old WP
	3232	m_current_value = m_source_value;   // old WP
3233	3233	if (VERBOSE>7) LOG("tms9995: interrupt service (3): Save WP to %04x\n", m_address);
3234	3234	break;
3235	3235	case 4:
r18983	r18984
3247	3247	m_int_pending &= ~PENDING_MID;
3248	3248	m_address = 0xfffc;
3249	3249	m_intmask = 0;
3250		MPC = 0;   // redo the interrupt service for the NMI
	3250	MPC = 0;    // redo the interrupt service for the NMI
3251	3251	}
3252	3252	else
3253	3253	{

trunk/src/emu/cpu/tms9900/tms9900.c

r18983	r18984
107	107	/* tms9900 ST register bits. */
108	108	enum
109	109	{
110		ST_LH = 0x8000,      // Logical higher (unsigned comparison)
111		ST_AGT = 0x4000,   // Arithmetical greater than (signed comparison)
112		ST_EQ = 0x2000,      // Equal
113		ST_C = 0x1000,      // Carry
114		ST_OV = 0x0800,      // Overflow (when using signed operations)
115		ST_OP = 0x0400,      // Odd parity (used with byte operations)
116		ST_X = 0x0200,      // XOP
117		ST_IM = 0x000f      // Interrupt mask
	110	ST_LH = 0x8000,     // Logical higher (unsigned comparison)
	111	ST_AGT = 0x4000,    // Arithmetical greater than (signed comparison)
	112	ST_EQ = 0x2000,     // Equal
	113	ST_C = 0x1000,      // Carry
	114	ST_OV = 0x0800,     // Overflow (when using signed operations)
	115	ST_OP = 0x0400,     // Odd parity (used with byte operations)
	116	ST_X = 0x0200,      // XOP
	117	ST_IM = 0x000f      // Interrupt mask
118	118	};
119	119
120	120	#define LOG logerror
r18983	r18984
128	128
129	129	tms99xx_device::tms99xx_device(const machine_config &mconfig, device_type type,  const char *name, const char *tag, int databus_width, int prg_addr_bits, int cru_addr_bits, device_t *owner, UINT32 clock)
130	130	: cpu_device(mconfig, type, name, tag, owner, clock),
131		m_program_config("program", ENDIANNESS_BIG, databus_width, prg_addr_bits),
132		m_io_config("cru", ENDIANNESS_BIG, 8, cru_addr_bits),
133		m_prgspace(NULL),
134		m_cru(NULL),
135		m_prgaddr_mask((1<<prg_addr_bits)-1),
136		m_cruaddr_mask((1<<cru_addr_bits)-1)
	131	m_program_config("program", ENDIANNESS_BIG, databus_width, prg_addr_bits),
	132	m_io_config("cru", ENDIANNESS_BIG, 8, cru_addr_bits),
	133	m_prgspace(NULL),
	134	m_cru(NULL),
	135	m_prgaddr_mask((1<<prg_addr_bits)-1),
	136	m_cruaddr_mask((1<<cru_addr_bits)-1)
137	137	{
138	138	}
139	139
r18983	r18984
167	167
168	168	// TODO: Restore state save feature
169	169
170		m_prgspace = &space(AS_PROGRAM);                  // dimemory.h
	170	m_prgspace = &space(AS_PROGRAM);                        // dimemory.h
171	171	m_cru = &space(AS_IO);
172	172
173	173	// Resolve our external connections
r18983	r18984
417	417	*/
418	418	MICROPROGRAM(data_derivation)
419	419	{
420		REG_READ, RET, 0, 0, 0, 0, 0, 0,                                    // Rx           (00)
	420	REG_READ, RET, 0, 0, 0, 0, 0, 0,                                                // Rx           (00)
421	421	0, 0, 0, 0, 0, 0, 0, 0,
422		REG_READ, ALU_SETADDR, MEMORY_READ, RET, 0, 0, 0, 0,                     // *Rx          (01)
	422	REG_READ, ALU_SETADDR, MEMORY_READ, RET, 0, 0, 0, 0,                            // *Rx          (01)
423	423	0, 0, 0, 0, 0, 0, 0, 0,
424		ALU_CLR, ALU_PCADDR_ADVANCE, MEMORY_READ, ALU_ADDREG, MEMORY_READ, RET, 0, 0,   // @sym         (10)
425		REG_READ, ALU_PCADDR_ADVANCE, MEMORY_READ, ALU_ADDREG, MEMORY_READ, RET, 0, 0,   // @sym(Rx)     (10)
426		REG_READ, ALU_SETADDR_ADDONE, ALU_ADDONE, REG_WRITE, MEMORY_READ, RET, 0, 0,   // *Rx+ (word)  (11)
427		REG_READ, ALU_SETADDR_ADDONE, REG_WRITE, MEMORY_READ, RET, 0, 0, 0            // *Rx+ (byte)  (11)
	424	ALU_CLR, ALU_PCADDR_ADVANCE, MEMORY_READ, ALU_ADDREG, MEMORY_READ, RET, 0, 0,   // @sym         (10)
	425	REG_READ, ALU_PCADDR_ADVANCE, MEMORY_READ, ALU_ADDREG, MEMORY_READ, RET, 0, 0,  // @sym(Rx)     (10)
	426	REG_READ, ALU_SETADDR_ADDONE, ALU_ADDONE, REG_WRITE, MEMORY_READ, RET, 0, 0,    // *Rx+ (word)  (11)
	427	REG_READ, ALU_SETADDR_ADDONE, REG_WRITE, MEMORY_READ, RET, 0, 0, 0              // *Rx+ (byte)  (11)
428	428	};
429	429
430	430	MICROPROGRAM(f1_mp)
431	431	{
432	432	ALU_NOP,
433	433	DATA_DERIVE,
434		ALU_SOURCE,         // Store the word
	434	ALU_SOURCE,         // Store the word
435	435	DATA_DERIVE,
436	436	ALU_F1,
437	437	MEMORY_WRITE,
r18983	r18984
445	445	ALU_SOURCE,
446	446	DATA_DERIVE,
447	447	ALU_COMP,
448		ALU_NOP,      // Compare operations do not write back any data
	448	ALU_NOP,        // Compare operations do not write back any data
449	449	END
450	450	};
451	451
r18983	r18984
454	454	ALU_NOP,
455	455	DATA_DERIVE,
456	456	ALU_F3,
457		MEMORY_READ,   // We have to distinguish this from the C/CB microprogram above
	457	MEMORY_READ,    // We have to distinguish this from the C/CB microprogram above
458	458	ALU_F3,
459		ALU_NOP,      // Compare operations do not write back any data
	459	ALU_NOP,        // Compare operations do not write back any data
460	460	END
461	461	};
462	462
r18983	r18984
467	467	ALU_F3,
468	468	MEMORY_READ,
469	469	ALU_F3,
470		MEMORY_WRITE,   // XOR again must write back data, cannot reuse f3_mp
	470	MEMORY_WRITE,   // XOR again must write back data, cannot reuse f3_mp
471	471	END
472	472	};
473	473
r18983	r18984
475	475	{
476	476	ALU_NOP,
477	477	DATA_DERIVE,
478		ALU_MPY,      // Save the value; put register number in m_regnumber
	478	ALU_MPY,        // Save the value; put register number in m_regnumber
479	479	MEMORY_READ,
480		ALU_MPY,      // 18 cycles for multiplication
481		MEMORY_WRITE,      // Write the high word
482		ALU_MPY,      // Get low word, increase m_address
	480	ALU_MPY,        // 18 cycles for multiplication
	481	MEMORY_WRITE,       // Write the high word
	482	ALU_MPY,        // Get low word, increase m_address
483	483	MEMORY_WRITE,
484	484	END
485	485	};
r18983	r18984
487	487	MICROPROGRAM(div_mp)
488	488	{
489	489	ALU_NOP,
490		DATA_DERIVE,   // Get divisor
491		ALU_DIV,      // 0 Store divisor and get register number
492		MEMORY_READ,   // Read register
493		ALU_DIV,      // 1 Check overflow, increase address (or abort here)
	490	DATA_DERIVE,    // Get divisor
	491	ALU_DIV,        // 0 Store divisor and get register number
	492	MEMORY_READ,    // Read register
	493	ALU_DIV,        // 1 Check overflow, increase address (or abort here)
494	494	ABORT,
495		MEMORY_READ,   // Read subsequent word (if reg=15 this is behind the workspace)
496		ALU_DIV,      // 2 Calculate quotient (takes variable amount of cycles; at least 32 machine cycles), set register number
497		MEMORY_WRITE,   // Write quotient into register
498		ALU_DIV,      // 3 Get remainder
499		MEMORY_WRITE,   // Write remainder
	495	MEMORY_READ,    // Read subsequent word (if reg=15 this is behind the workspace)
	496	ALU_DIV,        // 2 Calculate quotient (takes variable amount of cycles; at least 32 machine cycles), set register number
	497	MEMORY_WRITE,   // Write quotient into register
	498	ALU_DIV,        // 3 Get remainder
	499	MEMORY_WRITE,   // Write remainder
500	500	END
501	501	};
502	502
503	503	MICROPROGRAM(xop_mp)
504	504	{
505	505	ALU_NOP,
506		DATA_DERIVE,   // Get argument
507		ALU_XOP,      // 0 Save the address of the source operand, set address = 0x0040 + xopNr*4
508		MEMORY_READ,   // Read the new WP
509		ALU_XOP,      // 1 Save old WP, set new WP, get the source operand address
510		MEMORY_WRITE,   // Write the address of the source operand into the new R11
511		ALU_XOP,      // 2
512		MEMORY_WRITE,   // Write the ST into the new R15
513		ALU_XOP,      // 3
514		MEMORY_WRITE,   // Write the PC into the new R14
515		ALU_XOP,      // 4
516		MEMORY_WRITE,   // Write the WP into the new R13
517		ALU_XOP,      // 5 Set the X bit in the ST
518		MEMORY_READ,   // Read the new PC
519		ALU_XOP,      // 6 Set the new PC
	506	DATA_DERIVE,    // Get argument
	507	ALU_XOP,        // 0 Save the address of the source operand, set address = 0x0040 + xopNr*4
	508	MEMORY_READ,    // Read the new WP
	509	ALU_XOP,        // 1 Save old WP, set new WP, get the source operand address
	510	MEMORY_WRITE,   // Write the address of the source operand into the new R11
	511	ALU_XOP,        // 2
	512	MEMORY_WRITE,   // Write the ST into the new R15
	513	ALU_XOP,        // 3
	514	MEMORY_WRITE,   // Write the PC into the new R14
	515	ALU_XOP,        // 4
	516	MEMORY_WRITE,   // Write the WP into the new R13
	517	ALU_XOP,        // 5 Set the X bit in the ST
	518	MEMORY_READ,    // Read the new PC
	519	ALU_XOP,        // 6 Set the new PC
520	520	ALU_NOP,
521	521	END
522	522	};
r18983	r18984
534	534	{
535	535	ALU_NOP,
536	536	DATA_DERIVE,
537		ALU_ABS,      // two cycles
538		MEMORY_WRITE,   // skipped when ABS is not performed
	537	ALU_ABS,        // two cycles
	538	MEMORY_WRITE,   // skipped when ABS is not performed
539	539	ALU_NOP,
540	540	END
541	541	};
r18983	r18984
548	548	END
549	549	};
550	550
551		MICROPROGRAM(b_mp)      // Branch
	551	MICROPROGRAM(b_mp)      // Branch
552	552	{
553	553	ALU_NOP,
554	554	DATA_DERIVE,
r18983	r18984
556	556	END
557	557	};
558	558
559		MICROPROGRAM(bl_mp)      // Branch and Link
	559	MICROPROGRAM(bl_mp)     // Branch and Link
560	560	{
561	561	ALU_NOP,
562	562	DATA_DERIVE,
r18983	r18984
566	566	END
567	567	};
568	568
569		MICROPROGRAM(blwp_mp)      // Branch and Load WP
	569	MICROPROGRAM(blwp_mp)       // Branch and Load WP
570	570	{
571	571	ALU_NOP,
572		DATA_DERIVE,         // Get argument
573		ALU_BLWP,            // 0 Save old WP, set new WP, save position
574		MEMORY_WRITE,         // write ST to R15
575		ALU_BLWP,            // 1
576		MEMORY_WRITE,         // write PC to R14
577		ALU_BLWP,            // 2
578		MEMORY_WRITE,         // write WP to R13
579		ALU_BLWP,            // 3 Get saved position
580		MEMORY_READ,         // Read new PC
581		ALU_BLWP,            // 4 Set new PC
	572	DATA_DERIVE,            // Get argument
	573	ALU_BLWP,               // 0 Save old WP, set new WP, save position
	574	MEMORY_WRITE,           // write ST to R15
	575	ALU_BLWP,               // 1
	576	MEMORY_WRITE,           // write PC to R14
	577	ALU_BLWP,               // 2
	578	MEMORY_WRITE,           // write WP to R13
	579	ALU_BLWP,               // 3 Get saved position
	580	MEMORY_READ,            // Read new PC
	581	ALU_BLWP,               // 4 Set new PC
582	582	END
583	583	};
584	584
r18983	r18984
600	600	{
601	601	ALU_NOP,
602	602	DATA_DERIVE,
603		ALU_SOURCE,         // Store address and value
604		ALU_STCR,         // 0 Set register_number = 12
	603	ALU_SOURCE,         // Store address and value
	604	ALU_STCR,           // 0 Set register_number = 12
605	605	MEMORY_READ,
606		ALU_STCR,         // 1 Prepare CRU access
	606	ALU_STCR,           // 1 Prepare CRU access
607	607	CRU_INPUT,
608		ALU_STCR,         // 2 Create result; Cycles = 5 + (8-#C-1) or + (16-#C)
	608	ALU_STCR,           // 2 Create result; Cycles = 5 + (8-#C-1) or + (16-#C)
609	609	MEMORY_WRITE,
610	610	END
611	611	};
r18983	r18984
675	675	{
676	676	ALU_IMM,
677	677	MEMORY_READ,
678		ALU_LI,            // sets status bits
679		ALU_REG,         // set register number
	678	ALU_LI,             // sets status bits
	679	ALU_REG,            // set register number
680	680	MEMORY_WRITE,
681	681	END
682	682	};
r18983	r18984
686	686	ALU_IMM,
687	687	MEMORY_READ,
688	688	ALU_NOP,
689		ALU_LWPI,            // sets WP
	689	ALU_LWPI,               // sets WP
690	690	END
691	691	};
692	692
r18983	r18984
695	695	ALU_IMM,
696	696	MEMORY_READ,
697	697	ALU_NOP,
698		ALU_LIMI,            // sets interrupt mask in ST
	698	ALU_LIMI,               // sets interrupt mask in ST
699	699	ALU_NOP,
700	700	ALU_NOP,
701	701	END
r18983	r18984
715	715	END
716	716	};
717	717
718		MICROPROGRAM(rtwp_mp)      // Problem: This makes RTWP use 8 instead of 7 machine cycles.
	718	MICROPROGRAM(rtwp_mp)       // Problem: This makes RTWP use 8 instead of 7 machine cycles.
719	719	{
720	720	ALU_RTWP,
721	721	MEMORY_READ,
r18983	r18984
730	730	MICROPROGRAM(int_mp)
731	731	{
732	732	ALU_NOP,
733		ALU_INT,            // 0 Set address = 0
	733	ALU_INT,                // 0 Set address = 0
734	734	MEMORY_READ,
735		ALU_INT,            // 1 Save old WP, set new WP, save position
736		MEMORY_WRITE,         // write ST to R15
737		ALU_INT,            // 2
738		MEMORY_WRITE,         // write PC to R14
739		ALU_INT,            // 3
740		MEMORY_WRITE,         // write WP to R13
741		ALU_INT,            // 4 Get saved position
742		MEMORY_READ,         // Read new PC
743		ALU_INT,            // 5 Set new PC
	735	ALU_INT,                // 1 Save old WP, set new WP, save position
	736	MEMORY_WRITE,           // write ST to R15
	737	ALU_INT,                // 2
	738	MEMORY_WRITE,           // write PC to R14
	739	ALU_INT,                // 3
	740	MEMORY_WRITE,           // write WP to R13
	741	ALU_INT,                // 4 Get saved position
	742	MEMORY_READ,            // Read new PC
	743	ALU_INT,                // 5 Set new PC
744	744	END
745	745	};
746	746
r18983	r18984
1246	1246	{
1247	1247	m_clock_out_line(ASSERT_LINE);
1248	1248	m_clock_out_line(CLEAR_LINE);
1249		m_icount--;                     // This is the only location where we count down the cycles.
	1249	m_icount--;                         // This is the only location where we count down the cycles.
1250	1250	if (VERBOSE>7) LOG("tms99xx: pulse_clock\n");
1251	1251	}
1252	1252	}
r18983	r18984
1455	1455	// Read 8 bits (containing the desired bits)
1456	1456	value = m_cru->read_byte(location);
1457	1457
1458		if ((offset + m_count) > 8)   // spans two 8 bit cluster
	1458	if ((offset + m_count) > 8) // spans two 8 bit cluster
1459	1459	{
1460	1460	// Read next 8 bits
1461	1461	location = (location + 1) & (m_cruaddr_mask>>3);
1462	1462	value1 = m_cru->read_byte(location);
1463	1463	value |= (value1 << 8);
1464	1464
1465		if ((offset + m_count) > 16)   // spans three 8 bit cluster
	1465	if ((offset + m_count) > 16)    // spans three 8 bit cluster
1466	1466	{
1467	1467	// Read next 8 bits
1468	1468	location = (location + 1) & (m_cruaddr_mask>>3);
r18983	r18984
1543	1543	m_program = (UINT8*)data_derivation;
1544	1544	MPC = ircopy & 0x0030;
1545	1545
1546		if (((MPC == 0x0020) && (m_regnumber != 0))         // indexed
1547		|| ((MPC == 0x0030) && m_byteop))      // byte operation
	1546	if (((MPC == 0x0020) && (m_regnumber != 0))         // indexed
	1547	|| ((MPC == 0x0030) && m_byteop))       // byte operation
1548	1548	{
1549		MPC += 8;   // the second option
	1549	MPC += 8;   // the second option
1550	1550	}
1551		m_get_destination = true;   // when we call this the second time before END it's the destination
	1551	m_get_destination = true;   // when we call this the second time before END it's the destination
1552	1552	m_pass = 2;
1553	1553	}
1554	1554
r18983	r18984
1668	1668	// Save the destination value
1669	1669	UINT16 prev_dest_value = m_current_value;
1670	1670
1671		m_destination_even = ((m_address & 1)==0);   // this is the destination address; the source address has already been saved
	1671	m_destination_even = ((m_address & 1)==0);  // this is the destination address; the source address has already been saved
1672	1672	bool byteop = byte_operation();
1673	1673
1674	1674	if (byteop)
r18983	r18984
1775	1775
1776	1776	void tms99xx_device::alu_comp()
1777	1777	{
1778		m_destination_even = ((m_address & 1)==0);   // this is the destination address; the source address has already been saved
	1778	m_destination_even = ((m_address & 1)==0);  // this is the destination address; the source address has already been saved
1779	1779	if (byte_operation())
1780	1780	{
1781	1781	if (!m_destination_even) m_current_value <<= 8;
r18983	r18984
1840	1840	result = (m_source_value & 0x0000ffff) * (m_current_value & 0x0000ffff);
1841	1841	m_current_value = (result >> 16) & 0xffff;
1842	1842	m_value_copy = result & 0xffff;
1843		pulse_clock(34);                        // add 36 clock cycles (18 machine cycles); last one in main loop
	1843	pulse_clock(34);                                // add 36 clock cycles (18 machine cycles); last one in main loop
1844	1844	break;
1845	1845	case 2: // After writing the high word to the destination register
1846		m_current_value = m_value_copy;                  // Prepare to save low word
	1846	m_current_value = m_value_copy;                     // Prepare to save low word
1847	1847	m_address = (m_address + 2) & m_prgaddr_mask;
1848	1848	break;
1849	1849	}
r18983	r18984
1861	1861	switch (m_state)
1862	1862	{
1863	1863	case 0:
1864		m_source_value = m_current_value;   // store divisor
	1864	m_source_value = m_current_value;   // store divisor
1865	1865	// Set address of register
1866	1866	m_address = WP + ((IR >> 5) & 0x001e);
1867	1867	m_address_copy = m_address;
r18983	r18984
1871	1871	// This is the case when the dividend / divisor >= 0x10000,
1872	1872	// or equivalently, dividend / 0x10000 >= divisor
1873	1873
1874		if (m_current_value < m_source_value)   // also if source=0
	1874	if (m_current_value < m_source_value)   // also if source=0
1875	1875	{
1876		MPC++;   // skip the abort
	1876	MPC++;  // skip the abort
1877	1877	overflow = false;
1878	1878	}
1879	1879	set_status_bit(ST_OV, overflow);
1880		m_value_copy = m_current_value;         // Save the high word
1881		m_address = (m_address + 2) & m_prgaddr_mask;      // Read next word
	1880	m_value_copy = m_current_value;         // Save the high word
	1881	m_address = (m_address + 2) & m_prgaddr_mask;       // Read next word
1882	1882	break;
1883	1883	case 2:
1884	1884	// W2 is in m_current_value
r18983	r18984
1901	1901	// we need as many cycles as it takes to
1902	1902	// shift away the dividend. Thus, bigger dividends need more cycles.
1903	1903
1904		pulse_clock(62);   // one pulse is at the start, one at the end
	1904	pulse_clock(62);    // one pulse is at the start, one at the end
1905	1905	value1 = m_value_copy & 0xffff;
1906	1906
1907	1907	while (value1 != 0)
r18983	r18984
1935	1935	m_address = 0x0040 + ((IR >> 4) & 0x003c);
1936	1936	break;
1937	1937	case 1:
1938		m_value_copy = WP;                  // save the old WP
1939		WP = m_current_value & m_prgaddr_mask;   // the new WP has been read in the previous microoperation
1940		m_current_value = m_address_saved;      // we saved the address of the source operand; retrieve it
1941		m_address = WP + 0x0016;            // Next register is R11
	1938	m_value_copy = WP;                      // save the old WP
	1939	WP = m_current_value & m_prgaddr_mask;  // the new WP has been read in the previous microoperation
	1940	m_current_value = m_address_saved;      // we saved the address of the source operand; retrieve it
	1941	m_address = WP + 0x0016;                // Next register is R11
1942	1942	break;
1943	1943	case 2:
1944	1944	m_address = WP + 0x001e;
r18983	r18984
1950	1950	break;
1951	1951	case 4:
1952	1952	m_address = WP + 0x001a;
1953		m_current_value = m_value_copy;         // old WP into new R13
	1953	m_current_value = m_value_copy;         // old WP into new R13
1954	1954	break;
1955	1955	case 5:
1956		m_address =  0x0042 + ((IR >> 4) & 0x003c);      // location of new PC
	1956	m_address =  0x0042 + ((IR >> 4) & 0x003c);     // location of new PC
1957	1957	set_status_bit(ST_X, true);
1958	1958	break;
1959	1959	case 6:
r18983	r18984
2030	2030
2031	2031	if (setstatus)
2032	2032	{
2033		if (check_ov) set_status_bit(ST_OV, ((src_val & 0x8000)!=sign) && ((dest_new & 0x8000)==sign));
	2033	if (check_ov) set_status_bit(ST_OV, ((src_val & 0x8000)==sign) && ((dest_new & 0x8000)!=sign));
2034	2034	set_status_bit(ST_C, (dest_new & 0x10000) != 0);
2035	2035	m_current_value = dest_new & 0xffff;
2036	2036	compare_and_set_lae(m_current_value, 0);
r18983	r18984
2052	2052	if ((m_current_value & 0x8000)!=0)
2053	2053	{
2054	2054	m_current_value = (((~m_current_value) & 0x0000ffff) + 1) & 0xffff;
2055		pulse_clock(2);      // If ABS is performed it takes one machine cycle more
	2055	pulse_clock(2);     // If ABS is performed it takes one machine cycle more
2056	2056	}
2057	2057	else
2058	2058	{
r18983	r18984
2093	2093	{
2094	2094	case 0:
2095	2095	m_value_copy = WP;
2096		WP = m_current_value & m_prgaddr_mask;            // set new WP (*m_destination)
2097		m_address_saved = (m_address + 2) & m_prgaddr_mask;   // Save the location of the WP
	2096	WP = m_current_value & m_prgaddr_mask;              // set new WP (*m_destination)
	2097	m_address_saved = (m_address + 2) & m_prgaddr_mask; // Save the location of the WP
2098	2098	m_address = WP + 30;
2099		m_current_value = ST;                     // get status register
	2099	m_current_value = ST;                           // get status register
2100	2100	break;
2101	2101	case 1:
2102		m_current_value = PC;                     // get program counter
	2102	m_current_value = PC;                           // get program counter
2103	2103	m_address = m_address - 2;
2104	2104	break;
2105	2105	case 2:
2106		m_current_value = m_value_copy;               // retrieve the old WP
	2106	m_current_value = m_value_copy;                 // retrieve the old WP
2107	2107	m_address = m_address - 2;
2108	2108	break;
2109	2109	case 3:
2110		m_address = m_address_saved;               // point to PC component of branch vector
	2110	m_address = m_address_saved;                    // point to PC component of branch vector
2111	2111	break;
2112	2112	case 4:
2113	2113	PC = m_current_value & m_prgaddr_mask;
r18983	r18984
2138	2138	}
2139	2139	else
2140	2140	{
2141		value = m_source_value;   // copied by ALU_SOURCE
	2141	value = m_source_value; // copied by ALU_SOURCE
2142	2142	m_count = (IR >> 6) & 0x000f;
2143	2143	if (m_count == 0) m_count = 16;
2144	2144	if (m_count <= 8)
r18983	r18984
2264	2264	case JLT:   // LAECOP == x00xxx
2265	2265	cond = ((ST & (ST_AGT | ST_EQ))==0);
2266	2266	break;
2267		case JLE:   // LAECOP == 0xxxxx
	2267	case JLE:   // LAECOP == 0xxxxx
2268	2268	cond = ((ST & ST_LH)==0);
2269	2269	break;
2270		case JEQ:   // LAECOP == xx1xxx
	2270	case JEQ:   // LAECOP == xx1xxx
2271	2271	cond = ((ST & ST_EQ)!=0);
2272	2272	break;
2273		case JHE:   // LAECOP == 1x0xxx, 0x1xxx
	2273	case JHE:   // LAECOP == 1x0xxx, 0x1xxx
2274	2274	cond = ((ST & (ST_LH | ST_EQ)) != 0);
2275	2275	break;
2276		case JGT:   // LAECOP == x1xxxx
	2276	case JGT:   // LAECOP == x1xxxx
2277	2277	cond = ((ST & ST_AGT)!=0);
2278	2278	break;
2279		case JNE:   // LAECOP == xx0xxx
	2279	case JNE:   // LAECOP == xx0xxx
2280	2280	cond = ((ST & ST_EQ)==0);
2281	2281	break;
2282		case JNC:   // LAECOP == xxx0xx
	2282	case JNC:   // LAECOP == xxx0xx
2283	2283	cond = ((ST & ST_C)==0);
2284	2284	break;
2285		case JOC:   // LAECOP == xxx1xx
	2285	case JOC:   // LAECOP == xxx1xx
2286	2286	cond = ((ST & ST_C)!=0);
2287	2287	break;
2288		case JNO:   // LAECOP == xxxx0x
	2288	case JNO:   // LAECOP == xxxx0x
2289	2289	cond = ((ST & ST_OV)==0);
2290	2290	break;
2291		case JL:   // LAECOP == 0x0xxx
	2291	case JL:    // LAECOP == 0x0xxx
2292	2292	cond = ((ST & (ST_LH | ST_EQ)) == 0);
2293	2293	break;
2294		case JH:   // LAECOP == 1xxxxx
	2294	case JH:    // LAECOP == 1xxxxx
2295	2295	cond = ((ST & ST_LH)!=0);
2296	2296	break;
2297		case JOP:   // LAECOP == xxxxx1
	2297	case JOP:   // LAECOP == xxxxx1
2298	2298	cond = ((ST & ST_OP)!=0);
2299	2299	break;
2300	2300	}
r18983	r18984
2302	2302	if (!cond)
2303	2303	{
2304	2304	if (VERBOSE>7) LOG("tms99xx: Jump condition false\n");
2305		MPC+=1;   // skip next ALU call
	2305	MPC+=1; // skip next ALU call
2306	2306	}
2307	2307	else
2308	2308	if (VERBOSE>7) LOG("tms99xx: Jump condition true\n");
r18983	r18984
2385	2385	set_status_bit(ST_C, carry);
2386	2386	set_status_bit(ST_OV, overflow);
2387	2387	compare_and_set_lae(m_current_value, 0);
2388		m_address = m_address_saved;      // Register address
	2388	m_address = m_address_saved;        // Register address
2389	2389	if (VERBOSE>7) LOG("tms99xx: ST = %04x (val=%04x)\n", ST, m_current_value);
2390	2390	break;
2391	2391	}
r18983	r18984
2473	2473	switch (m_state)
2474	2474	{
2475	2475	case 0:
2476		m_address = WP + 30;      // R15
	2476	m_address = WP + 30;        // R15
2477	2477	break;
2478	2478	case 1:
2479	2479	ST = m_current_value;
2480		m_address -= 2;            // R14
	2480	m_address -= 2;             // R14
2481	2481	break;
2482	2482	case 2:
2483	2483	PC = m_current_value & m_prgaddr_mask;
2484		m_address -= 2;            // R13
	2484	m_address -= 2;             // R13
2485	2485	break;
2486	2486	case 3:
2487	2487	WP = m_current_value & m_prgaddr_mask;
r18983	r18984
2514	2514	break;
2515	2515	case 1:
2516	2516	m_address_copy = m_address;
2517		m_value_copy = WP;                     // old WP
2518		WP = m_current_value & m_prgaddr_mask;      // new WP
	2517	m_value_copy = WP;                          // old WP
	2518	WP = m_current_value & m_prgaddr_mask;      // new WP
2519	2519	m_current_value = ST;
2520	2520	m_address = (WP + 30) & m_prgaddr_mask;
2521	2521	break;
r18983	r18984
2524	2524	m_address = (WP + 28) & m_prgaddr_mask;
2525	2525	break;
2526	2526	case 3:
2527		m_current_value = m_value_copy;   // old WP
	2527	m_current_value = m_value_copy; // old WP
2528	2528	m_address = (WP + 26) & m_prgaddr_mask;
2529	2529	break;
2530	2530	case 4:

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