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r18806 Thursday 1st November, 2012 at 22:12:41 UTC by hap
added textlayer palettebase and bgcolor
[src/mame/drivers]namcos23.c

trunk/src/mame/drivers/namcos23.c
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13131313   int scanline;
13141314};
13151315
1316struct c404_t
1317{
1318   rgb_t bgcolor;
1319   UINT16 palbase;
1320   UINT8 layer;
1321};
1322
13161323struct render_t
13171324{
13181325   poly_manager *polymgr;
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13351342        m_rtc(*this, "rtc"),
13361343      m_mainram(*this, "mainram"),
13371344      m_shared_ram(*this, "shared_ram"),
1345      m_gammaram(*this, "gammaram"),
13381346      m_charram(*this, "charram"),
13391347      m_textram(*this, "textram"),
13401348      m_czattr(*this, "czattr"),
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13481356    required_device<rtc4543_device> m_rtc;
13491357   required_shared_ptr<UINT32> m_mainram;
13501358   required_shared_ptr<UINT32> m_shared_ram;
1359   required_shared_ptr<UINT32> m_gammaram;
13511360   required_shared_ptr<UINT32> m_charram;
13521361   required_shared_ptr<UINT32> m_textram;
13531362   optional_shared_ptr<UINT32> m_czattr;
13541363   optional_device<cpu_device> m_gmen_sh2;
13551364   optional_shared_ptr<UINT32> m_gmen_sh2_shared;
13561365
1366   c404_t m_c404;
13571367   c361_t m_c361;
13581368   c417_t m_c417;
13591369   c412_t m_c412;
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14091419   UINT8 m_s23_tssio_port_4;
14101420
14111421   void update_main_interrupts(UINT32 cause);
1422   void update_mixer();
14121423
14131424   DECLARE_WRITE32_MEMBER(namcos23_textram_w);
14141425   DECLARE_WRITE32_MEMBER(s23_txtchar_w);
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14701481};
14711482
14721483
1484static UINT8 nthbyte(const UINT32 *pSource, int offs)
1485{
1486   pSource += offs/4;
1487   return (pSource[0]<<((offs&3)*8))>>24;
1488}
1489
1490static UINT16 nthword(const UINT32 *pSource, int offs)
1491{
1492   pSource += offs/2;
1493   return (pSource[0]<<((offs&1)*16))>>16;
1494}
1495
1496
14731497void namcos23_state::update_main_interrupts(UINT32 cause)
14741498{
14751499   UINT32 changed = cause ^ m_main_irqcause;
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14981522   // level 6: C450
14991523}
15001524
1501static UINT16 nthword( const UINT32 *pSource, int offs )
1502{
1503   pSource += offs/2;
1504   return (pSource[0]<<((offs&1)*16))>>16;
1505}
15061525
15071526TILE_GET_INFO_MEMBER(namcos23_state::TextTilemapGetInfo)
15081527{
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15121531    * ----.xx--.----.---- flip
15131532    * ----.--xx.xxxx.xxxx code
15141533    */
1515   SET_TILE_INFO_MEMBER( 0, data&0x03ff, data>>12, TILE_FLIPYX((data&0x0c00)>>10) );
1516} /* TextTilemapGetInfo */
1534   SET_TILE_INFO_MEMBER(0, data&0x03ff, data>>12, TILE_FLIPYX((data&0x0c00)>>10));
1535}
15171536
15181537WRITE32_MEMBER(namcos23_state::namcos23_textram_w)
15191538{
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15281547   machine().gfx[0]->mark_dirty(offset/32);
15291548}
15301549
1531static UINT8 nthbyte( const UINT32 *pSource, int offs )
1550WRITE32_MEMBER(namcos23_state::namcos23_paletteram_w)
15321551{
1533   pSource += offs/4;
1534   return (pSource[0]<<((offs&3)*8))>>24;
1535}
1552   COMBINE_DATA(&m_generic_paletteram_32[offset]);
15361553
1537INLINE void UpdatePalette( running_machine &machine, int entry )
1538{
1539   namcos23_state *state = machine.driver_data<namcos23_state>();
1540   int j;
1541
1542   for( j=0; j<2; j++ )
1554   // each LONGWORD is 2 colors, each OFFSET is 2 colors
1555   for (int i = 0; i < 2; i++)
15431556   {
1544      int which = (entry*2)+(j*2);
1545      int r = nthbyte(state->m_generic_paletteram_32, which+0x00001);
1546      int g = nthbyte(state->m_generic_paletteram_32, which+0x10001);
1547      int b = nthbyte(state->m_generic_paletteram_32, which+0x20001);
1548      palette_set_color( machine, which/2, MAKE_RGB(r,g,b) );
1557      int which = (offset << 2 | i << 1) & 0xfffe;
1558      int r = nthbyte(m_generic_paletteram_32, which|0x00001);
1559      int g = nthbyte(m_generic_paletteram_32, which|0x10001);
1560      int b = nthbyte(m_generic_paletteram_32, which|0x20001);
1561      palette_set_color(machine(), which/2, MAKE_RGB(r,g,b));
15491562   }
15501563}
15511564
1552/* each LONGWORD is 2 colors.  each OFFSET is 2 colors */
1553
1554WRITE32_MEMBER(namcos23_state::namcos23_paletteram_w)
1555{
1556   COMBINE_DATA( &m_generic_paletteram_32[offset] );
1557
1558   UpdatePalette(machine(), (offset % (0x10000/4))*2);
1559}
1560
15611565READ16_MEMBER(namcos23_state::s23_c417_r)
15621566{
1563   c417_t &c417 = m_c417;
1564
15651567   switch (offset)
15661568   {
15671569      /* According to timecrs2c, +0 is the status word with bits being:
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15811583      case 0:
15821584         return 0x8e | (machine().primary_screen->vblank() ? 0x0000 : 0x8000);
15831585      case 1:
1584         return c417.adr;
1586         return m_c417.adr;
15851587      case 4:
15861588         //logerror("c417_r %04x = %04x (%08x, %08x)\n", c417.adr, c417.ram[c417.adr], space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1587         return c417.ram[c417.adr];
1589         return m_c417.ram[m_c417.adr];
15881590      case 5:
1589         if(c417.pointrom_adr >= m_ptrom_limit)
1591         if (m_c417.pointrom_adr >= m_ptrom_limit)
15901592            return 0xffff;
1591         return m_ptrom[c417.pointrom_adr] >> 16;
1593         return m_ptrom[m_c417.pointrom_adr] >> 16;
15921594      case 6:
1593         if(c417.pointrom_adr >= m_ptrom_limit)
1595         if (m_c417.pointrom_adr >= m_ptrom_limit)
15941596            return 0xffff;
1595         return m_ptrom[c417.pointrom_adr];
1597         return m_ptrom[m_c417.pointrom_adr];
15961598   }
15971599
15981600   logerror("c417_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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16011603
16021604WRITE16_MEMBER(namcos23_state::s23_c417_w)
16031605{
1604   c417_t &c417 = m_c417;
1605
1606   switch(offset)
1606   switch (offset)
16071607   {
16081608      case 0:
16091609         logerror("p3d PIO %04x\n", data);
16101610         break;
16111611      case 1:
1612         COMBINE_DATA(&c417.adr);
1612         COMBINE_DATA(&m_c417.adr);
16131613         break;
16141614      case 2:
1615         c417.pointrom_adr = (c417.pointrom_adr << 16) | data;
1615         m_c417.pointrom_adr = (m_c417.pointrom_adr << 16) | data;
16161616         break;
16171617      case 3:
1618         c417.pointrom_adr = 0;
1618         m_c417.pointrom_adr = 0;
16191619         break;
16201620      case 4:
16211621         //logerror("c417_w %04x = %04x (%08x, %08x)\n", c417.adr, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1622         COMBINE_DATA(c417.ram + c417.adr);
1622         COMBINE_DATA(m_c417.ram + m_c417.adr);
16231623         break;
16241624      case 7:
16251625         logerror("c417_w: ack IRQ 2 (%x)\n", data);
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16331633
16341634READ16_MEMBER(namcos23_state::s23_c412_ram_r)
16351635{
1636   c412_t &c412 = m_c412;
1637
16381636   //  logerror("c412_ram_r %06x (%08x, %08x)\n", offset, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
16391637   if(offset < 0x100000)
1640      return c412.sdram_a[offset & 0xfffff];
1638      return m_c412.sdram_a[offset & 0xfffff];
16411639   else if(offset < 0x200000)
1642      return c412.sdram_b[offset & 0xfffff];
1640      return m_c412.sdram_b[offset & 0xfffff];
16431641   else if(offset < 0x220000)
1644      return c412.sram   [offset & 0x1ffff];
1642      return m_c412.sram   [offset & 0x1ffff];
16451643   else if(offset < 0x220200)
1646      return c412.pczram [offset & 0x001ff];
1644      return m_c412.pczram [offset & 0x001ff];
16471645
16481646   return 0xffff;
16491647}
16501648
16511649WRITE16_MEMBER(namcos23_state::s23_c412_ram_w)
16521650{
1653   c412_t &c412 = m_c412;
1654
16551651   //  logerror("c412_ram_w %06x = %04x (%08x, %08x)\n", offset, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
16561652   if(offset < 0x100000)
1657      COMBINE_DATA(c412.sdram_a + (offset & 0xfffff));
1653      COMBINE_DATA(m_c412.sdram_a + (offset & 0xfffff));
16581654   else if(offset < 0x200000)
1659      COMBINE_DATA(c412.sdram_b + (offset & 0xfffff));
1655      COMBINE_DATA(m_c412.sdram_b + (offset & 0xfffff));
16601656   else if(offset < 0x220000)
1661      COMBINE_DATA(c412.sram    + (offset & 0x1ffff));
1657      COMBINE_DATA(m_c412.sram    + (offset & 0x1ffff));
16621658   else if(offset < 0x220200)
1663      COMBINE_DATA(c412.pczram  + (offset & 0x001ff));
1659      COMBINE_DATA(m_c412.pczram  + (offset & 0x001ff));
16641660}
16651661
16661662READ16_MEMBER(namcos23_state::s23_c412_r)
16671663{
1668   c412_t &c412 = m_c412;
1669
1670   switch(offset)
1664   switch (offset)
16711665   {
16721666      case 0x3:
16731667         return 0x0002; // 0001 = busy, 0002 = game uploads things
16741668      case 0x8:
1675         return c412.adr;
1669         return m_c412.adr;
16761670      case 0x9:
1677         return c412.adr >> 16;
1671         return m_c412.adr >> 16;
16781672      case 0xa:
1679         return s23_c412_ram_r(space, c412.adr, mem_mask);
1673         return s23_c412_ram_r(space, m_c412.adr, mem_mask);
16801674   }
16811675
16821676   logerror("c412_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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16851679
16861680WRITE16_MEMBER(namcos23_state::s23_c412_w)
16871681{
1688   c412_t &c412 = m_c412;
1689
16901682   switch (offset)
16911683   {
16921684      case 8:
1693         c412.adr = (data & mem_mask) | (c412.adr & (0xffffffff ^ mem_mask));
1685         m_c412.adr = (data & mem_mask) | (m_c412.adr & (0xffffffff ^ mem_mask));
16941686         break;
16951687      case 9:
1696         c412.adr = ((data & mem_mask) << 16) | (c412.adr & (0xffffffff ^ (mem_mask << 16)));
1688         m_c412.adr = ((data & mem_mask) << 16) | (m_c412.adr & (0xffffffff ^ (mem_mask << 16)));
16971689         break;
16981690      case 10:
1699         s23_c412_ram_w(space, c412.adr, data, mem_mask);
1700         c412.adr += 2;
1691         s23_c412_ram_w(space, m_c412.adr, data, mem_mask);
1692         m_c412.adr += 2;
17011693         break;
17021694      default:
17031695         logerror("c412_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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17071699
17081700READ16_MEMBER(namcos23_state::s23_c421_ram_r)
17091701{
1710   c421_t &c421 = m_c421;
1711
17121702   //  logerror("c421_ram_r %06x (%08x, %08x)\n", offset, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
17131703   if(offset < 0x40000)
1714      return c421.dram_a[offset & 0x3ffff];
1704      return m_c421.dram_a[offset & 0x3ffff];
17151705   else if(offset < 0x80000)
1716      return c421.dram_b[offset & 0x3ffff];
1706      return m_c421.dram_b[offset & 0x3ffff];
17171707   else if(offset < 0x88000)
1718      return c421.sram  [offset & 0x07fff];
1708      return m_c421.sram  [offset & 0x07fff];
17191709
17201710   return 0xffff;
17211711}
17221712
17231713WRITE16_MEMBER(namcos23_state::s23_c421_ram_w)
17241714{
1725   c421_t &c421 = m_c421;
1726
17271715   //  logerror("c421_ram_w %06x = %04x (%08x, %08x)\n", offset, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
17281716   if(offset < 0x40000)
1729      COMBINE_DATA(c421.dram_a + (offset & 0x3ffff));
1717      COMBINE_DATA(m_c421.dram_a + (offset & 0x3ffff));
17301718   else if(offset < 0x80000)
1731      COMBINE_DATA(c421.dram_b + (offset & 0x3ffff));
1719      COMBINE_DATA(m_c421.dram_b + (offset & 0x3ffff));
17321720   else if(offset < 0x88000)
1733      COMBINE_DATA(c421.sram   + (offset & 0x07fff));
1721      COMBINE_DATA(m_c421.sram   + (offset & 0x07fff));
17341722}
17351723
17361724READ16_MEMBER(namcos23_state::s23_c421_r)
17371725{
1738   c421_t &c421 = m_c421;
1739
17401726   switch (offset)
17411727   {
17421728      case 0:
1743         return s23_c421_ram_r(space, c421.adr & 0xfffff, mem_mask);
1729         return s23_c421_ram_r(space, m_c421.adr & 0xfffff, mem_mask);
17441730
17451731      case 2:
1746         return c421.adr >> 16;
1732         return m_c421.adr >> 16;
17471733      case 3:
1748         return c421.adr;
1734         return m_c421.adr;
17491735   }
17501736
17511737   logerror("c421_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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17541740
17551741WRITE16_MEMBER(namcos23_state::s23_c421_w)
17561742{
1757   c421_t &c421 = m_c421;
1758
17591743   switch (offset)
17601744   {
17611745      case 0:
1762         s23_c421_ram_w(space, c421.adr & 0xfffff, data, mem_mask);
1763         c421.adr += 2;
1746         s23_c421_ram_w(space, m_c421.adr & 0xfffff, data, mem_mask);
1747         m_c421.adr += 2;
17641748         break;
17651749      case 2:
1766         c421.adr = ((data & mem_mask) << 16) | (c421.adr & (0xffffffff ^ (mem_mask << 16)));
1750         m_c421.adr = ((data & mem_mask) << 16) | (m_c421.adr & (0xffffffff ^ (mem_mask << 16)));
17671751         break;
17681752      case 3:
1769         c421.adr = (data & mem_mask) | (c421.adr & (0xffffffff ^ mem_mask));
1753         m_c421.adr = (data & mem_mask) | (m_c421.adr & (0xffffffff ^ mem_mask));
17701754         break;
17711755      default:
17721756         logerror("c421_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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18061790
18071791      default:
18081792         logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1793         break;
18091794   }
18101795}
18111796
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18301815
18311816TIMER_CALLBACK_MEMBER(namcos23_state::c361_timer_cb)
18321817{
1833   c361_t &c361 = m_c361;
1834
1835   if (c361.scanline != 0x1ff)
1818   if (m_c361.scanline != 0x1ff)
18361819   {
18371820      // need to do a partial update here, but doesn't work properly yet
18381821      //machine().primary_screen->update_partial(machine().primary_screen->vpos());
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18471830
18481831WRITE16_MEMBER(namcos23_state::s23_c361_w)
18491832{
1850   c361_t &c361 = m_c361;
1851
18521833   switch (offset)
18531834   {
18541835      case 0:
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18601841         break;
18611842
18621843      case 4:   // interrupt control
1863         c361.scanline = data & 0x1ff;
1864         c361.timer->adjust(machine().primary_screen->time_until_pos(c361.scanline));
1844         m_c361.scanline = data & 0x1ff;
1845         m_c361.timer->adjust(machine().primary_screen->time_until_pos(m_c361.scanline));
18651846         break;
18661847
18671848      default:
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18901871
18911872READ16_MEMBER(namcos23_state::s23_c422_r)
18921873{
1893   c422_t &c422 = m_c422;
1894
1895   return c422.regs[offset];
1874   return m_c422.regs[offset];
18961875}
18971876
18981877WRITE16_MEMBER(namcos23_state::s23_c422_w)
18991878{
1900   c422_t &c422 = m_c422;
1901
19021879   switch (offset)
19031880   {
19041881      case 1:
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19191896         break;
19201897   }
19211898
1922   COMBINE_DATA(&c422.regs[offset]);
1899   COMBINE_DATA(&m_c422.regs[offset]);
19231900}
19241901
19251902
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19611938   }
19621939}
19631940
1964// Panic Park sits in a tight loop waiting for this AND 0002 to be non-zero (at PC=BFC02F00)
1941// panicprk sits in a tight loop waiting for this AND 0002 to be non-zero (at PC=BFC02F00)
1942// timecrs2 locks up in a similar way as panicprk, at the beginning of the 2nd level, by reading/writing to this register a couple of times
19651943READ32_MEMBER(namcos23_state::s23_unk_status_r)
19661944{
19671945   return 0x00020002;
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25192497   m_render.polymgr = poly_alloc(machine(), 10000, sizeof(namcos23_render_data), 0);
25202498}
25212499
2500
2501void namcos23_state::update_mixer()
2502{
2503   // should be similar to Super System 22 C404
2504   // 08 - background color red
2505   // 09 - background color green
2506   // 0a - background color blue
2507   // 1b - text layer palette base
2508   // 1f - layer enable (d0: polygons, d1: sprites, d2: text)
2509   m_c404.bgcolor = MAKE_RGB(nthword(m_gammaram,0x08), nthword(m_gammaram,0x09), nthword(m_gammaram,0x0a));
2510   m_c404.palbase = nthword(m_gammaram, 0x1b) << 8 & 0x7f00;
2511   m_c404.layer = nthword(m_gammaram, 0x1f) & 0xff;
2512}
2513
25222514UINT32 namcos23_state::screen_update_ss23(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
25232515{
2524   bitmap.fill(get_black_pen(machine()), cliprect);
2516   update_mixer();
2517   bitmap.fill(m_c404.bgcolor, cliprect);
25252518
2526   render_run( machine(), bitmap );
2519   render_run(machine(), bitmap);
25272520
2528   gfx_element *gfx = machine().gfx[0];
2529   gfx->mark_all_dirty();
2530
2531   m_bgtilemap->draw(bitmap, cliprect, 0/*flags*/, 0/*priority*/ ); /* opaque */
2521   m_bgtilemap->set_palette_offset(m_c404.palbase);
2522   if (m_c404.layer & 4)
2523      m_bgtilemap->draw(bitmap, cliprect, 0, 0);
25322524   return 0;
25332525}
25342526
25352527INTERRUPT_GEN_MEMBER(namcos23_state::s23_interrupt)
25362528{
2537   render_t &render = m_render;
2538
2539   if(!m_ctl_vbl_active)
2529   if (!m_ctl_vbl_active)
25402530   {
25412531      m_ctl_vbl_active = true;
25422532      update_main_interrupts(m_main_irqcause | MAIN_VBLANK_IRQ);
25432533   }
25442534
2545   render.cur = !render.cur;
2546   render.count[render.cur] = 0;
2535   m_render.cur = !m_render.cur;
2536   m_render.count[m_render.cur] = 0;
25472537}
25482538
25492539void namcos23_state::machine_start()
25502540{
2551   c361_t &c361 = m_c361;
2552   c361.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(namcos23_state::c361_timer_cb),this));
2553   c361.timer->adjust(attotime::never);
2541   m_c361.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(namcos23_state::c361_timer_cb),this));
2542   m_c361.timer->adjust(attotime::never);
25542543
25552544   mips3drc_add_fastram(m_maincpu, 0, m_mainram.bytes()-1, FALSE, reinterpret_cast<UINT32 *>(machine().root_device().memshare("mainram")->ptr()));
25562545}
r18805r18806
25642553   AM_RANGE(0x04c3ff00, 0x04c3ff0f) AM_WRITE16(s23_mcuen_w, 0xffffffff)
25652554   AM_RANGE(0x06080000, 0x0608000f) AM_RAM AM_SHARE("czattr")
25662555   AM_RANGE(0x06080200, 0x060803ff) AM_RAM // PCZ Convert RAM (C406) (should be banked)
2567   AM_RANGE(0x06108000, 0x061087ff) AM_RAM // Gamma RAM (C404)
2556   AM_RANGE(0x06108000, 0x061087ff) AM_RAM AM_SHARE("gammaram") // Gamma RAM (C404)
25682557   AM_RANGE(0x06110000, 0x0613ffff) AM_RAM_WRITE(namcos23_paletteram_w) AM_SHARE("paletteram") // Palette RAM (C404)
25692558   AM_RANGE(0x06400000, 0x0641dfff) AM_RAM_WRITE(s23_txtchar_w) AM_SHARE("charram") // Text CGRAM (C361)
25702559   AM_RANGE(0x0641e000, 0x0641ffff) AM_RAM_WRITE(namcos23_textram_w) AM_SHARE("textram") // Text VRAM (C361)
r18805r18806
25732562   AM_RANGE(0x0c000000, 0x0c00ffff) AM_RAM   AM_SHARE("nvram") // Backup RAM
25742563   AM_RANGE(0x0d000000, 0x0d00000f) AM_READWRITE16(s23_ctl_r, s23_ctl_w, 0xffffffff) // write for LEDs at d000000, watchdog at d000004
25752564   AM_RANGE(0x0e000000, 0x0e007fff) AM_RAM // C405 RAM - what is this?
2576   AM_RANGE(0x0f000000, 0x0f000003) AM_READ(s23_unk_status_r)
2565   AM_RANGE(0x0f000000, 0x0f000003) AM_READ(s23_unk_status_r) // error status, or protection? (also gets written to)
25772566   AM_RANGE(0x0f200000, 0x0f203fff) AM_RAM // C422 RAM
25782567   AM_RANGE(0x0f300000, 0x0f30000f) AM_READWRITE16(s23_c422_r, s23_c422_w, 0xffffffff) // C422 registers
25792568   AM_RANGE(0x0fc00000, 0x0fffffff) AM_WRITENOP AM_ROM AM_REGION("user1", 0)
r18805r18806
25922581   AM_RANGE(0x06800000, 0x0681dfff) AM_RAM_WRITE(s23_txtchar_w) AM_SHARE("charram") // Text CGRAM (C361)
25932582   AM_RANGE(0x0681e000, 0x0681ffff) AM_RAM_WRITE(namcos23_textram_w) AM_SHARE("textram") // Text VRAM (C361)
25942583   AM_RANGE(0x06820000, 0x0682000f) AM_READWRITE16(s23_c361_r, s23_c361_w, 0xffffffff) // C361
2595   AM_RANGE(0x06a08000, 0x06a087ff) AM_RAM // Blending control & GAMMA (C404)
2584   AM_RANGE(0x06a08000, 0x06a087ff) AM_RAM AM_SHARE("gammaram") // Gamma RAM (C404)
25962585   AM_RANGE(0x06a10000, 0x06a3ffff) AM_RAM_WRITE(namcos23_paletteram_w) AM_SHARE("paletteram") // Palette RAM (C404)
25972586   AM_RANGE(0x08000000, 0x08ffffff) AM_ROM AM_REGION("data", 0x0000000) AM_MIRROR(0x1000000) // data ROMs
25982587   AM_RANGE(0x0a000000, 0x0affffff) AM_ROM AM_REGION("data", 0x1000000) AM_MIRROR(0x1000000)
25992588   AM_RANGE(0x0c000000, 0x0c00001f) AM_READWRITE16(s23_c412_r, s23_c412_w, 0xffffffff)
26002589   AM_RANGE(0x0c400000, 0x0c400007) AM_READWRITE16(s23_c421_r, s23_c421_w, 0xffffffff)
26012590   AM_RANGE(0x0d000000, 0x0d00000f) AM_READWRITE16(s23_ctl_r, s23_ctl_w, 0xffffffff)
2602   AM_RANGE(0x0e800000, 0x0e800003) AM_READ(s23_unk_status_r)
2591   AM_RANGE(0x0e800000, 0x0e800003) AM_READ(s23_unk_status_r) // error status, or protection? (also gets written to)
26032592   AM_RANGE(0x0fc00000, 0x0fffffff) AM_WRITENOP AM_ROM AM_REGION("user1", 0)
26042593ADDRESS_MAP_END
26052594
r18805r18806
26292618
26302619
26312620static ADDRESS_MAP_START( gmen_sh2_map, AS_PROGRAM, 32, namcos23_state )
2632   AM_RANGE( 0x00000000, 0x00007fff ) AM_RAM AM_SHARE("gmen_sh2_shared")
2633   AM_RANGE( 0x04000000, 0x043fffff ) AM_RAM   // SH-2 main work RAM
2621   AM_RANGE(0x00000000, 0x00007fff) AM_RAM AM_SHARE("gmen_sh2_shared")
2622   AM_RANGE(0x04000000, 0x043fffff) AM_RAM   // SH-2 main work RAM
26342623ADDRESS_MAP_END
26352624
26362625MACHINE_RESET_MEMBER(namcos23_state,gmen)
r18805r18806
32073196
32083197DRIVER_INIT_MEMBER(namcos23_state,ss23)
32093198{
3210   render_t &render = m_render;
32113199   m_ptrom  = (const UINT32 *)memregion("pointrom")->base();
32123200   m_tmlrom = (const UINT16 *)memregion("textilemapl")->base();
32133201   m_tmhrom = memregion("textilemaph")->base();
r18805r18806
32283216   m_s23_tssio_port_4 = 0;
32293217   m_s23_porta = 0, m_s23_rtcstate = 0;
32303218   m_audiocpu_running = false;
3231   render.count[0] = render.count[1] = 0;
3232   render.cur = 0;
3219   m_render.count[0] = m_render.count[1] = 0;
3220   m_render.cur = 0;
32333221
32343222   if ((!strcmp(machine().system().name, "motoxgo")) ||
32353223       (!strcmp(machine().system().name, "panicprk")) ||
r18805r18806
32773265}; /* cg_layout */
32783266
32793267static GFXDECODE_START( namcos23 )
3280   GFXDECODE_ENTRY( NULL, 0, namcos23_cg_layout, 0x7f00, 0x80 )
3268   GFXDECODE_ENTRY( NULL, 0, namcos23_cg_layout, 0, 0x800 )
32813269GFXDECODE_END
32823270
32833271static const mips3_config r4650_config =

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