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r18804 Thursday 1st November, 2012 at 15:43:21 UTC by smf
turned znsec into a device [smf]

[src/emu/cpu/psx]	sio.h
[src/mame/drivers]	taitogn.c zn.c
[src/mame/machine]	znsec.c znsec.h

trunk/src/mame/drivers/taitogn.c

r18803	r18804
332	332	class taitogn_state : public psx_state
333	333	{
334	334	public:
335		taitogn_state(const machine_config &mconfig, device_type type, const char *tag)
336		: psx_state(mconfig, type, tag) { }
	335	taitogn_state(const machine_config &mconfig, device_type type, const char *tag) :
	336	psx_state(mconfig, type, tag),
	337	m_znsec0(*this,"znsec0"),
	338	m_znsec1(*this,"znsec1")
	339	{
	340	}
337	341
	342	required_device<znsec_device> m_znsec0;
	343	required_device<znsec_device> m_znsec1;
	344
338	345	intel_te28f160_device *m_biosflash;
339	346	intel_e28f400_device *m_pgmflash;
340	347	intel_te28f160_device *m_sndflash[3];
r18803	r18804
690	697	taitogn_state *state = machine.driver_data<taitogn_state>();
691	698
692	699	if( ( n_data & PSX_SIO_OUT_CLOCK ) == 0 )
693		{
694		if( state->m_b_lastclock )
695		psx_sio_input( machine, 0, PSX_SIO_IN_DATA, ( znsec_step( 0, ( n_data & PSX_SIO_OUT_DATA ) != 0 ) != 0 ) * PSX_SIO_IN_DATA );
696		state->m_b_lastclock = 0;
697		}
	700	{
	701	if( state->m_b_lastclock )
	702	psx_sio_input( machine, 0, PSX_SIO_IN_DATA, ( state->m_znsec0->step( ( n_data & PSX_SIO_OUT_DATA ) != 0 ) != 0 ) * PSX_SIO_IN_DATA );
	703
	704	state->m_b_lastclock = 0;
	705	}
698	706	else
699		{
700		state->m_b_lastclock = 1;
701		}
	707	{
	708	state->m_b_lastclock = 1;
	709	}
702	710	}
703	711
704	712	static void sio_znsec1_handler( running_machine &machine, int n_data )
r18803	r18804
706	714	taitogn_state *state = machine.driver_data<taitogn_state>();
707	715
708	716	if( ( n_data & PSX_SIO_OUT_CLOCK ) == 0 )
709		{
710		if( state->m_b_lastclock )
711		psx_sio_input( machine, 0, PSX_SIO_IN_DATA, ( znsec_step( 1, ( n_data & PSX_SIO_OUT_DATA ) != 0 ) != 0 ) * PSX_SIO_IN_DATA );
712		state->m_b_lastclock = 0;
713		}
	717	{
	718	if( state->m_b_lastclock )
	719	psx_sio_input( machine, 0, PSX_SIO_IN_DATA, ( state->m_znsec1->step( ( n_data & PSX_SIO_OUT_DATA ) != 0 ) != 0 ) * PSX_SIO_IN_DATA );
	720
	721	state->m_b_lastclock = 0;
	722	}
714	723	else
715		{
716		state->m_b_lastclock = 1;
717		}
	724	{
	725	state->m_b_lastclock = 1;
	726	}
718	727	}
719	728
720	729	static void sio_pad_handler( running_machine &machine, int n_data )
r18803	r18804
722	731	taitogn_state *state = machine.driver_data<taitogn_state>();
723	732
724	733	if( ( n_data & PSX_SIO_OUT_DTR ) != 0 )
725		{
726		state->m_b_znsecport = 1;
727		}
	734	{
	735	state->m_b_znsecport = 1;
	736	}
728	737	else
729		{
730		state->m_b_znsecport = 0;
731		}
	738	{
	739	state->m_b_znsecport = 0;
	740	}
732	741
733	742	psx_sio_input( machine, 0, PSX_SIO_IN_DATA | PSX_SIO_IN_DSR, PSX_SIO_IN_DATA | PSX_SIO_IN_DSR );
734	743	}
r18803	r18804
758	767	{
759	768	COMBINE_DATA( &m_n_znsecsel );
760	769
	770	m_znsec0->select( ( m_n_znsecsel >> 2 ) & 1 );
	771	m_znsec1->select( ( m_n_znsecsel >> 3 ) & 1 );
	772
761	773	if( ( m_n_znsecsel & 0x80 ) == 0 )
762		{
763		psx_sio_install_handler( machine(), 0, sio_pad_handler );
764		psx_sio_input( machine(), 0, PSX_SIO_IN_DSR, 0 );
765		}
	774	{
	775	psx_sio_install_handler( machine(), 0, sio_pad_handler );
	776	psx_sio_input( machine(), 0, PSX_SIO_IN_DSR, 0 );
	777	}
766	778	else if( ( m_n_znsecsel & 0x08 ) == 0 )
767		{
768		znsec_start( 1 );
769		psx_sio_install_handler( machine(), 0, sio_znsec1_handler );
770		psx_sio_input( machine(), 0, PSX_SIO_IN_DSR, 0 );
771		}
	779	{
	780	psx_sio_install_handler( machine(), 0, sio_znsec1_handler );
	781	psx_sio_input( machine(), 0, PSX_SIO_IN_DSR, 0 );
	782	}
772	783	else if( ( m_n_znsecsel & 0x04 ) == 0 )
773		{
774		znsec_start( 0 );
775		psx_sio_install_handler( machine(), 0, sio_znsec0_handler );
776		psx_sio_input( machine(), 0, PSX_SIO_IN_DSR, 0 );
777		}
	784	{
	785	psx_sio_install_handler( machine(), 0, sio_znsec0_handler );
	786	psx_sio_input( machine(), 0, PSX_SIO_IN_DSR, 0 );
	787	}
778	788	else
779		{
780		m_n_dip_bit = 0;
781		m_b_lastclock = 1;
	789	{
	790	m_n_dip_bit = 0;
	791	m_b_lastclock = 1;
782	792
783		psx_sio_install_handler( machine(), 0, sio_dip_handler );
784		psx_sio_input( machine(), 0, PSX_SIO_IN_DSR, 0 );
	793	psx_sio_install_handler( machine(), 0, sio_dip_handler );
	794	psx_sio_input( machine(), 0, PSX_SIO_IN_DSR, 0 );
785	795
786		m_dip_timer->adjust( downcast<cpu_device *>(&space.device())->cycles_to_attotime( 100 ), 1 );
787		}
	796	m_dip_timer->adjust( downcast<cpu_device *>(&space.device())->cycles_to_attotime( 100 ), 1 );
	797	}
788	798	}
789	799
790	800	TIMER_CALLBACK_MEMBER(taitogn_state::dip_timer_fired)
r18803	r18804
869	879	m_sndflash[2] = machine().device<intel_te28f160_device>("sndflash2");
870	880
871	881	psx_driver_init(machine());
872		znsec_init(0, tt10);
873		znsec_init(1, tt16);
	882	m_znsec0->init(tt10);
	883	m_znsec1->init(tt16);
874	884	psx_sio_install_handler(machine(), 0, sio_pad_handler);
875	885	m_dip_timer = machine().scheduler().timer_alloc( timer_expired_delegate(FUNC(taitogn_state::dip_timer_fired),this), NULL );
876	886
r18803	r18804
941	951	MCFG_CPU_ADD( "maincpu", CXD8661R, XTAL_100MHz )
942	952	MCFG_CPU_PROGRAM_MAP(taitogn_map)
943	953
	954	MCFG_DEVICE_ADD("znsec0", ZNSEC, 0)
	955	MCFG_DEVICE_ADD("znsec1", ZNSEC, 0)
	956
944	957	/* video hardware */
945	958	MCFG_PSXGPU_ADD( "maincpu", "gpu", CXD8654Q, 0x200000, XTAL_53_693175MHz )
946	959

trunk/src/mame/drivers/zn.c

r18803	r18804
34	34	public:
35	35	zn_state(const machine_config &mconfig, device_type type, const char *tag) :
36	36	psx_state(mconfig, type, tag),
37		m_gpu(*this, "gpu")
	37	m_gpu(*this, "gpu"),
	38	m_znsec0(*this,"znsec0"),
	39	m_znsec1(*this,"znsec1")
38	40	{
39	41	}
40	42
41	43	required_device<psxgpu_device> m_gpu;
	44	required_device<znsec_device> m_znsec0;
	45	required_device<znsec_device> m_znsec1;
42	46	UINT32 m_n_znsecsel;
43	47	UINT32 m_b_znsecport;
44	48	int m_n_dip_bit;
r18803	r18804
323	327	{
324	328	if( state->m_b_lastclock )
325	329	{
326		psx_sio_input( machine, 0, PSX_SIO_IN_DATA, ( znsec_step( 0, ( n_data & PSX_SIO_OUT_DATA ) != 0 ) != 0 ) * PSX_SIO_IN_DATA );
	330	psx_sio_input( machine, 0, PSX_SIO_IN_DATA, ( state->m_znsec0->step( ( n_data & PSX_SIO_OUT_DATA ) != 0 ) != 0 ) * PSX_SIO_IN_DATA );
327	331	}
	332
328	333	state->m_b_lastclock = 0;
329	334	}
330	335	else
r18803	r18804
341	346	{
342	347	if( state->m_b_lastclock )
343	348	{
344		psx_sio_input( machine, 0, PSX_SIO_IN_DATA, ( znsec_step( 1, ( n_data & PSX_SIO_OUT_DATA ) != 0 ) != 0 ) * PSX_SIO_IN_DATA );
	349	psx_sio_input( machine, 0, PSX_SIO_IN_DATA, ( state->m_znsec1->step( ( n_data & PSX_SIO_OUT_DATA ) != 0 ) != 0 ) * PSX_SIO_IN_DATA );
345	350	}
	351
346	352	state->m_b_lastclock = 0;
347	353	}
348	354	else
r18803	r18804
394	400	{
395	401	COMBINE_DATA( &m_n_znsecsel );
396	402
	403	m_znsec0->select( ( m_n_znsecsel >> 2 ) & 1 );
	404	m_znsec1->select( ( m_n_znsecsel >> 3 ) & 1 );
	405
397	406	if( ( m_n_znsecsel & 0x80 ) == 0 )
398	407	{
399	408	psx_sio_install_handler( machine(), 0, sio_pad_handler );
r18803	r18804
401	410	}
402	411	else if( ( m_n_znsecsel & 0x08 ) == 0 )
403	412	{
404		znsec_start( 1 );
405	413	psx_sio_install_handler( machine(), 0, sio_znsec1_handler );
406	414	psx_sio_input( machine(), 0, PSX_SIO_IN_DSR, 0 );
407	415	}
408	416	else if( ( m_n_znsecsel & 0x04 ) == 0 )
409	417	{
410		znsec_start( 0 );
411	418	psx_sio_install_handler( machine(), 0, sio_znsec0_handler );
412	419	psx_sio_input( machine(), 0, PSX_SIO_IN_DSR, 0 );
413	420	}
r18803	r18804
527	534	{
528	535	if( strcmp( machine.system().name, zn_config_table[ n_game ].s_name ) == 0 )
529	536	{
530		znsec_init( 0, zn_config_table[ n_game ].p_n_mainsec );
531		znsec_init( 1, zn_config_table[ n_game ].p_n_gamesec );
	537	state->m_znsec0->init( zn_config_table[ n_game ].p_n_mainsec );
	538	state->m_znsec1->init( zn_config_table[ n_game ].p_n_gamesec );
532	539	psx_sio_install_handler( machine, 0, sio_pad_handler );
533	540	break;
534	541	}
r18803	r18804
551	558	MCFG_CPU_ADD( "maincpu", CXD8530CQ, XTAL_67_7376MHz )
552	559	MCFG_CPU_PROGRAM_MAP( zn_map)
553	560
	561	MCFG_DEVICE_ADD("znsec0", ZNSEC, 0)
	562	MCFG_DEVICE_ADD("znsec1", ZNSEC, 0)
	563
554	564	/* video hardware */
555	565	MCFG_PSXGPU_ADD( "maincpu", "gpu", CXD8561Q, 0x100000, XTAL_53_693175MHz )
556	566
r18803	r18804
573	583	MCFG_CPU_ADD( "maincpu", CXD8661R, XTAL_100MHz )
574	584	MCFG_CPU_PROGRAM_MAP( zn_map)
575	585
	586	MCFG_DEVICE_ADD("znsec0", ZNSEC, 0)
	587	MCFG_DEVICE_ADD("znsec1", ZNSEC, 0)
	588
576	589	/* video hardware */
577	590	MCFG_PSXGPU_ADD( "maincpu", "gpu", CXD8654Q, 0x200000, XTAL_53_693175MHz )
578	591

trunk/src/mame/machine/znsec.c

r18803	r18804
82	82	= Shift(c[n-1, 6])^Shift(c[n-1, 7])
83	83	*/
84	84
85		#include "emu.h"
86	85	#include "znsec.h"
87	86
88		struct znsec_state {
89		const UINT8 *transform;
90		UINT8 state;
91		UINT8 bit;
92		};
	87	const device_type ZNSEC = &device_creator<znsec_device>;
93	88
94		static znsec_state zns[2];
	89	znsec_device::znsec_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	90	device_t(mconfig, ZNSEC, "ZNSEC", tag, owner, clock)
	91	{
	92	}
95	93
	94	void znsec_device::device_start()
	95	{
	96	save_item(NAME(m_select));
	97	save_item(NAME(m_state));
	98	save_item(NAME(m_bit));
	99	}
96	100
97	101	// Given the value for x7..x0 and linear transform coefficients a7..a0
98	102	// compute the value of the transform
r18803	r18804
111	115	#endif
112	116
113	117	// Derive the sbox xor mask for a given input and select bit
114		static UINT8 compute_sbox_coef(int chip, int sel, int bit)
	118	UINT8 znsec_device::compute_sbox_coef(int sel, int bit)
115	119	{
116		UINT8 r;
117	120	if(!sel)
118		return zns[chip].transform[bit];
119		r = compute_sbox_coef(chip, (sel-1) & 7, (bit-1) & 7);
	121	return m_transform[bit];
	122
	123	UINT8 r = compute_sbox_coef((sel-1) & 7, (bit-1) & 7);
120	124	r = (r << 1)|(((r >> 7)^(r >> 6)) & 1);
121	125	if(bit != 7)
122	126	return r;
123	127
124		return r ^ compute_sbox_coef(chip, sel, 0);
	128	return r ^ compute_sbox_coef(sel, 0);
125	129	}
126	130
127	131	// Apply the sbox for a input 0 bit
128		static UINT8 apply_bit_sbox(int chip, UINT8 state, int sel)
	132	void znsec_device::apply_bit_sbox(int sel)
129	133	{
130	134	int i;
131	135	UINT8 r = 0;
132	136	for(i=0; i<8; i++)
133		if(state & (1<<i))
134		r ^= compute_sbox_coef(chip, sel, i);
135		return r;
	137	if(m_state & (1<<i))
	138	r ^= compute_sbox_coef(sel, i);
	139
	140	m_state = r;
136	141	}
137	142
138	143	// Apply a sbox
139		static UINT8 apply_sbox(UINT8 state, const UINT8 *sbox)
	144	void znsec_device::apply_sbox(const UINT8 *sbox)
140	145	{
141	146	int i;
142	147	UINT8 r = 0;
143	148	for(i=0; i<8; i++)
144		if(state & (1<<i))
	149	if(m_state & (1<<i))
145	150	r ^= sbox[i];
146		return r;
	151
	152	m_state = r;
147	153	}
148	154
149		void znsec_init(int chip, const UINT8 *transform)
	155	void znsec_device::init(const UINT8 *transform)
150	156	{
151		zns[chip].transform = transform;
152		zns[chip].state = 0xfc;
153		zns[chip].bit = 0;
	157	m_transform = transform;
154	158	}
155	159
156		void znsec_start(int chip)
	160	void znsec_device::select(int select)
157	161	{
158		zns[chip].state = 0xfc;
159		zns[chip].bit = 0;
	162	if (m_select && !select)
	163	{
	164	m_state = 0xfc;
	165	m_bit = 0;
	166	}
	167
	168	m_select = select;
160	169	}
161	170
162		UINT8 znsec_step(int chip, UINT8 input)
	171	UINT8 znsec_device::step(UINT8 input)
163	172	{
164	173	UINT8 res;
165	174	static const UINT8 initial_sbox[8] = { 0xff, 0xfe, 0xfc, 0xf8, 0xf0, 0xe0, 0xc0, 0x7f };
166	175
167		if (zns[chip].bit==0)
	176	if (m_bit==0)
168	177	{
169		// Apply the initial xbox
170		zns[chip].state = apply_sbox(zns[chip].state, initial_sbox);
	178	// Apply the initial sbox
	179	apply_sbox(initial_sbox);
171	180	}
172	181
173	182	// Compute the output and change the state
174		res = (zns[chip].state>>zns[chip].bit) & 1;
	183	res = (m_state >> m_bit) & 1;
175	184	if((input & 1)==0)
176		zns[chip].state = apply_bit_sbox(chip, zns[chip].state, zns[chip].bit);
	185	apply_bit_sbox(m_bit);
177	186
178		zns[chip].bit++;
179		zns[chip].bit&=7;
	187	m_bit++;
	188	m_bit&=7;
180	189	return res;
181	190	}

trunk/src/mame/machine/znsec.h

r18803	r18804
1	1	/*  CAT702 ZN security chip */
2	2
3		void znsec_init(int chip, const UINT8 *transform);
4		void znsec_start(int chip);
5		UINT8 znsec_step(int chip, UINT8 input);
	3	#pragma once
	4
	5	#ifndef __ZNSEC_H__
	6	#define __ZNSEC_H__
	7
	8	#include "emu.h"
	9
	10	extern const device_type ZNSEC;
	11
	12	class znsec_device : public device_t
	13	{
	14	public:
	15	znsec_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	16
	17	void init(const UINT8 *transform);
	18	void select(int select);
	19	UINT8 step(UINT8 input);
	20
	21	protected:
	22	void device_start();
	23
	24	private:
	25	UINT8 compute_sbox_coef(int sel, int bit);
	26	void apply_bit_sbox(int sel);
	27	void apply_sbox(const UINT8 *sbox);
	28
	29	const UINT8 *m_transform;
	30	int m_select;
	31	UINT8 m_state;
	32	UINT8 m_bit;
	33	};
	34
	35	#endif

trunk/src/emu/cpu/psx/sio.h

r18803	r18804
100	100	devcb2_write_line m_irq1_handler;
101	101	};
102	102
103		DECLARE_WRITE32_HANDLER( psx_sio_w );
104		DECLARE_READ32_HANDLER( psx_sio_r );
105
106	103	#endif

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