trunk/src/emu/video/pc_vga.c
| r18791 | r18792 | |
|---|
| 2688 | 2688 | void s3_vga_device::s3_define_video_mode() |
| 2689 | 2689 | { |
| 2690 | 2690 | int divisor = 1; |
| 2691 | | int xtal = 1000000; |
| 2691 | int xtal = (vga.miscellaneous_output & 0xc) ? XTAL_28_63636MHz : XTAL_25_1748MHz; |
| 2692 | |
| 2693 | if((vga.miscellaneous_output & 0xc) == 0x0c) |
| 2694 | { |
| 2695 | switch(s3.cr42 & 0x0f) // TODO: confirm clock settings |
| 2696 | { |
| 2697 | case 0: |
| 2698 | xtal = XTAL_25_1748MHz; |
| 2699 | break; |
| 2700 | case 1: |
| 2701 | xtal = XTAL_28_63636MHz; |
| 2702 | break; |
| 2703 | case 2: |
| 2704 | xtal = 40000000; |
| 2705 | break; |
| 2706 | case 3: |
| 2707 | xtal = 3000000; |
| 2708 | break; |
| 2709 | case 4: |
| 2710 | xtal = 50000000; |
| 2711 | break; |
| 2712 | case 5: |
| 2713 | xtal = 77000000; |
| 2714 | break; |
| 2715 | case 6: |
| 2716 | xtal = 36000000; |
| 2717 | break; |
| 2718 | case 7: |
| 2719 | xtal = 45000000; |
| 2720 | break; |
| 2721 | case 8: |
| 2722 | xtal = 1000000; |
| 2723 | break; |
| 2724 | case 9: |
| 2725 | xtal = 1000000; |
| 2726 | break; |
| 2727 | case 10: |
| 2728 | xtal = 79000000; |
| 2729 | break; |
| 2730 | case 11: |
| 2731 | xtal = 31000000; |
| 2732 | break; |
| 2733 | case 12: |
| 2734 | xtal = 94000000; |
| 2735 | break; |
| 2736 | case 13: |
| 2737 | xtal = 65000000; |
| 2738 | break; |
| 2739 | case 14: |
| 2740 | xtal = 75000000; |
| 2741 | break; |
| 2742 | case 15: |
| 2743 | xtal = 71000000; |
| 2744 | break; |
| 2745 | default: |
| 2746 | xtal = 1000000; |
| 2747 | } |
| 2748 | } |
| 2749 | |
| 2692 | 2750 | if((s3.ext_misc_ctrl_2) >> 4) |
| 2693 | 2751 | { |
| 2694 | 2752 | svga.rgb8_en = 0; |
| r18791 | r18792 | |
|---|
| 2702 | 2760 | case 0x0d: svga.rgb32_en = 1; divisor = 2; break; |
| 2703 | 2761 | default: fatalerror("TODO: s3 video mode not implemented %02x\n",((s3.ext_misc_ctrl_2) >> 4)); break; |
| 2704 | 2762 | } |
| 2705 | | /* switch(s3.cr42 & 0x0f) // TODO: confirm clock settings |
| 2706 | | { |
| 2707 | | case 0: |
| 2708 | | xtal = XTAL_25_1748MHz; |
| 2709 | | break; |
| 2710 | | case 1: |
| 2711 | | xtal = XTAL_28_63636MHz; |
| 2712 | | break; |
| 2713 | | case 2: |
| 2714 | | xtal = 40000000; |
| 2715 | | break; |
| 2716 | | case 3: |
| 2717 | | xtal = 3000000; |
| 2718 | | break; |
| 2719 | | case 4: |
| 2720 | | xtal = 50000000; |
| 2721 | | break; |
| 2722 | | case 5: |
| 2723 | | xtal = 77000000; |
| 2724 | | break; |
| 2725 | | case 6: |
| 2726 | | xtal = 36000000; |
| 2727 | | break; |
| 2728 | | case 7: |
| 2729 | | xtal = 45000000; |
| 2730 | | break; |
| 2731 | | case 8: |
| 2732 | | xtal = 1000000; |
| 2733 | | break; |
| 2734 | | case 9: |
| 2735 | | xtal = 1000000; |
| 2736 | | break; |
| 2737 | | case 10: |
| 2738 | | xtal = 79000000; |
| 2739 | | break; |
| 2740 | | case 11: |
| 2741 | | xtal = 31000000; |
| 2742 | | break; |
| 2743 | | case 12: |
| 2744 | | xtal = 94000000; |
| 2745 | | break; |
| 2746 | | case 13: |
| 2747 | | xtal = 65000000; |
| 2748 | | break; |
| 2749 | | case 14: |
| 2750 | | xtal = 75000000; |
| 2751 | | break; |
| 2752 | | case 15: |
| 2753 | | xtal = 71000000; |
| 2754 | | break; |
| 2755 | | default: |
| 2756 | | xtal = 1000000; |
| 2757 | | }*/ |
| 2758 | 2763 | } |
| 2759 | 2764 | else |
| 2760 | 2765 | { |
| r18791 | r18792 | |
|---|
| 2763 | 2768 | svga.rgb16_en = 0; |
| 2764 | 2769 | svga.rgb32_en = 0; |
| 2765 | 2770 | } |
| 2766 | | // if((vga.miscellaneous_output & 0xc) != 0x0c) |
| 2767 | | xtal = (vga.miscellaneous_output & 0xc) ? XTAL_28_63636MHz : XTAL_25_1748MHz; |
| 2768 | 2771 | recompute_params_clock(divisor, xtal); |
| 2769 | 2772 | } |
| 2770 | 2773 | |
| r18791 | r18792 | |
|---|
| 2960 | 2963 | case 0x55: |
| 2961 | 2964 | s3.extended_dac_ctrl = data; |
| 2962 | 2965 | break; |
| 2966 | /* |
| 2967 | 3d4h index 5Dh (R/W): Extended Horizontal Overflow Register (80x +) |
| 2968 | bit 0 Horizontal Total bit 8. Bit 8 of the Horizontal Total register (3d4h |
| 2969 | index 0) |
| 2970 | 1 Horizontal Display End bit 8. Bit 8 of the Horizontal Display End |
| 2971 | register (3d4h index 1) |
| 2972 | 2 Start Horizontal Blank bit 8. Bit 8 of the Horizontal Start Blanking |
| 2973 | register (3d4h index 2). |
| 2974 | 3 (864,964) EHB+64. End Horizontal Blank +64. If set the /BLANK pulse |
| 2975 | is extended by 64 DCLKs. Note: Is this bit 6 of 3d4h index 3 or |
| 2976 | does it really extend by 64 ? |
| 2977 | 4 Start Horizontal Sync Position bit 8. Bit 8 of the Horizontal Start |
| 2978 | Retrace register (3d4h index 4). |
| 2979 | 5 (864,964) EHS+32. End Horizontal Sync +32. If set the HSYNC pulse |
| 2980 | is extended by 32 DCLKs. Note: Is this bit 5 of 3d4h index 5 or |
| 2981 | does it really extend by 32 ? |
| 2982 | 6 (928,964) Data Transfer Position bit 8. Bit 8 of the Data Transfer |
| 2983 | Position register (3d4h index 3Bh) |
| 2984 | 7 (928,964) Bus-Grant Terminate Position bit 8. Bit 8 of the Bus Grant |
| 2985 | Termination register (3d4h index 5Fh). |
| 2986 | */ |
| 2987 | case 0x5d: |
| 2988 | vga.crtc.horz_total = (vga.crtc.horz_total & 0xfeff) | ((data & 0x01) << 8); |
| 2989 | vga.crtc.horz_disp_end = (vga.crtc.horz_disp_end & 0xfeff) | ((data & 0x02) << 7); |
| 2990 | vga.crtc.horz_blank_start = (vga.crtc.horz_blank_start & 0xfeff) | ((data & 0x04) << 6); |
| 2991 | vga.crtc.horz_retrace_start = (vga.crtc.horz_retrace_start & 0xfeff) | ((data & 0x10) << 4); |
| 2992 | s3_define_video_mode(); |
| 2993 | break; |
| 2994 | /* |
| 2995 | 3d4h index 5Eh (R/W): Extended Vertical Overflow Register (80x +) |
| 2996 | bit 0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h |
| 2997 | index 6). Bits 8 and 9 are in 3d4h index 7 bit 0 and 5. |
| 2998 | 1 Vertical Display End bit 10. Bit 10 of the Vertical Display End |
| 2999 | register (3d4h index 12h). Bits 8 and 9 are in 3d4h index 7 bit 1 |
| 3000 | and 6 |
| 3001 | 2 Start Vertical Blank bit 10. Bit 10 of the Vertical Start Blanking |
| 3002 | register (3d4h index 15h). Bit 8 is in 3d4h index 7 bit 3 and bit 9 |
| 3003 | in 3d4h index 9 bit 5 |
| 3004 | 4 Vertical Retrace Start bit 10. Bit 10 of the Vertical Start Retrace |
| 3005 | register (3d4h index 10h). Bits 8 and 9 are in 3d4h index 7 bit 2 |
| 3006 | and 7. |
| 3007 | 6 Line Compare Position bit 10. Bit 10 of the Line Compare register |
| 3008 | (3d4h index 18h). Bit 8 is in 3d4h index 7 bit 4 and bit 9 in 3d4h |
| 3009 | index 9 bit 6. |
| 3010 | */ |
| 3011 | case 0x5e: |
| 3012 | vga.crtc.vert_total = (vga.crtc.vert_total & 0xfbff) | ((data & 0x01) << 10); |
| 3013 | vga.crtc.vert_disp_end = (vga.crtc.vert_disp_end & 0xfbff) | ((data & 0x02) << 9); |
| 3014 | vga.crtc.vert_blank_start = (vga.crtc.vert_blank_start & 0xfbff) | ((data & 0x04) << 8); |
| 3015 | vga.crtc.vert_retrace_start = (vga.crtc.vert_retrace_start & 0xfbff) | ((data & 0x10) << 6); |
| 3016 | vga.crtc.line_compare = (vga.crtc.line_compare & 0xfbff) | ((data & 0x40) << 4); |
| 3017 | s3_define_video_mode(); |
| 3018 | break; |
| 2963 | 3019 | case 0x67: |
| 2964 | 3020 | s3.ext_misc_ctrl_2 = data; |
| 2965 | 3021 | s3_define_video_mode(); |