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r18778 Tuesday 30th October, 2012 at 10:46:04 UTC by Ryan Holtz

-avr8.c: Added FMUL, FMULS, and FMULSU opcodes. [MooglyGuy] -avr8.c: Fixed incorrect N flag calculation in ROR opcode. [MooglyGuy] -avr8.c: Fixed incorrect bit testing in SBIC/SBIS opcodes. [MooglyGuy] -craft.c: Added port D readback, fixes on-screen VU level. [MooglyGuy] -craft.c: Sync video with Vsync output, fixes rolling image. [MooglyGuy] -craft.c: Fixed visible area and promoted to working. [MooglyGuy]

[src/emu/cpu/avr8]	avr8.c avr8dasm.c
[src/mess/drivers]	craft.c

trunk/src/emu/cpu/avr8/avr8dasm.c

r18777	r18778
21	21	#define QCONST6(op)     ((((op) >> 8) & 0x0020) | (((op) >> 7) & 0x0018) | ((op) & 0x0007))
22	22	#define ACONST5(op)     (((op) >> 3) & 0x001f)
23	23	#define ACONST6(op)     ((((op) >> 5) & 0x0030) | ((op) & 0x000f))
	24	#define MULCONST2(op)   ((((op) >> 6) & 0x0002) | (((op) >> 3) & 0x0001))
24	25
25	26	CPU_DISASSEMBLE( avr8 )
26	27	{
r18777	r18778
44	45	output += sprintf( output, "MULS    R%d, R%d", 16+RD4(op), 16+RR4(op) );
45	46	break;
46	47	case 0x0300:
47		output += sprintf( output, "MULSU   R%d, R%d", 16+RD4(op), 16+RR4(op) );
	48	switch(MULCONST2(op))
	49	{
	50	case 0:
	51	output += sprintf( output, "MULSU   R%d, R%d", 16+RD3(op), 16+RR3(op) );
	52	break;
	53	case 1:
	54	output += sprintf( output, "FMUL    R%d, R%d", 16+RD3(op), 16+RR3(op) );
	55	break;
	56	case 2:
	57	output += sprintf( output, "FMULS   R%d, R%d", 16+RD3(op), 16+RR3(op) );
	58	break;
	59	case 3:
	60	output += sprintf( output, "FMULSU  R%d, R%d", 16+RD3(op), 16+RR3(op) );
	61	break;
	62	}
48	63	break;
49	64	case 0x0400:
50	65	case 0x0500:

trunk/src/emu/cpu/avr8/avr8.c

r18777	r18778
109	109	#define QCONST6(op)     ((((op) >> 8) & 0x0020) | (((op) >> 7) & 0x0018) | ((op) & 0x0007))
110	110	#define ACONST5(op)     (((op) >> 3) & 0x001f)
111	111	#define ACONST6(op)     ((((op) >> 5) & 0x0030) | ((op) & 0x000f))
	112	#define MULCONST2(op)   ((((op) >> 6) & 0x0002) | (((op) >> 3) & 0x0001))
112	113
113	114	// Register Defines
114	115	#define XREG            ((cpustate->r[27] << 8) | cpustate->r[26])
r18777	r18778
1009	1010
1010	1011	case AVR8_REGIDX_SPL:
1011	1012	case AVR8_REGIDX_SPH:
	1013	cpustate->r[offset] = data;
	1014	return true;
	1015
1012	1016	case AVR8_REGIDX_GPIOR0:
	1017	verboselog(cpustate->pc, 0, "AVR8: GPIOR0 Write: %02x\n", data);
1013	1018	cpustate->r[offset] = data;
1014	1019	return true;
1015	1020
r18777	r18778
1018	1023	return true;
1019	1024
1020	1025	default:
1021		verboselog(cpustate->pc, 0, "AVR8: Unrecognized register write: %02x = %02x\n", offset, data );
1022	1026	return false;
1023	1027	}
1024	1028	return false;
r18777	r18778
1032	1036	case AVR8_REGIDX_SPH:
1033	1037	case AVR8_REGIDX_TCNT1L:
1034	1038	case AVR8_REGIDX_TCNT1H:
1035		case AVR8_REGIDX_GPIOR0:
1036	1039	case AVR8_REGIDX_TCNT2:
1037	1040	*data = cpustate->r[offset];
1038	1041	return true;
1039	1042
	1043	case AVR8_REGIDX_GPIOR0:
	1044	*data = cpustate->r[offset];
	1045	verboselog(cpustate->pc, 0, "AVR8: GPIOR0 Read: %02x\n", *data);
	1046	return true;
	1047
1040	1048	case AVR8_REGIDX_SREG:
1041	1049	*data = cpustate->status;
1042	1050	return true;
1043	1051
1044	1052	default:
1045		verboselog(cpustate->pc, 0, "AVR8: Unrecognized register read: %02x\n", offset );
1046	1053	return false;
1047	1054	}
1048	1055
r18777	r18778
1160	1167	SREG_W(AVR8_SREG_Z, (sd == 0) ? 1 : 0);
1161	1168	opcycles = 2;
1162	1169	break;
1163		case 0x0300:    // MULSU Rd,Rr
1164		sd = (INT8)cpustate->r[16 + RD3(op)] * (UINT8)cpustate->r[16 + RR3(op)];
1165		cpustate->r[1] = (sd >> 8) & 0x00ff;
1166		cpustate->r[0] = sd & 0x00ff;
1167		SREG_W(AVR8_SREG_C, (sd & 0x8000) ? 1 : 0);
1168		SREG_W(AVR8_SREG_Z, (sd == 0) ? 1 : 0);
1169		opcycles = 2;
	1170	case 0x0300:    // Multiplicatn
	1171	switch(MULCONST2(op))
	1172	{
	1173	case 0x0000: // MULSU Rd,Rr
	1174	sd = (INT8)cpustate->r[16 + RD3(op)] * (UINT8)cpustate->r[16 + RR3(op)];
	1175	cpustate->r[1] = (sd >> 8) & 0x00ff;
	1176	cpustate->r[0] = sd & 0x00ff;
	1177	SREG_W(AVR8_SREG_C, (sd & 0x8000) ? 1 : 0);
	1178	SREG_W(AVR8_SREG_Z, (sd == 0) ? 1 : 0);
	1179	opcycles = 2;
	1180	break;
	1181	case 0x0001: // FMUL Rd,Rr
	1182	sd = (UINT8)cpustate->r[16 + RD3(op)] * (UINT8)cpustate->r[16 + RR3(op)];
	1183	sd <<= 1;
	1184	cpustate->r[1] = (sd >> 8) & 0x00ff;
	1185	cpustate->r[0] = sd & 0x00ff;
	1186	SREG_W(AVR8_SREG_C, (sd & 0x8000) ? 1 : 0);
	1187	SREG_W(AVR8_SREG_Z, (sd == 0) ? 1 : 0);
	1188	opcycles = 2;
	1189	break;
	1190	case 0x0002: // FMULS Rd,Rr
	1191	sd = (INT8)cpustate->r[16 + RD3(op)] * (INT8)cpustate->r[16 + RR3(op)];
	1192	sd <<= 1;
	1193	cpustate->r[1] = (sd >> 8) & 0x00ff;
	1194	cpustate->r[0] = sd & 0x00ff;
	1195	SREG_W(AVR8_SREG_C, (sd & 0x8000) ? 1 : 0);
	1196	SREG_W(AVR8_SREG_Z, (sd == 0) ? 1 : 0);
	1197	opcycles = 2;
	1198	break;
	1199	case 0x0003: // FMULSU Rd,Rr
	1200	sd = (INT8)cpustate->r[16 + RD3(op)] * (UINT8)cpustate->r[16 + RR3(op)];
	1201	sd <<= 1;
	1202	cpustate->r[1] = (sd >> 8) & 0x00ff;
	1203	cpustate->r[0] = sd & 0x00ff;
	1204	SREG_W(AVR8_SREG_C, (sd & 0x8000) ? 1 : 0);
	1205	SREG_W(AVR8_SREG_Z, (sd == 0) ? 1 : 0);
	1206	opcycles = 2;
	1207	break;
	1208	}
1170	1209	break;
1171	1210	case 0x0400:
1172	1211	case 0x0500:
r18777	r18778
1266	1305	rr = cpustate->r[RR5(op)];
1267	1306	rd &= rr;
1268	1307	SREG_W(AVR8_SREG_V, 0);
1269		SREG_W(AVR8_SREG_N, rd & 0x80);
	1308	SREG_W(AVR8_SREG_N, BIT(rd,7));
1270	1309	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
1271	1310	SREG_W(AVR8_SREG_Z, (rd == 0) ? 1 : 0);
1272	1311	cpustate->r[RD5(op)] = rd;
r18777	r18778
1276	1315	rr = cpustate->r[RR5(op)];
1277	1316	rd ^= rr;
1278	1317	SREG_W(AVR8_SREG_V, 0);
1279		SREG_W(AVR8_SREG_N, rd & 0x80);
	1318	SREG_W(AVR8_SREG_N, BIT(rd,7));
1280	1319	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
1281	1320	SREG_W(AVR8_SREG_Z, (rd == 0) ? 1 : 0);
1282	1321	cpustate->r[RD5(op)] = rd;
r18777	r18778
1286	1325	rr = cpustate->r[RR5(op)];
1287	1326	rd |= rr;
1288	1327	SREG_W(AVR8_SREG_V, 0);
1289		SREG_W(AVR8_SREG_N, rd & 0x80);
	1328	SREG_W(AVR8_SREG_N, BIT(rd,7));
1290	1329	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
1291	1330	SREG_W(AVR8_SREG_Z, (rd == 0) ? 1 : 0);
1292	1331	cpustate->r[RD5(op)] = rd;
r18777	r18778
1336	1375	rr = KCONST8(op);
1337	1376	rd |= rr;
1338	1377	SREG_W(AVR8_SREG_V, 0);
1339		SREG_W(AVR8_SREG_N, rd & 0x80);
	1378	SREG_W(AVR8_SREG_N, BIT(rd,7));
1340	1379	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
1341	1380	SREG_W(AVR8_SREG_Z, (rd == 0) ? 1 : 0);
1342	1381	cpustate->r[16 + RD4(op)] = rd;
r18777	r18778
1346	1385	rr = KCONST8(op);
1347	1386	rd &= rr;
1348	1387	SREG_W(AVR8_SREG_V, 0);
1349		SREG_W(AVR8_SREG_N, rd & 0x80);
	1388	SREG_W(AVR8_SREG_N, BIT(rd,7));
1350	1389	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
1351	1390	SREG_W(AVR8_SREG_Z, (rd == 0) ? 1 : 0);
1352	1391	cpustate->r[16 + RD4(op)] = rd;
r18777	r18778
1560	1599	case 0x0005:    // ASR Rd
1561	1600	rd = cpustate->r[RD5(op)];
1562	1601	res = (rd & 0x80) | (rd >> 1);
1563		SREG_W(AVR8_SREG_C, rd & 0x01);
	1602	SREG_W(AVR8_SREG_C, BIT(rd,0));
1564	1603	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
1565		SREG_W(AVR8_SREG_N, (rd & 0x80) ? 1 : 0);
	1604	SREG_W(AVR8_SREG_N, BIT(rd,7));
1566	1605	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
1567	1606	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
1568	1607	cpustate->r[RD5(op)] = res;
r18777	r18778
1570	1609	case 0x0006:    // LSR Rd
1571	1610	rd = cpustate->r[RD5(op)];
1572	1611	res = rd >> 1;
1573		SREG_W(AVR8_SREG_C, rd & 0x01);
	1612	SREG_W(AVR8_SREG_C, BIT(rd,0));
1574	1613	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 :0);
1575	1614	SREG_W(AVR8_SREG_N, 0);
1576	1615	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
r18777	r18778
1581	1620	rd = cpustate->r[RD5(op)];
1582	1621	res = rd >> 1;
1583	1622	res |= (SREG_R(AVR8_SREG_C) << 7);
1584		SREG_W(AVR8_SREG_C, rd & 0x01);
	1623	SREG_W(AVR8_SREG_C, BIT(rd,0));
1585	1624	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 :0);
1586		SREG_W(AVR8_SREG_N, res & 7);
	1625	SREG_W(AVR8_SREG_N, BIT(res,7));
1587	1626	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
1588	1627	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
1589	1628	cpustate->r[RD5(op)] = res;
r18777	r18778
1705	1744	case 0x0005:    // ASR Rd
1706	1745	rd = cpustate->r[RD5(op)];
1707	1746	res = (rd & 0x80) | (rd >> 1);
1708		SREG_W(AVR8_SREG_C, rd & 0x01);
	1747	SREG_W(AVR8_SREG_C, BIT(rd,0));
1709	1748	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
1710		SREG_W(AVR8_SREG_N, (rd & 0x80) ? 1 : 0);
	1749	SREG_W(AVR8_SREG_N, BIT(rd,7));
1711	1750	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
1712	1751	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
1713	1752	cpustate->r[RD5(op)] = res;
r18777	r18778
1715	1754	case 0x0006:    // LSR Rd
1716	1755	rd = cpustate->r[RD5(op)];
1717	1756	res = rd >> 1;
1718		SREG_W(AVR8_SREG_C, rd & 0x01);
	1757	SREG_W(AVR8_SREG_C, BIT(rd,0));
1719	1758	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 :0);
1720	1759	SREG_W(AVR8_SREG_N, 0);
1721	1760	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
r18777	r18778
1726	1765	rd = cpustate->r[RD5(op)];
1727	1766	res = rd >> 1;
1728	1767	res |= (SREG_R(AVR8_SREG_C) << 7);
1729		SREG_W(AVR8_SREG_C, rd & 0x01);
	1768	SREG_W(AVR8_SREG_C, BIT(rd,0));
1730	1769	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 :0);
1731		SREG_W(AVR8_SREG_N, res & 7);
	1770	SREG_W(AVR8_SREG_N, BIT(res,7));
1732	1771	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
1733	1772	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
1734	1773	cpustate->r[RD5(op)] = res;
r18777	r18778
1860	1899	opcycles = 2;
1861	1900	break;
1862	1901	case 0x0900:    // SBIC A,b
1863		if(NOT(BIT(READ_IO_8(cpustate, 32 + ACONST5(op)), (1 << RR3(op)))))
	1902	if(NOT(BIT(READ_IO_8(cpustate, 32 + ACONST5(op)), RR3(op))))
1864	1903	{
	1904	op = (UINT32)READ_PRG_16(cpustate, cpustate->pc + 1);
1865	1905	opcycles = avr8_is_long_opcode(op) ? 3 : 2;
1866	1906	cpustate->pc += avr8_is_long_opcode(op) ? 2 : 1;
1867	1907	}
r18777	r18778
1871	1911	opcycles = 2;
1872	1912	break;
1873	1913	case 0x0b00:    // SBIS A,b
1874		if(BIT(READ_IO_8(cpustate, 32 + ACONST5(op)), (1 << RR3(op))))
	1914	if(BIT(READ_IO_8(cpustate, 32 + ACONST5(op)), RR3(op)))
1875	1915	{
	1916	op = (UINT32)READ_PRG_16(cpustate, cpustate->pc + 1);
1876	1917	opcycles = avr8_is_long_opcode(op) ? 3 : 2;
1877	1918	cpustate->pc += avr8_is_long_opcode(op) ? 2 : 1;
1878	1919	}

trunk/src/mess/drivers/craft.c

r18777	r18778
44	44	* I/O defines                                        *
45	45	\****************************************************/
46	46
	47	#define AVR8_PORTD            (state->m_regs[AVR8_REGIDX_PORTD])
47	48	#define AVR8_DDRD            (state->m_regs[AVR8_REGIDX_DDRD])
48	49	#define AVR8_PORTC            (state->m_regs[AVR8_REGIDX_PORTC])
49	50	#define AVR8_DDRC            (state->m_regs[AVR8_REGIDX_DDRC])
r18777	r18778
82	83
83	84	UINT8 m_regs[0x100];
84	85	UINT8* m_eeprom;
85		UINT32 last_cycles;
	86	UINT32 m_last_cycles;
86	87
87		bool spi_pending;
88		UINT32 spi_start_cycle;
	88	bool m_spi_pending;
	89	UINT64 m_spi_start_cycle;
89	90
90		UINT8 m_pixels[PIXELS_PER_FRAME + LINE_CYCLES]; // Allocate one extra line for wrapping in the video update
	91	UINT64 m_frame_start_cycle;
91	92
	93	UINT8 m_pixels[PIXELS_PER_FRAME];
	94
92	95	required_device<cpu_device> m_maincpu;
93	96
94	97	DECLARE_READ8_MEMBER(avr8_read);
r18777	r18778
110	113	switch( offset )
111	114	{
112	115	case AVR8_REGIDX_EEDR:
	116	case AVR8_REGIDX_PORTC:
	117	case AVR8_REGIDX_PORTD:
113	118	return m_regs[offset];
114	119
115	120	default:
r18777	r18778
162	167	craft_state *state = machine.driver_data<craft_state>();
163	168
164	169	UINT64 cycles = avr8_get_elapsed_cycles(state->m_maincpu);
165		UINT32 frame_cycles = (UINT32)(cycles % CYCLES_PER_FRAME);
	170	UINT32 frame_cycles = (UINT32)(cycles - state->m_frame_start_cycle);
166	171
167		if (state->last_cycles < frame_cycles)
	172	if (state->m_last_cycles < frame_cycles)
168	173	{
169		for (UINT32 pixidx = state->last_cycles; pixidx < frame_cycles; pixidx++)
	174	for (UINT32 pixidx = state->m_last_cycles; pixidx < frame_cycles; pixidx++)
170	175	{
171	176	UINT8 value = AVR8_PORTC & 0x3f;
172		if (state->spi_pending)
	177	if (state->m_spi_pending)
173	178	{
174		if (pixidx >= state->spi_start_cycle && pixidx < (state->spi_start_cycle + 16))
	179	if (pixidx >= state->m_spi_start_cycle && pixidx < (state->m_spi_start_cycle + 16))
175	180	{
176		UINT8 bitidx = 7 - ((pixidx - state->spi_start_cycle) >> 1);
	181	UINT8 bitidx = 7 - ((pixidx - state->m_spi_start_cycle) >> 1);
177	182	value = ((state->m_regs[AVR8_REGIDX_SPDR] & (1 << bitidx)) ? value : 0x3f);
178		if (pixidx == (state->spi_start_cycle + 15))
	183	if (pixidx == (state->m_spi_start_cycle + 15))
179	184	{
180		state->spi_pending = false;
	185	state->m_spi_pending = false;
181	186	state->m_regs[AVR8_REGIDX_SPDR] = 0;
182	187	}
183	188	}
r18777	r18778
185	190	state->m_pixels[pixidx] = value;
186	191	}
187	192	}
	193	else
	194	{
	195	memset(state->m_pixels + state->m_last_cycles, 0, sizeof(state->m_pixels) - state->m_last_cycles);
	196	memset(state->m_pixels, 0, frame_cycles);
	197	}
188	198
189		state->last_cycles = frame_cycles;
	199	state->m_last_cycles = frame_cycles;
190	200	}
191	201
192	202	static void avr8_change_port(running_machine &machine, int reg, UINT8 data)
r18777	r18778
204	214	//verboselog(machine, 0, "avr8_change_port: PORT%c lines %02x changed\n", avr8_reg_name[reg], changed);
205	215	}
206	216
207		if (reg == AVR8_REG_C)
	217	switch(reg)
208	218	{
209		avr8_video_update(machine);
	219	case AVR8_REG_A:
	220	// Unhandled
	221	break;
210	222
211		/*if (frame_cycles >= state->spi_start_cycle && frame_cycles < (state->spi_start_cycle + 16))
212		{
213		UINT8 bitidx = 7 - ((frame_cycles - state->spi_start_cycle) >> 1);
214		state->m_pixels[frame_cycles] = ((state->m_regs[AVR8_REGIDX_SPDR] & (1 << bitidx)) ? 0x3f : (data & 0x3f));
215		}
216		else
217		{
218		state->m_pixels[frame_cycles] = data & 0x3f;
219		}*/
	223	case AVR8_REG_B:
	224	AVR8_PORTB = data;
	225	if(newport & changed & 0x02)
	226	{
	227	state->m_frame_start_cycle = avr8_get_elapsed_cycles(state->m_maincpu);
	228	}
	229	break;
220	230
221		AVR8_PORTC = data;
222		}
	231	case AVR8_REG_C:
	232	avr8_video_update(machine);
	233	AVR8_PORTC = data;
	234	break;
223	235
224		if (reg == AVR8_REG_D)
225		{
226		UINT8 audio_sample = (data & 0x02) | ((data & 0xf4) >> 2);
227
228		state->dac->write_unsigned8(audio_sample << 2);
	236	case AVR8_REG_D:
	237	{
	238	UINT8 audio_sample = (data & 0x02) | ((data & 0xf4) >> 2);
	239	state->dac->write_unsigned8(audio_sample << 2);
	240	AVR8_PORTD = data;
	241	break;
	242	}
229	243	}
230	244	}
231	245
r18777	r18778
357	371	case AVR8_REGIDX_SPDR:
358	372	avr8_video_update(machine());
359	373	m_regs[offset] = data;
360		spi_pending = true;
361		spi_start_cycle = (UINT32)(avr8_get_elapsed_cycles(m_maincpu) % CYCLES_PER_FRAME);
	374	m_spi_pending = true;
	375	m_spi_start_cycle = avr8_get_elapsed_cycles(m_maincpu) - m_frame_start_cycle;
362	376	break;
363	377
364	378	case AVR8_REGIDX_EECR:
r18777	r18778
437	451	UINT32 *line = &bitmap.pix32(y);
438	452	for(int x = 0; x < LINE_CYCLES; x++)
439	453	{
440		UINT8 pixel = m_pixels[y * LINE_CYCLES + (x + HSYNC_CYCLES)];
	454	UINT8 pixel = m_pixels[y * LINE_CYCLES + x];
441	455	UINT8 r = 0x55 * ((pixel & 0x30) >> 4);
442	456	UINT8 g = 0x55 * ((pixel & 0x0c) >> 2);
443	457	UINT8 b = 0x55 * (pixel & 0x03);
444	458	line[x] = 0xff000000 | (r << 16) | (g << 8) | b;
445
446		// Clear behind us
447		m_pixels[y * LINE_CYCLES + (x + HSYNC_CYCLES)] = 0;
448	459	}
449	460	}
450	461	return 0;
r18777	r18778
467	478	state->dac->write_unsigned8(0x00);
468	479
469	480	state->m_eeprom = memregion("eeprom")->base();
	481
	482	state->m_frame_start_cycle = 0;
	483	state->m_last_cycles = 0;
	484
	485	state->m_spi_pending = false;
	486
	487	state->m_spi_start_cycle = 0;
470	488	}
471	489
472	490	static MACHINE_CONFIG_START( craft, craft_state )
r18777	r18778
482	500	MCFG_SCREEN_REFRESH_RATE(59.99)
483	501	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(1429)) /* accurate */
484	502	MCFG_SCREEN_SIZE(635, 525)
485		MCFG_SCREEN_VISIBLE_AREA(0, 634, 0, 524)
	503	MCFG_SCREEN_VISIBLE_AREA(47, 526, 36, 515)
486	504	MCFG_SCREEN_UPDATE_DRIVER(craft_state, screen_update_craft)
487	505	MCFG_PALETTE_LENGTH(0x1000)
488	506
r18777	r18778
500	518	ROM_END
501	519
502	520	/*   YEAR  NAME      PARENT    COMPAT    MACHINE   INPUT     INIT      COMPANY          FULLNAME */
503		CONS(2008, craft,    0,        0,        craft,    craft, craft_state,    craft,    "Linus Akesson", "Craft", GAME_NO_SOUND | GAME_NOT_WORKING)
	521	CONS(2008, craft,    0,        0,        craft,    craft, craft_state,    craft,    "Linus Akesson", "Craft", GAME_IMPERFECT_GRAPHICS)

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