MAME SVN History

199869 Revisions

r18775 Tuesday 30th October, 2012 at 07:07:38 UTC by Miodrag Milanović
Clean-ups and version bump

[hash]	amiga1000_flop.xml amiga1200_flop.xml amiga500_flop.xml amiga500plus_flop.xml amiga600_flop.xml amiga_flop.xml amigaaga_flop.xml coco_cart.xml pentagon_cass.xml spectrum_cass.xml
[src]	version.c
[src/emu]	delegate.h devcb2.c devcb2.h driver.h
[src/emu/cpu/avr8]	avr8.c
[src/emu/cpu/rsp]	rsp.h rspdrc.c
[src/emu/machine]	i8243.h pla.c scsicb.c
[src/emu/sound]	2151intf.c 2151intf.h
[src/emu/video]	mc6845.c mc6845.h pc_vga.c
[src/lib/formats]	tzx_cas.c upd765_dsk.c
[src/mame]	mame.lst
[src/mame/audio]	gottlieb.c
[src/mame/drivers]	3x3puzzl.c 8080bw.c aerofgt.c bingoman.c chihiro.c cops.c dblcrown.c dec0.c exidy.c funworld.c inufuku.c jpmimpct.c jpmsru.c lethalj.c maygay1b.c mcr3.c mpu12wbk.c namcos23.c naomi.c nemesis.c nmk16.c peyper.c pgm.c portrait.c rpunch.c s3.c s4.c s6.c s6a.c s8.c s9.c scobra.c suna16.c
[src/mame/includes]	aerofgt.h carpolo.h gottlieb.h gstriker.h liberatr.h suprslam.h
[src/mame/layout]	seawolf.lay seawolf2.lay
[src/mame/machine]	atarigen.c atarigen.h pgmprot1.c
[src/mame/video]	vsystem_spr.c vsystem_spr.h vsystem_spr2.c vsystem_spr2.h
[src/mess]	mess.lst
[src/mess/drivers]	a2600.c a7800.c amiga.c b2m.c c128.c c64.c cbm2.c craft.c hp9k.c mac.c plus4.c prof180x.c spectrum.c
[src/mess/includes]	c128.h fidelz80.h samcoupe.h
[src/mess/machine]	64h156.c b2m.c c128_comal80.c c8280.c cbm2_graphic.c isa_ide.c macadb.c macrtc.c macrtc.h mos8722.c rmnimbus.c upd765.c upd765.h vcsctrl.h
[src/mess/video]	mos6566.c mos6566.h nubus_m2video.c pds30_30hr.c pds30_cb264.c pds30_mc30.c pds30_procolor816.c pds30_sigmalview.c spectrum.c timex.c
[src/tools]	jedutil.c

trunk/hash/amiga_flop.xml
r18774	r18775
10	10	<description>Pinball Dreams</description>
11	11	<year>1992</year>
12	12	<publisher>21st Century Entertainment</publisher>
13
	13
14	14	<part name="flop1" interface="floppy_3_5">
15	15	<feature name="part_id" value="Disk 1" />
16	16	<dataarea name="flop" size="912864">
r18774	r18775
51	51
52	52	<!-- SPS Release -->
53	53	<software name="pballfnt">
54
	54
55	55	<description>Pinball Fantasies</description>
56	56	<year>1992</year>
57	57	<publisher>21st Century Entertainment</publisher>
58
	58
59	59	<part name="flop1" interface="floppy_3_5">
60	60	<feature name="part_id" value="Disk 1" />
61	61	<dataarea name="flop" size="1024172">
r18774	r18775
82	82	<dataarea name="flop" size="1024172">
83	83	<rom name="pinballfantasies_coursedisk3.ipf" size="1024172" crc="b63ad767" sha1="04620de7ce3bd25ee7c4a9e0af88f3fb19ccc855" offset="0"/>
84	84	</dataarea>
85		</part>
	85	</part>
86	86	</software>
87	87
88	88
r18774	r18775
99	99	<rom name="e-motion.ipf" size="1036838" crc="23088ad2" sha1="5c4001ebd8f03ad1e4307c8ab1776db95228c872" offset="0"/>
100	100	</dataarea>
101	101	</part>
102
	102
103	103	</software>
104	104
105	105	</softwarelist>

trunk/hash/spectrum_cass.xml
r18774	r18775
17	17
18	18	<!-- COMPATIBILITY
19	19	The MESS emulation at the time of writing isn't very good, the following emulators are used to determine how things should work
20
	20
21	21	EmuZWin (v2.7 release 2.8) - Closed Source, runs some images (Gremlin 2 type*) which fail on the emulators below - http://kolmck.net/apps/EmuZWin_Eng.htm
22	22	Fuse (Free Unix Spectrum Emulator) - Free, High Compatibility can run some of the trickier images, Windows port available - http://fuse-emulator.sourceforge.net/
23		Spectaculator - Commercial, a bit more user friendly than above, similar compatibility - http://www.spectaculator.com/
24
	23	Spectaculator - Commercial, a bit more user friendly than above, similar compatibility - http://www.spectaculator.com/
	24
25	25	Note, even with those emulators you'll have to turn off some of the speed cheats on loading to get good compatibilty for example, in Fuse
26	26	Use Tape Traps
27	27	Fastloading
28	28	Detect Loaders
29	29	Accelerate Loaders
30
	30
31	31	MESS doesn't have any accelerated loading so some games which require the tricks to be disabled in other emulators work in MESS without trickery, eg Xanthius
32
	32
33	33	http://newton.sunderland.ac.uk/~specfreak/Schemes/schemes.html is a rather outdated guide mentioning some of the custom loaders, and showing disassemblies of them.
34
	34
35	35	legacy emulators including Real Spectrum ( http://zxm.speccy.cz/realspec/ ) appear to struggle with some of the more complex tape protections
36	36
37	37	* Gremlin 2 type images include 'M.A.S.K' and 'Basil The Great Mouse Detective'
38
39
40	38
41	39
	40
	41
42	42	-->
43	43
44	44
r18774	r18775
457	457	<part name="cass" interface="spectrum_cass">
458	458	<dataarea name="cass" size="42011">
459	459	<rom name="snare - alternate - side a.tzx" size="42011" crc="48239344" sha1="eeaab4c697e35e2f7bd452906314948134933cfc" offset="0"/>
460		<!-- side B is for the Sam Coupe, see samcoupe_cass.xml -->
	460	<!-- side B is for the Sam Coupe, see samcoupe_cass.xml -->
461	461	</dataarea>
462	462	</part>
463	463	</software>

trunk/hash/amiga600_flop.xml
r18774	r18775
15	15	<dataarea name="flop" size="901120">
16	16	<rom name="workbench v2.05 rev 37.71 (1992)(commodore)(disk 1 of 4)(workbench).adf" size="901120" crc="be1cc8b9" sha1="4d5c1830e04d1302fdad1eb85638104ab94fb353" offset="0"/>
17	17	</dataarea>
18		</part>
	18	</part>
19	19
20	20	<part name="flop2" interface="floppy_3_5">
21	21	<feature name="part_id" value="Extras" />

trunk/hash/amiga1200_flop.xml
r18774	r18775
51	51	<rom name="workbench v3.0 rev 39.29 (1992)(commodore)(a1200-a4000)(m10)(disk 6 of 6)(fonts).adf" size="901120" crc="d7364bb4" sha1="4531651fe34a7f0a2dc1a1523ed4c2507670f5a6" offset="0"/>
52	52	</dataarea>
53	53	</part>
54
	54
55	55	</software>
56	56
57	57	</softwarelist>

trunk/hash/amiga500plus_flop.xml
r18774	r18775
15	15	<dataarea name="flop" size="901120">
16	16	<rom name="workbench v2.04 rev 37.67 (1991)(commodore)(disk 1 of 4)(workbench).adf" size="901120" crc="57714d34" sha1="8d5c0310a86f14fb3e6a1da001ceb50b9a592c51" offset="0"/>
17	17	</dataarea>
18		</part>
	18	</part>
19	19
20	20	<part name="flop2" interface="floppy_3_5">
21	21	<feature name="part_id" value="Extras" />

trunk/hash/coco_cart.xml
r18774	r18775
45	45	- JDOS v1.23 overdumped, trim to 8K works fine
46	46	- Spectaculator proper dump is 8K
47	47	- Cumana DOS v2.0
48
	48
49	49	* Notes: Mindroll, Robocop and Predator all have banking.
50	50	(see https://archive.org/stream/rainbowmagazine-1990-06/The_Rainbow_Magazine_06_1990#page/n59/mode/1up
51	51	for technique for the latter two)

trunk/hash/amiga1000_flop.xml
r18774	r18775
27	27	<dataarea name="flop" size="901120">
28	28	<rom name="kickstart-disk v1.3 r34.5 (1987)(commodore)(a1000).adf" size="901120" crc="5fd0ef3b" sha1="a80b001b98a997969bf709cecd07f8578f861148" offset="0"/>
29	29	</dataarea>
30		</part>
	30	</part>
31	31	</software>
32
	32
33	33	<!-- Todo, other Kickstart disks, and appropriate Workbench disks -->
34
	34
35	35	</softwarelist>
36	36
37	37

trunk/hash/amigaaga_flop.xml
r18774	r18775
1	1	<?xml version="1.0"?>
2	2	<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
3	3
4		<!-- General purpose software list for Amiga software requiring the AGA chipset (A1200 / A4000)
5
	4	<!-- General purpose software list for Amiga software requiring the AGA chipset (A1200 / A4000)
	5
6	6	the software listed here is not designed for use on systems without the AGA chipset and
7	7	will not function.
8	8	-->
r18774	r18775
116	116	<rom name="pinballillusions_disk4.ipf" size="1049612" crc="e551bc40" sha1="05757f0e6289385df204c2ced4fb0348aa4b39ee" offset="0"/>
117	117	</dataarea>
118	118	</part>
119
	119
120	120	</software>
121	121
122	122	<!-- simple 1 disk game using AGA mode -->

trunk/hash/amiga500_flop.xml
r18774	r18775
15	15	<dataarea name="flop" size="901120">
16	16	<rom name="workbench v1.3 rev 34.20 (1988)(commodore)(a500-a2000)(gb)(disk 1 of 2)(workbench).adf" size="901120" crc="30bef4c6" sha1="44bace7520746691969d08f28dd68ef5ab2f15fb" offset="0"/>
17	17	</dataarea>
18		</part>
	18	</part>
19	19
20	20	<part name="flop2" interface="floppy_3_5">
21	21	<feature name="part_id" value="Extras" />

trunk/hash/pentagon_cass.xml
r18774	r18775
1	1	<?xml version="1.0"?>
2	2	<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
3	3
4		<!-- Preliminary list.
	4	<!-- Preliminary list.
5	5
6	6	This list contains software for the Russian 'Pentagon 128' systems.
7
	7
8	8	These systems are Spectrum clones, but offer various extended features.
9
	9
10	10	The software listed here will not function correctly (if at all) on a regular Spectrum
11	11	-->
12	12
r18774	r18775
22	22	</dataarea>
23	23	</part>
24	24	</software>
25
	25
26	26	</softwarelist>
27	27
28	28

trunk/src/mame/includes/aerofgt.h
r18774	r18775
57	57
58	58	/* other devices */
59	59	cpu_device *m_audiocpu;
60
	60
61	61	/* handlers */
62	62	DECLARE_WRITE16_MEMBER(sound_command_w);
63	63	DECLARE_WRITE16_MEMBER(turbofrc_sound_command_w);

trunk/src/mame/includes/gstriker.h
r18774	r18775
43	43	m_VS920A_vram(*this, "vs920a_vram"),
44	44	m_work_ram(*this, "work_ram"),
45	45	m_lineram(*this, "lineram"),
46		m_spr(*this, "vsystem_spr")
	46	m_spr(*this, "vsystem_spr")
47	47	{ }
48	48
49	49	virtual void machine_start()

trunk/src/mame/includes/suprslam.h
r18774	r18775
34	34	UINT16 m_screen_bank;
35	35	UINT16 m_bg_bank;
36	36	UINT32 suprslam_tile_callback( UINT32 code );
37
	37
38	38	/* misc */
39	39	int m_pending_command;
40	40

trunk/src/mame/includes/carpolo.h
r18774	r18775
82	82	DECLARE_WRITE_LINE_MEMBER(carpolo_7474_2s_2_q_cb);
83	83	DECLARE_WRITE_LINE_MEMBER(carpolo_7474_2u_1_q_cb);
84	84	DECLARE_WRITE_LINE_MEMBER(carpolo_7474_2u_2_q_cb);
85
	85
86	86	};
87	87
88	88

trunk/src/mame/includes/liberatr.h
r18774	r18775
36	36	protected:
37	37	virtual void machine_start();
38	38	virtual void video_start();
39
	39
40	40	virtual void update_interrupts() { }
41	41
42	42	struct planet;

trunk/src/mame/includes/gottlieb.h
r18774	r18775
281	281	double m_weights[4];
282	282
283	283	void qbert_knocker(UINT8 knock);
284
	284
285	285	DECLARE_WRITE8_MEMBER(gottlieb_analog_reset_w);
286	286	DECLARE_WRITE8_MEMBER(general_output_w);
287	287	DECLARE_WRITE8_MEMBER(reactor_output_w);

trunk/src/mame/video/vsystem_spr.c
r18774	r18775
218	218	curr_sprite.zoomy = 32 - curr_sprite.zoomy;
219	219
220	220	int ystart, yend, yinc;
221
	221
222	222	if (!curr_sprite.flipy) { ystart = 0; yend = curr_sprite.ysize+1; yinc = 1; }
223	223	else { ystart = curr_sprite.ysize; yend = -1; yinc = -1; }
224	224
r18774	r18775
237	237	if (m_pdraw)
238	238	{
239	239	pdrawgfxzoom_transpen(bitmap, cliprect, gfx, startno, curr_sprite.color + m_pal_base, curr_sprite.flipx, curr_sprite.flipy, curr_sprite.ox + xcnt * curr_sprite.zoomx/2, curr_sprite.oy + ycnt * curr_sprite.zoomy/2, curr_sprite.zoomx << 11, curr_sprite.zoomy << 11, machine.priority_bitmap,priority_mask, m_transpen);
240		pdrawgfxzoom_transpen(bitmap, cliprect, gfx, startno, curr_sprite.color + m_pal_base, curr_sprite.flipx, curr_sprite.flipy, -0x200+curr_sprite.ox + xcnt * curr_sprite.zoomx/2, curr_sprite.oy + ycnt * curr_sprite.zoomy/2, curr_sprite.zoomx << 11, curr_sprite.zoomy << 11, machine.priority_bitmap,priority_mask, m_transpen);
	240	pdrawgfxzoom_transpen(bitmap, cliprect, gfx, startno, curr_sprite.color + m_pal_base, curr_sprite.flipx, curr_sprite.flipy, -0x200+curr_sprite.ox + xcnt * curr_sprite.zoomx/2, curr_sprite.oy + ycnt * curr_sprite.zoomy/2, curr_sprite.zoomx << 11, curr_sprite.zoomy << 11, machine.priority_bitmap,priority_mask, m_transpen);
241	241	pdrawgfxzoom_transpen(bitmap, cliprect, gfx, startno, curr_sprite.color + m_pal_base, curr_sprite.flipx, curr_sprite.flipy, curr_sprite.ox + xcnt * curr_sprite.zoomx/2, -0x200+curr_sprite.oy + ycnt * curr_sprite.zoomy/2, curr_sprite.zoomx << 11, curr_sprite.zoomy << 11, machine.priority_bitmap,priority_mask, m_transpen);
242		pdrawgfxzoom_transpen(bitmap, cliprect, gfx, startno, curr_sprite.color + m_pal_base, curr_sprite.flipx, curr_sprite.flipy, -0x200+curr_sprite.ox + xcnt * curr_sprite.zoomx/2, -0x200+curr_sprite.oy + ycnt * curr_sprite.zoomy/2, curr_sprite.zoomx << 11, curr_sprite.zoomy << 11, machine.priority_bitmap,priority_mask, m_transpen);
	242	pdrawgfxzoom_transpen(bitmap, cliprect, gfx, startno, curr_sprite.color + m_pal_base, curr_sprite.flipx, curr_sprite.flipy, -0x200+curr_sprite.ox + xcnt * curr_sprite.zoomx/2, -0x200+curr_sprite.oy + ycnt * curr_sprite.zoomy/2, curr_sprite.zoomx << 11, curr_sprite.zoomy << 11, machine.priority_bitmap,priority_mask, m_transpen);
243	243	}
244	244	else
245	245	{
246	246	drawgfxzoom_transpen(bitmap, cliprect, gfx, startno, curr_sprite.color + m_pal_base, curr_sprite.flipx, curr_sprite.flipy, curr_sprite.ox + xcnt * curr_sprite.zoomx/2, curr_sprite.oy + ycnt * curr_sprite.zoomy/2, curr_sprite.zoomx << 11, curr_sprite.zoomy << 11, m_transpen);
247		drawgfxzoom_transpen(bitmap, cliprect, gfx, startno, curr_sprite.color + m_pal_base, curr_sprite.flipx, curr_sprite.flipy, -0x200+curr_sprite.ox + xcnt * curr_sprite.zoomx/2, curr_sprite.oy + ycnt * curr_sprite.zoomy/2, curr_sprite.zoomx << 11, curr_sprite.zoomy << 11, m_transpen);
	247	drawgfxzoom_transpen(bitmap, cliprect, gfx, startno, curr_sprite.color + m_pal_base, curr_sprite.flipx, curr_sprite.flipy, -0x200+curr_sprite.ox + xcnt * curr_sprite.zoomx/2, curr_sprite.oy + ycnt * curr_sprite.zoomy/2, curr_sprite.zoomx << 11, curr_sprite.zoomy << 11, m_transpen);
248	248	drawgfxzoom_transpen(bitmap, cliprect, gfx, startno, curr_sprite.color + m_pal_base, curr_sprite.flipx, curr_sprite.flipy, curr_sprite.ox + xcnt * curr_sprite.zoomx/2, -0x200+curr_sprite.oy + ycnt * curr_sprite.zoomy/2, curr_sprite.zoomx << 11, curr_sprite.zoomy << 11, m_transpen);
249		drawgfxzoom_transpen(bitmap, cliprect, gfx, startno, curr_sprite.color + m_pal_base, curr_sprite.flipx, curr_sprite.flipy, -0x200+curr_sprite.ox + xcnt * curr_sprite.zoomx/2, -0x200+curr_sprite.oy + ycnt * curr_sprite.zoomy/2, curr_sprite.zoomx << 11, curr_sprite.zoomy << 11, m_transpen);
	249	drawgfxzoom_transpen(bitmap, cliprect, gfx, startno, curr_sprite.color + m_pal_base, curr_sprite.flipx, curr_sprite.flipy, -0x200+curr_sprite.ox + xcnt * curr_sprite.zoomx/2, -0x200+curr_sprite.oy + ycnt * curr_sprite.zoomy/2, curr_sprite.zoomx << 11, curr_sprite.zoomy << 11, m_transpen);
250	250	}
251	251	xcnt+=xinc;
252	252	}
253	253	ycnt+=yinc;
254	254	}
255
	255
256	256	}
257	257
258	258

trunk/src/mame/video/vsystem_spr.h
r18774	r18775
14	14
15	15	#define MCFG_VSYSTEM_SPR_SET_PALMASK( _palmask ) \
16	16	vsystem_spr_device::set_pal_mask(*device, _palmask); \
17
	17
18	18	#define MCFG_VSYSTEM_SPR_SET_TRANSPEN( _transpen ) \
19	19	vsystem_spr_device::CG10103_set_transpen(*device, _transpen); \
20	20

trunk/src/mame/video/vsystem_spr2.c
r18774	r18775
122	122	sx = ((curr_sprite.ox + curr_sprite.zoomx * x / 2 + 16) & 0x1ff) - 16;
123	123
124	124	curr = spriteram1[curr_sprite.map % (spriteram1_bytes/2)];
125
	125
126	126	pdrawgfxzoom_transpen(bitmap,cliprect,machine.gfx[sprite_gfx],
127	127	curr,
128	128	curr_sprite.color,
r18774	r18775
200	200	sx = ((curr_sprite.ox + curr_sprite.zoomx * x / 2 + 16) & 0x1ff) - 16;
201	201
202	202	curr = spriteram1[curr_sprite.map % (spriteram1_bytes/2)];
203
	203
204	204	pdrawgfxzoom_transpen(bitmap,cliprect,machine.gfx[sprite_gfx],
205	205	curr,
206	206	curr_sprite.color,
r18774	r18775
399	399	{
400	400	static const UINT8 zoomtable[16] = { 0,7,14,20,25,30,34,38,42,46,49,52,54,57,59,61 };
401	401	const rectangle &visarea = screen.visible_area();
402		// UINT8 *spriteram = spriteram;
	402	// UINT8 *spriteram = spriteram;
403	403	int offs;
404	404
405	405	/* draw the sprites */
r18774	r18775
413	413	{
414	414	if (!get_sprite_attributes((UINT16*)&spriteram[offs]))
415	415	continue;
416
	416
417	417	curr_sprite.ysize++;
418	418	curr_sprite.xsize++;
419	419	curr_sprite.oy -= 6;
420	420	curr_sprite.ox -= 13;
421	421
422	422
423
	423
424	424	int xt, yt;
425	425
426	426

trunk/src/mame/video/vsystem_spr2.h
r18774	r18775
5	5	{
6	6	public:
7	7	vsystem_spr2_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
8
	8
9	9	struct vsystem_sprite_attributes
10	10	{
11	11	int ox;
r18774	r18775
26	26
27	27	template<class _BitmapClass>
28	28	void turbofrc_draw_sprites_common( UINT16* spriteram3, int spriteram3_bytes, UINT16* spriteram1, int spriteram1_bytes, int sprite_gfx, int spritepalettebank, running_machine &machine, _BitmapClass &bitmap, const rectangle &cliprect, int chip_disabled_pri );
29
	29
30	30	void turbofrc_draw_sprites( UINT16* spriteram3, int spriteram3_bytes, UINT16* spriteram1, int spriteram1_bytes, int sprite_gfx, int spritepalettebank, running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, int chip_disabled_pri );
31	31	void turbofrc_draw_sprites( UINT16* spriteram3, int spriteram3_bytes, UINT16* spriteram1, int spriteram1_bytes, int sprite_gfx, int spritepalettebank, running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect, int chip_disabled_pri );
32	32
33	33	template<class _BitmapClass>
34	34	void spinlbrk_draw_sprites_common( UINT16* spriteram3, int spriteram3_bytes, UINT16* spriteram1, int spriteram1_bytes, int sprite_gfx, int spritepalettebank, running_machine &machine, _BitmapClass &bitmap, const rectangle &cliprect, int chip_disabled_pri );
35
	35
36	36	void spinlbrk_draw_sprites( UINT16* spriteram3, int spriteram3_bytes, UINT16* spriteram1, int spriteram1_bytes, int sprite_gfx, int spritepalettebank, running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, int chip_disabled_pri );
37	37	void spinlbrk_draw_sprites( UINT16* spriteram3, int spriteram3_bytes, UINT16* spriteram1, int spriteram1_bytes, int sprite_gfx, int spritepalettebank, running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect, int chip_disabled_pri );
38	38

trunk/src/mame/layout/seawolf.lay
r18774	r18775
80	80	<color red="0.25" green="0.05" blue="0.0" />
81	81	<bounds x="1.5" y="0" width="1" height="1" />
82	82	</disk>
83
	83
84	84	<rect state="1">
85	85	<color red="1.0" green="0.25" blue="0.10" />
86	86	<bounds x="0.5" y="0" width="1.5" height="1" />
r18774	r18775
114	114	<color red="0.25" green="0.05" blue="0.0" />
115	115	<bounds x="1.5" y="0" width="1" height="1" />
116	116	</disk>
117
	117
118	118	<rect state="1">
119	119	<color red="1.0" green="0.25" blue="0.10" />
120	120	<bounds x="0.5" y="0" width="1.5" height="1" />

trunk/src/mame/layout/seawolf2.lay
r18774	r18775
73	73	<color red="0.25" green="0.05" blue="0.0" />
74	74	<bounds x="1.5" y="0" width="1" height="1" />
75	75	</disk>
76
	76
77	77	<rect state="1">
78	78	<color red="1.0" green="0.25" blue="0.10" />
79	79	<bounds x="0.5" y="0" width="1.5" height="1" />
r18774	r18775
107	107	<color red="0.25" green="0.05" blue="0.0" />
108	108	<bounds x="1.5" y="0" width="1" height="1" />
109	109	</disk>
110
	110
111	111	<rect state="1">
112	112	<color red="1.0" green="0.25" blue="0.10" />
113	113	<bounds x="0.5" y="0" width="1.5" height="1" />

trunk/src/mame/drivers/exidy.c
r18774	r18775
1019	1019	ROM_LOAD( "targ82s.123", 0x0000, 0x0020, CRC(9eb9125c) SHA1(660ad9b2c7c28c3fda4b10c1401c03165d131c61) ) /* unknown */
1020	1020	ROM_END
1021	1021
1022		ROM_START( rallysa )
	1022	ROM_START( rallysa )
1023	1023	ROM_REGION( 0x10000, "maincpu", 0 )
1024	1024	ROM_LOAD( "rallys.01", 0x1000, 0x0400, CRC(a192b22b) SHA1(aaae0b1822f934df30b354f787ffa8848c71b52f) ) // 1a
1025	1025	ROM_LOAD( "rallys.02", 0x1400, 0x0400, CRC(19e730aa) SHA1(4f4e87d26c14a9ff2be5b4173c4e5804db551e33) ) // 2a

trunk/src/mame/drivers/aerofgt.c
r18774	r18775
1612	1612
1613	1613	MCFG_DEVICE_ADD("vsystem_spr_old", VSYSTEM_SPR2, 0)
1614	1614	MCFG_DEVICE_ADD("vsystem_spr_ol2", VSYSTEM_SPR2, 0)
1615
	1615
1616	1616	MCFG_VIDEO_START_OVERRIDE(aerofgt_state,turbofrc)
1617	1617
1618	1618	/* sound hardware */

trunk/src/mame/drivers/suna16.c
r18774	r18775
121	121	case 0x0311/2:
122	122	ret = 0x03;
123	123	break;
124
	124
125	125	default:
126	126	//logerror("uballoon_prot_r %04X\n", offset);
127	127	break;
r18774	r18775
137	137	case 0x0001/2:
138	138	m_prot = data;
139	139	break;
140
	140
141	141	default:
142	142	//logerror("uballoon_prot_w %04X=%02X\n", offset, data);
143	143	break;

trunk/src/mame/drivers/nmk16.c
r18774	r18775
900	900	AM_RANGE(0x0d0000, 0x0d07ff) AM_RAM_WRITE(nmk_txvideoram_w) AM_SHARE("nmk_txvideoram")
901	901	ADDRESS_MAP_END
902	902
903		// No sprites without this. Is it actually protection?
	903	// No sprites without this. Is it actually protection?
904	904	READ16_MEMBER(nmk16_state::tdragonb_prot_r)
905	905	{
906	906	return 0x0003;

trunk/src/mame/drivers/8080bw.c
r18774	r18775
683	683	/* basic machine hardware */
684	684	MCFG_CPU_MODIFY("maincpu")
685	685	MCFG_CPU_IO_MAP(invrvnge_io_map)
686
	686
687	687	MCFG_CPU_ADD("audiocpu", M6808, XTAL_4MHz/2) // MC6808P
688	688	MCFG_CPU_PROGRAM_MAP(invrvnge_sound_map)
689	689

trunk/src/mame/drivers/lethalj.c
r18774	r18775
325	325	PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
326	326	PORT_DIPSETTING( 0x1000, DEF_STR( On ) )
327	327	PORT_DIPUNUSED_DIPLOC( 0x2000, IP_ACTIVE_LOW, "SW3:3" ) // Manual says switches 1-3 are reserved
328		PORT_DIPUNUSED_DIPLOC( 0x4000, IP_ACTIVE_LOW, "SW3:2" )
329		PORT_DIPUNUSED_DIPLOC( 0x8000, IP_ACTIVE_LOW, "SW3:1" )
	328	PORT_DIPUNUSED_DIPLOC( 0x4000, IP_ACTIVE_LOW, "SW3:2" )
	329	PORT_DIPUNUSED_DIPLOC( 0x8000, IP_ACTIVE_LOW, "SW3:1" )
330	330
331	331	PORT_START("IN1")
332	332	PORT_BIT( 0x000f, IP_ACTIVE_LOW, IPT_UNUSED )

trunk/src/mame/drivers/dblcrown.c
r18774	r18775
1	1	/***************************************************************************
2	2
3		Double Crown (c) 1997 Cadence Technology / Dyna
	3	Double Crown (c) 1997 Cadence Technology / Dyna
4	4
5		driver by Angelo Salese
	5	driver by Angelo Salese
6	6
7		TODO:
8		- Bogus "Hole" in main screen display;
9		- Is the background pen really black?
10		- Lots of unmapped I/Os (game doesn't make much use of the HW);
11		- outputs / lamps;
12		- video / irq timings;
	7	TODO:
	8	- Bogus "Hole" in main screen display;
	9	- Is the background pen really black?
	10	- Lots of unmapped I/Os (game doesn't make much use of the HW);
	11	- outputs / lamps;
	12	- video / irq timings;
13	13
14		Notes:
15		- at POST the SW tries to write to the palette RAM in a banking fashion.
16		I think it's just an HW left-over.
17		- there are various bogus checks to ROM region throughout the whole SW
18		(0x0030-0x0033? O.o), trying to change the values of these ones changes
19		the functionality of the game, almost like that the DSWs are tied to
20		these ...
	14	Notes:
	15	- at POST the SW tries to write to the palette RAM in a banking fashion.
	16	I think it's just an HW left-over.
	17	- there are various bogus checks to ROM region throughout the whole SW
	18	(0x0030-0x0033? O.o), trying to change the values of these ones changes
	19	the functionality of the game, almost like that the DSWs are tied to
	20	these ...
21	21
22	22	============================================================================
23		Excellent System
24		boardlabel: ES-9411B
	23	Excellent System
	24	boardlabel: ES-9411B
25	25
26		28.6363 xtal
27		ES-9409 QFP is 208 pins.. for graphics only?
28		Z0840006PSC Zilog z80, is rated 6.17 MHz
29		OKI M82C55A-2
30		65764H-5 .. 64kbit ram CMOS
31		2 * N341256P-25 - CMOS SRAM 256K-BIT(32KX8)
32		4 * dipsw 8pos
33		YMZ284-D (ay8910, but without i/o ports)
34		MAXIM MAX693ACPE is a "Microprocessor Supervisory Circuit", for watchdog? and for keeping nvram stable?
	26	28.6363 xtal
	27	ES-9409 QFP is 208 pins.. for graphics only?
	28	Z0840006PSC Zilog z80, is rated 6.17 MHz
	29	OKI M82C55A-2
	30	65764H-5 .. 64kbit ram CMOS
	31	2 * N341256P-25 - CMOS SRAM 256K-BIT(32KX8)
	32	4 * dipsw 8pos
	33	YMZ284-D (ay8910, but without i/o ports)
	34	MAXIM MAX693ACPE is a "Microprocessor Supervisory Circuit", for watchdog? and for keeping nvram stable?
35	35
36	36	***************************************************************************/
37	37
r18774	r18775
169	169	READ8_MEMBER( dblcrown_state::palette_r)
170	170	{
171	171	//if(m_bank & 8) /* TODO: verify this */
172		// offset+=0x200;
	172	// offset+=0x200;
173	173
174	174	return m_pal_ram[offset];
175	175	}
r18774	r18775
179	179	int r,g,b,datax;
180	180
181	181	//if(m_bank & 8) /* TODO: verify this */
182		// offset+=0x200;
	182	// offset+=0x200;
183	183
184	184	m_pal_ram[offset] = data;
185	185	offset>>=1;
r18774	r18775
323	323	AM_RANGE(0x11, 0x11) AM_READWRITE(bank_r,bank_w)
324	324	AM_RANGE(0x12, 0x12) AM_READWRITE(mux_r,mux_w)
325	325	AM_RANGE(0x20, 0x21) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
326		// AM_RANGE(0x30, 0x30) always 1?
	326	// AM_RANGE(0x30, 0x30) always 1?
327	327	AM_RANGE(0x40, 0x40) AM_WRITE(output_w)
328	328	ADDRESS_MAP_END
329	329
r18774	r18775
591	591	ROM_START( dblcrown )
592	592	ROM_REGION( 0x40000, "maincpu", ROMREGION_ERASE00 )
593	593	ROM_LOAD("1.u33", 0x00000, 0x40000, CRC(5df95a9c) SHA1(799333206089989c25ff9f167363073d4cf64bd2) )
594		// ROM_FILL( 0x0030, 4, 0xff )
	594	// ROM_FILL( 0x0030, 4, 0xff )
595	595
596	596	ROM_REGION( 0x80000, "gfx1", ROMREGION_ERASE00 )
597	597	ROM_LOAD("2.u43", 0x00000, 0x80000, CRC(58200bd4) SHA1(2795cfc41056111f66bfb82916343d1c733baa83) )

trunk/src/mame/drivers/maygay1b.c
r18774	r18775
113	113	maygay1b_state(const machine_config &mconfig, device_type type, const char *tag)
114	114	: driver_device(mconfig, type, tag),
115	115	m_vfd(*this, "vfd")
116		{
117
	116	{
	117
118	118	m_NMIENABLE = 0;
119	119	}
120	120
r18774	r18775
376	376	m1_draw_lamps(chip->ram[chip->disp_address],chip->disp_address, 0);
377	377	}
378	378	chip->ram[chip->disp_address] = data;
379
	379
380	380	if ( chip->disp_auto_inc )
381	381	chip->disp_address ++;
382	382	}
r18774	r18775
575	575	return i;
576	576	}
577	577
578		// NMI is periodic? or triggered by a write?
	578	// NMI is periodic? or triggered by a write?
579	579	TIMER_DEVICE_CALLBACK_MEMBER( maygay1b_state::maygay1b_nmitimer_callback )
580	580	{
581	581	if (m_NMIENABLE)
r18774	r18775
594	594	// some games might differ..
595	595	WRITE8_MEMBER(maygay1b_state::m1_pia_porta_w)
596	596	{
597		// printf("m1_pia_porta_w %02x\n",data);
	597	// printf("m1_pia_porta_w %02x\n",data);
598	598
599	599	if((data & 0x40))
600	600	{
r18774	r18775
882	882	device_t *ay8910 = machine().device("aysnd");
883	883	return ~ay8910_read_ym(ay8910);
884	884	}
885
	885
886	886	static ADDRESS_MAP_START( m1_memmap, AS_PROGRAM, 8, maygay1b_state )
887	887	AM_RANGE(0x0000, 0x1fff) AM_RAM AM_SHARE("nvram")
888	888
r18774	r18775
893	893	// there is actually an 8279 and an 8051..
894	894	AM_RANGE(0x2030, 0x2031) AM_READWRITE(m1_8279_r,m1_8279_w)
895	895	AM_RANGE(0x2040, 0x2041) AM_READWRITE(m1_8279_2_r,m1_8279_2_w)
896		// AM_RANGE(0x2050, 0x2050)// SCAN on M1B
	896	// AM_RANGE(0x2050, 0x2050)// SCAN on M1B
897	897
898	898	AM_RANGE(0x2070, 0x207f) AM_DEVREADWRITE_LEGACY("duart68681", duart68681_r, duart68681_w )
899	899
r18774	r18775
911	911
912	912	AM_RANGE(0x2412, 0x2412) AM_READ(m1_firq_trg_r) // firq, sample playback?
913	913
914
915	914
	915
916	916	AM_RANGE(0x2420, 0x2421) AM_WRITE(latch_ch2_w ) // oki
917	917
918	918	AM_RANGE(0x2800, 0xffff) AM_ROM

trunk/src/mame/drivers/inufuku.c
r18774	r18775
153	153
154	154	AM_RANGE(0x780000, 0x780013) AM_WRITE(inufuku_palettereg_w) // bg & text palettebank register
155	155	AM_RANGE(0x7a0000, 0x7a0023) AM_WRITE(inufuku_scrollreg_w) // bg & text scroll register
156		// AM_RANGE(0x7e0000, 0x7e0001) AM_WRITENOP // ?
	156	// AM_RANGE(0x7e0000, 0x7e0001) AM_WRITENOP // ?
157	157
158	158	AM_RANGE(0x800000, 0xbfffff) AM_ROM // data rom
159	159	AM_RANGE(0xfd0000, 0xfdffff) AM_RAM // work ram

trunk/src/mame/drivers/s3.c
r18774	r18775
465	465
466	466	READ8_MEMBER( s3_state::dac_r )
467	467	{
468		return m_sound_data;
	468	return m_sound_data;
469	469	}
470	470
471	471	WRITE8_MEMBER( s3_state::dac_w )

trunk/src/mame/drivers/nemesis.c
r18774	r18775
1751	1751	MCFG_SOUND_ROUTE(1, "rspeaker", 0.08)
1752	1752
1753	1753	MCFG_YM2151_ADD("ymsnd", 3579545)
1754		// MCFG_YM2151_IRQ_HANDLER(INPUTLINE("audiocpu", 0)) ... Interrupts _are_ generated, I wonder where they go
	1754	// MCFG_YM2151_IRQ_HANDLER(INPUTLINE("audiocpu", 0)) ... Interrupts _are_ generated, I wonder where they go
1755	1755	MCFG_SOUND_ROUTE(0, "rspeaker", 1.2) // reversed according to MT #4565
1756	1756	MCFG_SOUND_ROUTE(1, "lspeaker", 1.2)
1757	1757	MACHINE_CONFIG_END
r18774	r18775
1793	1793	MCFG_SOUND_ROUTE(1, "rspeaker", 0.10)
1794	1794
1795	1795	MCFG_YM2151_ADD("ymsnd", 3579545)
1796		// MCFG_YM2151_IRQ_HANDLER(INPUTLINE("audiocpu", 0)) ... Interrupts _are_ generated, I wonder where they go
	1796	// MCFG_YM2151_IRQ_HANDLER(INPUTLINE("audiocpu", 0)) ... Interrupts _are_ generated, I wonder where they go
1797	1797	MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
1798	1798	MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
1799	1799	MACHINE_CONFIG_END
r18774	r18775
1929	1929	MCFG_SOUND_ROUTE(1, "rspeaker", 0.10)
1930	1930
1931	1931	MCFG_YM2151_ADD("ymsnd", 3579545)
1932		// MCFG_YM2151_IRQ_HANDLER(INPUTLINE("audiocpu", 0)) ... Interrupts _are_ generated, I wonder where they go
	1932	// MCFG_YM2151_IRQ_HANDLER(INPUTLINE("audiocpu", 0)) ... Interrupts _are_ generated, I wonder where they go
1933	1933	MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
1934	1934	MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
1935	1935	MACHINE_CONFIG_END

trunk/src/mame/drivers/naomi.c
r18774	r18775
434	434	Moero Justice Gakuen / Project Justice (Rev A) 841-0015C 23548A 11 (128Mb) 315-6319A present 317-5065-COM
435	435	Oinori-daimyoujin Matsuri 840-0126B 24053 5 (128Mb) 315-6319A present not present
436	436	Samba de Amigo Ver. 2000 840-0047C 23600 21 (64Mb) 315-6319A present 317-0295-COM
437		Star Horse (Rev A) 840-0123C 24122A 7 (128Mb) 315-6319A present not present requires an additional middle board n° 837-13785
	437	Star Horse (Rev A) 840-0123C 24122A 7 (128Mb) 315-6319A present not present requires an additional middle board n? 837-13785
438	438	Virtua Striker 3 (Rev B) 840-0061C 23663B 11 (128Mb) 315-6319A present 317-0310-COM
439	439	Virtua Striker 3 (Rev C) 840-0061C 23663C 11 (128Mb) 315-6319A present 317-0310-COM
440	440	Wave Runner GP 840-0064C 24059 6 (128Mb) 315-6319A present not present

trunk/src/mame/drivers/mpu12wbk.c
r18774	r18775
45	45
46	46	PCB Layout:
47	47
48		.--------------------------------------------------------------------------------------.
	48	.--------------------------------------------------------------------------------------.
49	49	\| .---------. .---------. \|
50	50	\| \|74LS174N \| \|74LS174N \| .------------. \|
51	51	\| '---------' '---------' \|8 1\| .------------. \|
r18774	r18775
260	260	---- ---- bank select.
261	261	---- ---- color code.
262	262	*/
263		// int attr = m_colorram[tile_index];
264		// int code = m_videoram[tile_index] \| ((attr & 0xc0) << 2);
265		// int color = (attr & 0x0f);
	263	// int attr = m_colorram[tile_index];
	264	// int code = m_videoram[tile_index] \| ((attr & 0xc0) << 2);
	265	// int color = (attr & 0x0f);
266	266
267		// SET_TILE_INFO_MEMBER( 0, code, color, 0);
	267	// SET_TILE_INFO_MEMBER( 0, code, color, 0);
268	268	SET_TILE_INFO_MEMBER( 0, 0 ,0 ,0);
269	269	}
270	270
r18774	r18775
327	327
328	328	1800-1801 R (input?)
329	329	1e00-1e01 RW (psg?)
330
	330
331	331	*/
332	332
333	333
r18774	r18775
437	437	static const gfx_layout charlayout =
438	438
439	439	{
440		// 8, 8,
441		// RGN_FRAC(3,3),
442		// 1, /* 1 bpp */
443		// { 0 },
444		// { 0, 1, 2, 3, 4, 5, 6, 7 },
445		// { 08, 18, 28, 38, 48, 58, 68, 78 },
446		// 88 / every char takes 8 consecutive bytes */
	440	// 8, 8,
	441	// RGN_FRAC(3,3),
	442	// 1, /* 1 bpp */
	443	// { 0 },
	444	// { 0, 1, 2, 3, 4, 5, 6, 7 },
	445	// { 08, 18, 28, 38, 48, 58, 68, 78 },
	446	// 88 / every char takes 8 consecutive bytes */
447	447
448		// 8, 8,
449		// RGN_FRAC(1,3),
450		// 3,
451		// { 0, RGN_FRAC(1,3), RGN_FRAC(2,3) }, /* bitplanes are separated */
452		// { 0, 1, 2, 3, 4, 5, 6, 7 },
453		// { 08, 18, 28, 38, 48, 58, 68, 78 },
454		// 8*8
	448	// 8, 8,
	449	// RGN_FRAC(1,3),
	450	// 3,
	451	// { 0, RGN_FRAC(1,3), RGN_FRAC(2,3) }, /* bitplanes are separated */
	452	// { 0, 1, 2, 3, 4, 5, 6, 7 },
	453	// { 08, 18, 28, 38, 48, 58, 68, 78 },
	454	// 8*8
455	455
456	456	4,8,
457	457	RGN_FRAC(1,2),
r18774	r18775
562	562	ROM_REGION( 0x20000, "gfx1", 0 )
563	563	ROM_LOAD( "fruit1.ic37", 0x00000, 0x10000, CRC(c1834a6d) SHA1(ece1e47641087be342d3c5c092d8a7233ae871f3) )
564	564	ROM_LOAD( "fruit2.ic38", 0x10000, 0x10000, CRC(32d282a8) SHA1(792174d75dc7ec5f1e6f145539a5ec8e3953e1dd) )
565		// ROM_LOAD( "fruit3.ic39", 0x20000, 0x10000, CRC(311a6d4e) SHA1(62cf670b605906f7f4225905118524ee30d0e85b) ) // and this one?
	565	// ROM_LOAD( "fruit3.ic39", 0x20000, 0x10000, CRC(311a6d4e) SHA1(62cf670b605906f7f4225905118524ee30d0e85b) ) // and this one?
566	566
567	567	ROM_REGION( 0x0400, "proms", 0 )
568	568	ROM_LOAD( "82s131.ic47", 0x0000, 0x0200, CRC(54565d41) SHA1(8e412a3441c9c1e7f8309f2087389ac4250896e6) )

trunk/src/mame/drivers/s9.c
r18774	r18775
199	199
200	200	WRITE8_MEMBER( s9_state::sol3_w )
201	201	{
202		// if (BIT(data, 1))
203		// m_samples->start(0, 6); // knocker
	202	// if (BIT(data, 1))
	203	// m_samples->start(0, 6); // knocker
204	204	}
205	205
206	206	WRITE8_MEMBER( s9_state::sound_w )
r18774	r18775
351	351
352	352	READ8_MEMBER( s9_state::dac_r )
353	353	{
354		return m_sound_data;
	354	return m_sound_data;
355	355	}
356	356
357	357	WRITE8_MEMBER( s9_state::dac_w )

trunk/src/mame/drivers/3x3puzzl.c
r18774	r18775
225	225
226	226	PORT_START("VBLANK")
227	227	PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_VBLANK("screen")
228
	228
229	229	PORT_START("DSW01")
230	230	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unused ) )
231	231	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )

trunk/src/mame/drivers/dec0.c
r18774	r18775
1659	1659	MCFG_CPU_ADD("audiocpu", M6502, XTAL_12MHz / 8)
1660	1660	MCFG_CPU_PROGRAM_MAP(dec0_s_map)
1661	1661
1662		// MCFG_CPU_ADD("sub", H6280, XTAL_21_4772MHz / 16)
1663		// MCFG_CPU_PROGRAM_MAP(hippodrm_sub_map)
	1662	// MCFG_CPU_ADD("sub", H6280, XTAL_21_4772MHz / 16)
	1663	// MCFG_CPU_PROGRAM_MAP(hippodrm_sub_map)
1664	1664
1665		// MCFG_QUANTUM_TIME(attotime::from_hz(300)) /* Interleave between H6280 & 68000 */
	1665	// MCFG_QUANTUM_TIME(attotime::from_hz(300)) /* Interleave between H6280 & 68000 */
1666	1666
1667	1667	/* video hardware */
1668	1668	MCFG_SCREEN_ADD("screen", RASTER)
r18774	r18775
3088	3088	READ16_MEMBER(dec0_state::ffantasybl_242024_r)
3089	3089	{
3090	3090	/*
3091		000152: 41F9 0024 2020 lea $242020.l, A0
3092		000158: 4A68 0004 tst.w ($4,A0)
3093		00015C: 6700 00A0 beq $1fe
	3091	000152: 41F9 0024 2020 lea $242020.l, A0
	3092	000158: 4A68 0004 tst.w ($4,A0)
	3093	00015C: 6700 00A0 beq $1fe
3094	3094
3095		This allows us to at insert a coin...
	3095	This allows us to at insert a coin...
3096	3096	*/
3097	3097
3098	3098	return 0xffff;

trunk/src/mame/drivers/funworld.c
r18774	r18775
780	780	- Fixed Power Card graphics ROM load..
781	781	- Moved jolycdat program to Bonus Card, making it parent.
782	782	This program is a real original Bonus Card program, and the PCB
783		was populated with Jolly Card graphics wrongly. The other Bonus Card set
784		was turned as clone, since has a fake copyright string (hack).
	783	was populated with Jolly Card graphics wrongly. The other Bonus Card set
	784	was turned as clone, since has a fake copyright string (hack).
785	785	- Renamed the internal layout artwork: bigdeal --> bonuscrd.
786	786	- Default Bonus Card & Big Deal DIP switches positions, that
787	787	allow boot the system without errors.
r18774	r18775
2292	2292	The game could have 2 different palettes, located
2293	2293	in the first and second half of the bipolar PROM.
2294	2294	*/
2295
	2295
2296	2296	static GFXDECODE_START( fw1stpal ) /* Adressing the first half of the palette */
2297	2297	GFXDECODE_ENTRY( "gfx1", 0, charlayout, 0, 16 )
2298	2298	GFXDECODE_END
r18774	r18775
3051	3051
3052	3052	ROM_REGION( 0x0400, "proms", 0 )
3053	3053	ROM_LOAD( "n82s147an.bin", 0x0000, 0x0200, BAD_DUMP CRC(136245f3) SHA1(715309982fcafbce88b08237ca46acec31273938) ) // from power card, original fun world encrypted bonus card clone.
3054		ROM_LOAD( "74s472n.bin", 0x0200, 0x0200, CRC(e56780cb) SHA1(c06b854f21b1dcee465ac9c8c9a2934b7e99565f) ) // original dump, but doesn't match the cards colors in real board.
	3054	ROM_LOAD( "74s472n.bin", 0x0200, 0x0200, CRC(e56780cb) SHA1(c06b854f21b1dcee465ac9c8c9a2934b7e99565f) ) // original dump, but doesn't match the cards colors in real board.
3055	3055	ROM_END
3056	3056
3057	3057
r18774	r18775
3065	3065
3066	3066	ROM_REGION( 0x0400, "proms", 0 )
3067	3067	ROM_LOAD( "n82s147an.bin", 0x0000, 0x0200, BAD_DUMP CRC(136245f3) SHA1(715309982fcafbce88b08237ca46acec31273938) ) // from power card, original fun world encrypted bonus card clone.
3068		ROM_LOAD( "74s472n.bin", 0x0200, 0x0200, CRC(e56780cb) SHA1(c06b854f21b1dcee465ac9c8c9a2934b7e99565f) ) // original dump, but doesn't match the cards colors in real board.
	3068	ROM_LOAD( "74s472n.bin", 0x0200, 0x0200, CRC(e56780cb) SHA1(c06b854f21b1dcee465ac9c8c9a2934b7e99565f) ) // original dump, but doesn't match the cards colors in real board.
3069	3069	ROM_END
3070	3070
3071	3071
r18774	r18775
3843	3843	the encrypted graphics set.
3844	3844
3845	3845	All these games have some weird things...
3846		1) Some CPU instructions seems wrong (see below, in driver init)
3847		2) The CRTC is injected with some wrong register values (fact),
3848		that place the game wrongly, and screw up the input test screen.
3849
	3846	1) Some CPU instructions seems wrong (see below, in driver init)
	3847	2) The CRTC is injected with some wrong register values (fact),
	3848	that place the game wrongly, and screw up the input test screen.
	3849
3850	3850	*/
3851	3851
3852	3852	ROM_START( magicrd2 ) /* Impera... but seems Bulgarian hack, just for copyright */
r18774	r18775
3866	3866	ROM_LOAD( "mc2-82s147.bin", 0x0000, 0x0200, CRC(aa91cc35) SHA1(79f9a755441500e618c4183f524f969fffd44100) )
3867	3867
3868	3868	ROM_REGION( 0x0200, "plds", 0 )
3869		ROM_LOAD( "gal16v8uni.bin", 0x0000, 0x0117, CRC(b81d7e0a) SHA1(7fef0b2bcea931a830d38ae0f1102434cf281d2d) ) /* Universal GAL */
	3869	ROM_LOAD( "gal16v8uni.bin", 0x0000, 0x0117, CRC(b81d7e0a) SHA1(7fef0b2bcea931a830d38ae0f1102434cf281d2d) ) /* Universal GAL */
3870	3870	ROM_END
3871	3871
3872	3872
r18774	r18775
3892	3892	ROM_START( magicrd2b ) /* Imatic Yugoslavian hack for green TAB or Impera boards */
3893	3893	ROM_REGION( 0x10000, "maincpu", 0 )
3894	3894	ROM_LOAD( "mc2prgv1.bin", 0x8000, 0x8000, CRC(7f759b70) SHA1(23a1a6e8eda57c4a90c51a970302f9a7bf590083) )
3895		// ROM_LOAD( "mc2prgv2.bin", 0x8000, 0x8000, CRC(b0ed6b40) SHA1(7167e67608f1b0b1cd956c838dacc1310861cb4a) ) // there are also pcbs with this program
	3895	// ROM_LOAD( "mc2prgv2.bin", 0x8000, 0x8000, CRC(b0ed6b40) SHA1(7167e67608f1b0b1cd956c838dacc1310861cb4a) ) // there are also pcbs with this program
3896	3896
3897	3897	ROM_REGION( 0x10000, "gfx1", 0 )
3898	3898	ROM_LOAD( "mc2gr2.bin", 0x0000, 0x8000, CRC(733da697) SHA1(45122c64d5a371ec91cecc67b7faf179078e714d) )
r18774	r18775
3909	3909	ROM_START( magicrd2c ) /* Imatic Yugoslavian hack for blue TAB board (encrypted)*/
3910	3910	ROM_REGION( 0x10000, "maincpu", 0 )
3911	3911	ROM_LOAD( "mc2prgv2.bin", 0x8000, 0x8000, CRC(b0ed6b40) SHA1(7167e67608f1b0b1cd956c838dacc1310861cb4a) )
3912		// ROM_LOAD( "mc2prgv1.bin", 0x8000, 0x8000, CRC(7f759b70) SHA1(23a1a6e8eda57c4a90c51a970302f9a7bf590083) ) // there are also pcbs with this program
	3912	// ROM_LOAD( "mc2prgv1.bin", 0x8000, 0x8000, CRC(7f759b70) SHA1(23a1a6e8eda57c4a90c51a970302f9a7bf590083) ) // there are also pcbs with this program
3913	3913
3914	3914	ROM_REGION( 0x10000, "gfx1", 0 )
3915	3915	ROM_LOAD( "mc2gr1b.bin", 0x0000, 0x8000, CRC(ce2629a7) SHA1(84767ed5da8dcee44a210255537e10372bcc264b) )
r18774	r18775
4242	4242	\| \|
4243	4243	'----------------------------------------------------------------------------------------------------------------------'
4244	4244
4245		DIP SW Bank
	4245	DIP SW Bank
4246	4246	.---------------.
4247	4247	\|#\| \|#\|#\|#\|#\|#\|#\|
4248	4248	\|---------------\|

trunk/src/mame/drivers/jpmsru.c
r18774	r18775
101	101	ROM_REGION( 0x10000, "maincpu", 0 )
102	102	ROM_LOAD( "ews13c1.bin", 0x0000, 0x000400, CRC(2eec7c4d) SHA1(a1740d27e60192659392ba7602b9b62947c4f6db) )
103	103	ROM_LOAD( "ews13b2.bin", 0x0400, 0x000400, CRC(b84b7858) SHA1(90fd64881d52e1f4362ccbcb9434dbf7b25b97f9) )
104		ROM_LOAD( "ews13.3", 0x0800, 0x000400, CRC(4d8e197a) SHA1(1569327f0e4b5d7632658b69abf59076effb2600) )
	104	ROM_LOAD( "ews13.3", 0x0800, 0x000400, CRC(4d8e197a) SHA1(1569327f0e4b5d7632658b69abf59076effb2600) )
105	105	ROM_END
106	106
107	107	ROM_START( j_ews8a )

trunk/src/mame/drivers/chihiro.c
r18774	r18775
56	56	\|*\|Quest Of D (Ver.1.01C) \| Sega, 2004 \| CDROM CDV-10005C \| \|
57	57	\|*\|Sangokushi Taisen (Ver.1.002) \| Sega, 2005 \| DVDROM CDV-10009D \| \|
58	58	\|*\|Sangokushi Taisen 2 (Ver.2.007) \| Sega, 2006 \| DVDROM CDV-10019A \| \|
59		\|*\|Sangokushi Taisen \| Sega, 2005 \| DVDROM CDV-10022 \| \|
	59	\|*\|Sangokushi Taisen \| Sega, 2005 \| DVDROM CDV-10022 \| \|
60	60	\|*\|Sangokushi Taisen 2 Firmware Update \| Sega, 2006 \| DVDROM CDV-10023 \| \|
61	61	\|*\|Sangokushi Taisen 2 \| Sega, 2006 \| DVDROM CDV-10029 \| \|
62	62	\|*\|Sangokushi Taisen 3 \| Sega, 2008 \| DVDROM CDV-10036 \| \|

trunk/src/mame/drivers/rpunch.c
r18774	r18775
740	740	ROM_LOAD16_BYTE( "3-prg.bin", 0x20001, 0x08000, CRC(b6b24910) SHA1(2e4cf80a8eb1fcd9448405ff881bb99ae4ce8909) )
741	741
742	742	ROM_REGION( 0x080000, "gfx1", 0 )
743		ROM_LOAD32_BYTE( "7.bin", 0x000000, 0x010000, CRC(9596a4c0) SHA1(1f233bb2fa662fb8cd9c0db478e392ca26d9484b) )
	743	ROM_LOAD32_BYTE( "7.bin", 0x000000, 0x010000, CRC(9596a4c0) SHA1(1f233bb2fa662fb8cd9c0db478e392ca26d9484b) )
744	744	ROM_LOAD32_BYTE( "10.bin", 0x000001, 0x010000, CRC(a05249e6) SHA1(8671e0c980ba87ea14895176fb5c8a48bb4c932e) )
745	745	ROM_LOAD32_BYTE( "13.bin", 0x000002, 0x010000, CRC(429159f3) SHA1(4395413c4ab4a1fd322a1af6f2b93bb62b044223) )
746	746	ROM_LOAD32_BYTE( "16.bin", 0x000003, 0x010000, CRC(f5436c8d) SHA1(d29508cc5ee43d7b072112c6d95c36ee0328e5fb) )
r18774	r18775
757	757
758	758	ROM_REGION( 0x080000, "gfx3", ROMREGION_INVERT )
759	759	ROM_LOAD32_BYTE( "19.bin", 0x000000, 0x010000, CRC(12a67e3f) SHA1(c77b264eae0f55af36728b6e5e5e1fec3d366eb1) )
760		ROM_LOAD32_BYTE( "20.bin", 0x000001, 0x010000, CRC(31828996) SHA1(b324902b9fff0bab1daa3af5136b96d50d12956f) )
	760	ROM_LOAD32_BYTE( "20.bin", 0x000001, 0x010000, CRC(31828996) SHA1(b324902b9fff0bab1daa3af5136b96d50d12956f) )
761	761	ROM_LOAD32_BYTE( "21.bin", 0x000002, 0x010000, CRC(51cbe0d6) SHA1(d60b2a297d7e994c60db28e8ba60b0664e01f61d) )
762	762	ROM_LOAD32_BYTE( "22.bin", 0x000003, 0x010000, CRC(c289bfc0) SHA1(4a8929c5f304a1d203cad04c72fc6e96764dc858) )
763	763
r18774	r18775
804	804	GAME( 1989, svolleyk, svolley, rpunch, svolley, rpunch_state, svolley, ROT0, "V-System Co.", "Super Volleyball (Korea)", GAME_NO_COCKTAIL )
805	805	GAME( 1989, svolleyu, svolley, rpunch, svolley, rpunch_state, svolley, ROT0, "V-System Co. (Data East license)", "Super Volleyball (US)", GAME_NO_COCKTAIL )
806	806
807		// video registers are changed, and there's some kind of RAM at 090xxx, possible a different sprite scheme for the bootleg (even if the original is intact)
	807	// video registers are changed, and there's some kind of RAM at 090xxx, possible a different sprite scheme for the bootleg (even if the original is intact)
808	808	// the sound system seems to be ripped from the later Power Spikes (see aerofgt.c)
809	809	GAME( 1991, spikes91a,svolley, spikes91a,svolley, rpunch_state, svolley, ROT0, "bootleg", "Super Volleyball (bootleg)", GAME_SUPPORTS_SAVE \| GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_NO_COCKTAIL ) // aka 1991 Spikes?

trunk/src/mame/drivers/s4.c
r18774	r18775
466	466
467	467	READ8_MEMBER( s4_state::dac_r )
468	468	{printf("%X ",m_sound_data);
469		return m_sound_data;
	469	return m_sound_data;
470	470	}
471	471
472	472	WRITE8_MEMBER( s4_state::dac_w )

trunk/src/mame/drivers/s6a.c
r18774	r18775
448	448
449	449	READ8_MEMBER( s6a_state::dac_r )
450	450	{printf("%X ",m_sound_data);
451		return m_sound_data;
	451	return m_sound_data;
452	452	}
453	453
454	454	WRITE8_MEMBER( s6a_state::dac_w )

trunk/src/mame/drivers/pgm.c
r18774	r18775
2387	2387
2388	2388	ROM_REGION( 0x2800000, "sprcol", 0 ) /* Sprite Colour Data */
2389	2389	ROM_LOAD( "a1200.rom", 0x0000000, 0x0800000, CRC(ceeb81d8) SHA1(5476729443fc1bc9593ae10fbf7cbc5d7290b017) )
2390		ROM_LOAD( "a1201.rom", 0x0800000, 0x0800000, CRC(21063ca7) SHA1(cf561b44902425a920d5cbea5bf65dd9530b2289) )
	2390	ROM_LOAD( "a1201.rom", 0x0800000, 0x0800000, CRC(21063ca7) SHA1(cf561b44902425a920d5cbea5bf65dd9530b2289) )
2391	2391	ROM_LOAD( "a1202.rom", 0x1000000, 0x0800000, CRC(4bb92fae) SHA1(f0b6d72ed425de1c69dc8f8d5795ea760a4a59b0) )
2392	2392	ROM_LOAD( "a1203.rom", 0x1800000, 0x0800000, CRC(e73cb627) SHA1(4c6e48b845a5d1e8f9899010fbf273d54c2b8899) )
2393	2393	ROM_LOAD( "a1204.rom", 0x2000000, 0x0200000, CRC(14b4b5bb) SHA1(d7db5740eec971f2782fb2885ee3af8f2a796550) )
r18774	r18775
2418	2418
2419	2419	ROM_REGION( 0x2800000, "sprcol", 0 ) /* Sprite Colour Data */
2420	2420	ROM_LOAD( "a1200.rom", 0x0000000, 0x0800000, CRC(ceeb81d8) SHA1(5476729443fc1bc9593ae10fbf7cbc5d7290b017) )
2421		ROM_LOAD( "a1201.rom", 0x0800000, 0x0800000, CRC(21063ca7) SHA1(cf561b44902425a920d5cbea5bf65dd9530b2289) )
	2421	ROM_LOAD( "a1201.rom", 0x0800000, 0x0800000, CRC(21063ca7) SHA1(cf561b44902425a920d5cbea5bf65dd9530b2289) )
2422	2422	ROM_LOAD( "a1202.rom", 0x1000000, 0x0800000, CRC(4bb92fae) SHA1(f0b6d72ed425de1c69dc8f8d5795ea760a4a59b0) )
2423	2423	ROM_LOAD( "a1203.rom", 0x1800000, 0x0800000, CRC(e73cb627) SHA1(4c6e48b845a5d1e8f9899010fbf273d54c2b8899) )
2424	2424	ROM_LOAD( "a1204.rom", 0x2000000, 0x0200000, CRC(14b4b5bb) SHA1(d7db5740eec971f2782fb2885ee3af8f2a796550) )

trunk/src/mame/drivers/s6.c
r18774	r18775
323	323
324	324	READ8_MEMBER( s6_state::dac_r )
325	325	{
326		return m_sound_data;
	326	return m_sound_data;
327	327	}
328	328
329	329	WRITE8_MEMBER( s6_state::dac_w )

trunk/src/mame/drivers/cops.c
r18774	r18775
1	1	/***************************************************************************
2	2
3		Atari Games Cops
4		(hardware developed by Nova Productions Limited)
	3	Atari Games Cops
	4	(hardware developed by Nova Productions Limited)
5	5
6		Preliminary driver by Mariusz Wojcieszek
	6	Preliminary driver by Mariusz Wojcieszek
7	7
8	8	***************************************************************************/
9	9
r18774	r18775
565	565	AM_RANGE(0xb000, 0xb00f) AM_DEVREADWRITE("via6522_1", via6522_device, read, write) /* VIA 1 */
566	566	AM_RANGE(0xb800, 0xb80f) AM_DEVREADWRITE("via6522_2", via6522_device, read, write) /* VIA 2 */
567	567	AM_RANGE(0xc000, 0xcfff) AM_READWRITE(io2_r, io2_w)
568		// AM_RANGE(0xd000, 0xd003) AM_DEVREADWRITE("acia6551_1", acia6551_device, read, write )
569		// AM_RANGE(0xd004, 0xd007) AM_DEVREADWRITE("acia6551_2", acia6551_device, read, write )
	568	// AM_RANGE(0xd000, 0xd003) AM_DEVREADWRITE("acia6551_1", acia6551_device, read, write )
	569	// AM_RANGE(0xd004, 0xd007) AM_DEVREADWRITE("acia6551_2", acia6551_device, read, write )
570	570	AM_RANGE(0xd000, 0xd007) AM_READWRITE(dacia_r, dacia_w)
571	571	AM_RANGE(0xd800, 0xd80f) AM_DEVREADWRITE("via6522_3", via6522_device, read, write) /* VIA 3 */
572	572	AM_RANGE(0xe000, 0xffff) AM_ROM AM_REGION("system", 0)
r18774	r18775
645	645	MCFG_VIA6522_ADD("via6522_3", 0, via_3_interface)
646	646
647	647	/* acia */
648		// MCFG_ACIA6551_ADD("acia6551_1")
649		// MCFG_ACIA6551_ADD("acia6551_2")
	648	// MCFG_ACIA6551_ADD("acia6551_1")
	649	// MCFG_ACIA6551_ADD("acia6551_2")
650	650
651	651	/* sound hardware */
652	652	MCFG_SPEAKER_STANDARD_MONO("mono")

trunk/src/mame/drivers/peyper.c
r18774	r18775
652	652	ROM_END
653	653
654	654
655		GAME( 1985, odin, 0, peyper, odin_dlx, peyper_state, peyper, ROT0, "Sonic", "Odin", GAME_IS_SKELETON_MECHANICAL)
	655	GAME( 1985, odin, 0, peyper, odin_dlx, peyper_state, peyper, ROT0, "Sonic", "Odin", GAME_IS_SKELETON_MECHANICAL)
656	656	GAME( 1985, odin_dlx, 0, peyper, odin_dlx, peyper_state, peyper, ROT0, "Sonic", "Odin De Luxe", GAME_IS_SKELETON_MECHANICAL)
657	657	GAME( 1986, solarwap, 0, peyper, solarwap, peyper_state, peyper, ROT0, "Sonic", "Solar Wars (Sonic)", GAME_IS_SKELETON_MECHANICAL)
658	658	GAME( 1986, gamatros, 0, peyper, solarwap, peyper_state, peyper, ROT0, "Sonic", "Gamatron (Sonic)", GAME_IS_SKELETON_MECHANICAL)

trunk/src/mame/drivers/jpmimpct.c
r18774	r18775
5008	5008	ROM_LOAD16_BYTE( "ewn8_8.b16", 0x0000, 0x040000, CRC(674fd826) SHA1(34b17cdc4b8eb67c1100e62dee8bf13c66a5fa82) )
5009	5009	ROM_LOAD16_BYTE( "ewnc1ss.bin", 0x0000, 0x020000, CRC(cc2c4712) SHA1(15729b5bccdb5f0e71bdedbe8817988c186a9d7e) )
5010	5010	ROM_LOAD16_BYTE( "ewncp1.bin", 0x0000, 0x020000, CRC(27b2132a) SHA1(144f491eeaed2b6e0203e31fe5f78280edc41c1e) )
5011
	5011
5012	5012	ROM_REGION( 0x80000, "upd", ROMREGION_ERASE00 )
5013		/* missing? */
	5013	/* missing? */
5014	5014	ROM_END
5015	5015
5016	5016

trunk/src/mame/drivers/scobra.c
r18774	r18775
207	207
208	208	// NOTE: hardware does not have any 8255 chip. Is this handled through TTL, or a leftover?
209	209	// Is b800 the actual sound comms? The soundroms are not dumped, so we can't know...
210		// AM_RANGE(0xb800, 0xb800) AM_WRITENOP
	210	// AM_RANGE(0xb800, 0xb800) AM_WRITENOP
211	211	AM_RANGE(0xc200, 0xc203) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)
212	212	ADDRESS_MAP_END
213	213
r18774	r18775
625	625	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_COCKTAIL
626	626	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_COCKTAIL
627	627	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
628
	628
629	629	// 6-pos dipswitch on mainboard K4
630	630	PORT_DIPNAME( 0x40, 0x00, "Half Coinage" )
631	631	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )

trunk/src/mame/drivers/s8.c
r18774	r18775
21	21	- When you have 3 strikes, you are Out
22	22	- When you have 3 Outs, your Innings ends (other player gets a turn)
23	23	- After 3 Innings, it's game over.
24		- Match digit appears in Outs digit.
	24	- Match digit appears in Outs digit.
25	25
26	26	- Still Crazy, a novelty game where the playfield is completely vertical. It has
27	27	4 flippers and the idea is to get the ball up to the alcohol 'still' before
r18774	r18775
375	375
376	376	READ8_MEMBER( s8_state::dac_r )
377	377	{
378		return m_sound_data;
	378	return m_sound_data;
379	379	}
380	380
381	381	WRITE8_MEMBER( s8_state::dac_w )

trunk/src/mame/drivers/portrait.c
r18774	r18775
244	244	{
245	245	DEVCB_NULL
246	246	};
247
248	247
	248
249	249	static MACHINE_CONFIG_START( portrait, portrait_state )
250	250	MCFG_CPU_ADD("maincpu", Z80, 4000000) /* 4 MHz ? */
251	251	MCFG_CPU_PROGRAM_MAP(portrait_map)

trunk/src/mame/drivers/mcr3.c
r18774	r18775
642	642	PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) )
643	643	PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
644	644	PORT_DIPSETTING( 0x10, DEF_STR( 1C_2C ) )
645		// PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) // dupe/invalid
	645	// PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) // dupe/invalid
646	646	PORT_DIPUNUSED( 0x40, 0x40 )
647	647	PORT_DIPUNUSED( 0x80, 0x80 )
648	648
r18774	r18775
677	677	PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) )
678	678	PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
679	679	PORT_DIPSETTING( 0x10, DEF_STR( 1C_2C ) )
680		// PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) // dupe/invalid
	680	// PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) // dupe/invalid
681	681	PORT_BIT( 0xc7, IP_ACTIVE_LOW, IPT_UNKNOWN )
682	682
683	683	PORT_START("MONO.IP4") /* J4 1-7,9 */

trunk/src/mame/drivers/namcos23.c
r18774	r18775
1472	1472	{
1473	1473	UINT32 changed = cause ^ m_main_irqcause;
1474	1474	m_main_irqcause = cause;
1475
	1475
1476	1476	// level 2: vblank
1477	1477	if (changed & MAIN_VBLANK_IRQ)
1478	1478	m_maincpu->set_input_line(MIPS3_IRQ0, (cause & MAIN_VBLANK_IRQ) ? ASSERT_LINE : CLEAR_LINE);

trunk/src/mame/drivers/bingoman.c
r18774	r18775
36	36	1x Xtal 25 MHz @ u61
37	37	1x Xtal 40 MHz @ u04 (near TMS34010)
38	38
39		1x empty DIP8 socket. (Maybe for a serial EPROM) @ u03
	39	1x empty DIP8 socket. (Maybe for a serial EPROM) @ u03
40	40	1x empty DIP32 socket. Near H8/520. @ u17
41	41
42	42	1x 2x8 edge connector.
r18774	r18775
86	86	\| +-------+ \|
87	87	\| +------+ +--------+ \|
88	88	\| +----------------+ +----------------+ \|H99470\| +------+ +-------+ \| XTAL \| \|
89		\| \| EMPTY SOCKET \| \| EMPTY SOCKET \| \|045 \| \|74AS74\| \|74AS32N\| \|25.00Mhz\| \|
90		\| \| CONNECTION FOR \| \| CONNECTION FOR \| \| \| +------+ +-------+ +--------+ \|
91		\| \| TOP-BOARD \| \| TOP-BOARD \| \|M48T08\| \|
	89	\| \| EMPTY SOCKET \| \| EMPTY SOCKET \| \|045 \| \|74AS74\| \|74AS32N\| \|25.00Mhz\| \|
	90	\| \| CONNECTION FOR \| \| CONNECTION FOR \| \| \| +------+ +-------+ +--------+ \|
	91	\| \| TOP-BOARD \| \| TOP-BOARD \| \|M48T08\| \|
92	92	\| +----------------+ +----------------+ \|-150PC\| +------+ +------+ +------+ \|
93		\| +----------------+ +----------------+ \| \| \|74AS74\| \|74AS74\| \|74AS04\| \|
	93	\| +----------------+ +----------------+ \| \| \|74AS74\| \|74AS74\| \|74AS04\| \|
94	94	\| \|SAMSUNG \| \|PS.020 \| \| TIME \| +------+ +------+ +------+ \|
95		\| \| K6T1008C2E \| \| \| \|KEEPER\| \|
	95	\| \| K6T1008C2E \| \| \| \|KEEPER\| \|
96	96	\| \| \| \| 27C4001\| \| RAM \| +---------+ +---------+ +-------+ \|
97		\| +----------------+ +----------------+ \| \| \|102U5500 \| \|102U5400 \| \|74AS161\| \|
	97	\| +----------------+ +----------------+ \| \| \|102U5500 \| \|102U5400 \| \|74AS161\| \|
98	98	\| +------+ +---------+ +---------+ +-------+ \|
99		\| +-------+ +-------+ +-------+ \|
100		\| \|411GR-1\| \|411GR-1\| \|411GR-1\| \|
101		\| +-------+ +-------+ +-------+ +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
102		\| \|
103		\| +----------+ +----------+ +----------+ +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
	99	\| +-------+ +-------+ +-------+ \|
	100	\| \|411GR-1\| \|411GR-1\| \|411GR-1\| \|
	101	\| +-------+ +-------+ +-------+ +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
	102	\| \|
	103	\| +----------+ +----------+ +----------+ +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
104	104	\| \|74HCT541N \| \|74HCT541N \| \|74HCT541N \| \|
105		\| +----------+ +----------+ +----------+ +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
106		\| \|
107		\| +-------+ +--+ +--+ +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
108		\| \|411GR-1\| +-------------+ \|10\| \|10\| \|
109		\| +-------+ \| \| \|2U\| \|2U\| +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
110		\| \| H8/534 \| \|30\| \|29\| \|
111		\| +----------+ \| HD6475348 \| \|10\| \|20\| +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
112		\| \|74HCT541N \| \| CP16 \| \| \| \| \| \|
113		\| +----------+ \| \| \| \| \| \| +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
114		\| \| \| \| \| \| \| \|
115		\| +----+ +--+ \| \| +--+ +--+ +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
116		\| \|XTAL\| \|74\| \| \| \|
117		\| \| \| \|HC\| +-------------+ +------+ +-------+ +---------+ +---------+ \|
118		\| \|20.0\| \|T0\| \| A0 \| \|411GR-1\| \|74ALS245A\| \|74ALS245A\| \|
119		\| \|0Mhz\| \|4N\| +------+ +-------+ +---------+ +---------+ \|
	105	\| +----------+ +----------+ +----------+ +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
	106	\| \|
	107	\| +-------+ +--+ +--+ +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
	108	\| \|411GR-1\| +-------------+ \|10\| \|10\| \|
	109	\| +-------+ \| \| \|2U\| \|2U\| +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
	110	\| \| H8/534 \| \|30\| \|29\| \|
	111	\| +----------+ \| HD6475348 \| \|10\| \|20\| +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
	112	\| \|74HCT541N \| \| CP16 \| \| \| \| \| \|
	113	\| +----------+ \| \| \| \| \| \| +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
	114	\| \| \| \| \| \| \| \|
	115	\| +----+ +--+ \| \| +--+ +--+ +KM424C2572-6+ +MB81C4256A-70PSZ+ \|
	116	\| \|XTAL\| \|74\| \| \| \|
	117	\| \| \| \|HC\| +-------------+ +------+ +-------+ +---------+ +---------+ \|
	118	\| \|20.0\| \|T0\| \| A0 \| \|411GR-1\| \|74ALS245A\| \|74ALS245A\| \|
	119	\| \|0Mhz\| \|4N\| +------+ +-------+ +---------+ +---------+ \|
120	120	\| +----+ +--+ \|
121		\| \|
122		\| \|
123		\| +---+ +------------+ +---------+ +-------+ +---------+ \|
	121	\| \|
	122	\| \|
	123	\| +---+ +------------+ +---------+ +-------+ +---------+ \|
124	124	\| \| A5\| \| \| +----------------+ \|74AS573N \| \|411GR-1\| \|74AS573N \| \|
125		\| +---+ \| H8/520 \| \| EMPTY SOCKET \| +---------+ +-------+ +---------+ \|
126		\| \| HD6435208 \| \| CONNECTION FOR \| \|
127		\| \| CP10 \| \| TOP-BOARD \| +------+ +---------+ +------------+ \|
128		\| \| \| +----------------+ \| A1 \| \|74AS244N \| \| 102U1400 \| \|
	125	\| +---+ \| H8/520 \| \| EMPTY SOCKET \| +---------+ +-------+ +---------+ \|
	126	\| \| HD6435208 \| \| CONNECTION FOR \| \|
	127	\| \| CP10 \| \| TOP-BOARD \| +------+ +---------+ +------------+ \|
	128	\| \| \| +----------------+ \| A1 \| \|74AS244N \| \| 102U1400 \| \|
129	129	\| \| \| +------+ +---------+ +------------+ \|
130		\| \| \| \|
	130	\| \| \| \|
131	131	\| +------------+ +------+ +---------+ +---------+ +------+ +------------+ \|
132		\| \| A2 \| \|74HCT573N\| \|74HCT245N\| \|74AS08\| \| \| \|
133		\| +------+ +---------+ +---------+ +------+ \| TMS34010 \| \|
134		\| \| FNL-50 \| \|
135		\| \| \| \|
136		\| +------+ +---------+ +------+ +---------+ +------+ \| WEU9310 \| \|
137		\| \| A4 \| \|74LS682N \| \| A3 \| \|102U0520 \| \| XTAL \| \| \| \|
138		\| +------+ +---------+ +------+ +---------+ \|40.000\| \| \| \|
139		\| +------+ +------------+ \|
140		\| +--+ +--+ \|
	132	\| \| A2 \| \|74HCT573N\| \|74HCT245N\| \|74AS08\| \| \| \|
	133	\| +------+ +---------+ +---------+ +------+ \| TMS34010 \| \|
	134	\| \| FNL-50 \| \|
	135	\| \| \| \|
	136	\| +------+ +---------+ +------+ +---------+ +------+ \| WEU9310 \| \|
	137	\| \| A4 \| \|74LS682N \| \| A3 \| \|102U0520 \| \| XTAL \| \| \| \|
	138	\| +------+ +---------+ +------+ +---------+ \|40.000\| \| \| \|
	139	\| +------+ +------------+ \|
	140	\| +--+ +--+ \|
141	141	\| \| \| \| \| \|
142	142	\| \|TL\| \|A6\| \|
143	143	\| \|07\| \| \| +-------+ \|
r18774	r18775
352	352	#endif
353	353
354	354	static GFXDECODE_START( bingoman )
355		// GFXDECODE_ENTRY( "gfx1", 0, charlayout, 0, 1 )
	355	// GFXDECODE_ENTRY( "gfx1", 0, charlayout, 0, 1 )
356	356	GFXDECODE_END
357	357
358	358

trunk/src/mame/mame.lst
r18774	r18775
11569	11569
11570	11570	// JPM SRU?
11571	11571	j_ewnud // Each Way Nudger
11572		j_ewnda
	11572	j_ewnda
11573	11573	j_ewnd20
11574	11574	j_ews // Each Way Shifter
11575	11575	j_ews8a

trunk/src/mame/audio/gottlieb.c
r18774	r18775
299	299	void gottlieb_state::qbert_knocker(UINT8 knock)
300	300	{
301	301	output_set_value("knocker0", knock);
302
	302
303	303	// start sound on rising edge
304	304	if (knock & ~m_knocker_prev)
305	305	m_knocker_sample->start(0, 0);

trunk/src/mame/machine/atarigen.c
r18774	r18775
223	223	slapstic_reset();
224	224	slapstic_update_bank(slapstic_bank());
225	225	}
226
	226
227	227	// reset sound I/O
228	228	sound_io_reset();
229	229	}
r18774	r18775
240	240	timer.adjust(screen->frame_period());
241	241	break;
242	242	}
243
	243
244	244	case TID_SCANLINE_TIMER:
245	245	scanline_timer(timer, reinterpret_cast<screen_device >(ptr), param);
246	246	break;
247
	247
248	248	case TID_ATARIVC_EOF:
249	249	atarivc_eof_update(timer, reinterpret_cast<screen_device >(ptr));
250	250	break;
251
	251
252	252	// sound I/O
253	253	case TID_SOUND_RESET:
254	254	delayed_sound_reset(param);
255	255	break;
256
	256
257	257	case TID_SOUND_WRITE:
258	258	delayed_sound_write(param);
259	259	break;
260
	260
261	261	case TID_6502_WRITE:
262	262	delayed_6502_write(param);
263	263	break;
264
	264
265	265	// unhalt the CPU that was passed as a pointer
266	266	case TID_UNHALT_CPU:
267	267	reinterpret_cast<device_t *>(ptr)->execute().set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
r18774	r18775
559	559
560	560
561	561	//-------------------------------------------------
562		// m6502_irq_gen: Generates an IRQ signal to the
	562	// m6502_irq_gen: Generates an IRQ signal to the
563	563	// 6502 sound processor.
564	564	//-------------------------------------------------
565	565
r18774	r18775
613	613
614	614
615	615	//-------------------------------------------------
616		// sound_cpu_reset: Resets the state of the sound
	616	// sound_cpu_reset: Resets the state of the sound
617	617	// CPU manually.
618	618	//-------------------------------------------------
619	619
r18774	r18775
652	652
653	653
654	654	//-------------------------------------------------
655		// m6502_sound_w: Handles communication from the
	655	// m6502_sound_w: Handles communication from the
656	656	// sound CPU to the main CPU.
657	657	//-------------------------------------------------
658	658
r18774	r18775
663	663
664	664
665	665	//-------------------------------------------------
666		// m6502_sound_r: Handles reading data
667		// communicated from the main CPU to the sound
	666	// m6502_sound_r: Handles reading data
	667	// communicated from the main CPU to the sound
668	668	// CPU.
669	669	//-------------------------------------------------
670	670
r18774	r18775
717	717
718	718
719	719	//-------------------------------------------------
720		// delayed_sound_write: Synchronizes a data write
	720	// delayed_sound_write: Synchronizes a data write
721	721	// from the main CPU to the sound CPU.
722	722	//-------------------------------------------------
723	723
r18774	r18775
739	739
740	740
741	741	//-------------------------------------------------
742		// delayed_6502_write: Synchronizes a data write
	742	// delayed_6502_write: Synchronizes a data write
743	743	// from the sound CPU to the main CPU.
744	744	//-------------------------------------------------
745	745
r18774	r18775
762	762	***************************************************************************/
763	763
764	764	//-------------------------------------------------
765		// set_volume_by_type: Scans for a particular
766		// sound chip and changes the volume on all
	765	// set_volume_by_type: Scans for a particular
	766	// sound chip and changes the volume on all
767	767	// channels associated with it.
768	768	//-------------------------------------------------
769	769
r18774	r18775
777	777
778	778
779	779	//-------------------------------------------------
780		// set_XXXXX_volume: Sets the volume for a given
	780	// set_XXXXX_volume: Sets the volume for a given
781	781	// type of chip.
782	782	//-------------------------------------------------
783	783
r18774	r18775
829	829
830	830	//-------------------------------------------------
831	831	// scanline_timer: Called once every n scanlines
832		// to generate the periodic callback to the main
	832	// to generate the periodic callback to the main
833	833	// system.
834	834	//-------------------------------------------------
835	835

trunk/src/mame/machine/atarigen.h
r18774	r18775
101	101	// callbacks provided by the derived class
102	102	virtual void update_interrupts() = 0;
103	103	virtual void scanline_update(screen_device &screen, int scanline);
104
	104
105	105	// interrupt handling
106	106	void scanline_int_set(screen_device &screen, int scanline);
107	107	INTERRUPT_GEN_MEMBER(scanline_int_gen);
r18774	r18775
110	110	DECLARE_WRITE16_MEMBER(sound_int_ack_w);
111	111	INTERRUPT_GEN_MEMBER(video_int_gen);
112	112	DECLARE_WRITE16_MEMBER(video_int_ack_w);
113
	113
114	114	// EEPROM helpers
115	115	WRITE16_MEMBER(eeprom_enable_w);
116	116	WRITE16_MEMBER(eeprom_w);
r18774	r18775
124	124	DECLARE_DIRECT_UPDATE_MEMBER(slapstic_setdirect);
125	125	DECLARE_WRITE16_MEMBER(slapstic_w);
126	126	DECLARE_READ16_MEMBER(slapstic_r);
127
	127
128	128	// sound I/O helpers
129	129	void sound_io_reset();
130	130	INTERRUPT_GEN_MEMBER(m6502_irq_gen);
r18774	r18775
141	141	void delayed_sound_reset(int param);
142	142	void delayed_sound_write(int data);
143	143	void delayed_6502_write(int data);
144
	144
145	145	// sound helpers
146	146	void set_volume_by_type(int volume, device_type type);
147	147	void set_ym2151_volume(int volume);
r18774	r18775
196	196	DECLARE_READ8_MEMBER( earom_r );
197	197	DECLARE_WRITE8_MEMBER( earom_w );
198	198	DECLARE_WRITE8_MEMBER( earom_control_w );
199
	199
200	200	// timer IDs
201	201	enum
202	202	{

trunk/src/mame/machine/pgmprot1.c
r18774	r18775
1018	1018
1019	1019	default:
1020	1020	state->m_valueresponse = 0x880000;
1021		// logerror("Unknown ASIC27 command: %2.2x data: %4.4x\n", (data ^ state->m_valuekey) & 0xff, state->m_value0);
	1021	// logerror("Unknown ASIC27 command: %2.2x data: %4.4x\n", (data ^ state->m_valuekey) & 0xff, state->m_value0);
1022	1022	break;
1023	1023	}
1024	1024	}

trunk/src/tools/jedutil.c
r18774	r18775
1233	1233
1234	1234	if (pal->is_product_term_enabled && !pal->is_product_term_enabled(pal, jed, fuserow))
1235	1235	{
1236		return;
	1236	return;
1237	1237	}
1238	1238
1239	1239	for (index = 0; index < inputpinscount; ++index)

trunk/src/version.c
r18774	r18775
38	38	***************************************************************************/
39	39
40	40	extern const char build_version[];
41		const char build_version[] = "0.147u1 ("__DATE__")";
	41	const char build_version[] = "0.147u2 ("__DATE__")";

trunk/src/lib/formats/upd765_dsk.c
r18774	r18775
299	299	extract_sectors(image, f, sectors, track, head);
300	300	io_generic_write(io, sectdata, (trackf.head_count + head)track_size, track_size);
301	301	}
302
	302
303	303	return true;
304	304	}
305	305

trunk/src/lib/formats/tzx_cas.c
r18774	r18775
496	496	else
497	497	{
498	498	current_block++;
499		}
	499	}
500	500	break;
501	501
502	502	case 0x21: /* Group Start */

trunk/src/emu/video/mc6845.c
r18774	r18775
798	798	UINT8 data = VSS_COPY ? read_videoram(m_block_addr++) : m_data;
799	799
800	800	write_videoram(m_update_addr++, data);
801
	801
802	802	if (--m_word_count)
803	803	{
804	804	m_block_copy_timer->adjust( attotime::from_ticks( 1, m_clock ) );
r18774	r18775
1238	1238	m_de_begin = 0;
1239	1239	m_dram_refresh = 0;
1240	1240	m_sync_polarity = 0;
1241
	1241
1242	1242	m_revision = 1;
1243	1243
1244	1244	// initialize video RAM
1245	1245	UINT8 data = 0xff;
1246
	1246
1247	1247	for (offs_t offset = 0; offset < 0x10000; offset++)
1248	1248	{
1249	1249	write_videoram(offset, data);
r18774	r18775
1527	1527
1528	1528	if (m_max_ras_addr < 16)
1529	1529	{
1530		font_addr = ((m_char_base_addr & 0xe0) << 8) \| (ATTR_ALTERNATE_CHARSET << 12) \| (code << 4) \| (ra & 0x0f);
	1530	font_addr = ((m_char_base_addr & 0xe0) << 8) \| (ATTR_ALTERNATE_CHARSET << 12) \| (code << 4) \| (ra & 0x0f);
1531	1531	}
1532	1532	else
1533	1533	{
1534		font_addr = ((m_char_base_addr & 0xc0) << 8) \| (ATTR_ALTERNATE_CHARSET << 13) \| (code << 5) \| (ra & 0x1f);
	1534	font_addr = ((m_char_base_addr & 0xc0) << 8) \| (ATTR_ALTERNATE_CHARSET << 13) \| (code << 5) \| (ra & 0x1f);
1535	1535	}
1536
	1536
1537	1537	UINT8 data = read_videoram(font_addr);
1538	1538
1539	1539	if (ra >= cdv) data = 0;

trunk/src/emu/video/mc6845.h
r18774	r18775
434	434	virtual UINT8 draw_scanline(int y, bitmap_rgb32 &bitmap, const rectangle &cliprect, void *param);
435	435
436	436	static const device_timer_id TIMER_BLOCK_COPY = 9;
437
	437
438	438	emu_timer *m_block_copy_timer;
439	439	};
440	440

trunk/src/emu/video/pc_vga.c
r18774	r18775
2702	2702	case 0x0d: svga.rgb32_en = 1; divisor = 2; break;
2703	2703	default: fatalerror("TODO: s3 video mode not implemented %02x\n",((s3.ext_misc_ctrl_2) >> 4)); break;
2704	2704	}
2705		/* switch(s3.cr42 & 0x0f) // TODO: confirm clock settings
2706		{
2707		case 0:
2708		xtal = XTAL_25_1748MHz;
2709		break;
2710		case 1:
2711		xtal = XTAL_28_63636MHz;
2712		break;
2713		case 2:
2714		xtal = 40000000;
2715		break;
2716		case 3:
2717		xtal = 3000000;
2718		break;
2719		case 4:
2720		xtal = 50000000;
2721		break;
2722		case 5:
2723		xtal = 77000000;
2724		break;
2725		case 6:
2726		xtal = 36000000;
2727		break;
2728		case 7:
2729		xtal = 45000000;
2730		break;
2731		case 8:
2732		xtal = 1000000;
2733		break;
2734		case 9:
2735		xtal = 1000000;
2736		break;
2737		case 10:
2738		xtal = 79000000;
2739		break;
2740		case 11:
2741		xtal = 31000000;
2742		break;
2743		case 12:
2744		xtal = 94000000;
2745		break;
2746		case 13:
2747		xtal = 65000000;
2748		break;
2749		case 14:
2750		xtal = 75000000;
2751		break;
2752		case 15:
2753		xtal = 71000000;
2754		break;
2755		default:
2756		xtal = 1000000;
2757		}*/
	2705	/* switch(s3.cr42 & 0x0f) // TODO: confirm clock settings
	2706	{
	2707	case 0:
	2708	xtal = XTAL_25_1748MHz;
	2709	break;
	2710	case 1:
	2711	xtal = XTAL_28_63636MHz;
	2712	break;
	2713	case 2:
	2714	xtal = 40000000;
	2715	break;
	2716	case 3:
	2717	xtal = 3000000;
	2718	break;
	2719	case 4:
	2720	xtal = 50000000;
	2721	break;
	2722	case 5:
	2723	xtal = 77000000;
	2724	break;
	2725	case 6:
	2726	xtal = 36000000;
	2727	break;
	2728	case 7:
	2729	xtal = 45000000;
	2730	break;
	2731	case 8:
	2732	xtal = 1000000;
	2733	break;
	2734	case 9:
	2735	xtal = 1000000;
	2736	break;
	2737	case 10:
	2738	xtal = 79000000;
	2739	break;
	2740	case 11:
	2741	xtal = 31000000;
	2742	break;
	2743	case 12:
	2744	xtal = 94000000;
	2745	break;
	2746	case 13:
	2747	xtal = 65000000;
	2748	break;
	2749	case 14:
	2750	xtal = 75000000;
	2751	break;
	2752	case 15:
	2753	xtal = 71000000;
	2754	break;
	2755	default:
	2756	xtal = 1000000;
	2757	}*/
2758	2758	}
2759	2759	else
2760	2760	{
r18774	r18775
2763	2763	svga.rgb16_en = 0;
2764	2764	svga.rgb32_en = 0;
2765	2765	}
2766		// if((vga.miscellaneous_output & 0xc) != 0x0c)
	2766	// if((vga.miscellaneous_output & 0xc) != 0x0c)
2767	2767	xtal = (vga.miscellaneous_output & 0xc) ? XTAL_28_63636MHz : XTAL_25_1748MHz;
2768	2768	recompute_params_clock(divisor, xtal);
2769	2769	}

trunk/src/emu/driver.h
r18774	r18775
202	202	(machine.driver_data<_DriverClass>()->*_Function)();
203	203	}
204	204
205		// member-to-legacy-static wrappers
	205	// member-to-legacy-static wrappers
206	206	template<read_line_device_func _Func>
207	207	DECLARE_READ_LINE_MEMBER( member_wrapper_line ) { return (*_Func)(this); }
208	208	template<write_line_device_func _Func>

trunk/src/emu/sound/2151intf.c
r18774	r18775
1	1	/***************************************************************************
2	2
3		2151intf.c
	3	2151intf.c
4	4
5		Support interface YM2151(OPM)
	5	Support interface YM2151(OPM)
6	6
7	7	***************************************************************************/
8	8
r18774	r18775
75	75	{
76	76	m_irqhandler.resolve_safe();
77	77	m_portwritehandler.resolve_safe();
78
	78
79	79	// stream setup
80	80	int rate = clock() / 64;
81	81	m_stream = stream_alloc(0, 2, rate);

trunk/src/emu/sound/2151intf.h
r18774	r18775
34	34
35	35	// ======================> ym2151_device
36	36
37		class ym2151_device : public device_t,
	37	class ym2151_device : public device_t,
38	38	public device_sound_interface
39	39	{
40	40	public:
r18774	r18775
48	48	// read/write
49	49	DECLARE_READ8_MEMBER( read );
50	50	DECLARE_WRITE8_MEMBER( write );
51
	51
52	52	DECLARE_READ8_MEMBER( status_r );
53	53	DECLARE_WRITE8_MEMBER( register_w );
54	54	DECLARE_WRITE8_MEMBER( data_w );

trunk/src/emu/delegate.h
r18774	r18775
256	256	: m_rawdata(s_null_mfp),
257	257	m_realobject(NULL),
258	258	m_stubfunction(NULL) { }
259
	259
260	260	// copy constructor
261		delegate_mfp(const delegate_mfp &src)
	261	delegate_mfp(const delegate_mfp &src)
262	262	: m_rawdata(src.m_rawdata),
263	263	m_realobject(src.m_realobject),
264	264	m_stubfunction(src.m_stubfunction) { }
r18774	r18775
277	277	// comparison helpers
278	278	bool operator==(const delegate_mfp &rhs) const { return (m_rawdata == rhs.m_rawdata); }
279	279	bool isnull() const { return (m_rawdata == s_null_mfp); }
280
	280
281	281	// getters
282	282	delegate_generic_class real_object(delegate_generic_class original) const { return m_realobject; }
283
	283
284	284	// binding helper
285	285	template<typename _FunctionType>
286	286	void update_after_bind(_FunctionType &funcptr, delegate_generic_class *&object)
r18774	r18775
345	345	mfptype &mfp = reinterpret_cast<mfptype >(&_this->m_rawdata);
346	346	return (reinterpret_cast<_FunctionClass >(_this->m_realobject)->mfp)(p1, p2, p3, p4, p5);
347	347	}
348
	348
349	349	// helper to convert a function of a given type to a generic function, forcing template
350	350	// instantiation to match the source type
351	351	template <typename _SourceType>
r18774	r18775
362	362	};
363	363
364	364	// internal state
365		raw_mfp_data m_rawdata; // raw buffer to hold the copy of the function pointer
	365	raw_mfp_data m_rawdata; // raw buffer to hold the copy of the function pointer
366	366	delegate_generic_class * m_realobject; // pointer to the object used for calling
367	367	delegate_generic_function m_stubfunction; // pointer to our matching stub function
368	368	static raw_mfp_data s_null_mfp; // NULL mfp
r18774	r18775
400	400
401	401	// getters
402	402	delegate_generic_class real_object(delegate_generic_class original) const { return original; }
403
	403
404	404	// binding helper
405	405	template<typename _FunctionType>
406	406	void update_after_bind(_FunctionType &funcptr, delegate_generic_class *&object)
r18774	r18775
546	546	// getters
547	547	bool has_object() const { return (object() != NULL); }
548	548	const char *name() const { return m_name; }
549
	549
550	550	// helpers
551	551	bool isnull() const { return (m_raw_function == NULL && m_raw_mfp.isnull()); }
552	552	bool is_mfp() const { return !m_raw_mfp.isnull(); }
r18774	r18775
575	575	void bind(delegate_generic_class *object)
576	576	{
577	577	m_object = object;
578
	578
579	579	// if we're wrapping a member function pointer, handle special stuff
580	580	if (m_object != NULL && is_mfp())
581	581	m_raw_mfp.update_after_bind(m_function, m_object);

trunk/src/emu/devcb2.c
r18774	r18775
79	79
80	80	//-------------------------------------------------
81	81	// resolve_ioport - resolve an I/O port or fatal
82		// error if we can't find it
	82	// error if we can't find it
83	83	//-------------------------------------------------
84	84
85	85	void devcb2_base::resolve_ioport()
r18774	r18775
93	93
94	94	//-------------------------------------------------
95	95	// resolve_inputline - resolve a device and input
96		// number or fatal error if we can't find it
	96	// number or fatal error if we can't find it
97	97	//-------------------------------------------------
98	98
99	99	void devcb2_base::resolve_inputline()
r18774	r18775
111	111
112	112
113	113	//-------------------------------------------------
114		// resolve_space - resolve an address space or
115		// fatal error if we can't find it
	114	// resolve_space - resolve an address space or
	115	// fatal error if we can't find it
116	116	//-------------------------------------------------
117	117
118	118	void devcb2_base::resolve_space()
r18774	r18775
150	150	{
151	151	// parent first
152	152	devcb2_base::reset(type);
153
	153
154	154	// local stuff
155	155	m_readline = read_line_delegate();
156	156	m_read8 = read8_delegate();
r18774	r18775
163	163
164	164	//-------------------------------------------------
165	165	// resolve - resolve the specified callback to
166		// its final form
	166	// its final form
167	167	//-------------------------------------------------
168	168
169	169	void devcb2_read_base::resolve()
r18774	r18775
181	181	{
182	182	case CALLBACK_NONE:
183	183	break;
184
	184
185	185	case CALLBACK_LINE:
186	186	m_readline.bind_relative_to(*m_device.owner());
187	187	m_target_int = 0;
r18774	r18775
211	211	m_target_int = 0;
212	212	m_adapter = m_read64.isnull() ? &devcb2_read_base::read_constant_adapter : &devcb2_read_base::read64_adapter;
213	213	break;
214
	214
215	215	case CALLBACK_IOPORT:
216	216	resolve_ioport();
217	217	m_target_int = 0;
218	218	m_adapter = (m_target.ioport == NULL) ? &devcb2_read_base::read_constant_adapter : &devcb2_read_base::read_ioport_adapter;
219	219	break;
220
	220
221	221	case CALLBACK_LOG:
222	222	m_adapter = &devcb2_read_base::read_logged_adapter;
223	223	break;
224
	224
225	225	case CALLBACK_CONSTANT:
226	226	m_adapter = &devcb2_read_base::read_constant_adapter;
227	227	break;
228
	228
229	229	case CALLBACK_INPUTLINE:
230	230	throw emu_fatalerror("Device read callbacks can't be connected to input lines\n");
231	231	}
r18774	r18775
239	239
240	240	//-------------------------------------------------
241	241	// resolve_safe - resolve the callback; if not
242		// specified, resolve to a constant callback with
243		// the given value
	242	// specified, resolve to a constant callback with
	243	// the given value
244	244	//-------------------------------------------------
245	245
246	246	void devcb2_read_base::resolve_safe(UINT64 none_constant_value)
r18774	r18775
256	256
257	257
258	258	//-------------------------------------------------
259		// read_unresolved_adapter - error-generating
260		// unresolved adapter
	259	// read_unresolved_adapter - error-generating
	260	// unresolved adapter
261	261	//-------------------------------------------------
262	262
263	263	UINT64 devcb2_read_base::read_unresolved_adapter(address_space &space, offs_t offset, UINT64 mask)
r18774	r18775
328	328
329	329	//-------------------------------------------------
330	330	// read_logged_adapter - log a read and return a
331		// constant
	331	// constant
332	332	//-------------------------------------------------
333	333
334	334	UINT64 devcb2_read_base::read_logged_adapter(address_space &space, offs_t offset, UINT64 mask)
r18774	r18775
371	371	{
372	372	// parent first
373	373	devcb2_base::reset(type);
374
	374
375	375	// local stuff
376	376	m_writeline = write_line_delegate();
377	377	m_write8 = write8_delegate();
r18774	r18775
384	384
385	385	//-------------------------------------------------
386	386	// resolve - resolve the specified callback to
387		// its final form
	387	// its final form
388	388	//-------------------------------------------------
389	389
390	390	void devcb2_write_base::resolve()
r18774	r18775
402	402	{
403	403	case CALLBACK_NONE:
404	404	break;
405
	405
406	406	case CALLBACK_LINE:
407	407	m_writeline.bind_relative_to(*m_device.owner());
408	408	m_adapter = m_writeline.isnull() ? &devcb2_write_base::write_noop_adapter : &devcb2_write_base::write_line_adapter;
r18774	r18775
427	427	m_write64.bind_relative_to(*m_device.owner());
428	428	m_adapter = m_write64.isnull() ? &devcb2_write_base::write_noop_adapter : &devcb2_write_base::write64_adapter;
429	429	break;
430
	430
431	431	case CALLBACK_IOPORT:
432	432	resolve_ioport();
433	433	m_adapter = (m_target.ioport == NULL) ? &devcb2_write_base::write_noop_adapter : &devcb2_write_base::write_ioport_adapter;
434	434	break;
435
	435
436	436	case CALLBACK_LOG:
437	437	m_adapter = &devcb2_write_base::write_logged_adapter;
438	438	break;
439
	439
440	440	case CALLBACK_CONSTANT:
441	441	m_adapter = &devcb2_write_base::write_noop_adapter;
442	442	break;
443
	443
444	444	case CALLBACK_INPUTLINE:
445	445	resolve_inputline();
446	446	m_adapter = &devcb2_write_base::write_inputline_adapter;
r18774	r18775
456	456
457	457	//-------------------------------------------------
458	458	// resolve_safe - resolve the callback; if not
459		// specified, resolve to a no-op
	459	// specified, resolve to a no-op
460	460	//-------------------------------------------------
461	461
462	462	void devcb2_write_base::resolve_safe()
r18774	r18775
469	469
470	470
471	471	//-------------------------------------------------
472		// write_unresolved_adapter - error-generating
473		// unresolved adapter
	472	// write_unresolved_adapter - error-generating
	473	// unresolved adapter
474	474	//-------------------------------------------------
475	475
476	476	void devcb2_write_base::write_unresolved_adapter(address_space &space, offs_t offset, UINT64 data, UINT64 mask)
r18774	r18775
540	540
541	541
542	542	//-------------------------------------------------
543		// write_logged_adapter - logging unresolved
544		// adapter
	543	// write_logged_adapter - logging unresolved
	544	// adapter
545	545	//-------------------------------------------------
546	546
547	547	void devcb2_write_base::write_logged_adapter(address_space &space, offs_t offset, UINT64 data, UINT64 mask)
r18774	r18775
562	562
563	563	//-------------------------------------------------
564	564	// write_inputline_adapter - write to an device's
565		// input line
	565	// input line
566	566	//-------------------------------------------------
567	567
568	568	void devcb2_write_base::write_inputline_adapter(address_space &space, offs_t offset, UINT64 data, UINT64 mask)

trunk/src/emu/devcb2.h
r18774	r18775
59	59	#define DEVCB2_LOGGER(_string, _value) devcb2_base::logger_desc(_string, _value)
60	60	#define DEVCB2_INPUTLINE(_tag, _line) devcb2_base::inputline_desc(_tag, _line)
61	61
62		// wrappers for read callbacks into the owner device
	62	// wrappers for read callbacks into the owner device
63	63	#define DEVCB2_READLINE(_class, _func) read_line_delegate(&_class::_func, #_class "::" #_func, DEVICE_SELF, (_class *)0)
64	64	#define DEVCB2_READ8(_class, _func) read8_delegate(&_class::_func, #_class "::" #_func, DEVICE_SELF, (_class *)0)
65	65	#define DEVCB2_READ16(_class, _func) read16_delegate(&_class::_func, #_class "::" #_func, DEVICE_SELF, (_class *)0)
66	66	#define DEVCB2_READ32(_class, _func) read32_delegate(&_class::_func, #_class "::" #_func, DEVICE_SELF, (_class *)0)
67	67	#define DEVCB2_READ64(_class, _func) read64_delegate(&_class::_func, #_class "::" #_func, DEVICE_SELF, (_class *)0)
68
69		// wrappers for read callbacks into any tagged device
	68
	69	// wrappers for read callbacks into any tagged device
70	70	#define DEVCB2_DEVREADLINE(tag, _class, _func) read_line_delegate(&_class::_func, #_class "::" #_func, tag, (_class *)0)
71	71	#define DEVCB2_DEVREAD8(tag, _class, _func) read8_delegate(&_class::_func, #_class "::" #_func, tag, (_class *)0)
72	72	#define DEVCB2_DEVREAD16(tag, _class, _func) read16_delegate(&_class::_func, #_class "::" #_func, tag, (_class *)0)
73	73	#define DEVCB2_DEVREAD32(tag, _class, _func) read32_delegate(&_class::_func, #_class "::" #_func, tag, (_class *)0)
74	74	#define DEVCB2_DEVREAD64(tag, _class, _func) read64_delegate(&_class::_func, #_class "::" #_func, tag, (_class *)0)
75
76		// wrappers for write callbacks into the owner device
	75
	76	// wrappers for write callbacks into the owner device
77	77	#define DEVCB2_WRITELINE(_class, _func) write_line_delegate(&_class::_func, #_class "::" #_func, DEVICE_SELF, (_class *)0)
78	78	#define DEVCB2_WRITE8(_class, _func) write8_delegate(&_class::_func, #_class "::" #_func, DEVICE_SELF, (_class *)0)
79	79	#define DEVCB2_WRITE16(_class, _func) write16_delegate(&_class::_func, #_class "::" #_func, DEVICE_SELF, (_class *)0)
80	80	#define DEVCB2_WRITE32(_class, _func) write32_delegate(&_class::_func, #_class "::" #_func, DEVICE_SELF, (_class *)0)
81	81	#define DEVCB2_WRITE64(_class, _func) write64_delegate(&_class::_func, #_class "::" #_func, DEVICE_SELF, (_class *)0)
82
83		// wrappers for write callbacks into any tagged device
	82
	83	// wrappers for write callbacks into any tagged device
84	84	#define DEVCB2_DEVWRITELINE(tag, _class, _func) write_line_delegate(&_class::_func, #_class "::" #_func, tag, (_class *)0)
85	85	#define DEVCB2_DEVWRITE8(tag, _class, _func) write8_delegate(&_class::_func, #_class "::" #_func, tag, (_class *)0)
86	86	#define DEVCB2_DEVWRITE16(tag, _class, _func) write16_delegate(&_class::_func, #_class "::" #_func, tag, (_class *)0)
r18774	r18775
137	137	devcb2_base &set_rshift(int rshift) { m_rshift = rshift; return *this; }
138	138	devcb2_base &set_mask(UINT64 mask) { m_mask = mask; return *this; }
139	139	devcb2_base &set_xor(UINT64 xorval) { m_xor = xorval; return *this; }
140
	140
141	141	// construction helper classes
142	142	class null_desc
143	143	{
144	144	public:
145	145	null_desc() { }
146	146	};
147
	147
148	148	class ioport_desc
149	149	{
150	150	public:
151	151	ioport_desc(const char *tag) { m_tag = tag; }
152	152	const char *m_tag;
153	153	};
154
	154
155	155	class constant_desc
156	156	{
157	157	public:
158	158	constant_desc(UINT64 value) { m_value = value; }
159	159	UINT64 m_value;
160	160	};
161
	161
162	162	class logger_desc
163	163	{
164	164	public:
r18774	r18775
191	191	void resolve_ioport();
192	192	void resolve_inputline();
193	193	void resolve_space();
194
	194
195	195	// the callback target is going to be one of these
196	196	union callback_target
197	197	{
r18774	r18775
199	199	device_t * device;
200	200	ioport_port * ioport;
201	201	};
202
	202
203	203	// configuration
204	204	device_t & m_device; // reference to our owning device
205	205	callback_type m_type; // type of callback registered
r18774	r18775
212	212	address_space * m_space; // target address space
213	213	callback_target m_target; // resolved pointer to target object
214	214	int m_rshift; // right shift to apply to data read
215		UINT64 m_mask; // mask to apply to data read
216		UINT64 m_xor; // XOR to apply to data read
	215	UINT64 m_mask; // mask to apply to data read
	216	UINT64 m_xor; // XOR to apply to data read
217	217	};
218	218
219	219
r18774	r18775
224	224	protected:
225	225	// construction/destruction
226	226	devcb2_read_base(device_t &device, UINT64 defmask);
227
	227
228	228	public:
229	229	// callback configuration
230	230	using devcb2_base::set_callback;
r18774	r18775
233	233	devcb2_base &set_callback(read16_delegate func) { reset(CALLBACK_16); m_read16 = func; return *this; }
234	234	devcb2_base &set_callback(read32_delegate func) { reset(CALLBACK_32); m_read32 = func; return *this; }
235	235	devcb2_base &set_callback(read64_delegate func) { reset(CALLBACK_64); m_read64 = func; return *this; }
236
	236
237	237	// resolution
238	238	void resolve();
239	239	void resolve_safe(UINT64 none_constant_value);
r18774	r18775
273	273	protected:
274	274	// construction/destruction
275	275	devcb2_write_base(device_t &device, UINT64 defmask);
276
	276
277	277	public:
278	278	// callback configuration
279	279	using devcb2_base::set_callback;

trunk/src/emu/cpu/avr8/avr8.c
r18774	r18775
1750	1750	SREG_W(AVR8_SREG_I, 1);
1751	1751	/*if (cpustate->interrupt_pending)
1752	1752	{
1753		avr8_poll_interrupt(cpustate);
1754		cpustate->interrupt_pending = false;
1755		}*/
	1753	avr8_poll_interrupt(cpustate);
	1754	cpustate->interrupt_pending = false;
	1755	}*/
1756	1756	opcycles = 4;
1757	1757	break;
1758	1758	case 0x0080: // SLEEP
r18774	r18775
2032	2032	/* --- the following bits of info are set as 64-bit signed integers --- */
2033	2033	case CPUINFO_INT_PC: /* intentional fallthrough */
2034	2034	case CPUINFO_INT_REGISTER + AVR8_PC: cpustate->pc = info->i; break;
2035		case CPUINFO_INT_REGISTER + AVR8_SREG: cpustate->status = info->i; break;
	2035	case CPUINFO_INT_REGISTER + AVR8_SREG: cpustate->status = info->i; break;
2036	2036	case CPUINFO_INT_REGISTER + AVR8_R0: cpustate->r[ 0] = info->i; break;
2037	2037	case CPUINFO_INT_REGISTER + AVR8_R1: cpustate->r[ 1] = info->i; break;
2038	2038	case CPUINFO_INT_REGISTER + AVR8_R2: cpustate->r[ 2] = info->i; break;
r18774	r18775
2098	2098
2099	2099	case CPUINFO_INT_PC: /* intentional fallthrough */
2100	2100	case CPUINFO_INT_REGISTER + AVR8_PC: info->i = cpustate->pc << 1; break;
2101		case CPUINFO_INT_REGISTER + AVR8_SREG: info->i = cpustate->status; break;
	2101	case CPUINFO_INT_REGISTER + AVR8_SREG: info->i = cpustate->status; break;
2102	2102
2103	2103	/* --- the following bits of info are returned as pointers to data or functions --- */
2104	2104	case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(avr8); break;

trunk/src/emu/cpu/rsp/rspdrc.c
r18774	r18775
592	592	rsp->sp_reg_r_func.resolve(config->sp_reg_r_cb, *device);
593	593	rsp->sp_reg_w_func.resolve(config->sp_reg_w_cb, *device);
594	594	rsp->sp_set_status_func.resolve(config->sp_set_status_cb, *device);
595
	595
596	596	rsp->irq_callback = irqcallback;
597	597	rsp->device = device;
598	598	rsp->program = &device->space(AS_PROGRAM);

trunk/src/emu/cpu/rsp/rsp.h
r18774	r18775
188	188	UINT8 *imem8;
189	189
190	190	rspimp_state* impstate;
191
	191
192	192	devcb_resolved_read32 dp_reg_r_func;
193	193	devcb_resolved_write32 dp_reg_w_func;
194	194	devcb_resolved_read32 sp_reg_r_func;
195	195	devcb_resolved_write32 sp_reg_w_func;
196		devcb_resolved_write32 sp_set_status_func;
	196	devcb_resolved_write32 sp_set_status_func;
197	197	};
198	198
199	199	DECLARE_LEGACY_CPU_DEVICE(RSP, rsp);

trunk/src/emu/machine/i8243.h
r18774	r18775
49	49	// static configuration helpers
50	50	template<class _Object> static devcb2_base &set_read_handler(device_t &device, _Object object) { return downcast<i8243_device &>(device).m_readhandler.set_callback(object); }
51	51	template<class _Object> static devcb2_base &set_write_handler(device_t &device, _Object object) { return downcast<i8243_device &>(device).m_writehandler.set_callback(object); }
52
	52
53	53	DECLARE_READ8_MEMBER(i8243_p2_r);
54	54	DECLARE_WRITE8_MEMBER(i8243_p2_w);
55	55

trunk/src/emu/machine/pla.c
r18774	r18775
77	77	{
78	78	memory_region *region = machine().root_device().memregion(tag());
79	79	jed_data jed;
80
	80
81	81	jedbin_parse(region->base(), region->bytes(), &jed);
82	82
83	83	UINT32 fusenum = 0;

trunk/src/emu/machine/scsicb.c
r18774	r18775
128	128	state = 0;
129	129	}
130	130
131		verboselog( 1, machine(), "%s get_scsi_line %s %d\n", tag(), get_line_name( mask ), state );
	131	verboselog( 1, machine(), "%s get_scsi_line %s %d\n", tag(), get_line_name( mask ), state );
132	132
133	133	return state;
134	134	}
135	135
136	136	void scsicb_device::set_scsi_line( UINT32 mask, UINT8 state )
137	137	{
138		verboselog( 1, machine(), "%s set_scsi_line %s %d\n", tag(), get_line_name( mask ), state );
	138	verboselog( 1, machine(), "%s set_scsi_line %s %d\n", tag(), get_line_name( mask ), state );
139	139
140	140	if( state )
141	141	{

trunk/src/mess/machine/rmnimbus.c
r18774	r18775
2987	2987	{
2988	2988	/*
2989	2989
2990		bit description
	2990	bit description
2991	2991
2992		0 JOY 0-Up or mouse XB
2993		1 JOY 0-Down or mouse XA
2994		2 JOY 0-Left or mouse YA
2995		3 JOY 0-Right or mouse YB
2996		4 JOY 0-b0 or mouse rbutton
2997		5 JOY 0-b1 or mouse lbutton
2998		6 ?? always reads 1
2999		7 ?? always reads 1
	2992	0 JOY 0-Up or mouse XB
	2993	1 JOY 0-Down or mouse XA
	2994	2 JOY 0-Left or mouse YA
	2995	3 JOY 0-Right or mouse YB
	2996	4 JOY 0-b0 or mouse rbutton
	2997	5 JOY 0-b1 or mouse lbutton
	2998	6 ?? always reads 1
	2999	7 ?? always reads 1
3000	3000
3001		*/
	3001	*/
3002	3002	UINT8 result;
3003	3003	//int pc=machine().device(MAINCPU_TAG)->safe_pc();
3004	3004	mouse_joy_state *state = &m_nimbus_mouse;

trunk/src/mess/machine/b2m.c
r18774	r18775
206	206	{
207	207	UINT8 drive = ((data >> 1) & 1) ^ 1;
208	208	UINT8 side = (data & 1) ^ 1;
209
	209
210	210	static const char *names[] = { "fd0", "fd1"};
211	211	floppy_image_device *floppy = NULL;
212	212	floppy_connector *con = machine().device<floppy_connector>(names[drive]);
r18774	r18775
219	219	m_b2m_drive = drive;
220	220	}
221	221	floppy->ss_w(side);
222		if (m_b2m_side!=side) {
	222	if (m_b2m_side!=side) {
223	223	m_b2m_side = side;
224	224	}
225	225	}

trunk/src/mess/machine/64h156.c
r18774	r18775
658	658	{
659	659	int track = floppy_drive_get_current_track(m_image);
660	660	int tracks = (data - track) & 0x03;
661
	661
662	662	if (tracks == 3)
663	663	{
664	664	tracks = -1;

trunk/src/mess/machine/macadb.c
r18774	r18775
1	1	/***************************************************************************
2	2
3	3	macadb.c - handles various aspects of ADB on the Mac.
4
	4
5	5	***************************************************************************/
6	6
7	7	#include "emu.h"
r18774	r18775
1254	1254	}
1255	1255	break;
1256	1256
1257		case LST_BIT0:
1258		case LST_BIT1:
1259		case LST_BIT2:
1260		case LST_BIT3:
1261		case LST_BIT4:
1262		case LST_BIT5:
1263		case LST_BIT6:
1264		case LST_BIT7:
	1257	case LST_BIT0:
	1258	case LST_BIT1:
	1259	case LST_BIT2:
	1260	case LST_BIT3:
	1261	case LST_BIT4:
	1262	case LST_BIT5:
	1263	case LST_BIT6:
	1264	case LST_BIT7:
1265	1265	if (!state)
1266	1266	{
1267	1267	if (dtime >= 90) // "1" bit

trunk/src/mess/machine/upd765.c
r18774	r18775
444	444	}
445	445	fifo[fifo_pos++] = data;
446	446	fifo_expected--;
447
	447
448	448	int thr = (fifocfg & FIF_THR)+1;
449	449	if(!fifo_write && (!fifo_expected \|\| fifo_pos >= thr \|\| (fifocfg & FIF_DIS)))
450	450	enable_transfer();
r18774	r18775
674	674	if(cur_live.bit_counter & 15)
675	675	break;
676	676	int slot = (cur_live.bit_counter >> 4)-1;
677
	677
678	678	if(0)
679	679	fprintf(stderr, "%s: slot=%d data=%02x crc=%04x\n", tts(cur_live.tm).cstr(), slot, cur_live.data_reg, cur_live.crc);
680	680	cur_live.idbuf[slot] = cur_live.data_reg;
r18774	r18775
910	910	return;
911	911	}
912	912	break;
913
	913
914	914	default:
915	915	logerror("%s: Unknown live state %d\n", tts(cur_live.tm).cstr(), cur_live.state);
916	916	return;
r18774	r18775
1623	1623
1624	1624	case SCAN_ID_FAILED:
1625	1625	fprintf(stderr, "RNF\n");
1626		// command_end(fi, true, 1);
	1626	// command_end(fi, true, 1);
1627	1627	return;
1628	1628
1629	1629	case SECTOR_READ:
r18774	r18775
1645	1645	result[5] = command[4];
1646	1646	result[6] = command[5];
1647	1647	result_pos = 7;
1648		// command_end(fi, true, 0);
	1648	// command_end(fi, true, 0);
1649	1649	return;
1650	1650
1651	1651	default:
r18774	r18775
1992	1992
1993	1993	void upd765_family_device::live_write_raw(UINT16 raw)
1994	1994	{
1995		// logerror("write %04x %04x\n", raw, cur_live.crc);
	1995	// logerror("write %04x %04x\n", raw, cur_live.crc);
1996	1996	cur_live.shift_reg = raw;
1997	1997	cur_live.data_bit_context = raw & 1;
1998	1998	}
r18774	r18775
2012	2012	cur_live.data_reg = mfm;
2013	2013	cur_live.shift_reg = raw;
2014	2014	cur_live.data_bit_context = context;
2015		// logerror("write %02x %04x %04x\n", mfm, cur_live.crc, raw);
	2015	// logerror("write %02x %04x %04x\n", mfm, cur_live.crc, raw);
2016	2016	}
2017	2017
2018	2018	bool upd765_family_device::sector_matches() const

trunk/src/mess/machine/upd765.h
r18774	r18775
52	52	virtual void setup_drq_cb(line_cb cb) = 0;
53	53
54	54	/* Note that the address map must cover and handle the whole 0-7
55		* range. The upd765, while conforming to the rest of the
56		* interface, is not eligible as a result.
57		*/
	55	* range. The upd765, while conforming to the rest of the
	56	* interface, is not eligible as a result.
	57	*/
58	58
59	59	virtual DECLARE_ADDRESS_MAP(map, 8) = 0;
60	60
r18774	r18775
168	168	SPEC_ND = 0x0001,
169	169	};
170	170
171
	171
172	172	enum {
173	173	// General "doing nothing" state
174	174	IDLE,

trunk/src/mess/machine/c8280.c
r18774	r18775
313	313	NULL
314	314	};
315	315
316		static struct wd17xx_interface fdc_intf =
	316	static struct wd17xx_interface fdc_intf =
317	317	{
318	318	DEVCB_NULL,
319	319	DEVCB_CPU_INPUT_LINE(M6502_FDC_TAG, M6502_IRQ_LINE),
r18774	r18775
407	407	// state saving
408	408	save_item(NAME(m_rfdo));
409	409	save_item(NAME(m_daco));
410		save_item(NAME(m_atna));
	410	save_item(NAME(m_atna));
411	411	save_item(NAME(m_fk5));
412	412	}
413	413
r18774	r18775
467	467	READ8_MEMBER( c8280_device::fk5_r )
468	468	{
469	469	/*
470
471		bit description
472
473		0 DS1
474		1 DS2
475		2 _DDEN
476		3 DCHG
477		4 TSID
478		5 MOTOR ENABLE
479		6 0
480		7 0
481
482		*/
483	470
	471	bit description
	472
	473	0 DS1
	474	1 DS2
	475	2 _DDEN
	476	3 DCHG
	477	4 TSID
	478	5 MOTOR ENABLE
	479	6 0
	480	7 0
	481
	482	*/
	483
484	484	UINT8 data = m_fk5;
485	485
486	486	if (BIT(m_fk5, 0))
r18774	r18775
500	500	WRITE8_MEMBER( c8280_device::fk5_w )
501	501	{
502	502	/*
503
504		bit description
505
506		0 DS1
507		1 DS2
508		2 _DDEN
509		3
510		4
511		5 MOTOR ENABLE
512		6
513		7
514
515		*/
516	503
	504	bit description
	505
	506	0 DS1
	507	1 DS2
	508	2 _DDEN
	509	3
	510	4
	511	5 MOTOR ENABLE
	512	6
	513	7
	514
	515	*/
	516
517	517	m_fk5 = data & 0x3f;
518	518
519	519	// drive select

trunk/src/mess/machine/vcsctrl.h
r18774	r18775
47	47
48	48	// computer interface
49	49
50		// Data returned by the joy_r methods:
	50	// Data returned by the joy_r methods:
51	51	// bit 0 - pin 1 - Up
52	52	// bit 1 - pin 2 - Down
53	53	// bit 2 - pin 3 - Left
54	54	// bit 3 - pin 4 - Right
55		// bit 4 - pin 5 -
	55	// bit 4 - pin 5 -
56	56	// bit 5 - pin 6 - Button
57	57	// pin 7 - +5V
58	58	// pin 8 - GND
59		// bit 6 - pin 9 -
	59	// bit 6 - pin 9 -
60	60	//
61	61	UINT8 joy_r();
62	62	DECLARE_READ8_MEMBER( joy_r );

trunk/src/mess/machine/isa_ide.c
r18774	r18775
36	36	{
37	37	m_isa->irq14_w(state);
38	38	}
39		else
	39	else
40	40	{
41	41	m_isa->irq15_w(state);
42	42	}

trunk/src/mess/machine/c128_comal80.c
r18774	r18775
94	94	4 A14
95	95	5 A15
96	96	6 A16
97		7 A17
	97	7 A17
98	98
99	99	*/
100	100

trunk/src/mess/machine/cbm2_graphic.c
r18774	r18775
43	43	/*
44	44	static const ef9365_interface gdp_intf =
45	45	{
46		SCREEN_TAG
	46	SCREEN_TAG
47	47	};
48	48	*/
49	49
r18774	r18775
52	52	//-------------------------------------------------
53	53
54	54	static MACHINE_CONFIG_FRAGMENT( cbm2_graphic_a )
55		/* MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
56		MCFG_SCREEN_UPDATE_DEVICE(EF9365_TAG, ef9365_device, screen_update)
57		MCFG_SCREEN_SIZE(512, 512)
58		MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 0, 512-1)
59		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
60		MCFG_SCREEN_REFRESH_RATE(50)
	55	/* MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
	56	MCFG_SCREEN_UPDATE_DEVICE(EF9365_TAG, ef9365_device, screen_update)
	57	MCFG_SCREEN_SIZE(512, 512)
	58	MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 0, 512-1)
	59	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
	60	MCFG_SCREEN_REFRESH_RATE(50)
61	61
62		MCFG_EF9365_ADD(EF9365_TAG, gdp_intf)*/
	62	MCFG_EF9365_ADD(EF9365_TAG, gdp_intf)*/
63	63	MACHINE_CONFIG_END
64	64
65	65
r18774	r18775
68	68	//-------------------------------------------------
69	69
70	70	static MACHINE_CONFIG_FRAGMENT( cbm2_graphic_b )
71		/* MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
72		MCFG_SCREEN_UPDATE_DEVICE(EF9366_TAG, ef9366_device, screen_update)
73		MCFG_SCREEN_SIZE(512, 256)
74		MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 0, 256-1)
75		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
76		MCFG_SCREEN_REFRESH_RATE(50)
	71	/* MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
	72	MCFG_SCREEN_UPDATE_DEVICE(EF9366_TAG, ef9366_device, screen_update)
	73	MCFG_SCREEN_SIZE(512, 256)
	74	MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 0, 256-1)
	75	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
	76	MCFG_SCREEN_REFRESH_RATE(50)
77	77
78		MCFG_EF9366_ADD(EF9366_TAG, gdp_intf)*/
	78	MCFG_EF9366_ADD(EF9366_TAG, gdp_intf)*/
79	79	MACHINE_CONFIG_END
80	80
81	81

trunk/src/mess/machine/mos8722.c
r18774	r18775
258	258	int fsdir = MCR_FSDIR;
259	259
260	260	m_reg[MCR] = data;
261
	261
262	262	if (_8500 != MCR_8500) m_out_z80en_func(MCR_8500);
263	263	if (fsdir != MCR_FSDIR) m_out_fsdir_func(MCR_FSDIR);
264	264	break;

trunk/src/mess/machine/macrtc.c
r18774	r18775
2	2
3	3	macrtc.c - the real-time clock & NVRAM chip used in early 680x0 Macs,
4	4	Apple part numbers 343-0040 (original) and 343-0042 (with extended PRAM)
5
	5
6	6	The IIgs has this chip also, but the VGC contains a relatively
7	7	sophisticated logic block that offloads the low-level serial comms
8	8	from the CPU, which makes it look quite different to software.
9
	9
10	10	***************************************************************************/
11	11
12	12	#include "emu.h"

trunk/src/mess/machine/macrtc.h
r18774	r18775
29	29	// ======================> rtc3430042_device
30	30
31	31	class rtc3430042_device : public device_t,
32		public device_rtc_interface,
	32	public device_rtc_interface,
33	33	public device_nvram_interface
34	34	{
35	35	public:

trunk/src/mess/includes/fidelz80.h
r18774	r18775
66	66	DECLARE_INPUT_CHANGED_MEMBER(fidelz80_trigger_reset);
67	67	DECLARE_INPUT_CHANGED_MEMBER(abc_trigger_reset);
68	68	TIMER_DEVICE_CALLBACK_MEMBER(nmi_timer);
69
	69
70	70	DECLARE_WRITE8_MEMBER(digit_w);
71	71	};
72	72

trunk/src/mess/includes/samcoupe.h
r18774	r18775
44	44	sam_bank_read_ptr[2] = NULL;
45	45	sam_bank_write_ptr[2] = NULL;
46	46	sam_bank_read_ptr[3] = NULL;
47		sam_bank_write_ptr[3] = NULL;
	47	sam_bank_write_ptr[3] = NULL;
48	48	}
49	49
50	50	virtual void video_start();

trunk/src/mess/includes/c128.h
r18774	r18775
109	109
110	110	inline void check_interrupts();
111	111	void read_pla(offs_t offset, offs_t ca, offs_t vma, int ba, int rw, int aec, int z80io, int ms3, int ms2, int ms1, int ms0,
112		int sden, int dir, int gwe, int rom1, int rom2, int rom3, int rom4, int charom, int colorram, int vic,
	112	int sden, int dir, int gwe, int rom1, int rom2, int rom3, int rom4, int charom, int colorram, int vic,
113	113	int from1, int romh, int roml, int dwe, int ioacc, int clrbank, int iocs, int casenb);
114	114	UINT8 read_memory(address_space &space, offs_t offset, offs_t vma, int ba, int aec, int z80io);
115	115	void write_memory(address_space &space, offs_t offset, offs_t vma, UINT8 data, int ba, int aec, int z80io);
r18774	r18775
133	133	INTERRUPT_GEN_MEMBER( frame_interrupt );
134	134	DECLARE_WRITE_LINE_MEMBER( vic_irq_w );
135	135	DECLARE_WRITE8_MEMBER( vic_k_w );
136
	136
137	137	DECLARE_READ8_MEMBER( sid_potx_r );
138	138	DECLARE_READ8_MEMBER( sid_poty_r );
139	139

trunk/src/mess/video/mos6566.c
r18774	r18775
363	363	if (m_ba)
364	364	{
365	365	set_ba(CLEAR_LINE);
366		m_rdy_cycles += 55 - m_cycle;
	366	m_rdy_cycles += 55 - m_cycle;
367	367	}
368	368	}
369	369	else
r18774	r18775
437	437
438	438	if (!m_ba && m_aec)
439	439	{
440		m_matrix_line[m_ml_index] = 0xff;
	440	m_matrix_line[m_ml_index] = 0xff;
441	441	}
442	442	else
443	443	{
r18774	r18775
1427	1427	// Last cycle
1428	1428	m_cycle = 1;
1429	1429	}
1430
	1430
1431	1431	m_phi0 = 1;
1432	1432	set_aec(BIT(m_aec_delay, 2));
1433	1433
r18774	r18775
1827	1827	check_sprite_dma();
1828	1828
1829	1829	spr_ba(0);
1830
	1830
1831	1831	m_cycle++;
1832	1832	break;
1833	1833
r18774	r18775
1996	1996	// Last cycle
1997	1997	m_cycle = 1;
1998	1998	}
1999
	1999
2000	2000	m_phi0 = 1;
2001	2001	set_aec(BIT(m_aec_delay, 2));
2002	2002
r18774	r18775
2780	2780	{
2781	2781	m_cpu->set_unscaled_clock(clock() << BIT(data, 0));
2782	2782	}
2783
	2783
2784	2784	m_reg[offset] = data \| 0xfc;
2785	2785
2786	2786	m_on = !BIT(data, 0);

trunk/src/mess/video/mos6566.h
r18774	r18775
314	314	DECLARE_WRITE8_MEMBER( write );
315	315
316	316	DECLARE_WRITE_LINE_MEMBER( lp_w );
317
	317
318	318	DECLARE_READ_LINE_MEMBER( phi0_r );
319	319	DECLARE_READ_LINE_MEMBER( ba_r );
320	320	DECLARE_READ_LINE_MEMBER( aec_r );

trunk/src/mess/video/pds30_procolor816.c
r18774	r18775
1	1	/***************************************************************************
2	2
3	3	Lapis ProColor Server 8*16 video card
4
	4
5	5	FsFF6001: DAC color # (seems to have the data bits perfectly reversed)
6	6	FsFF6003: DAC color write (not bitswapped)
7	7	FsFF6017: Mode (13 = 1bpp, 17 = 2bpp, 1b = 4bpp, 1e = 8bpp, 0a = 15bpp)
8	8	FsFF7000: Bit 2 is VBL IRQ enable/ack
9	9	FsFF7001: Bit 0 is VBL status
10
	10
11	11	***************************************************************************/
12	12
13	13	#include "emu.h"

trunk/src/mess/video/nubus_m2video.c
r18774	r18775
1	1	/***************************************************************************
2	2
3	3	Apple Macintosh II Video Card (630-0153) emulation
4
	4
5	5	Video ASIC is "TFB" 344-0001
6	6	RAMDAC is Bt453: control at Fs09001C, data at Fs090018
7	7	Fs08000x is general framebuffer control (video mode at 0)

trunk/src/mess/video/pds30_30hr.c
r18774	r18775
1	1	/***************************************************************************
2	2
3		Micron/XCEED Technologies Color 30HR
4
	3	Micron/XCEED Technologies Color 30HR
	4
5	5	Fs800000 - Mode A
6	6	FsA00000 - Mode B
7	7	FsC00000 - RAMDAC write offset
8	8	FsC00004 - RAMDAC write data
9	9	FsC00008 - RAMDAC write mask
10	10	FsC0000C - RAMDAC read offset
11
	11
12	12	***************************************************************************/
13	13
14	14	#include "emu.h"

trunk/src/mess/video/pds30_sigmalview.c
r18774	r18775
1	1	/***************************************************************************
2	2
3	3	Sigma Designs L-View card
4
	4
5	5	***************************************************************************/
6	6
7	7	#include "emu.h"
r18774	r18775
22	22
23	23	ROM_START( lview )
24	24	ROM_REGION(0x4000, LVIEW_ROM_REGION, 0)
25		ROM_LOAD( "lv_asi_4_00.bin", 0x000000, 0x004000, CRC(b806f875) SHA1(1e58593b1a8720193d1651b0d8a0d43e4e47563d) )
	25	ROM_LOAD( "lv_asi_4_00.bin", 0x000000, 0x004000, CRC(b806f875) SHA1(1e58593b1a8720193d1651b0d8a0d43e4e47563d) )
26	26	ROM_END
27	27
28	28	//**************************************************************************

trunk/src/mess/video/timex.c
r18774	r18775
182	182	{
183	183	/* for now TS2068 will do a full-refresh */
184	184	int count;
185
	185
186	186	if (m_border_bitmap.valid())
187	187	copyscrollbitmap(bitmap, m_border_bitmap, 0, 0, 0, 0, cliprect);
188	188

trunk/src/mess/video/pds30_mc30.c
r18774	r18775
1	1	/***************************************************************************
2	2
3	3	Micron/XCEED Technologies MacroColor 30
4
	4
5	5	Similar to the 30HR, but registers are rearranged and 24bpp support
6	6	was added.
7	7
r18774	r18775
25	25
26	26	ROM_START( xceedmc30 )
27	27	ROM_REGION(0x8000, XCEEDMC30_ROM_REGION, 0)
28		ROM_LOAD( "0390.bin", 0x000000, 0x008000, CRC(adea7a18) SHA1(9141eb1a0e5061e0409d65a89b4eaeb119ee4ffb) )
	28	ROM_LOAD( "0390.bin", 0x000000, 0x008000, CRC(adea7a18) SHA1(9141eb1a0e5061e0409d65a89b4eaeb119ee4ffb) )
29	29	ROM_END
30	30
31	31	//**************************************************************************

trunk/src/mess/video/spectrum.c
r18774	r18775
59	59	if (state)
60	60	{
61	61	m_frame_number++;
62
	62
63	63	if (m_frame_number >= m_frame_invert_count)
64	64	{
65	65	m_frame_number = 0;
r18774	r18775
110	110	int x, y, b, scrx, scry;
111	111	unsigned short ink, pap;
112	112	unsigned char attr, scr;
113		// int full_refresh = 1;
	113	// int full_refresh = 1;
114	114
115	115	if (m_border_bitmap.valid())
116	116	copyscrollbitmap(bitmap, m_border_bitmap, 0, 0, 0, 0, cliprect);
r18774	r18775
224	224	UINT16* bm = &state->m_border_bitmap.pix16(state->m_previous_border_y);
225	225
226	226	if (state->m_previous_border_x < width)
227		bm[state->m_previous_border_x] = colour;
	227	bm[state->m_previous_border_x] = colour;
228	228	}
229	229
230	230	spectrum_GetNextPos(machine, state->m_previous_border_x, state->m_previous_border_y);
r18774	r18775
238	238	}
239	239
240	240
241		}
		No newline at end of file
	241	}

trunk/src/mess/video/pds30_cb264.c
r18774	r18775
1	1	/***************************************************************************
2	2
3	3	RasterOps ColorBoard 264/SE30 video card emulation
4
	4
5	5	***************************************************************************/
6	6
7	7	#include "emu.h"

trunk/src/mess/mess.lst
r18774	r18775
657	657	a3000 // Commodore Amiga 3000
658	658	a3000n //
659	659	a1200 // Commodore Amiga 1200
660		a1200n //
	660	a1200n //
661	661	cdtv // Commodore CDTV
662	662	cd32 // Commodore Amiga CD32
663	663

trunk/src/mess/drivers/mac.c
r18774	r18775
33	33	SCC:
34	34	PB_EXT from mouse Y circuitry
35	35	PA_EXT from mouse X circuitry
36
	36
37	37	NOTES:
38	38	- pmac6100: with recent PPC fixes now gets into the 68000 emulator and executes part of the 680x0 startup code.
39	39	'g 6802c73c' to get to the interesting part (wait past the boot chime). PPC register r24 is the 68000 PC.
40	40	when the PC hits GetCPUID, the move.l (a2), d0 at PC = 0x10000 will cause an MMU fault (jump to 0xFFF00300). why?
41	41	a2 = 0x5ffffffc (the CPU ID register). MMU is unable to resolve this; defect in the MMU emulation probable.
42
	42
43	43	****************************************************************************/
44	44
45	45

trunk/src/mess/drivers/plus4.c
r18774	r18775
849	849	{
850	850	m_c2 = memregion("c2")->base();
851	851	}
852
	852
853	853	// initialize memory
854	854	UINT8 data = 0xff;
855	855

trunk/src/mess/drivers/prof180x.c
r18774	r18775
173	173	AM_RANGE(0x09, 0x09) AM_MASK(0xff00) AM_READ(status_r)
174	174
175	175	// Seriously?
176		// AM_RANGE(0x0a, 0x0a) AM_MIRROR(0xff00) AM_DEVREADWRITE_LEGACY(FDC9268_TAG, upd765_dack_r, upd765_dack_w)
	176	// AM_RANGE(0x0a, 0x0a) AM_MIRROR(0xff00) AM_DEVREADWRITE_LEGACY(FDC9268_TAG, upd765_dack_r, upd765_dack_w)
177	177	AM_RANGE(0x0b, 0x0b) AM_MIRROR(0xff00) AM_DEVWRITE(CENTRONICS_TAG, centronics_device, write)
178	178	AM_RANGE(0x0c, 0x0d) AM_MIRROR(0xff00) AM_DEVICE(FDC9268_TAG, upd765a_device, map)
179	179	ADDRESS_MAP_END

trunk/src/mess/drivers/a2600.c
r18774	r18775
1284	1284	/* Right controller port */
1285	1285	m_joy2->joy_w( data & 0x0f );
1286	1286
1287		// switch( machine().root_device().ioport("CONTROLLERS")->read() % CATEGORY_SELECT )
1288		// {
1289		// case 0x0a: /* KidVid voice module */
1290		// machine().device<cassette_image_device>(CASSETTE_TAG)->change_state(( data & 0x02 ) ? (cassette_state)CASSETTE_MOTOR_DISABLED : (cassette_state)(CASSETTE_MOTOR_ENABLED \| CASSETTE_PLAY), (cassette_state)CASSETTE_MOTOR_DISABLED );
1291		// break;
1292		// }
	1287	// switch( machine().root_device().ioport("CONTROLLERS")->read() % CATEGORY_SELECT )
	1288	// {
	1289	// case 0x0a: /* KidVid voice module */
	1290	// machine().device<cassette_image_device>(CASSETTE_TAG)->change_state(( data & 0x02 ) ? (cassette_state)CASSETTE_MOTOR_DISABLED : (cassette_state)(CASSETTE_MOTOR_ENABLED \| CASSETTE_PLAY), (cassette_state)CASSETTE_MOTOR_DISABLED );
	1291	// break;
	1292	// }
1293	1293	}
1294	1294
1295	1295	READ8_MEMBER(a2600_state::switch_A_r)

trunk/src/mess/drivers/hp9k.c
r18774	r18775
31	31
32	32	===
33	33
34		TODO: boot tests fail
	34	TODO: boot tests fail
35	35
36	36	****************************************************************************/
37	37
r18774	r18775
53	53	0x00, // 256 bytes idprom
54	54	'2', '0', '1', '0', 'A', '0', '0', '0', '0', '0', '0', // serial in ascii DDDDCSSSSSS date code, country, serial number
55	55	'9', '8', '1', '6', 'A', ' ', ' ', // product number
56		0xff, // 8 bits processor board config
	56	0xff, // 8 bits processor board config
57	57	0x01, // keyboard 98203B
58	58	0x02, // CRT alpha see crtid for monitor
59	59	0x03, // HP-IB
60	60	0x04, // Graphics
61		0xff, // end
	61	0xff, // end
62	62	0xff,
63	63	0xff,
64	64	0xff,
r18774	r18775
113	113	int crtc_curreg;
114	114	int crtc_addrStartHi;
115	115	int crtc_addrStartLow;
116
	116
117	117	void calc_prom_crc(UINT8* prom);
118	118	void putChar(UINT8 thec,int x,int y,bitmap_ind16 &bitmap);
119
	119
120	120	public:
121	121	hp9k_state(const machine_config &mconfig, device_type type, const char *tag)
122	122	: driver_device(mconfig, type, tag),
r18774	r18775
136	136	required_device<cpu_device> m_maincpu;
137	137	//required_device<device_t> m_terminal;
138	138	required_device<mc6845_device> m_6845;
139
	139
140	140	UINT8 m_videoram[0x4000];
141	141	UINT8 m_screen[0x800];
142	142
r18774	r18775
168	168	{
169	169	int chksum;
170	170	int i;
171
	171
172	172	chksum = 0;
173		for (i=0; i < 256; i+=2)
	173	for (i=0; i < 256; i+=2)
174	174	{
175	175	chksum += ((prom[i] << 8) \| prom[i+1]);
176	176	if (chksum&0x10000) chksum++;
177	177	chksum&=0xffff;
178	178	}
179
	179
180	180	chksum=(chksum+1)&0xffff;
181
182		if (chksum!=0)
	181
	182	if (chksum!=0)
183	183	{
184	184	chksum=(0x10000-chksum);
185	185	prom[0]=(UINT8)(chksum>>8);
r18774	r18775
268	268	else
269	269	{
270	270	//printf("videoram write [%x] at [%x]\n",data,offset);
271
	271
272	272	if (mem_mask==0xff00)
273	273	{
274	274	m_screen[offset&0x7ff]=data>>8;
r18774	r18775
346	346	void hp9k_state::putChar(UINT8 thec,int x,int y,bitmap_ind16 &bitmap)
347	347	{
348	348	const UINT8* pchar=machine().gfx[0]->get_data(thec);
349
	349
350	350	for (int py=0;py<HP9816_CHDIMY;py++)
351	351	{
352	352	for (int px=0;px<HP9816_CHDIMX;px++)
r18774	r18775
375	375	chStart++;
376	376	}
377	377	}
378
	378
379	379	//putChar(0x44,0,0,pscr);
380	380	return 0;
381	381	}
r18774	r18775
416	416	MCFG_GFXDECODE(hp9k)
417	417	MCFG_PALETTE_LENGTH(2)
418	418	MCFG_PALETTE_INIT(black_and_white)
419
	419
420	420	MCFG_MC6845_ADD( "mc6845", MC6845, XTAL_16MHz / 16, hp9k_mc6845_intf )
421	421	MACHINE_CONFIG_END
422	422
r18774	r18775
429	429	ROMX_LOAD( "rom40.bin", 0x0000, 0x10000, CRC(36005480) SHA1(645a077ffd95e4c31f05cd8bbd6e4554b12813f1), ROM_BIOS(1) )
430	430	ROM_SYSTEM_BIOS(1, "bios30", "Bios v3.0")
431	431	ROMX_LOAD( "rom30.bin", 0x0000, 0x10000, CRC(05c07e75) SHA1(3066a65e6137482041f9a77d09ee2289fe0974aa), ROM_BIOS(2) )
432
	432
433	433	ROM_END
434	434
435	435	/* Driver */

trunk/src/mess/drivers/amiga.c
r18774	r18775
178	178
179	179	static ADDRESS_MAP_START( amiga_mem32, AS_PROGRAM, 32, a1200_state )
180	180	ADDRESS_MAP_UNMAP_HIGH
181		// ADDRESS_MAP_GLOBAL_MASK(0xffffff) // not sure
	181	// ADDRESS_MAP_GLOBAL_MASK(0xffffff) // not sure
182	182	AM_RANGE(0x000000, 0x1fffff) AM_RAMBANK("bank1") AM_SHARE("chip_ram")
183	183	AM_RANGE(0xbfd000, 0xbfefff) AM_READWRITE16_LEGACY(amiga_cia_r, amiga_cia_w, 0xffffffff)
184	184	AM_RANGE(0xc00000, 0xdfffff) AM_READWRITE16_LEGACY(amiga_custom_r, amiga_custom_w, 0xffffffff) AM_SHARE("custom_regs")
r18774	r18775
862	862	MCFG_SOFTWARE_LIST_ADD("flop_common","amiga_flop")
863	863	MCFG_SOFTWARE_LIST_ADD("flop_list","amiga1200_flop")
864	864	MCFG_SOFTWARE_LIST_ADD("flop_aga","amigaaga_flop")
865
866	865
	866
867	867	MACHINE_CONFIG_END
868	868
869	869
r18774	r18775
1226	1226
1227	1227	// from A600HD (had HDD by default)
1228	1228	ROM_SYSTEM_BIOS(1, "kick205a", "Kickstart 2.05 (37.300)")
1229		ROMX_LOAD("kickstart v2.05 r37.300 (1991)(commodore)(a600hd).rom", 0x000000, 0x080000, CRC(64466c2a) SHA1(f72d89148dac39c696e30b10859ebc859226637b), ROM_GROUPWORD \| ROM_BIOS(1))
	1229	ROMX_LOAD("kickstart v2.05 r37.300 (1991)(commodore)(a600hd).rom", 0x000000, 0x080000, CRC(64466c2a) SHA1(f72d89148dac39c696e30b10859ebc859226637b), ROM_GROUPWORD \| ROM_BIOS(1))
1230	1230	ROM_SYSTEM_BIOS(2, "kick205b", "Kickstart 2.05 (37.300)")
1231	1231	ROMX_LOAD("kickstart v2.05 r37.350 (1992)(commodore)(a600hd)[!].rom", 0x000000, 0x080000, CRC(43b0df7b) SHA1(02843c4253bbd29aba535b0aa3bd9a85034ecde4), ROM_GROUPWORD \| ROM_BIOS(2))
1232	1232
r18774	r18775
1248	1248	ROM_SYSTEM_BIOS(0, "kick30", "Kickstart 3.0 (39.106)")
1249	1249	ROMX_LOAD("391523-01.u6a", 0x000000, 0x040000, CRC(c742a412) SHA1(999eb81c65dfd07a71ee19315d99c7eb858ab186), ROM_GROUPWORD \| ROM_REVERSE \| ROM_SKIP(2) \| ROM_BIOS(1))
1250	1250	ROMX_LOAD("391524-01.u6b", 0x000002, 0x040000, CRC(d55c6ec6) SHA1(3341108d3a402882b5ef9d3b242cbf3c8ab1a3e9), ROM_GROUPWORD \| ROM_REVERSE \| ROM_SKIP(2) \| ROM_BIOS(1))
1251		// ROMX_LOAD("kickstart v3.0 r39.106 (1992)(commodore)(a1200)[!].rom", 0x000000, 0x080000, CRC(6c9b07d2) SHA1(70033828182fffc7ed106e5373a8b89dda76faa5), ROM_BIOS(1))
	1251	// ROMX_LOAD("kickstart v3.0 r39.106 (1992)(commodore)(a1200)[!].rom", 0x000000, 0x080000, CRC(6c9b07d2) SHA1(70033828182fffc7ed106e5373a8b89dda76faa5), ROM_BIOS(1))
1252	1252
1253	1253	ROM_SYSTEM_BIOS(1, "kick31", "Kickstart 3.1 (40.068)")
1254	1254	ROMX_LOAD("391773-01.u6a", 0x000000, 0x040000, CRC(08dbf275) SHA1(b8800f5f909298109ea69690b1b8523fa22ddb37), ROM_GROUPWORD \| ROM_REVERSE \| ROM_SKIP(2) \| ROM_BIOS(2))
r18774	r18775
1328	1328	COMP( 1992, a600, 0, 0, a600, amiga, amiga_state, amiga, "Commodore Business Machines", "Amiga 600 (PAL, ECS)", GAME_NOT_WORKING \| GAME_IMPERFECT_GRAPHICS )
1329	1329	COMP( 1992, a600n, a600, 0, a600n, amiga, amiga_state, amiga, "Commodore Business Machines", "Amiga 600 (NTSC, ECS)", GAME_NOT_WORKING \| GAME_IMPERFECT_GRAPHICS )
1330	1330
1331		COMP( 1992, a1200, 0, 0, a1200, amiga, a1200_state,a1200, "Commodore Business Machines", "Amiga 1200 (PAL, AGA)" , GAME_NOT_WORKING )
	1331	COMP( 1992, a1200, 0, 0, a1200, amiga, a1200_state,a1200, "Commodore Business Machines", "Amiga 1200 (PAL, AGA)" , GAME_NOT_WORKING )
1332	1332	COMP( 1992, a1200n, a1200, 0, a1200n, amiga, a1200_state,a1200, "Commodore Business Machines", "Amiga 1200 (NTSC, AGA)" , GAME_NOT_WORKING )
1333	1333
1334		COMP( 1992, a3000, 0, 0, a3000, amiga, amiga_state, a3000, "Commodore Business Machines", "Amiga 3000 (PAL, ECS, 68030)" , GAME_NOT_WORKING )
	1334	COMP( 1992, a3000, 0, 0, a3000, amiga, amiga_state, a3000, "Commodore Business Machines", "Amiga 3000 (PAL, ECS, 68030)" , GAME_NOT_WORKING )
1335	1335	COMP( 1992, a3000n, a3000, 0, a3000n, amiga, amiga_state, a3000, "Commodore Business Machines", "Amiga 3000 (NTSC, ECS, 68030)" , GAME_NOT_WORKING )
1336	1336
1337	1337

trunk/src/mess/drivers/a7800.c
r18774	r18775
9	9	2002/05/13 kubecj added more banks for bankswitching
10	10	added PAL machine description
11	11	changed clock to be precise
12
13		2012/10/25 Robert Tuccitto NTSC Color Generator utilized for
14		color palette with hue shift/start
15		based on observation of several
16		systems across multiple displays
17	12
	13	2012/10/25 Robert Tuccitto NTSC Color Generator utilized for
	14	color palette with hue shift/start
	15	based on observation of several
	16	systems across multiple displays
	17
18	18	***************************************************************************/
19	19
20	20	#include "emu.h"

trunk/src/mess/drivers/c64.c
r18774	r18775
80	80	int exrom = m_exp->exrom_r(offset, sphi2, ba, rw, m_hiram);
81	81	int cas = 0;
82	82
83		UINT32 input = VA12 << 15 \| VA13 << 14 \| game << 13 \| exrom << 12 \| rw << 11 \| aec << 10 \| ba << 9 \| A12 << 8 \|
	83	UINT32 input = VA12 << 15 \| VA13 << 14 \| game << 13 \| exrom << 12 \| rw << 11 \| aec << 10 \| ba << 9 \| A12 << 8 \|
84	84	A13 << 7 \| A14 << 6 \| A15 << 5 \| m_va14 << 4 \| m_charen << 3 \| m_hiram << 2 \| m_loram << 1 \| cas;
85	85
86	86	UINT32 data = m_pla->read(input);
r18774	r18775
195	195	int sphi2 = m_vic->phi0_r();
196	196
197	197	read_pla(offset, va, rw, !aec, ba, &casram, &basic, &kernal, &charom, &grw, &io, &roml, &romh);
198
	198
199	199	if (offset < 0x0002)
200	200	{
201	201	// write to internal CPU register
r18774	r18775
259	259
260	260	// VIC address bus is floating
261	261	offs_t va = 0x3fff;
262
	262
263	263	return read_memory(space, offset, va, aec, ba);
264	264	}
265	265
r18774	r18775
271	271	WRITE8_MEMBER( c64_state::write )
272	272	{
273	273	int aec = 1, ba = 1;
274
	274
275	275	write_memory(space, offset, data, aec, ba);
276	276	}
277	277
r18774	r18775
287	287
288	288	// A15/A14 are not connected to VIC so they are floating
289	289	offset \|= 0xc000;
290
	290
291	291	return read_memory(space, offset, va, aec, ba);
292	292	}
293	293

trunk/src/mess/drivers/spectrum.c
r18774	r18775
116	116	completly messed timings.
117	117	25/10/2012 DH - simplified border emulation to be a (manual) partial
118	118	update with bitmap
119		Removed legacy fff4 interrupt hack, modern version of
120		MAME can handle this just fine
	119	Removed legacy fff4 interrupt hack, modern version of
	120	MAME can handle this just fine
121	121
122	122	Initialisation values used when determining which model is being emulated:
123	123	48K Spectrum doesn't use either port.

trunk/src/mess/drivers/b2m.c
r18774	r18775
175	175	INPUT_PORTS_END
176	176	/*
177	177	static LEGACY_FLOPPY_OPTIONS_START(b2m)
178		LEGACY_FLOPPY_OPTION(b2m, "cpm", "Bashkiria-2M disk image", basicdsk_identify_default, basicdsk_construct_default, NULL,
179		HEADS([2])
180		TRACKS([80])
181		SECTORS([5])
182		SECTOR_LENGTH([1024])
183		FIRST_SECTOR_ID([1]))
	178	LEGACY_FLOPPY_OPTION(b2m, "cpm", "Bashkiria-2M disk image", basicdsk_identify_default, basicdsk_construct_default, NULL,
	179	HEADS([2])
	180	TRACKS([80])
	181	SECTORS([5])
	182	SECTOR_LENGTH([1024])
	183	FIRST_SECTOR_ID([1]))
184	184	LEGACY_FLOPPY_OPTIONS_END
185	185	*/
186	186

trunk/src/mess/drivers/cbm2.c
r18774	r18775
2	2
3	3	TODO:
4	4
5		- 8088 board
	5	- 8088 board
6	6	- CIA timers fail in burn-in test
7	7	- NTSC variants unable to load from disk
8	8	- shift lock
r18774	r18775
291	291	}
292	292	if (!extbufcs && m_extbuf_ram)
293	293	{
294		m_extbuf_ram[offset & 0x7ff] = data;
	294	m_extbuf_ram[offset & 0x7ff] = data;
295	295	}
296	296	if (!vidramcs)
297	297	{
r18774	r18775
334	334	}
335	335
336	336	m_exp->write(space, offset & 0x1fff, data, csbank1, csbank2, csbank3);
337		}
	337	}
338	338	}
339	339
340	340
r18774	r18775
411	411	{
412	412	int sphi2 = m_vic->phi0_r();
413	413	int bras = 1;
414
	414
415	415	UINT32 input = P0 << 15 \| P2 << 14 \| bras << 13 \| P1 << 12 \| P3 << 11 \| busy2 << 10 \| m_statvid << 9 \| sphi2 << 8 \|
416	416	clrnibcsb << 7 \| m_dramon << 6 \| procvid << 5 \| refen << 4 \| m_vicdotsel << 3 \| ba << 2 \| aec << 1 \| srw;
417	417
r18774	r18775
757	757	&cs1, &sidcs, &extprtcs, &ciacs, &aciacs, &tript1cs, &tript2cs, &aec, &vsysaden);
758	758
759	759	UINT8 data = 0xff;
760		// UINT8 clrnib = 0xf;
	760	// UINT8 clrnib = 0xf;
761	761
762	762	if (vsysaden)
763	763	{
r18774	r18775
765	765	{
766	766	data = m_ram->pointer()[(m_vicbnksel << 14) \| offset];
767	767	}
768		/* if (!clrnibcs)
769		{
770		clrnib = m_color_ram[offset & 0x3ff];
771		}*/
	768	/* if (!clrnibcs)
	769	{
	770	clrnib = m_color_ram[offset & 0x3ff];
	771	}*/
772	772	if (!vidmatcs)
773	773	{
774	774	data = m_video_ram[offset & 0x3ff];
r18774	r18775
1740	1740	READ8_MEMBER( cbm2_state::ext_tpi_pb_r )
1741	1741	{
1742	1742	/*
1743
1744		bit description
1745
1746		0 _BUSY1
1747		1 CIA PB1
1748		2 CIA PB2
1749		3 CIA PB3
1750		4 CIA PB4
1751		5 CIA PB5
1752		6 1
1753		7 1
1754
1755		*/
1756	1743
	1744	bit description
	1745
	1746	0 _BUSY1
	1747	1 CIA PB1
	1748	2 CIA PB2
	1749	3 CIA PB3
	1750	4 CIA PB4
	1751	5 CIA PB5
	1752	6 1
	1753	7 1
	1754
	1755	*/
	1756
1757	1757	UINT8 data = 0xc0;
1758	1758
1759	1759	// _BUSY1
r18774	r18775
1768	1768	WRITE8_MEMBER( cbm2_state::ext_tpi_pb_w )
1769	1769	{
1770	1770	/*
1771
1772		bit description
1773
1774		0 U22B CL
1775		1
1776		2
1777		3
1778		4
1779		5
1780		6 CIA FLAG
1781		7
1782
1783		*/
1784	1771
	1772	bit description
	1773
	1774	0 U22B CL
	1775	1
	1776	2
	1777	3
	1778	4
	1779	5
	1780	6 CIA FLAG
	1781	7
	1782
	1783	*/
	1784
1785	1785	// _BUSY2
1786	1786	if (!BIT(data, 0))
1787	1787	{
r18774	r18775
1795	1795	WRITE8_MEMBER( cbm2_state::ext_tpi_pc_w )
1796	1796	{
1797	1797	/*
1798
1799		bit description
1800
1801		0
1802		1
1803		2
1804		3
1805		4
1806		5 U22 CLK
1807		6
1808		7
1809
1810		*/
	1798
	1799	bit description
	1800
	1801	0
	1802	1
	1803	2
	1804	3
	1805	4
	1806	5 U22 CLK
	1807	6
	1808	7
	1809
	1810	*/
1811	1811	}
1812	1812
1813	1813	static const tpi6525_interface ext_tpi_intf =
r18774	r18775
1831	1831	READ8_MEMBER( cbm2_state::ext_cia_pb_r )
1832	1832	{
1833	1833	/*
1834
1835		bit description
1836
1837		0 _BUSY1
1838		1 TPI PB1
1839		2 TPI PB2
1840		3 TPI PB3
1841		4 TPI PB4
1842		5 TPI PB5
1843		6 1
1844		7 1
1845
1846		*/
1847	1834
	1835	bit description
	1836
	1837	0 _BUSY1
	1838	1 TPI PB1
	1839	2 TPI PB2
	1840	3 TPI PB3
	1841	4 TPI PB4
	1842	5 TPI PB5
	1843	6 1
	1844	7 1
	1845
	1846	*/
	1847
1848	1848	UINT8 data = 0xc0;
1849	1849
1850	1850	// _BUSY1
r18774	r18775
1859	1859	WRITE8_MEMBER( cbm2_state::ext_cia_pb_w )
1860	1860	{
1861	1861	/*
1862
1863		bit description
1864
1865		0 U22B CL
1866		1
1867		2
1868		3
1869		4
1870		5
1871		6 PIC IR0, U29B CL, U22B PR
1872		7 PIC IR7
1873
1874		*/
1875	1862
	1863	bit description
	1864
	1865	0 U22B CL
	1866	1
	1867	2
	1868	3
	1869	4
	1870	5
	1871	6 PIC IR0, U29B CL, U22B PR
	1872	7 PIC IR7
	1873
	1874	*/
	1875
1876	1876	// _BUSY2
1877	1877	if (!BIT(data, 0))
1878	1878	{

trunk/src/mess/drivers/craft.c
r18774	r18775
29	29	#define verboselog(x,y,z,...)
30	30	#endif
31	31
32		#define MASTER_CLOCK 20000000
	32	#define MASTER_CLOCK 20000000
33	33
34		#define VISIBLE_CYCLES 480
35		#define HSYNC_CYCLES 155
	34	#define VISIBLE_CYCLES 480
	35	#define HSYNC_CYCLES 155
36	36	#define LINE_CYCLES (VISIBLE_CYCLES + HSYNC_CYCLES)
37	37	#define VISIBLE_LINES 480
38	38	#define VSYNC_LINES 45
r18774	r18775
209	209	avr8_video_update(machine);
210	210
211	211	/*if (frame_cycles >= state->spi_start_cycle && frame_cycles < (state->spi_start_cycle + 16))
212		{
213		UINT8 bitidx = 7 - ((frame_cycles - state->spi_start_cycle) >> 1);
214		state->m_pixels[frame_cycles] = ((state->m_regs[AVR8_REGIDX_SPDR] & (1 << bitidx)) ? 0x3f : (data & 0x3f));
215		}
216		else
217		{
218		state->m_pixels[frame_cycles] = data & 0x3f;
219		}*/
	212	{
	213	UINT8 bitidx = 7 - ((frame_cycles - state->spi_start_cycle) >> 1);
	214	state->m_pixels[frame_cycles] = ((state->m_regs[AVR8_REGIDX_SPDR] & (1 << bitidx)) ? 0x3f : (data & 0x3f));
	215	}
	216	else
	217	{
	218	state->m_pixels[frame_cycles] = data & 0x3f;
	219	}*/
220	220
221	221	AVR8_PORTC = data;
222	222	}

trunk/src/mess/drivers/c128.c
r18774	r18775
3	3	TODO:
4	4
5	5	- connect CAPS LOCK to charom A12 on international variants
6		- DCR models won't boot with 1571CR drive
	6	- DCR models won't boot with 1571CR drive
7	7	- fix fast serial
8	8	- remove frame interrupt handler
9	9	- expansion DMA
r18774	r18775
957	957
958	958	*/
959	959
960		m_vic->lp_w(BIT(data, 4));
	960	m_vic->lp_w(BIT(data, 4));
961	961	}
962	962
963	963	WRITE_LINE_MEMBER( c128_state::cia1_cnt_w )
r18774	r18775
1055	1055	m_iec->atn_w(!BIT(data, 3));
1056	1056	m_iec->clk_w(!BIT(data, 4));
1057	1057	m_iec_data_out = BIT(data, 5);
1058
	1058
1059	1059	update_iec();
1060	1060	}
1061	1061
r18774	r18775
1085	1085	P0 1
1086	1086	P1 1
1087	1087	P2 1
1088		P3
1089		P4 CASS SENSE
1090		P5
1091		P6 CAPS LOCK
	1088	P3
	1089	P4 CASS SENSE
	1090	P5
	1091	P6 CAPS LOCK
1092	1092
1093	1093	*/
1094	1094
r18774	r18775
1693	1693
1694	1694	ROM_START( c128cr )
1695	1695	/* C128CR prototype, owned by Bo Zimmers
1696		PCB markings: "COMMODORE 128CR REV.3 // PCB NO.252270" and "PCB ASSY NO.250783"
1697		Sticker on rom cart shield: "C128CR No.2 // ENG. SAMPLE // Jun/9/'86 KNT"
1698		3 ROMs (combined basic, combined c64/kernal, plain character rom)
1699		6526A-1 CIAs
1700		?prototype? 2568R1X VDC w/ 1186 datecode
1701		*/
	1696	PCB markings: "COMMODORE 128CR REV.3 // PCB NO.252270" and "PCB ASSY NO.250783"
	1697	Sticker on rom cart shield: "C128CR No.2 // ENG. SAMPLE // Jun/9/'86 KNT"
	1698	3 ROMs (combined basic, combined c64/kernal, plain character rom)
	1699	6526A-1 CIAs
	1700	?prototype? 2568R1X VDC w/ 1186 datecode
	1701	*/
1702	1702	ROM_REGION( 0x10000, M8502_TAG, 0 )
1703	1703	ROM_LOAD( "252343-03.u34", 0x4000, 0x8000, CRC(bc07ed87) SHA1(0eec437994a3f2212343a712847213a8a39f4a7b) ) // "252343-03 // U34"
1704	1704	ROM_LOAD( "252343-04.u32", 0x0000, 0x4000, CRC(cc6bdb69) SHA1(36286b2e8bea79f7767639fd85e12c5447c7041b) ) // "252343-04 // US // U32"

199869 Revisions