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r18769 Monday 29th October, 2012 at 16:05:49 UTC by Curt Coder
(MESS) cbm2: Fixed graphics, and some 8088 WIP. (nw)

[src/mess/drivers]	cbm2.c
[src/mess/includes]	cbm2.h

trunk/src/mess/drivers/cbm2.c

r18768	r18769
2	2
3	3	TODO:
4	4
	5	- 8088 board
5	6	- CIA timers fail in burn-in test
6	7	- NTSC variants unable to load from disk
7	8	- shift lock
8	9	- Hungarian keyboard
9	10	- cbm620hu charom banking?
	11	- DIN roms 324866-03a / 324867-02
10	12	- user port
11		- co-processor bus
12		- 8088 co-processor board
13	13
14	14	*/
15	15
r18768	r18769
44	44	//  read_pla - low profile PLA read
45	45	//-------------------------------------------------
46	46
47		void cbm2_state::read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas, int busy2,
	47	void cbm2_state::read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas,
48	48	int *casseg1, int *casseg2, int *casseg3, int *casseg4, int *rasseg1, int *rasseg2, int *rasseg3, int *rasseg4)
49	49	{
50		UINT32 input = P0 << 15 | P1 << 14 | P2 << 13 | P3 << 12 | busy2 << 11 | eras << 10 | ecas << 9 | refen << 8 | cas << 7 | ras << 6;
	50	UINT32 input = P0 << 15 | P1 << 14 | P2 << 13 | P3 << 12 | m_busy2 << 11 | eras << 10 | ecas << 9 | refen << 8 | cas << 7 | ras << 6;
51	51	UINT32 data = m_pla1->read(input);
52	52
53	53	*casseg1 = BIT(data, 0);
r18768	r18769
65	65	//  read_pla - high profile PLA read
66	66	//-------------------------------------------------
67	67
68		void cbm2hp_state::read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas, int busy2,
	68	void cbm2hp_state::read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas,
69	69	int *casseg1, int *casseg2, int *casseg3, int *casseg4, int *rasseg1, int *rasseg2, int *rasseg3, int *rasseg4)
70	70	{
71		UINT32 input = ras << 13 | cas << 12 | refen << 11 | eras << 10 | ecas << 9 | busy2 << 8 | P3 << 3 | P2 << 2 | P1 << 1 | P0;
	71	UINT32 input = ras << 13 | cas << 12 | refen << 11 | eras << 10 | ecas << 9 | m_busy2 << 8 | P3 << 3 | P2 << 2 | P1 << 1 | P0;
72	72	UINT32 data = m_pla1->read(input);
73	73
74	74	*casseg1 = BIT(data, 0);
r18768	r18769
86	86	//  bankswitch -
87	87	//-------------------------------------------------
88	88
89		void cbm2_state::bankswitch(offs_t offset, int busy2, int eras, int ecas, int refen, int cas, int ras, int *sysioen, int *dramen,
	89	void cbm2_state::bankswitch(offs_t offset, int eras, int ecas, int refen, int cas, int ras, int *sysioen, int *dramen,
90	90	int *casseg1, int *casseg2, int *casseg3, int *casseg4, int *buframcs, int *extbufcs, int *vidramcs,
91	91	int *diskromcs, int *csbank1, int *csbank2, int *csbank3, int *basiccs, int *knbcs, int *kernalcs,
92	92	int *crtccs, int *cs1, int *sidcs, int *extprtcs, int *ciacs, int *aciacs, int *tript1cs, int *tript2cs)
93	93	{
94	94	int rasseg1 = 1, rasseg2 = 1, rasseg3 = 1, rasseg4 = 1;
95	95
96		this->read_pla(offset, ras, cas, refen, eras, ecas, busy2, casseg1, casseg2, casseg3, casseg4, &rasseg1, &rasseg2, &rasseg3, &rasseg4);
	96	this->read_pla(offset, ras, cas, refen, eras, ecas, casseg1, casseg2, casseg3, casseg4, &rasseg1, &rasseg2, &rasseg3, &rasseg4);
97	97
98		int busen1 = m_dramon;
99	98	int decoden = 0;
100		*sysioen = !(P0 && P1 && P2 && P3) && busen1;
101		*dramen = !((!(P0 && P1 && P2 && P3)) && busen1);
	99	*sysioen = !(P0 && P1 && P2 && P3) && m_busen1;
	100	*dramen = !((!(P0 && P1 && P2 && P3)) && m_busen1);
102	101
103	102	if (!decoden && !*sysioen)
104	103	{
r18768	r18769
151	150
152	151	READ8_MEMBER( cbm2_state::read )
153	152	{
154		int busy2 = 1, eras = 1, ecas = 1, refen = 0, cas = 0, ras = 1, sysioen = 1, dramen = 1;
	153	int eras = 1, ecas = 0, refen = 0, cas = 0, ras = 1, sysioen = 1, dramen = 1;
155	154	int casseg1 = 1, casseg2 = 1, casseg3 = 1, casseg4 = 1, buframcs = 1, extbufcs = 1, vidramcs = 1;
156	155	int diskromcs = 1, csbank1 = 1, csbank2 = 1, csbank3 = 1, basiccs = 1, knbcs = 1, kernalcs = 1;
157	156	int crtccs = 1, cs1 = 1, sidcs = 1, extprtcs = 1, ciacs = 1, aciacs = 1, tript1cs = 1, tript2cs = 1;
158	157
159		bankswitch(offset, busy2, eras, ecas, refen, cas, ras, &sysioen, &dramen,
	158	bankswitch(offset, eras, ecas, refen, cas, ras, &sysioen, &dramen,
160	159	&casseg1, &casseg2, &casseg3, &casseg4, &buframcs, &extbufcs, &vidramcs,
161	160	&diskromcs, &csbank1, &csbank2, &csbank3, &basiccs, &knbcs, &kernalcs,
162	161	&crtccs, &cs1, &sidcs, &extprtcs, &ciacs, &aciacs, &tript1cs, &tript2cs);
r18768	r18769
189	188	{
190	189	data = m_buffer_ram[offset & 0x7ff];
191	190	}
	191	if (!extbufcs && m_extbuf_ram)
	192	{
	193	data = m_extbuf_ram[offset & 0x7ff];
	194	}
192	195	if (!vidramcs)
193	196	{
194	197	data = m_video_ram[offset & 0x7ff];
r18768	r18769
216	219	{
217	220	data = m_sid->read(space, offset & 0x1f);
218	221	}
	222	if (!extprtcs && m_ext_cia)
	223	{
	224	data = m_ext_cia->read(space, offset & 0x0f);
	225	}
219	226	if (!ciacs)
220	227	{
221	228	data = m_cia->read(space, offset & 0x0f);
r18768	r18769
246	253
247	254	WRITE8_MEMBER( cbm2_state::write )
248	255	{
249		int busy2 = 1, eras = 1, ecas = 1, refen = 0, cas = 0, ras = 1, sysioen = 1, dramen = 1;
	256	int eras = 1, ecas = 0, refen = 0, cas = 0, ras = 1, sysioen = 1, dramen = 1;
250	257	int casseg1 = 1, casseg2 = 1, casseg3 = 1, casseg4 = 1, buframcs = 1, extbufcs = 1, vidramcs = 1;
251	258	int diskromcs = 1, csbank1 = 1, csbank2 = 1, csbank3 = 1, basiccs = 1, knbcs = 1, kernalcs = 1;
252	259	int crtccs = 1, cs1 = 1, sidcs = 1, extprtcs = 1, ciacs = 1, aciacs = 1, tript1cs = 1, tript2cs = 1;
253	260
254		bankswitch(offset, busy2, eras, ecas, refen, cas, ras, &sysioen, &dramen,
	261	bankswitch(offset, eras, ecas, refen, cas, ras, &sysioen, &dramen,
255	262	&casseg1, &casseg2, &casseg3, &casseg4, &buframcs, &extbufcs, &vidramcs,
256	263	&diskromcs, &csbank1, &csbank2, &csbank3, &basiccs, &knbcs, &kernalcs,
257	264	&crtccs, &cs1, &sidcs, &extprtcs, &ciacs, &aciacs, &tript1cs, &tript2cs);
r18768	r18769
282	289	{
283	290	m_buffer_ram[offset & 0x7ff] = data;
284	291	}
	292	if (!extbufcs && m_extbuf_ram)
	293	{
	294	m_extbuf_ram[offset & 0x7ff] = data;
	295	}
285	296	if (!vidramcs)
286	297	{
287	298	m_video_ram[offset & 0x7ff] = data;
r18768	r18769
301	312	{
302	313	m_sid->write(space, offset & 0x1f, data);
303	314	}
	315	if (!extprtcs && m_ext_cia)
	316	{
	317	m_ext_cia->write(space, offset & 0x0f, data);
	318	}
304	319	if (!ciacs)
305	320	{
306	321	m_cia->write(space, offset & 0x0f, data);
r18768	r18769
319	334	}
320	335
321	336	m_exp->write(space, offset & 0x1fff, data, csbank1, csbank2, csbank3);
	337	}
	338	}
	339
	340
	341	//-------------------------------------------------
	342	//  ext_read -
	343	//-------------------------------------------------
	344
	345	READ8_MEMBER( cbm2_state::ext_read )
	346	{
	347	int ras = 1, cas = 1, refen = 1, eras = 1, ecas = 0;
	348	int casseg1 = 1, casseg2 = 1, casseg3 = 1, casseg4 = 1, rasseg1 = 1, rasseg2 = 1, rasseg3 = 1, rasseg4 = 1;
	349
	350	this->read_pla(offset, ras, cas, refen, eras, ecas, &casseg1, &casseg2, &casseg3, &casseg4, &rasseg1, &rasseg2, &rasseg3, &rasseg4);
	351
	352	UINT8 data = 0xff;
	353
	354	if (!casseg1)
	355	{
	356	data = m_ram->pointer()[offset & 0xffff];
322	357	}
	358	if (!casseg2)
	359	{
	360	data = m_ram->pointer()[0x10000 | (offset & 0xffff)];
	361	}
	362	if (!casseg3 && (m_ram->size() > 0x20000))
	363	{
	364	data = m_ram->pointer()[0x20000 | (offset & 0xffff)];
	365	}
	366	if (!casseg4 && (m_ram->size() > 0x30000))
	367	{
	368	data = m_ram->pointer()[0x30000 | (offset & 0xffff)];
	369	}
	370
	371	return data;
323	372	}
324	373
325	374
326	375	//-------------------------------------------------
	376	//  ext_write -
	377	//-------------------------------------------------
	378
	379	WRITE8_MEMBER( cbm2_state::ext_write )
	380	{
	381	int ras = 1, cas = 1, refen = 1, eras = 1, ecas = 0;
	382	int casseg1 = 1, casseg2 = 1, casseg3 = 1, casseg4 = 1, rasseg1 = 1, rasseg2 = 1, rasseg3 = 1, rasseg4 = 1;
	383
	384	this->read_pla(offset, ras, cas, refen, eras, ecas, &casseg1, &casseg2, &casseg3, &casseg4, &rasseg1, &rasseg2, &rasseg3, &rasseg4);
	385
	386	if (!casseg1)
	387	{
	388	m_ram->pointer()[offset & 0xffff] = data;
	389	}
	390	if (!casseg2)
	391	{
	392	m_ram->pointer()[0x10000 | (offset & 0xffff)] = data;
	393	}
	394	if (!casseg3 && (m_ram->size() > 0x20000))
	395	{
	396	m_ram->pointer()[0x20000 | (offset & 0xffff)] = data;
	397	}
	398	if (!casseg4 && (m_ram->size() > 0x30000))
	399	{
	400	m_ram->pointer()[0x30000 | (offset & 0xffff)] = data;
	401	}
	402	}
	403
	404
	405	//-------------------------------------------------
327	406	//  read_pla1 - P500 PLA #1 read
328	407	//-------------------------------------------------
329	408
r18768	r18769
750	829
751	830
752	831	//-------------------------------------------------
	832	//  ADDRESS_MAP( ext_mem )
	833	//-------------------------------------------------
	834
	835	static ADDRESS_MAP_START( ext_mem, AS_PROGRAM, 8, cbm2_state )
	836	AM_RANGE(0x00000, 0xeffff) AM_READWRITE(ext_read, ext_write)
	837	AM_RANGE(0xf0000, 0xf0fff) AM_MIRROR(0xf000) AM_ROM AM_REGION(EXT_I8088_TAG, 0)
	838	ADDRESS_MAP_END
	839
	840
	841	//-------------------------------------------------
	842	//  ADDRESS_MAP( ext_io )
	843	//-------------------------------------------------
	844
	845	static ADDRESS_MAP_START( ext_io, AS_IO, 8, cbm2_state )
	846	ADDRESS_MAP_GLOBAL_MASK(0xff)
	847	AM_RANGE(0x0000, 0x0001) AM_MIRROR(0x1e) AM_DEVREADWRITE_LEGACY(EXT_I8259A_TAG, pic8259_r, pic8259_w)
	848	AM_RANGE(0x0020, 0x0027) AM_MIRROR(0x18) AM_DEVREADWRITE(EXT_MOS6525_TAG, tpi6525_device, read, write)
	849	ADDRESS_MAP_END
	850
	851
	852	//-------------------------------------------------
753	853	//  ADDRESS_MAP( p500_mem )
754	854	//-------------------------------------------------
755	855
r18768	r18769
975	1075	//  mc6845_interface crtc_intf
976	1076	//-------------------------------------------------
977	1077
978		static MC6845_UPDATE_ROW( lp_crtc_update_row )
	1078	static MC6845_UPDATE_ROW( crtc_update_row )
979	1079	{
980	1080	cbm2_state *state = device->machine().driver_data<cbm2_state>();
981	1081
r18768	r18769
987	1087	offs_t char_rom_addr = (ma & 0x1000) | (state->m_graphics << 11) | ((code & 0x7f) << 4) | (ra & 0x0f);
988	1088	UINT8 data = state->m_charom[char_rom_addr & 0xfff];
989	1089
990		for (int bit = 0; bit < 8; bit++)
	1090	for (int bit = 0; bit < 9; bit++)
991	1091	{
992	1092	int color = BIT(data, 7) ^ BIT(code, 7) ^ BIT(ma, 13);
993	1093	if (cursor_x == column) color ^= 1;
994	1094
995	1095	bitmap.pix32(y, x++) = RGB_MONOCHROME_GREEN[color];
996	1096
997		data <<= 1;
	1097	if (bit < 8 || !state->m_graphics) data <<= 1;
998	1098	}
999	1099	}
1000	1100	}
1001	1101
1002		static const mc6845_interface lp_crtc_intf =
	1102	static const mc6845_interface crtc_intf =
1003	1103	{
1004	1104	SCREEN_TAG,
1005		8,
	1105	9,
1006	1106	NULL,
1007		lp_crtc_update_row,
	1107	crtc_update_row,
1008	1108	NULL,
1009	1109	DEVCB_NULL,
1010	1110	DEVCB_NULL,
r18768	r18769
1014	1114	};
1015	1115
1016	1116
1017		static MC6845_UPDATE_ROW( hp_crtc_update_row )
1018		{
1019		cbm2_state *state = device->machine().driver_data<cbm2_state>();
1020
1021		int x = 0;
1022
1023		for (int column = 0; column < x_count; column++)
1024		{
1025		UINT8 code = state->m_video_ram[(ma + column) & 0x7ff];
1026		offs_t char_rom_addr = (ma & 0x1000) | (state->m_graphics << 11) | ((code & 0x7f) << 4) | (ra & 0x0f);
1027		UINT8 data = state->m_charom[char_rom_addr & 0xfff];
1028
1029		for (int bit = 0; bit < 8; bit++)
1030		{
1031		int color = BIT(data, 7) ^ BIT(code, 7) ^ BIT(ma, 13);
1032		if (cursor_x == column) color ^= 1;
1033
1034		bitmap.pix32(y, x++) = RGB_MONOCHROME_GREEN[color];
1035
1036		data <<= 1;
1037		}
1038
1039		bitmap.pix32(y, x++) = RGB_MONOCHROME_GREEN[BIT(code, 7) ^ BIT(ma, 13)];
1040		}
1041		}
1042
1043		static const mc6845_interface hp_crtc_intf =
1044		{
1045		SCREEN_TAG,
1046		9,
1047		NULL,
1048		hp_crtc_update_row,
1049		NULL,
1050		DEVCB_NULL,
1051		DEVCB_NULL,
1052		DEVCB_NULL,
1053		DEVCB_NULL,
1054		NULL
1055		};
1056
1057	1117	//-------------------------------------------------
1058	1118	//  vic2_interface vic_intf
1059	1119	//-------------------------------------------------
r18768	r18769
1252	1312
1253	1313	// memory
1254	1314	m_dramon = BIT(data, 4);
	1315	if (m_busy2) m_busen1 = m_dramon;
1255	1316
1256	1317	// cassette
1257	1318	m_cassette->write(BIT(data, 5));
r18768	r18769
1653	1714	};
1654	1715
1655	1716
	1717	//-------------------------------------------------
	1718	//  pic8259_interface ext_pic_intf
	1719	//-------------------------------------------------
1656	1720
	1721	static IRQ_CALLBACK( pic_irq_callback )
	1722	{
	1723	cbm2_state *state = device->machine().driver_data<cbm2_state>();
	1724
	1725	return pic8259_acknowledge(state->m_ext_pic);
	1726	}
	1727
	1728	static pic8259_interface ext_pic_intf =
	1729	{
	1730	DEVCB_CPU_INPUT_LINE(EXT_I8088_TAG, INPUT_LINE_IRQ0),
	1731	DEVCB_LINE_VCC,
	1732	DEVCB_NULL
	1733	};
	1734
	1735
	1736	//-------------------------------------------------
	1737	//  tpi6525_interface ext_tpi_intf
	1738	//-------------------------------------------------
	1739
	1740	READ8_MEMBER( cbm2_state::ext_tpi_pb_r )
	1741	{
	1742	/*
	1743
	1744	bit     description
	1745
	1746	0       _BUSY1
	1747	1       CIA PB1
	1748	2       CIA PB2
	1749	3       CIA PB3
	1750	4       CIA PB4
	1751	5       CIA PB5
	1752	6       1
	1753	7       1
	1754
	1755	*/
	1756
	1757	UINT8 data = 0xc0;
	1758
	1759	// _BUSY1
	1760	data |= !m_busen1;
	1761
	1762	// CIA
	1763	data = m_ext_cia->pb_r() & 0x3e;
	1764
	1765	return data;
	1766	}
	1767
	1768	WRITE8_MEMBER( cbm2_state::ext_tpi_pb_w )
	1769	{
	1770	/*
	1771
	1772	bit     description
	1773
	1774	0       U22B CL
	1775	1
	1776	2
	1777	3
	1778	4
	1779	5
	1780	6       CIA FLAG
	1781	7
	1782
	1783	*/
	1784
	1785	// _BUSY2
	1786	if (!BIT(data, 0))
	1787	{
	1788	m_busy2 = 1;
	1789	m_busen1 = m_dramon;
	1790	}
	1791
	1792	m_ext_cia->flag_w(BIT(data, 6));
	1793	}
	1794
	1795	WRITE8_MEMBER( cbm2_state::ext_tpi_pc_w )
	1796	{
	1797	/*
	1798
	1799	bit     description
	1800
	1801	0
	1802	1
	1803	2
	1804	3
	1805	4
	1806	5       U22 CLK
	1807	6
	1808	7
	1809
	1810	*/
	1811	}
	1812
	1813	static const tpi6525_interface ext_tpi_intf =
	1814	{
	1815	DEVCB_NULL,
	1816	DEVCB_DEVICE_MEMBER(EXT_MOS6526_TAG, mos6526_device, pa_r),
	1817	DEVCB_NULL,
	1818	DEVCB_DRIVER_MEMBER(cbm2_state, ext_tpi_pb_r),
	1819	DEVCB_DRIVER_MEMBER(cbm2_state, ext_tpi_pb_w),
	1820	DEVCB_NULL,
	1821	DEVCB_DRIVER_MEMBER(cbm2_state, ext_tpi_pc_w),
	1822	DEVCB_NULL,
	1823	DEVCB_NULL
	1824	};
	1825
	1826
	1827	//-------------------------------------------------
	1828	//  MOS6526_INTERFACE( ext_cia_intf )
	1829	//-------------------------------------------------
	1830
	1831	READ8_MEMBER( cbm2_state::ext_cia_pb_r )
	1832	{
	1833	/*
	1834
	1835	bit     description
	1836
	1837	0       _BUSY1
	1838	1       TPI PB1
	1839	2       TPI PB2
	1840	3       TPI PB3
	1841	4       TPI PB4
	1842	5       TPI PB5
	1843	6       1
	1844	7       1
	1845
	1846	*/
	1847
	1848	UINT8 data = 0xc0;
	1849
	1850	// _BUSY1
	1851	data |= !m_busen1;
	1852
	1853	// TPI
	1854	data |= tpi6525_portb_r(m_ext_tpi, space, 0) & 0x3e;
	1855
	1856	return data;
	1857	}
	1858
	1859	WRITE8_MEMBER( cbm2_state::ext_cia_pb_w )
	1860	{
	1861	/*
	1862
	1863	bit     description
	1864
	1865	0       U22B CL
	1866	1
	1867	2
	1868	3
	1869	4
	1870	5
	1871	6       PIC IR0, U29B CL, U22B PR
	1872	7       PIC IR7
	1873
	1874	*/
	1875
	1876	// _BUSY2
	1877	if (!BIT(data, 0))
	1878	{
	1879	m_busy2 = 1;
	1880	m_busen1 = m_dramon;
	1881	}
	1882	else if (!BIT(data, 6))
	1883	{
	1884	m_busy2 = 0;
	1885	m_busen1 = 0;
	1886	}
	1887
	1888	pic8259_ir0_w(m_ext_pic, !BIT(data, 6));
	1889	pic8259_ir7_w(m_ext_pic, BIT(data, 7));
	1890	}
	1891
	1892	static MOS6526_INTERFACE( ext_cia_intf )
	1893	{
	1894	DEVCB_DEVICE_LINE_MEMBER(MOS6525_1_TAG, tpi6525_device, i3_w),
	1895	DEVCB_NULL,
	1896	DEVCB_NULL,
	1897	DEVCB_NULL,
	1898	DEVCB_DEVICE_HANDLER(EXT_MOS6525_TAG, tpi6525_porta_r),
	1899	DEVCB_NULL,
	1900	DEVCB_DRIVER_MEMBER(cbm2_state, ext_cia_pb_r),
	1901	DEVCB_DRIVER_MEMBER(cbm2_state, ext_cia_pb_w)
	1902	};
	1903
	1904
	1905
1657	1906	//**************************************************************************
1658	1907	//  MACHINE INITIALIZATION
1659	1908	//**************************************************************************
r18768	r18769
1666	1915	{
1667	1916	m_tpi1->i0_w(m_todclk);
1668	1917
	1918	if (m_ext_pic) pic8259_ir2_w(m_ext_pic, m_todclk);
	1919
1669	1920	m_todclk = !m_todclk;
1670	1921	}
1671	1922
r18768	r18769
1693	1944
1694	1945	// state saving
1695	1946	save_item(NAME(m_dramon));
	1947	save_item(NAME(m_busen1));
	1948	save_item(NAME(m_busy2));
1696	1949	save_item(NAME(m_graphics));
1697	1950	save_item(NAME(m_ntsc));
1698	1951	save_item(NAME(m_todclk));
r18768	r18769
1730	1983
1731	1984
1732	1985	//-------------------------------------------------
	1986	//  MACHINE_START( cbm2x_ntsc )
	1987	//-------------------------------------------------
	1988
	1989	MACHINE_START_MEMBER( cbm2_state, cbm2x_ntsc )
	1990	{
	1991	// register CPU IRQ callback
	1992	m_ext_cpu->set_irq_acknowledge_callback(pic_irq_callback);
	1993
	1994	// allocate memory
	1995	m_extbuf_ram.allocate(0x800);
	1996
	1997	MACHINE_START_CALL_MEMBER(cbm2_ntsc);
	1998	}
	1999
	2000
	2001	//-------------------------------------------------
	2002	//  MACHINE_START( cbm2x_pal )
	2003	//-------------------------------------------------
	2004
	2005	MACHINE_START_MEMBER( cbm2_state, cbm2x_pal )
	2006	{
	2007	// register CPU IRQ callback
	2008	m_ext_cpu->set_irq_acknowledge_callback(pic_irq_callback);
	2009
	2010	// allocate memory
	2011	m_extbuf_ram.allocate(0x800);
	2012
	2013	MACHINE_START_CALL_MEMBER(cbm2_pal);
	2014	}
	2015
	2016
	2017	//-------------------------------------------------
1733	2018	//  MACHINE_START( p500 )
1734	2019	//-------------------------------------------------
1735	2020
r18768	r18769
1781	2066	MACHINE_RESET_MEMBER( cbm2_state, cbm2 )
1782	2067	{
1783	2068	m_dramon = 1;
	2069	m_busen1 = 1;
	2070	m_busy2 = 1;
1784	2071	m_graphics = 1;
1785	2072	m_tpi1_irq = CLEAR_LINE;
1786	2073	m_cass_rd = 1;
r18768	r18769
1877	2164	MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
1878	2165	MCFG_CBM2_EXPANSION_SLOT_ADD(CBM2_EXPANSION_SLOT_TAG, VIC6567_CLOCK, cbm2_expansion_cards, NULL, NULL)
1879	2166	//MCFG_CBM2_USER_PORT_ADD(CBM2_USER_PORT_TAG, user_intf, cbm2_user_port_cards, NULL, NULL)
1880		//MCFG_CBM2_SYSTEM_PORT_ADD(CBM2_SYSTEM_PORT_TAG, system_intf, cbm2_system_port_cards, NULL, NULL)
1881	2167
1882	2168	// internal ram
1883	2169	MCFG_FRAGMENT_ADD(128k)
r18768	r18769
1927	2213	MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
1928	2214	MCFG_CBM2_EXPANSION_SLOT_ADD(CBM2_EXPANSION_SLOT_TAG, VIC6569_CLOCK, cbm2_expansion_cards, NULL, NULL)
1929	2215	//MCFG_CBM2_USER_PORT_ADD(CBM2_USER_PORT_TAG, user_intf, cbm2_user_port_cards, NULL, NULL)
1930		//MCFG_CBM2_SYSTEM_PORT_ADD(CBM2_SYSTEM_PORT_TAG, system_intf, cbm2_system_port_cards, NULL, NULL)
1931	2216
1932	2217	// internal ram
1933	2218	MCFG_FRAGMENT_ADD(128k)
r18768	r18769
1960	2245	MCFG_SCREEN_SIZE(768, 312)
1961	2246	MCFG_SCREEN_VISIBLE_AREA(0, 768-1, 0, 312-1)
1962	2247
1963		MCFG_MC6845_ADD(MC68B45_TAG, MC6845, XTAL_18MHz/9, lp_crtc_intf)
	2248	MCFG_MC6845_ADD(MC68B45_TAG, MC6845, XTAL_18MHz/9, crtc_intf)
1964	2249
1965	2250	// sound hardware
1966	2251	MCFG_SPEAKER_STANDARD_MONO("mono")
r18768	r18769
1984	2269	MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
1985	2270	MCFG_CBM2_EXPANSION_SLOT_ADD(CBM2_EXPANSION_SLOT_TAG, XTAL_18MHz/9, cbm2_expansion_cards, NULL, NULL)
1986	2271	//MCFG_CBM2_USER_PORT_ADD(CBM2_USER_PORT_TAG, user_intf, cbm2_user_port_cards, NULL, NULL)
1987		//MCFG_CBM2_SYSTEM_PORT_ADD(CBM2_SYSTEM_PORT_TAG, system_intf, cbm2_system_port_cards, NULL, NULL)
1988	2272
1989	2273	// software list
1990	2274	MCFG_SOFTWARE_LIST_ADD("flop_list", "cbm2_flop")
r18768	r18769
2053	2337	static MACHINE_CONFIG_START( cbm2hp_ntsc, cbm2hp_state )
2054	2338	MCFG_FRAGMENT_ADD(cbm2lp_ntsc)
2055	2339
2056		MCFG_DEVICE_REMOVE(MC68B45_TAG)
2057		MCFG_MC6845_ADD(MC68B45_TAG, MC6845, XTAL_18MHz/9, hp_crtc_intf)
2058
2059	2340	// devices
2060	2341	MCFG_DEVICE_REMOVE(MOS6525_2_TAG)
2061	2342	MCFG_TPI6525_ADD(MOS6525_2_TAG, hp_tpi2_intf)
r18768	r18769
2089	2370	static MACHINE_CONFIG_START( bx256hp, cbm2hp_state )
2090	2371	MCFG_FRAGMENT_ADD(b256hp)
2091	2372
2092		//MCFG_DEVICE_REMOVE(CBM2_SYSTEM_PORT_TAG)
2093		//MCFG_CBM2_SYSTEM_PORT_ADD(CBM2_SYSTEM_PORT_TAG, system_intf, cbm2_system_port_cards, "8088", NULL)
	2373	MCFG_MACHINE_START_OVERRIDE(cbm2_state, cbm2x_ntsc)
	2374
	2375	MCFG_CPU_ADD(EXT_I8088_TAG, I8088, XTAL_12MHz)
	2376	MCFG_CPU_PROGRAM_MAP(ext_mem)
	2377	MCFG_CPU_IO_MAP(ext_io)
	2378
	2379	MCFG_PIC8259_ADD(EXT_I8259A_TAG, ext_pic_intf)
	2380	MCFG_TPI6525_ADD(EXT_MOS6525_TAG, ext_tpi_intf)
	2381	MCFG_MOS6526_ADD(EXT_MOS6526_TAG, XTAL_18MHz/9, 50, ext_cia_intf)
2094	2382	MACHINE_CONFIG_END
2095	2383
2096	2384
r18768	r18769
2139	2427	static MACHINE_CONFIG_START( cbm730, cbm2hp_state )
2140	2428	MCFG_FRAGMENT_ADD(cbm720)
2141	2429
2142		//MCFG_DEVICE_REMOVE(CBM2_SYSTEM_PORT_TAG)
2143		//MCFG_CBM2_SYSTEM_PORT_ADD(CBM2_SYSTEM_PORT_TAG, system_intf, cbm2_system_port_cards, "8088", NULL)
	2430	MCFG_MACHINE_START_OVERRIDE(cbm2_state, cbm2x_pal)
	2431
	2432	MCFG_CPU_ADD(EXT_I8088_TAG, I8088, XTAL_12MHz)
	2433	MCFG_CPU_PROGRAM_MAP(ext_mem)
	2434	MCFG_CPU_IO_MAP(ext_io)
	2435
	2436	MCFG_PIC8259_ADD(EXT_I8259A_TAG, ext_pic_intf)
	2437	MCFG_TPI6525_ADD(EXT_MOS6525_TAG, ext_tpi_intf)
	2438	MCFG_MOS6526_ADD(EXT_MOS6526_TAG, XTAL_18MHz/9, 60, ext_cia_intf)
2144	2439	MACHINE_CONFIG_END
2145	2440
2146	2441
r18768	r18769
2347	2642	ROM_LOAD( "901241-03.u59", 0x0000, 0x2000, CRC(5c1f3347) SHA1(2d46be2cd89594b718cdd0a86d51b6f628343f42) )
2348	2643	ROM_LOAD( "901240-03.u60", 0x2000, 0x2000, CRC(72aa44e1) SHA1(0d7f77746290afba8d0abeb87c9caab9a3ad89ce) )
2349	2644
2350		ROM_REGION( 0x1000, "8088", 0)
	2645	ROM_REGION( 0x1000, EXT_I8088_TAG, 0)
2351	2646	ROM_LOAD( "8088.u14", 0x0000, 0x1000, CRC(195e0281) SHA1(ce8acd2a5fb6cbd70d837811d856d656544a1f97) )
2352	2647
2353	2648	ROM_REGION( 0x2000, "kernal", 0 )

trunk/src/mess/includes/cbm2.h

r18768	r18769
5	5
6	6	#include "emu.h"
7	7	#include "cpu/m6502/m6509.h"
	8	#include "cpu/i86/i86.h"
8	9	#include "formats/cbm_snqk.h"
9	10	#include "includes/cbm.h"
10	11	#include "machine/6525tpi.h"
r18768	r18769
16	17	#include "machine/ieee488.h"
17	18	#include "machine/mos6526.h"
18	19	#include "machine/petcass.h"
	20	#include "machine/pic8259.h"
19	21	#include "machine/pla.h"
20	22	#include "machine/ram.h"
21	23	#include "machine/vcsctrl.h"
r18768	r18769
41	43	#define CONTROL1_TAG   "joy1"
42	44	#define CONTROL2_TAG   "joy2"
43	45
	46	#define EXT_I8088_TAG   "ext_u1"
	47	#define EXT_I8087_TAG   "ext_u4"
	48	#define EXT_I8259A_TAG   "ext_u3"
	49	#define EXT_MOS6526_TAG   "ext_u15"
	50	#define EXT_MOS6525_TAG   "ext_u16"
	51
44	52	class cbm2_state : public driver_device
45	53	{
46	54	public:
r18768	r18769
62	70	m_ram(*this, RAM_TAG),
63	71	m_cassette(*this, PET_DATASSETTE_PORT_TAG),
64	72	m_ieee(*this, IEEE488_TAG),
	73	m_ext_cpu(*this, EXT_I8088_TAG),
	74	m_ext_pic(*this, EXT_I8259A_TAG),
	75	m_ext_cia(*this, EXT_MOS6526_TAG),
	76	m_ext_tpi(*this, EXT_MOS6525_TAG),
65	77	m_buffer_ram(*this, "buffer_ram"),
	78	m_extbuf_ram(*this, "extbuf_ram"),
66	79	m_dramon(1),
67	80	m_video_ram(*this, "video_ram"),
68	81	m_video_ram_size(0x800),
r18768	r18769
93	106	required_device<pet_datassette_port_device> m_cassette;
94	107	required_device<ieee488_device> m_ieee;
95	108
	109	optional_device<cpu_device> m_ext_cpu;
	110	optional_device<pic8259_device> m_ext_pic;
	111	optional_device<mos6526_device> m_ext_cia;
	112	optional_device<tpi6525_device> m_ext_tpi;
	113
96	114	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
97	115
98	116	DECLARE_MACHINE_START( cbm2 );
99	117	DECLARE_MACHINE_START( cbm2_ntsc );
100	118	DECLARE_MACHINE_START( cbm2_pal );
	119	DECLARE_MACHINE_START( cbm2x_ntsc );
	120	DECLARE_MACHINE_START( cbm2x_pal );
101	121	DECLARE_MACHINE_RESET( cbm2 );
102	122
103		virtual void read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas, int busy2,
	123	virtual void read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas,
104	124	int *casseg1, int *casseg2, int *casseg3, int *casseg4, int *rasseg1, int *rasseg2, int *rasseg3, int *rasseg4);
105	125
106		void bankswitch(offs_t offset, int busy2, int eras, int ecas, int refen, int cas, int ras, int *sysioen, int *dramen,
	126	void bankswitch(offs_t offset, int eras, int ecas, int refen, int cas, int ras, int *sysioen, int *dramen,
107	127	int *casseg1, int *casseg2, int *casseg3, int *casseg4, int *buframcs, int *extbufcs, int *vidramcs,
108	128	int *diskromcs, int *csbank1, int *csbank2, int *csbank3, int *basiccs, int *knbcs, int *kernalcs,
109	129	int *crtccs, int *cs1, int *sidcs, int *extprtcs, int *ciacs, int *aciacs, int *tript1cs, int *tript2cs);
r18768	r18769
112	132
113	133	DECLARE_READ8_MEMBER( read );
114	134	DECLARE_WRITE8_MEMBER( write );
	135	DECLARE_READ8_MEMBER( ext_read );
	136	DECLARE_WRITE8_MEMBER( ext_write );
115	137
116	138	DECLARE_READ8_MEMBER( sid_potx_r );
117	139	DECLARE_READ8_MEMBER( sid_poty_r );
r18768	r18769
135	157
136	158	DECLARE_WRITE_LINE_MEMBER( tape_read_w );
137	159
	160	DECLARE_READ8_MEMBER( ext_tpi_pb_r );
	161	DECLARE_WRITE8_MEMBER( ext_tpi_pb_w );
	162	DECLARE_WRITE8_MEMBER( ext_tpi_pc_w );
	163
	164	DECLARE_READ8_MEMBER( ext_cia_pb_r );
	165	DECLARE_WRITE8_MEMBER( ext_cia_pb_w );
	166
138	167	// memory state
139	168	optional_shared_ptr<UINT8> m_buffer_ram;
	169	optional_shared_ptr<UINT8> m_extbuf_ram;
140	170	UINT8 *m_basic;
141	171	UINT8 *m_kernal;
142	172	UINT8 *m_charom;
143	173	int m_dramon;
	174	int m_busen1;
	175	int m_busy2;
144	176
145	177	// video state
146	178	optional_shared_ptr<UINT8> m_video_ram;
r18768	r18769
172	204	: cbm2_state(mconfig, type, tag)
173	205	{ }
174	206
175		virtual void read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas, int busy2,
	207	virtual void read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas,
176	208	int *casseg1, int *casseg2, int *casseg3, int *casseg4, int *rasseg1, int *rasseg2, int *rasseg3, int *rasseg4);
177	209
178	210	DECLARE_READ8_MEMBER( tpi2_pc_r );

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