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r18706 Thursday 25th October, 2012 at 16:51:48 UTC by smf
Hooked up PSX IRQ's using DEVCB2 [smf]

[src/emu/cpu/psx]	dma.c dma.h irq.c irq.h psx.c rcnt.c rcnt.h sio.c sio.h
[src/emu/machine]	am53cf96.c am53cf96.h
[src/emu/sound]	spu.c spu.h
[src/emu/video]	psx.c psx.h
[src/mame/drivers]	konamigq.c konamigv.c ksys573.c taitogn.c twinkle.c zn.c
[src/mame/machine]	psx.c
[src/mess/drivers]	psx.c
[src/mess/machine]	psxcd.c psxcd.h

trunk/src/emu/cpu/psx/sio.c

r18705	r18706
25	25
26	26	const device_type PSX_SIO = &device_creator<psxsio_device>;
27	27
28		psxsio_device::psxsio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
29		: device_t(mconfig, PSX_SIO, "PSX SIO", tag, owner, clock)
	28	psxsio_device::psxsio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	29	device_t(mconfig, PSX_SIO, "PSX SIO", tag, owner, clock),
	30	m_irq0_handler(*this),
	31	m_irq1_handler(*this)
30	32	{
31	33	int n;
32	34
r18705	r18706
54	56	{
55	57	int n;
56	58
	59	m_irq0_handler.resolve_safe();
	60	m_irq1_handler.resolve_safe();
	61
57	62	for( n = 0; n < 2; n++ )
58	63	{
59	64	port[ n ].timer = machine().scheduler().timer_alloc( timer_expired_delegate( FUNC( psxsio_device::sio_clock ), this ) );
r18705	r18706
105	110	sio->n_status |= SIO_STATUS_IRQ;
106	111	if( n_port == 0 )
107	112	{
108		psx_irq_set( machine(), PSX_IRQ_SIO0 );
	113	m_irq0_handler(1);
109	114	}
110	115	else
111	116	{
112		psx_irq_set( machine(), PSX_IRQ_SIO1 );
	117	m_irq1_handler(1);
113	118	}
114	119	}
115	120

trunk/src/emu/cpu/psx/irq.c

r18705	r18706
10	10
11	11	#define VERBOSE_LEVEL ( 0 )
12	12
	13	#define PSX_IRQ_MASK ( 0x7fd )
	14
13	15	INLINE void ATTR_PRINTF(3,4) verboselog( running_machine& machine, int n_level, const char *s_fmt, ... )
14	16	{
15	17	if( VERBOSE_LEVEL >= n_level )
r18705	r18706
110	112	}
111	113	return 0;
112	114	}
	115
	116	WRITE_LINE_MEMBER( psxirq_device::intin0 )
	117	{
	118	if( state )
	119	{
	120	set( 1 << 0 );
	121	}
	122	}
	123
	124	WRITE_LINE_MEMBER( psxirq_device::intin1 )
	125	{
	126	if( state )
	127	{
	128	set( 1 << 3 );
	129	}
	130	}
	131
	132	WRITE_LINE_MEMBER( psxirq_device::intin2 )
	133	{
	134	if( state )
	135	{
	136	set( 1 << 3 );
	137	}
	138	}
	139
	140	WRITE_LINE_MEMBER( psxirq_device::intin3 )
	141	{
	142	if( state )
	143	{
	144	set( 1 << 3 );
	145	}
	146	}
	147
	148	WRITE_LINE_MEMBER( psxirq_device::intin4 )
	149	{
	150	if( state )
	151	{
	152	set( 1 << 3 );
	153	}
	154	}
	155
	156	WRITE_LINE_MEMBER( psxirq_device::intin5 )
	157	{
	158	if( state )
	159	{
	160	set( 1 << 3 );
	161	}
	162	}
	163
	164	WRITE_LINE_MEMBER( psxirq_device::intin6 )
	165	{
	166	if( state )
	167	{
	168	set( 1 << 3 );
	169	}
	170	}
	171
	172	WRITE_LINE_MEMBER( psxirq_device::intin7 )
	173	{
	174	if( state )
	175	{
	176	set( 1 << 7 );
	177	}
	178	}
	179
	180	WRITE_LINE_MEMBER( psxirq_device::intin8 )
	181	{
	182	if( state )
	183	{
	184	set( 1 << 8 );
	185	}
	186	}
	187
	188	WRITE_LINE_MEMBER( psxirq_device::intin9 )
	189	{
	190	if( state )
	191	{
	192	set( 1 << 9 );
	193	}
	194	}
	195
	196	WRITE_LINE_MEMBER( psxirq_device::intin10 )
	197	{
	198	if( state )
	199	{
	200	set( 1 << 10 );
	201	}
	202	}

trunk/src/emu/cpu/psx/sio.h

r18705	r18706
16	16
17	17	typedef void ( *psx_sio_handler )( running_machine &, int );
18	18
	19	#define MCFG_PSX_SIO_IRQ0_HANDLER(_devcb) \
	20	devcb = &psxsio_device::set_irq0_handler(*device, DEVCB2_##_devcb); \
	21
	22	#define MCFG_PSX_SIO_IRQ1_HANDLER(_devcb) \
	23	devcb = &psxsio_device::set_irq1_handler(*device, DEVCB2_##_devcb); \
	24
19	25	#define PSX_SIO_OUT_DATA ( 1 )   /* COMMAND */
20	26	#define PSX_SIO_OUT_DTR ( 2 )   /* ATT */
21	27	#define PSX_SIO_OUT_RTS ( 4 )
r18705	r18706
67	73	public:
68	74	psxsio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
69	75
	76	// static configuration helpers
	77	template<class _Object> static devcb2_base &set_irq0_handler(device_t &device, _Object object) { return downcast<psxsio_device &>(device).m_irq0_handler.set_callback(object); }
	78	template<class _Object> static devcb2_base &set_irq1_handler(device_t &device, _Object object) { return downcast<psxsio_device &>(device).m_irq1_handler.set_callback(object); }
	79
70	80	void install_handler( int n_port, psx_sio_handler p_f_sio_handler );
71	81
72	82	DECLARE_WRITE32_MEMBER( write );
r18705	r18706
85	95	TIMER_CALLBACK_MEMBER(sio_clock);
86	96
87	97	psx_sio port[2];
	98
	99	devcb2_write_line m_irq0_handler;
	100	devcb2_write_line m_irq1_handler;
88	101	};
89	102
90	103	DECLARE_WRITE32_HANDLER( psx_sio_w );

trunk/src/emu/cpu/psx/irq.h

r18705	r18706
12	12
13	13	#include "emu.h"
14	14
15		#define PSX_IRQ_VBLANK         0x0001
16		#define PSX_IRQ_CDROM         0x0004
17		#define PSX_IRQ_DMA            0x0008
18		#define PSX_IRQ_ROOTCOUNTER0   0x0010
19		#define PSX_IRQ_ROOTCOUNTER1   0x0020
20		#define PSX_IRQ_ROOTCOUNTER2   0x0040
21		#define PSX_IRQ_SIO0         0x0080
22		#define PSX_IRQ_SIO1         0x0100
23		#define PSX_IRQ_SPU            0x0200
24		#define PSX_IRQ_EXTCD         0x0400
25		#define PSX_IRQ_MASK         (PSX_IRQ_VBLANK | PSX_IRQ_CDROM | PSX_IRQ_DMA | PSX_IRQ_ROOTCOUNTER2 | PSX_IRQ_ROOTCOUNTER1 | PSX_IRQ_ROOTCOUNTER0 | PSX_IRQ_SIO0 | PSX_IRQ_SIO1 | PSX_IRQ_SPU | PSX_IRQ_EXTCD)
26
27	15	extern const device_type PSX_IRQ;
28	16
29	17	class psxirq_device : public device_t
r18705	r18706
34	22	DECLARE_READ32_MEMBER( read );
35	23	DECLARE_WRITE32_MEMBER( write );
36	24
	25	DECLARE_WRITE_LINE_MEMBER( intin0 );
	26	DECLARE_WRITE_LINE_MEMBER( intin1 );
	27	DECLARE_WRITE_LINE_MEMBER( intin2 );
	28	DECLARE_WRITE_LINE_MEMBER( intin3 );
	29	DECLARE_WRITE_LINE_MEMBER( intin4 );
	30	DECLARE_WRITE_LINE_MEMBER( intin5 );
	31	DECLARE_WRITE_LINE_MEMBER( intin6 );
	32	DECLARE_WRITE_LINE_MEMBER( intin7 );
	33	DECLARE_WRITE_LINE_MEMBER( intin8 );
	34	DECLARE_WRITE_LINE_MEMBER( intin9 );
	35	DECLARE_WRITE_LINE_MEMBER( intin10 );
	36
37	37	void set( UINT32 bitmask );
38	38
39	39	protected:

trunk/src/emu/cpu/psx/dma.c

r18705	r18706
26	26
27	27	const device_type PSX_DMA = &device_creator<psxdma_device>;
28	28
29		psxdma_device::psxdma_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
30		: device_t(mconfig, PSX_DMA, "PSX DMA", tag, owner, clock)
	29	psxdma_device::psxdma_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	30	device_t(mconfig, PSX_DMA, "PSX DMA", tag, owner, clock),
	31	m_irq_handler(*this)
31	32	{
32	33	}
33	34
r18705	r18706
56	57
57	58	void psxdma_device::device_start()
58	59	{
	60	m_irq_handler.resolve_safe();
	61
59	62	for( int index = 0; index < 7; index++ )
60	63	{
61	64	psx_dma_channel *dma = &channel[ index ];
r18705	r18706
116	119	{
117	120	verboselog( machine(), 2, "dma_interrupt_update( %02x, %02x ) interrupt triggered\n", n_int, n_mask );
118	121	n_dicr |= 0x80000000;
119		psx_irq_set( machine(), PSX_IRQ_DMA );
	122	m_irq_handler(1);
120	123	}
121	124	else if( n_int != 0 )
122	125	{

trunk/src/emu/cpu/psx/rcnt.c

r18705	r18706
25	25
26	26	const device_type PSX_RCNT = &device_creator<psxrcnt_device>;
27	27
28		psxrcnt_device::psxrcnt_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
29		: device_t(mconfig, PSX_RCNT, "PSX RCNT", tag, owner, clock)
	28	psxrcnt_device::psxrcnt_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	29	device_t(mconfig, PSX_RCNT, "PSX RCNT", tag, owner, clock),
	30	m_irq0_handler(*this),
	31	m_irq1_handler(*this),
	32	m_irq2_handler(*this)
30	33	{
31	34	}
32	35
r18705	r18706
47	50	{
48	51	int n;
49	52
	53	m_irq0_handler.resolve_safe();
	54	m_irq1_handler.resolve_safe();
	55	m_irq2_handler.resolve_safe();
	56
50	57	for( n = 0; n < 3; n++ )
51	58	{
52	59	root_counter[ n ].timer = machine().scheduler().timer_alloc( timer_expired_delegate( FUNC( psxrcnt_device::root_finished ), this ) );
r18705	r18706
232	239	if( ( root->n_mode & PSX_RC_IRQOVERFLOW ) != 0 ||
233	240	( root->n_mode & PSX_RC_IRQTARGET ) != 0 )
234	241	{
235		psx_irq_set( machine(), PSX_IRQ_ROOTCOUNTER0 << n_counter );
	242	switch( n_counter )
	243	{
	244	case 0:
	245	m_irq0_handler(1);
	246	break;
	247	case 1:
	248	m_irq1_handler(1);
	249	break;
	250	case 2:
	251	m_irq2_handler(1);
	252	break;
	253	}
236	254	}
237	255	}

trunk/src/emu/cpu/psx/dma.h

r18705	r18706
14	14
15	15	extern const device_type PSX_DMA;
16	16
	17	#define MCFG_PSX_DMA_IRQ_HANDLER(_devcb) \
	18	devcb = &psxdma_device::set_irq_handler(*device, DEVCB2_##_devcb);
	19
17	20	typedef delegate<void (UINT32, INT32)> psx_dma_read_delegate;
18	21	typedef delegate<void (UINT32, INT32)> psx_dma_write_delegate;
19	22
r18705	r18706
34	37	public:
35	38	psxdma_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
36	39
	40	// static configuration helpers
	41	template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<psxdma_device &>(device).m_irq_handler.set_callback(object); }
	42
37	43	void install_read_handler( int n_channel, psx_dma_read_delegate p_fn_dma_read );
38	44	void install_write_handler( int n_channel, psx_dma_read_delegate p_fn_dma_write );
39	45
r18705	r18706
58	64	psx_dma_channel channel[7];
59	65	UINT32 n_dpcp;
60	66	UINT32 n_dicr;
	67
	68	devcb2_write_line m_irq_handler;
61	69	};
62	70
63	71	#endif

trunk/src/emu/cpu/psx/psx.c

r18705	r18706
3196	3196	static MACHINE_CONFIG_FRAGMENT( psx )
3197	3197	MCFG_DEVICE_ADD("irq", PSX_IRQ, 0)
3198	3198	MCFG_DEVICE_ADD("dma", PSX_DMA, 0)
	3199	MCFG_PSX_DMA_IRQ_HANDLER(DEVWRITELINE("irq", psxirq_device, intin3))
3199	3200
3200	3201	MCFG_DEVICE_ADD("mdec", PSX_MDEC, 0)
3201	3202	MCFG_PSX_DMA_CHANNEL_WRITE( DEVICE_SELF, 0, psx_dma_write_delegate( FUNC( psxmdec_device::dma_write ), (psxmdec_device *) device ) )
3202	3203	MCFG_PSX_DMA_CHANNEL_READ( DEVICE_SELF, 1, psx_dma_read_delegate( FUNC( psxmdec_device::dma_read ), (psxmdec_device *) device ) )
3203	3204
3204	3205	MCFG_DEVICE_ADD("rcnt", PSX_RCNT, 0)
	3206	MCFG_PSX_RCNT_IRQ0_HANDLER(DEVWRITELINE("irq", psxirq_device, intin4))
	3207	MCFG_PSX_RCNT_IRQ1_HANDLER(DEVWRITELINE("irq", psxirq_device, intin5))
	3208	MCFG_PSX_RCNT_IRQ2_HANDLER(DEVWRITELINE("irq", psxirq_device, intin6))
	3209
3205	3210	MCFG_DEVICE_ADD("sio", PSX_SIO, 0)
	3211	MCFG_PSX_SIO_IRQ0_HANDLER(DEVWRITELINE("irq", psxirq_device, intin7))
	3212	MCFG_PSX_SIO_IRQ1_HANDLER(DEVWRITELINE("irq", psxirq_device, intin8))
3206	3213	MACHINE_CONFIG_END
3207	3214
3208	3215	//-------------------------------------------------

trunk/src/emu/cpu/psx/rcnt.h

r18705	r18706
14	14
15	15	extern const device_type PSX_RCNT;
16	16
	17	#define MCFG_PSX_RCNT_IRQ0_HANDLER(_devcb) \
	18	devcb = &psxrcnt_device::set_irq0_handler(*device, DEVCB2_##_devcb); \
	19
	20	#define MCFG_PSX_RCNT_IRQ1_HANDLER(_devcb) \
	21	devcb = &psxrcnt_device::set_irq1_handler(*device, DEVCB2_##_devcb); \
	22
	23	#define MCFG_PSX_RCNT_IRQ2_HANDLER(_devcb) \
	24	devcb = &psxrcnt_device::set_irq2_handler(*device, DEVCB2_##_devcb); \
	25
17	26	#define PSX_RC_STOP ( 0x01 )
18	27	#define PSX_RC_RESET ( 0x04 ) /* guess */
19	28	#define PSX_RC_COUNTTARGET ( 0x08 )
r18705	r18706
37	46	public:
38	47	psxrcnt_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
39	48
	49	// static configuration helpers
	50	template<class _Object> static devcb2_base &set_irq0_handler(device_t &device, _Object object) { return downcast<psxrcnt_device &>(device).m_irq0_handler.set_callback(object); }
	51	template<class _Object> static devcb2_base &set_irq1_handler(device_t &device, _Object object) { return downcast<psxrcnt_device &>(device).m_irq1_handler.set_callback(object); }
	52	template<class _Object> static devcb2_base &set_irq2_handler(device_t &device, _Object object) { return downcast<psxrcnt_device &>(device).m_irq2_handler.set_callback(object); }
	53
40	54	DECLARE_WRITE32_MEMBER( write );
41	55	DECLARE_READ32_MEMBER( read );
42	56
r18705	r18706
54	68	int root_target( int n_counter );
55	69	void root_timer_adjust( int n_counter );
56	70	TIMER_CALLBACK_MEMBER(root_finished);
	71
	72	devcb2_write_line m_irq0_handler;
	73	devcb2_write_line m_irq1_handler;
	74	devcb2_write_line m_irq2_handler;
57	75	};
58	76
59	77	#endif

trunk/src/emu/machine/am53cf96.c

r18705	r18706
50	50	{
51	51	scsi_regs[REG_IRQSTATE] = 8;   // indicate success
52	52	scsi_regs[REG_STATUS] |= 0x80;   // indicate IRQ
53		irq_callback(machine());
	53	m_irq_handler(1);
54	54	}
55	55
56	56	WRITE8_MEMBER( am53cf96_device::write )
r18705	r18706
157	157	}
158	158	}
159	159
160		am53cf96_device::am53cf96_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
161		: device_t(mconfig, AM53CF96, "53CF96 SCSI", tag, owner, clock)
	160	am53cf96_device::am53cf96_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	161	device_t(mconfig, AM53CF96, "53CF96 SCSI", tag, owner, clock),
	162	m_irq_handler(*this)
162	163	{
163	164	}
164	165
165		void am53cf96_device::device_config_complete()
166		{
167		// inherit a copy of the static data
168		const AM53CF96interface *intf = reinterpret_cast<const AM53CF96interface *>(static_config());
169		if (intf != NULL)
170		{
171		*static_cast<AM53CF96interface *>(this) = *intf;
172		}
173		}
174
175	166	void am53cf96_device::device_start()
176	167	{
	168	m_irq_handler.resolve_safe();
	169
177	170	memset(scsi_regs, 0, sizeof(scsi_regs));
178	171	memset(devices, 0, sizeof(devices));
179	172

trunk/src/emu/machine/am53cf96.h

r18705	r18706
8	8
9	9	#include "machine/scsihle.h"
10	10
11		struct AM53CF96interface
12		{
13		void (*irq_callback)(running_machine &machine);   /* irq callback */
14		};
	11	#define MCFG_AM53CF96_ADD( _tag ) \
	12	MCFG_DEVICE_ADD( _tag, AM53CF96, 0 )
15	13
16		#define MCFG_AM53CF96_ADD( _tag, _config ) \
17		MCFG_DEVICE_ADD( _tag, AM53CF96, 0 ) \
18		MCFG_DEVICE_CONFIG(_config)
	14	#define MCFG_AM53CF96_IRQ_HANDLER(_devcb) \
	15	devcb = &am53cf96_device::set_irq_handler(*device, DEVCB2_##_devcb); \
19	16
20	17	// 53CF96 register set
21	18	enum
r18705	r18706
39	36	REG_DATAALIGN      // data alignment (write only)
40	37	};
41	38
42		class am53cf96_device : public device_t,
43		public AM53CF96interface
	39	class am53cf96_device : public device_t
44	40	{
45	41	public:
46	42	// construction/destruction
47	43	am53cf96_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
48	44
	45	// static configuration helpers
	46	template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<am53cf96_device &>(device).m_irq_handler.set_callback(object); }
	47
49	48	DECLARE_READ8_MEMBER(read);
50	49	DECLARE_WRITE8_MEMBER(write);
51	50
r18705	r18706
54	53
55	54	protected:
56	55	// device-level overrides
57		virtual void device_config_complete();
58	56	virtual void device_start();
59	57	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
60	58
r18705	r18706
70	68	UINT8 last_id;
71	69
72	70	emu_timer* m_transfer_timer;
	71	devcb2_write_line m_irq_handler;
73	72	};
74	73
75	74	// device type definition

trunk/src/emu/video/psx.h

r18705	r18706
12	12
13	13	#include "emu.h"
14	14
	15	#define MCFG_PSX_GPU_VBLANK_HANDLER(_devcb) \
	16	devcb = &psxgpu_device::set_vblank_handler(*device, DEVCB2_##_devcb);
	17
15	18	#define MCFG_PSXGPU_ADD( cputag, tag, type, _vramSize, clock ) \
16	19	MCFG_DEVICE_MODIFY( cputag ) \
17	20	MCFG_PSX_GPU_READ_HANDLER(DEVREAD32(tag, psxgpu_device, read)) \
18	21	MCFG_PSX_GPU_WRITE_HANDLER(DEVWRITE32(tag, psxgpu_device, write)) \
19	22	MCFG_DEVICE_ADD( tag, type, clock ) \
20	23	((psxgpu_device *) device)->vramSize = _vramSize; \
	24	MCFG_PSX_GPU_VBLANK_HANDLER(DEVWRITELINE(cputag ":irq", psxirq_device, intin0)) \
21	25	MCFG_PSX_DMA_CHANNEL_READ( cputag, 2, psx_dma_write_delegate( FUNC( psxgpu_device::dma_read ), (psxgpu_device *) device ) ) \
22	26	MCFG_PSX_DMA_CHANNEL_WRITE( cputag, 2, psx_dma_read_delegate( FUNC( psxgpu_device::dma_write ), (psxgpu_device *) device ) )
23	27
r18705	r18706
27	31	MCFG_PSX_GPU_WRITE_HANDLER(DEVWRITE32(tag, psxgpu_device, write)) \
28	32	MCFG_DEVICE_REPLACE( tag, type, clock ) \
29	33	((psxgpu_device *) device)->vramSize = _vramSize; \
	34	MCFG_PSX_GPU_VBLANK_HANDLER(DEVWRITELINE(cputag ":irq", psxirq_device, intin0)) \
30	35	MCFG_PSX_DMA_CHANNEL_READ( cputag, 2, psx_dma_write_delegate( FUNC( psxgpu_device::dma_read ), (psxgpu_device *) device ) ) \
31	36	MCFG_PSX_DMA_CHANNEL_WRITE( cputag, 2, psx_dma_read_delegate( FUNC( psxgpu_device::dma_write ), (psxgpu_device *) device ) )
32	37
r18705	r18706
186	191	psxgpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
187	192	virtual machine_config_constructor device_mconfig_additions() const;
188	193
	194	// static configuration helpers
	195	template<class _Object> static devcb2_base &set_vblank_handler(device_t &device, _Object object) { return downcast<psxgpu_device &>(device).m_vblank_handler.set_callback(object); }
	196
189	197	UINT32 update_screen(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
190	198	DECLARE_WRITE32_MEMBER( write );
191	199	DECLARE_READ32_MEMBER( read );
r18705	r18706
300	308	UINT16 p_n_b0[ 0x10000 ];
301	309	UINT16 p_n_r1[ 0x10000 ];
302	310	UINT16 p_n_b1g1[ 0x10000 ];
	311
	312	devcb2_write_line m_vblank_handler;
303	313	};
304	314
305	315	class cxd8514q_device : public psxgpu_device

trunk/src/emu/video/psx.c

r18705	r18706
19	19	const device_type CXD8561CQ = &device_creator<cxd8561cq_device>;
20	20	const device_type CXD8654Q = &device_creator<cxd8654q_device>;
21	21
22		psxgpu_device::psxgpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock)
23		: device_t(mconfig, type, name, tag, owner, clock)
	22	psxgpu_device::psxgpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
	23	device_t(mconfig, type, name, tag, owner, clock),
	24	m_vblank_handler(*this)
24	25	{
25	26	}
26	27
27	28	void psxgpu_device::device_start( void )
28	29	{
	30	m_vblank_handler.resolve_safe();
	31
29	32	if( m_type == CXD8538Q )
30	33	{
31	34	psx_gpu_init( 1 );
r18705	r18706
3661	3664	#endif
3662	3665
3663	3666	n_gpustatus ^= ( 1L << 31 );
3664		psx_irq_set( machine(), 0x0001 );
	3667	m_vblank_handler(1);
3665	3668	}
3666	3669	}
3667	3670

trunk/src/emu/sound/spu.c

r18705	r18706
954	954	//  spu_device - constructor
955	955	//-------------------------------------------------
956	956
957		spu_device::spu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
958		: device_t(mconfig, SPU, "SPU", tag, owner, clock),
959		device_sound_interface(mconfig, *this),
960		m_irq_cb(NULL),
961		dirty_flags(-1),
	957	spu_device::spu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	958	device_t(mconfig, SPU, "SPU", tag, owner, clock),
	959	device_sound_interface(mconfig, *this),
	960	m_irq_handler(*this),
	961	dirty_flags(-1),
962	962	status_enabled(false),
963	963	xa_voll(0x8000),
964	964	xa_volr(0x8000),
965		changed_xa_vol(0)
966
	965	changed_xa_vol(0)
967	966	{
968	967	}
969	968
r18705	r18706
972	971	//  the IRQ callback
973	972	//-------------------------------------------------
974	973
975		void spu_device::static_set_irqf(device_t &device, void (*irqf)(device_t *device, UINT32 state))
976		{
977		spu_device &spu = downcast<spu_device &>(device);
978		spu.m_irq_cb = irqf;
979		}
980
981	974	void spu_device::device_start()
982	975	{
	976	m_irq_handler.resolve_safe();
	977
983	978	voice=new voiceinfo [24];
984	979	spu_ram=new unsigned char [spu_ram_size];
985	980
r18705	r18706
1858	1853	if (hitirq)
1859	1854	{
1860	1855	// Went past IRQ address, trigger IRQ
1861		m_irq_cb(this, 1);
	1856	m_irq_handler(1);
1862	1857
1863	1858	vi->samplestoirq=spu_infinity;
1864	1859	vi->hitirq=true;
r18705	r18706
2656	2651	{
2657	2652	if (voice[i].samplestoirq==0)
2658	2653	{
2659		m_irq_cb(this, 1);
	2654	m_irq_handler(1);
2660	2655
2661	2656	voice[i].samplestoirq=spu_infinity;
2662	2657	voice[i].hitirq=true;

trunk/src/emu/sound/spu.h

r18705	r18706
9	9	//  INTERFACE CONFIGURATION MACROS
10	10	//**************************************************************************
11	11
12		#define MCFG_SPU_ADD(_tag, _clock, _irqf) \
	12	#define MCFG_SPU_IRQ_HANDLER(_devcb) \
	13	devcb = &spu_device::set_irq_handler(*device, DEVCB2_##_devcb);
	14
	15	#define MCFG_SPU_ADD(_tag, _clock) \
13	16	MCFG_DEVICE_ADD(_tag, SPU, _clock) \
	17	MCFG_SPU_IRQ_HANDLER(DEVWRITELINE("maincpu:irq", psxirq_device, intin9)) \
14	18	MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 4, psx_dma_read_delegate( FUNC( spu_device::dma_read ), (spu_device *) device ) ) \
15		MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 4, psx_dma_write_delegate( FUNC( spu_device::dma_write ), (spu_device *) device ) ) \
16		MCFG_IRQ_FUNC(_irqf)
	19	MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 4, psx_dma_write_delegate( FUNC( spu_device::dma_write ), (spu_device *) device ) )
17	20
18		#define MCFG_IRQ_FUNC(_irqf) \
19		spu_device::static_set_irqf(*device, _irqf); \
20
21	21	// ======================> spu_device
22	22
23	23	const unsigned int spu_base_frequency_hz=44100;
r18705	r18706
49	49	virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
50	50
51	51	// internal state
52		void (*m_irq_cb)(device_t *device, UINT32 state);
	52	devcb2_write_line m_irq_handler;
53	53
54	54	unsigned char *spu_ram;
55	55	reverb *rev;
r18705	r18706
217	217	public:
218	218	spu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
219	219
220		// inline configuration helpers
221		static void static_set_irqf(device_t &device, void (*irqf)(device_t *device, UINT32 state));
	220	// static configuration helpers
	221	template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<spu_device &>(device).m_irq_handler.set_callback(object); }
222	222
223	223	void dma_read( UINT32 n_address, INT32 n_size );
224	224	void dma_write( UINT32 n_address, INT32 n_size );

trunk/src/mess/machine/psxcd.c

r18705	r18706
106	106	psxcd.m_devname = devname;
107	107	}
108	108
109		psxcd_device::psxcd_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
110		: device_t(mconfig, PSXCD, "PSXCD", tag, owner, clock)
	109	psxcd_device::psxcd_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	110	device_t(mconfig, PSXCD, "PSXCD", tag, owner, clock),
	111	m_irq_handler(*this)
111	112	{
112	113	}
113	114
114	115	void psxcd_device::device_start()
115	116	{
	117	m_irq_handler.resolve_safe();
	118
116	119	unsigned int sysclk=machine().device<cpu_device>("maincpu")->clock()/2;
117	120	start_read_delay=(sysclk/60);
118	121	read_sector_cycles=(sysclk/75);
r18705	r18706
891	894
892	895	if (doint)
893	896	{
894		psx_irq_set(machine(), 0x0004);
	897	m_irq_handler(1);
895	898	}
896	899
897	900	add_result(res);

trunk/src/mess/machine/psxcd.h

r18705	r18706
25	25	//**************************************************************************
26	26
27	27	#define MCFG_PSXCD_ADD(_devname) \
28		MCFG_DEVICE_ADD(PSXCD_TAG, PSXCD, 0) \
	28	MCFG_DEVICE_ADD(PSXCD_TAG, PSXCD, 0) \
29	29	MCFG_PSXCD_DEVNAME(_devname)
30	30
	31	#define MCFG_PSXCD_IRQ_HANDLER(_devcb) \
	32	devcb = &psxcd_device::set_irq_handler(*device, DEVCB2_##_devcb);
	33
31	34	#define MCFG_PSXCD_DEVNAME(_name) \
32	35	psxcd_device::static_set_devname(*device, _name); \
33	36
r18705	r18706
41	44	public:
42	45
43	46	psxcd_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
44		// inline configuration helpers
	47
	48	// static configuration helpers
	49	template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<psxcd_device &>(device).m_irq_handler.set_callback(object); }
45	50	static void static_set_devname(device_t &device, const char *devname);
46	51	private:
47	52	struct command_result
r18705	r18706
164	169	bool m_timerinuse[MAX_PSXCD_TIMERS];
165	170
166	171	void add_system_event(event *ev);
	172
	173	devcb2_write_line m_irq_handler;
167	174	};
168	175
169	176

trunk/src/mess/drivers/psx.c

r18705	r18706
754	754	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON8 ) PORT_PLAYER(2) PORT_NAME("P2 L2")
755	755	INPUT_PORTS_END
756	756
757		static void spu_irq(device_t *device, UINT32 data)
758		{
759		if (data)
760		{
761		psx_irq_set(device->machine(), 1<<9);
762		}
763		}
764
765	757	struct cdrom_interface psx_cdrom =
766	758	{
767	759	"psx_cdrom",
r18705	r18706
780	772
781	773	/* sound hardware */
782	774	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
783		MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &spu_irq )
	775	MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
784	776	MCFG_SOUND_ROUTE( 0, "lspeaker", 1.00 )
785	777	MCFG_SOUND_ROUTE( 1, "rspeaker", 1.00 )
786	778
r18705	r18706
791	783	MCFG_SOFTWARE_LIST_ADD("cd_list","psx")
792	784
793	785	MCFG_PSXCD_ADD("cdrom")
	786	MCFG_PSXCD_IRQ_HANDLER(DEVWRITELINE("^maincpu:irq", psxirq_device, intin2))
794	787	MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 3, psx_dma_read_delegate( FUNC( cd_dma_read ), (psxcd_device *) device ) )
795	788	MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 3, psx_dma_write_delegate( FUNC( cd_dma_write ), (psxcd_device *) device ) )
796	789
r18705	r18706
811	804
812	805	/* sound hardware */
813	806	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
814		MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &spu_irq )
	807	MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
815	808	MCFG_SOUND_ROUTE( 0, "lspeaker", 1.00 )
816	809	MCFG_SOUND_ROUTE( 1, "rspeaker", 1.00 )
817	810
r18705	r18706
822	815	MCFG_SOFTWARE_LIST_ADD("cd_list","psx")
823	816
824	817	MCFG_PSXCD_ADD("cdrom")
	818	MCFG_PSXCD_IRQ_HANDLER(DEVWRITELINE("^maincpu:irq", psxirq_device, intin2))
825	819	MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 3, psx_dma_read_delegate( FUNC( cd_dma_read ), (psxcd_device *) device ) )
826	820	MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 3, psx_dma_write_delegate( FUNC( cd_dma_write ), (psxcd_device *) device ) )
827	821

trunk/src/mame/machine/psx.c

r18705	r18706
49	49	return p_psx->n_com_delay;
50	50	}
51	51
52		/* IRQ */
53
54		void psx_irq_set( running_machine &machine, UINT32 data )
55		{
56		psxcpu_device::irq_set( *machine.device("maincpu^"), "maincpu", data );
57		}
58
59	52	/* SIO */
60	53
61	54	void psx_sio_install_handler( running_machine &machine, int n_port, psx_sio_handler p_f_sio_handler )

trunk/src/mame/drivers/ksys573.c

r18705	r18706
479	479	class ksys573_state : public psx_state
480	480	{
481	481	public:
482		ksys573_state(const machine_config &mconfig, device_type type, const char *tag)
483		: psx_state(mconfig, type, tag),
484		m_cr589(*this, ":cdrom") { }
	482	ksys573_state(const machine_config &mconfig, device_type type, const char *tag) :
	483	psx_state(mconfig, type, tag),
	484	m_psxirq(*this, ":maincpu:irq"),
	485	m_cr589(*this, ":cdrom")
	486	{
	487	}
485	488
	489	required_device<psxirq_device> m_psxirq;
	490
486	491	int m_flash_bank;
487	492	fujitsu_29f016a_device *m_flash_device[5][16];
488	493	int m_security_cart_number;
r18705	r18706
758	763	atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO | ATAPI_INTREASON_COMMAND;
759	764	}
760	765
761		psx_irq_set(machine(), 0x400);
	766	m_psxirq->intin10(1);
762	767
763	768	verboselog( machine(), 2, "atapi_xfer_end: %d %d\n", m_atapi_xferlen, m_atapi_xfermod );
764	769	}
r18705	r18706
809	814	atapi_regs[ATAPI_REG_COUNTLOW] = m_atapi_xferlen & 0xff;
810	815	atapi_regs[ATAPI_REG_COUNTHIGH] = (m_atapi_xferlen>>8)&0xff;
811	816
812		psx_irq_set(machine(), 0x400);
	817	m_psxirq->intin10(1);
813	818	}
814	819
815	820	if( m_atapi_data_ptr < m_atapi_data_len )
r18705	r18706
826	831	{
827	832	atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
828	833	atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
829		psx_irq_set(machine(), 0x400);
	834	m_psxirq->intin10(1);
830	835	}
831	836	}
832	837	}
r18705	r18706
910	915	m_cr589->WriteData( atapi_data, m_atapi_cdata_wait );
911	916
912	917	// assert IRQ
913		psx_irq_set(machine(), 0x400);
	918	m_psxirq->intin10(1);
914	919
915	920	// not sure here, but clear DRQ at least?
916	921	atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
r18705	r18706
983	988	}
984	989
985	990	// assert IRQ
986		psx_irq_set(machine(), 0x400);
	991	m_psxirq->intin10(1);
987	992	}
988	993	else
989	994	{
r18705	r18706
1100	1105	atapi_regs[ATAPI_REG_COUNTLOW] = 0;
1101	1106	atapi_regs[ATAPI_REG_COUNTHIGH] = 2;
1102	1107
1103		psx_irq_set(machine(), 0x400);
	1108	m_psxirq->intin10(1);
1104	1109	break;
1105	1110
1106	1111	case 0xef:   // SET FEATURES
r18705	r18706
1109	1114	m_atapi_data_ptr = 0;
1110	1115	m_atapi_data_len = 0;
1111	1116
1112		psx_irq_set(machine(), 0x400);
	1117	m_psxirq->intin10(1);
1113	1118	break;
1114	1119
1115	1120	default:
r18705	r18706
1408	1413	update_mode(machine());
1409	1414	}
1410	1415
1411		static void spu_irq(device_t *device, UINT32 data)
1412		{
1413		if (data)
1414		{
1415		psx_irq_set(device->machine(), 1<<9);
1416		}
1417		}
1418
1419	1416	void sys573_vblank(ksys573_state *state, screen_device &screen, bool vblank_state)
1420	1417	{
1421	1418	UINT32 *p_n_psxram = state->m_p_n_psxram;
r18705	r18706
3061	3058	/* sound hardware */
3062	3059	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3063	3060
3064		MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &spu_irq )
	3061	MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
3065	3062	MCFG_SOUND_ROUTE( 0, "lspeaker", 1.0 )
3066	3063	MCFG_SOUND_ROUTE( 1, "rspeaker", 1.0 )
3067	3064

trunk/src/mame/drivers/taitogn.c

r18705	r18706
930	930	ADDRESS_MAP_END
931	931
932	932
933		static void spu_irq(device_t *device, UINT32 data)
934		{
935		if (data)
936		{
937		psx_irq_set(device->machine(), 1<<9);
938		}
939		}
940
941	933	static const ide_config ide_intf =
942	934	{
943	935	NULL,
r18705	r18706
956	948	/* sound hardware */
957	949	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
958	950
959		MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &spu_irq )
	951	MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
960	952	MCFG_SOUND_ROUTE(0, "lspeaker", 0.35)
961	953	MCFG_SOUND_ROUTE(1, "rspeaker", 0.35)
962	954

trunk/src/mame/drivers/konamigv.c

r18705	r18706
292	292	}
293	293	}
294	294
295		static void scsi_irq(running_machine &machine)
296		{
297		psx_irq_set(machine, 0x400);
298		}
299
300		static const struct AM53CF96interface am53cf96_intf =
301		{
302		&scsi_irq,      /* command completion IRQ */
303		};
304
305	295	DRIVER_INIT_MEMBER(konamigv_state,konamigv)
306	296	{
307	297	psx_driver_init(machine());
r18705	r18706
309	299
310	300	MACHINE_START_MEMBER(konamigv_state,konamigv)
311	301	{
312
313	302	save_item(NAME(m_sector_buffer));
314	303	save_item(NAME(m_flash_address));
315	304	save_item(NAME(m_trackball_prev));
r18705	r18706
318	307	save_item(NAME(m_btc_trackball_data));
319	308	}
320	309
321		static void spu_irq(device_t *device, UINT32 data)
322		{
323		if (data)
324		{
325		psx_irq_set(device->machine(), 1<<9);
326		}
327		}
328
329	310	static MACHINE_CONFIG_START( konamigv, konamigv_state )
330	311	/* basic machine hardware */
331	312	MCFG_CPU_ADD( "maincpu", CXD8530BQ, XTAL_67_7376MHz )
r18705	r18706
340	321
341	322	MCFG_SCSIBUS_ADD("scsi")
342	323	MCFG_SCSIDEV_ADD("scsi:cdrom", SCSICD, SCSI_ID_4)
343		MCFG_AM53CF96_ADD("scsi:am53cf96", am53cf96_intf)
	324	MCFG_AM53CF96_ADD("scsi:am53cf96")
	325	MCFG_AM53CF96_IRQ_HANDLER(DEVWRITELINE("^maincpu:irq", psxirq_device, intin10))
344	326
345	327	/* video hardware */
346	328	MCFG_PSXGPU_ADD( "maincpu", "gpu", CXD8514Q, 0x100000, XTAL_53_693175MHz )
r18705	r18706
348	330	/* sound hardware */
349	331	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
350	332
351		MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &spu_irq )
	333	MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
352	334	MCFG_SOUND_ROUTE( 0, "lspeaker", 0.75 )
353	335	MCFG_SOUND_ROUTE( 1, "rspeaker", 0.75 )
354	336

trunk/src/mame/drivers/konamigq.c

r18705	r18706
303	303	{
304	304	}
305	305
306		static void scsi_irq(running_machine &machine)
307		{
308		psx_irq_set(machine, 0x400);
309		}
310
311		static const struct AM53CF96interface am53cf96_intf =
312		{
313		&scsi_irq,      /* command completion IRQ */
314		};
315
316	306	DRIVER_INIT_MEMBER(konamigq_state,konamigq)
317	307	{
318
319	308	psx_driver_init(machine());
320	309
321	310	m_p_n_pcmram = memregion( "shared" )->base() + 0x80000;
r18705	r18706
323	312
324	313	MACHINE_START_MEMBER(konamigq_state,konamigq)
325	314	{
326
327	315	save_pointer(NAME(m_p_n_pcmram), 0x380000);
328	316	save_item(NAME(m_sndto000));
329	317	save_item(NAME(m_sndtor3k));
r18705	r18706
353	341
354	342	MCFG_SCSIBUS_ADD("scsi")
355	343	MCFG_SCSIDEV_ADD("scsi:disk", SCSIHD, SCSI_ID_0)
356		MCFG_AM53CF96_ADD("scsi:am53cf96", am53cf96_intf)
	344	MCFG_AM53CF96_ADD("scsi:am53cf96")
	345	MCFG_AM53CF96_IRQ_HANDLER(DEVWRITELINE("^maincpu:irq", psxirq_device, intin10))
357	346
358	347	/* video hardware */
359	348	MCFG_PSXGPU_ADD( "maincpu", "gpu", CXD8538Q, 0x200000, XTAL_53_693175MHz )

trunk/src/mame/drivers/twinkle.c

r18705	r18706
849	849	}
850	850	}
851	851
852		static void scsi_irq(running_machine &machine)
853		{
854		psx_irq_set(machine, 0x400);
855		}
856
857		static const struct AM53CF96interface am53cf96_intf =
858		{
859		&scsi_irq,      /* command completion IRQ */
860		};
861
862	852	DRIVER_INIT_MEMBER(twinkle_state,twinkle)
863	853	{
864	854	psx_driver_init(machine());
r18705	r18706
870	860	i2cmem_wc_write( i2cmem, 0 );
871	861	}
872	862
873		static void spu_irq(device_t *device, UINT32 data)
874		{
875		if (data)
876		{
877		psx_irq_set(device->machine(), 1<<9);
878		}
879		}
880
881	863	static const i2cmem_interface i2cmem_interface =
882	864	{
883	865	I2CMEM_SLAVE_ADDRESS, 0, 0x100
r18705	r18706
912	894
913	895	MCFG_SCSIBUS_ADD("scsi")
914	896	MCFG_SCSIDEV_ADD("scsi:cdrom", SCSICD, SCSI_ID_4)
915		MCFG_AM53CF96_ADD("scsi:am53cf96", am53cf96_intf)
	897	MCFG_AM53CF96_ADD("scsi:am53cf96")
	898	MCFG_AM53CF96_IRQ_HANDLER(DEVWRITELINE("^maincpu:irq", psxirq_device, intin10))
916	899
917	900	MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
918	901	MCFG_RTC65271_ADD("rtc", twinkle_rtc)
r18705	r18706
923	906	/* sound hardware */
924	907	MCFG_SPEAKER_STANDARD_STEREO("speakerleft", "speakerright")
925	908
926		MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &spu_irq )
	909	MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
927	910	MCFG_SOUND_ROUTE( 0, "speakerleft", 0.75 )
928	911	MCFG_SOUND_ROUTE( 1, "speakerright", 0.75 )
929	912

trunk/src/mame/drivers/zn.c

r18705	r18706
538	538	state->m_dip_timer = machine.scheduler().timer_alloc( timer_expired_delegate(FUNC(zn_state::dip_timer_fired),state), NULL );
539	539	}
540	540
541		static void psx_spu_irq(device_t *device, UINT32 data)
542		{
543		if (data)
544		{
545		psx_irq_set(device->machine(), 1<<9);
546		}
547		}
548
549	541	static void zn_machine_init( running_machine &machine )
550	542	{
551	543	zn_state *state = machine.driver_data<zn_state>();
r18705	r18706
565	557	/* sound hardware */
566	558	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
567	559
568		MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &psx_spu_irq )
	560	MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
569	561	MCFG_SOUND_ROUTE(0, "lspeaker", 0.35)
570	562	MCFG_SOUND_ROUTE(1, "rspeaker", 0.35)
571	563
r18705	r18706
587	579	/* sound hardware */
588	580	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
589	581
590		MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &psx_spu_irq )
	582	MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
591	583	MCFG_SOUND_ROUTE(0, "lspeaker", 0.35)
592	584	MCFG_SOUND_ROUTE(1, "rspeaker", 0.35)
593	585
r18705	r18706
1479	1471	*2                  - Unpopulated DIP28 socket
1480	1472	*/
1481	1473
	1474	/* IRQ */
	1475
	1476	void psx_irq_set( running_machine &machine, UINT32 data )
	1477	{
	1478	psxcpu_device::irq_set( *machine.device("maincpu^"), "maincpu", data );
	1479	}
	1480
1482	1481	static void atpsx_interrupt(device_t *device, int state)
1483	1482	{
1484	1483	if (state)

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